| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: peu_init.h |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #include "peu_defines.h" |
| 39 | |
| 40 | #define PEU_DEVICE_CNTRL_REG_ADDR FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_ADDR |
| 41 | #define PEU_DEVICE_CNTRL__MPS_128 0x00 |
| 42 | #define PEU_DEVICE_CNTRL__MPS_256 0x20 |
| 43 | #define PEU_DEVICE_CNTRL__MPS_512 0x40 |
| 44 | |
| 45 | ! NonPosted Header Credit - hw default 0x10 |
| 46 | #ifndef PEU_NPH_CREDIT |
| 47 | #define PEU_NPH_CREDIT 0x10 |
| 48 | #else |
| 49 | #define PEU_SET_CREDITS 0 |
| 50 | #endif |
| 51 | |
| 52 | ! Posted Header Credit - hw default 0x20. Changes must satisfy (PEU_PH_CREDIT+PEU_NPH_CREDIT) <= 0x30 |
| 53 | #ifndef PEU_PH_CREDIT |
| 54 | #define PEU_PH_CREDIT 0x20 |
| 55 | #else |
| 56 | #define PEU_SET_CREDITS 0 |
| 57 | #endif |
| 58 | |
| 59 | ! Posted Data Credit - hw default 0xc0. Changes must be less than 0xc0 |
| 60 | #ifndef PEU_PD_CREDIT |
| 61 | #define PEU_PD_CREDIT 0xc0 |
| 62 | #else |
| 63 | #define PEU_SET_CREDITS 0 |
| 64 | #endif |
| 65 | |
| 66 | PEU_LINK_TRAINING_START: |
| 67 | ! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.PEU_LINK_TRAINING_START)) -> printf("\n\nIn peu_init.h\n") |
| 68 | |
| 69 | |
| 70 | #ifdef PEU_SET_CREDITS |
| 71 | ! before doing link training, set the Ingress Initial Credits |
| 72 | |
| 73 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_ADDR, %g2, %g3 |
| 74 | setx mpeval((PEU_NPH_CREDIT<<32)|(PEU_PH_CREDIT<<12)|(PEU_PD_CREDIT)), %g2, %g4 |
| 75 | stx %g4, [%g3] |
| 76 | #endif |
| 77 | |
| 78 | #ifdef ENABLE_PCIE_MPS_512 |
| 79 | ! before doing link training, set the MPS to 512 |
| 80 | |
| 81 | setx PEU_DEVICE_CNTRL_REG_ADDR, %g2, %g3 |
| 82 | mov PEU_DEVICE_CNTRL__MPS_512, %g4 |
| 83 | stx %g4, [%g3] |
| 84 | #else |
| 85 | #ifdef ENABLE_PCIE_MPS_256 |
| 86 | ! before doing link training, set the MPS to 256 |
| 87 | |
| 88 | setx PEU_DEVICE_CNTRL_REG_ADDR, %g2, %g3 |
| 89 | mov PEU_DEVICE_CNTRL__MPS_256, %g4 |
| 90 | stx %g4, [%g3] |
| 91 | #endif |
| 92 | #endif |
| 93 | |
| 94 | #ifdef SET_PCIE_ACK_FREQ |
| 95 | ! before doing link training, set the ACK_FREQ |
| 96 | |
| 97 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_ADDR, %g2, %g3 |
| 98 | mov SET_PCIE_ACK_FREQ, %g4 |
| 99 | sll %g4, 8, %g4 |
| 100 | or %g4, 1, %g4 ! bit 0 defaults to 1 == data link layer enable |
| 101 | stx %g4, [%g3] |
| 102 | #endif |
| 103 | |
| 104 | /* |
| 105 | ! The following registers must be initialized in the PEU to start Link Training. |
| 106 | ! * FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL Reg to reset Detect.QuietilupeuScenario |
| 107 | ! |
| 108 | ! Following registers are optional. |
| 109 | ! * FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL Reg to set FTS (Fast Training Sequence) to a smaller value |
| 110 | ! * FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_RW1S_ALIAS_ADDR Set FTS (Fast Training Sequence) to a smaller value |
| 111 | ! |
| 112 | */ |
| 113 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR, %g2, %g3 |
| 114 | ldx [%g3], %g4 |
| 115 | #ifdef PCI_NORMAL_LINK_INIT |
| 116 | mov 0x0000, %g5 ! Mission mode (normal) |
| 117 | #else |
| 118 | mov 0x0010, %g5 ! FAST LINK MODE, for simulation. |
| 119 | #endif |
| 120 | or %g4, %g5, %g5 |
| 121 | stx %g5, [%g3] |
| 122 | |
| 123 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g2, %g3 |
| 124 | #ifndef PCIE_NPWR_EN_DISABLE |
| 125 | setx mpeval(FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_DATA+0x00100000), %g2, %g4 |
| 126 | #else |
| 127 | mov FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_DATA, %g4 |
| 128 | #endif |
| 129 | stx %g4, [%g3] |
| 130 | |
| 131 | |
| 132 | #ifndef FC_NO_PEU_VERA |
| 133 | TrigPEUStart: |
| 134 | nop ! $EV trig_pc_d(1, @VA(.RED_EXT_SEC.TrigPEUStart)) -> set_StartPEUTest() |
| 135 | #endif |
| 136 | |
| 137 | ! |
| 138 | ! Set up the Base and Mask registers in the NCU to enable PIO reads and writes |
| 139 | ! |
| 140 | setx MEM32_OFFSET_BASE_REG_ADDR, %g2, %g3 ! 0x8000002000 |
| 141 | setx MEM32_OFFSET_BASE_REG_DATA, %g2, %g4 |
| 142 | stx %g4, [%g3] |
| 143 | |
| 144 | !setx MEM32_OFFSET_MASK_REG_ADDR, %g2, %g3 ! 0x8000002008 |
| 145 | setx MEM32_OFFSET_MASK_REG_DATA, %g2, %g4 |
| 146 | stx %g4, [%g3 + 0x8] |
| 147 | |
| 148 | !setx MEM64_OFFSET_BASE_REG_ADDR, %g2, %g3 ! 0x8000002010 |
| 149 | setx MEM64_OFFSET_BASE_REG_DATA, %g2, %g4 |
| 150 | stx %g4, [%g3 + 0x10] |
| 151 | |
| 152 | !setx MEM64_OFFSET_MASK_REG_ADDR, %g2, %g3 ! 0x8000002018 |
| 153 | setx MEM64_OFFSET_MASK_REG_DATA, %g2, %g4 |
| 154 | stx %g4, [%g3 + 0x18] |
| 155 | |
| 156 | !setx IOCFG_OFFSET_BASE_REG_ADDR, %g2, %g3 ! 0x8000002020 |
| 157 | setx IOCFG_OFFSET_BASE_REG_DATA, %g2, %g4 |
| 158 | stx %g4, [%g3 + 0x20] |
| 159 | |
| 160 | !setx IOCFG_OFFSET_MASK_REG_ADDR, %g2, %g3 ! 0x8000002028 |
| 161 | setx IOCFG_OFFSET_MASK_REG_DATA, %g2, %g4 |
| 162 | stx %g4, [%g3 + 0x28] |
| 163 | |
| 164 | ! Load the PCIE MEM64 OFFSET Register (and pio deadlock mode bits) |
| 165 | |
| 166 | setx FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_ADDR, %g2, %g3 |
| 167 | #ifndef PEU_PIO_MODE |
| 168 | #define PCIE_MEM64_OFFSET_PLUS_PIO_MODE PCIE_MEM64_OFFSET |
| 169 | #else |
| 170 | #define PCIE_MEM64_OFFSET_PLUS_PIO_MODE mpeval(PCIE_MEM64_OFFSET | (PEU_PIO_MODE & 3)) |
| 171 | #endif |
| 172 | setx PCIE_MEM64_OFFSET_PLUS_PIO_MODE, %g2, %g4 |
| 173 | stx %g4, [%g3] |
| 174 | |
| 175 | ! enable bypass in IOMMU |
| 176 | |
| 177 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g2, %g3 |
| 178 | mov FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g4 |
| 179 | stx %g4, [%g3] |