| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: tsotool_1t_75971.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define N_CPUS 1 |
| 39 | #define REGION_MAPPED_SIZE_RTL 8192 |
| 40 | #define REGION_SIZE_RTL (64 * 1024) |
| 41 | #define RESULTS_BUF_SIZE_PER_CPU_RTL 128 |
| 42 | #define PRIVATE_DATA_AREA_PER_CPU_RTL 64 |
| 43 | |
| 44 | #define ALIGN_PAGE_8K .align 8192 |
| 45 | #define ALIGN_PAGE_64K .align 65536 |
| 46 | #define ALIGN_PAGE_512K .align 524288 |
| 47 | #define ALIGN_PAGE_4M .align 4194304 |
| 48 | SECTION .MY_HYP_SEC TEXT_VA = 0x1100150000 |
| 49 | attr_text { |
| 50 | Name=.MY_HYP_SEC, |
| 51 | hypervisor |
| 52 | } |
| 53 | .text |
| 54 | .global intr0x60_custom_trap |
| 55 | intr0x60_custom_trap: |
| 56 | ldxa [%g0] 0x72, %g2; |
| 57 | ldxa [%g0] 0x74, %g1; |
| 58 | retry; |
| 59 | |
| 60 | .global intr0x190_custom_trap |
| 61 | intr0x190_custom_trap: |
| 62 | |
| 63 | .global intr0x190_custom_trap |
| 64 | intr0x190_custom_trap: |
| 65 | |
| 66 | #ifdef SJM |
| 67 | ! programming the JBI - not quite rrugho |
| 68 | !===================== |
| 69 | !setx 0x0000000006040012, %g1, %g2 |
| 70 | !setx 0x8503000010, %g1, %g3 |
| 71 | !stx %g2, [%g3] |
| 72 | !!===================== |
| 73 | !setx 0x0000000000000003, %g1, %g2 |
| 74 | !setx 0x8500000100, %g1, %g3 |
| 75 | !stx %g2, [%g3] |
| 76 | !!===================== |
| 77 | !setx 0x0000000000000000, %g1, %g2 |
| 78 | !setx 0x9800000000, %g1, %g3 |
| 79 | !stx %g2, [%g3] |
| 80 | !!===================== |
| 81 | !setx 0x0000000000000000, %g1, %g2 |
| 82 | !setx 0x9800000400, %g1, %g3 |
| 83 | !stx %g2, [%g3] |
| 84 | !!===================== |
| 85 | !setx 0x0000000000000003, %g1, %g2 |
| 86 | !setx 0x8500000108, %g1, %g3 |
| 87 | !stx %g2, [%g3] |
| 88 | !!===================== |
| 89 | !setx 0x0000000000000101, %g1, %g2 |
| 90 | !setx 0x9800000008, %g1, %g3 |
| 91 | !stx %g2, [%g3] |
| 92 | !!===================== |
| 93 | !setx 0x0000000000000000, %g1, %g2 |
| 94 | !setx 0x9800000408, %g1, %g3 |
| 95 | !stx %g2, [%g3] |
| 96 | !!===================== |
| 97 | !setx 0x0000000000000003, %g1, %g2 |
| 98 | !setx 0x8500000110, %g1, %g3 |
| 99 | !stx %g2, [%g3] |
| 100 | !!===================== |
| 101 | !setx 0x0000000000000202, %g1, %g2 |
| 102 | !setx 0x9800000010, %g1, %g3 |
| 103 | !stx %g2, [%g3] |
| 104 | !!===================== |
| 105 | !setx 0x0000000000000000, %g1, %g2 |
| 106 | !setx 0x9800000410, %g1, %g3 |
| 107 | !stx %g2, [%g3] |
| 108 | !!===================== |
| 109 | !setx 0x0000000000000003, %g1, %g2 |
| 110 | !setx 0x8500000118, %g1, %g3 |
| 111 | !stx %g2, [%g3] |
| 112 | !!===================== |
| 113 | !setx 0x0000000000000303, %g1, %g2 |
| 114 | !setx 0x9800000018, %g1, %g3 |
| 115 | !stx %g2, [%g3] |
| 116 | !!===================== |
| 117 | !setx 0x0000000000000000, %g1, %g2 |
| 118 | !setx 0x9800000418, %g1, %g3 |
| 119 | !stx %g2, [%g3] |
| 120 | !!===================== |
| 121 | !setx 0x0000000000000003, %g1, %g2 |
| 122 | !setx 0x8500000120, %g1, %g3 |
| 123 | !stx %g2, [%g3] |
| 124 | !!===================== |
| 125 | !setx 0x0000000000000404, %g1, %g2 |
| 126 | !setx 0x9800000020, %g1, %g3 |
| 127 | !stx %g2, [%g3] |
| 128 | !!===================== |
| 129 | !setx 0x0000000000000000, %g1, %g2 |
| 130 | !setx 0x9800000420, %g1, %g3 |
| 131 | !stx %g2, [%g3] |
| 132 | !!===================== |
| 133 | !setx 0x0000000000000003, %g1, %g2 |
| 134 | !setx 0x8500000128, %g1, %g3 |
| 135 | !stx %g2, [%g3] |
| 136 | !!===================== |
| 137 | !setx 0x0000000000000505, %g1, %g2 |
| 138 | !setx 0x9800000028, %g1, %g3 |
| 139 | !stx %g2, [%g3] |
| 140 | !!===================== |
| 141 | !setx 0x0000000000000000, %g1, %g2 |
| 142 | !setx 0x9800000428, %g1, %g3 |
| 143 | !stx %g2, [%g3] |
| 144 | !!===================== |
| 145 | !setx 0x0000000000000003, %g1, %g2 |
| 146 | !setx 0x8500000130, %g1, %g3 |
| 147 | !stx %g2, [%g3] |
| 148 | !!===================== |
| 149 | !setx 0x0000000000000606, %g1, %g2 |
| 150 | !setx 0x9800000030, %g1, %g3 |
| 151 | !stx %g2, [%g3] |
| 152 | !!===================== |
| 153 | !setx 0x0000000000000000, %g1, %g2 |
| 154 | !setx 0x9800000430, %g1, %g3 |
| 155 | !stx %g2, [%g3] |
| 156 | !!===================== |
| 157 | !setx 0x0000000000000003, %g1, %g2 |
| 158 | !setx 0x8500000138, %g1, %g3 |
| 159 | !stx %g2, [%g3] |
| 160 | !!===================== |
| 161 | !setx 0x0000000000000707, %g1, %g2 |
| 162 | !setx 0x9800000038, %g1, %g3 |
| 163 | !stx %g2, [%g3] |
| 164 | !!===================== |
| 165 | !setx 0x0000000000000000, %g1, %g2 |
| 166 | !setx 0x9800000438, %g1, %g3 |
| 167 | !stx %g2, [%g3] |
| 168 | !!===================== |
| 169 | !setx 0x0000000000000003, %g1, %g2 |
| 170 | !setx 0x8500000140, %g1, %g3 |
| 171 | !stx %g2, [%g3] |
| 172 | !!===================== |
| 173 | !setx 0x0000000000000808, %g1, %g2 |
| 174 | !setx 0x9800000040, %g1, %g3 |
| 175 | !stx %g2, [%g3] |
| 176 | !!===================== |
| 177 | !setx 0x0000000000000000, %g1, %g2 |
| 178 | !setx 0x9800000440, %g1, %g3 |
| 179 | !stx %g2, [%g3] |
| 180 | !!===================== |
| 181 | !setx 0x0000000000000003, %g1, %g2 |
| 182 | !setx 0x8500000148, %g1, %g3 |
| 183 | !stx %g2, [%g3] |
| 184 | !!===================== |
| 185 | !setx 0x0000000000000909, %g1, %g2 |
| 186 | !setx 0x9800000048, %g1, %g3 |
| 187 | !stx %g2, [%g3] |
| 188 | !!===================== |
| 189 | !setx 0x0000000000000000, %g1, %g2 |
| 190 | !setx 0x9800000448, %g1, %g3 |
| 191 | !stx %g2, [%g3] |
| 192 | !!===================== |
| 193 | !setx 0x0000000000000003, %g1, %g2 |
| 194 | !setx 0x8500000150, %g1, %g3 |
| 195 | !stx %g2, [%g3] |
| 196 | !!===================== |
| 197 | !setx 0x0000000000000a0a, %g1, %g2 |
| 198 | !setx 0x9800000050, %g1, %g3 |
| 199 | !stx %g2, [%g3] |
| 200 | !!===================== |
| 201 | !setx 0x0000000000000000, %g1, %g2 |
| 202 | !setx 0x9800000450, %g1, %g3 |
| 203 | !stx %g2, [%g3] |
| 204 | !!===================== |
| 205 | !setx 0x0000000000000003, %g1, %g2 |
| 206 | !setx 0x8500000158, %g1, %g3 |
| 207 | !stx %g2, [%g3] |
| 208 | !!===================== |
| 209 | !setx 0x0000000000000b0b, %g1, %g2 |
| 210 | !setx 0x9800000058, %g1, %g3 |
| 211 | !stx %g2, [%g3] |
| 212 | !!===================== |
| 213 | !setx 0x0000000000000000, %g1, %g2 |
| 214 | !setx 0x9800000458, %g1, %g3 |
| 215 | !stx %g2, [%g3] |
| 216 | !!===================== |
| 217 | !setx 0x0000000000000003, %g1, %g2 |
| 218 | !setx 0x8500000160, %g1, %g3 |
| 219 | !stx %g2, [%g3] |
| 220 | !!===================== |
| 221 | !setx 0x0000000000000c0c, %g1, %g2 |
| 222 | !setx 0x9800000060, %g1, %g3 |
| 223 | !stx %g2, [%g3] |
| 224 | !!===================== |
| 225 | !setx 0x0000000000000000, %g1, %g2 |
| 226 | !setx 0x9800000460, %g1, %g3 |
| 227 | !stx %g2, [%g3] |
| 228 | !!===================== |
| 229 | !setx 0x0000000000000003, %g1, %g2 |
| 230 | !setx 0x8500000168, %g1, %g3 |
| 231 | !stx %g2, [%g3] |
| 232 | !!===================== |
| 233 | !setx 0x0000000000000d0d, %g1, %g2 |
| 234 | !setx 0x9800000068, %g1, %g3 |
| 235 | !stx %g2, [%g3] |
| 236 | !!===================== |
| 237 | !setx 0x0000000000000000, %g1, %g2 |
| 238 | !setx 0x9800000468, %g1, %g3 |
| 239 | !stx %g2, [%g3] |
| 240 | !!===================== |
| 241 | !setx 0x0000000000000003, %g1, %g2 |
| 242 | !setx 0x8500000170, %g1, %g3 |
| 243 | !stx %g2, [%g3] |
| 244 | !!===================== |
| 245 | !setx 0x0000000000000e0e, %g1, %g2 |
| 246 | !setx 0x9800000070, %g1, %g3 |
| 247 | !stx %g2, [%g3] |
| 248 | !!===================== |
| 249 | !setx 0x0000000000000000, %g1, %g2 |
| 250 | !setx 0x9800000470, %g1, %g3 |
| 251 | !stx %g2, [%g3] |
| 252 | !!===================== |
| 253 | !setx 0x0000000000000003, %g1, %g2 |
| 254 | !setx 0x8500000178, %g1, %g3 |
| 255 | !stx %g2, [%g3] |
| 256 | !!===================== |
| 257 | !setx 0x0000000000000f0f, %g1, %g2 |
| 258 | !setx 0x9800000078, %g1, %g3 |
| 259 | !stx %g2, [%g3] |
| 260 | !!===================== |
| 261 | !setx 0x0000000000000000, %g1, %g2 |
| 262 | !setx 0x9800000478, %g1, %g3 |
| 263 | !stx %g2, [%g3] |
| 264 | !!===================== |
| 265 | !setx 0x000000000000007f, %g1, %g2 |
| 266 | !setx 0x8503000008, %g1, %g3 |
| 267 | !stx %g2, [%g3] |
| 268 | !!===================== |
| 269 | !setx 0x0000000000001010, %g1, %g2 |
| 270 | !setx 0x9800000080, %g1, %g3 |
| 271 | !stx %g2, [%g3] |
| 272 | !!===================== |
| 273 | !setx 0x0000000000000000, %g1, %g2 |
| 274 | !setx 0x9800000480, %g1, %g3 |
| 275 | !stx %g2, [%g3] |
| 276 | !!===================== |
| 277 | !setx 0x0000000000001111, %g1, %g2 |
| 278 | !setx 0x9800000088, %g1, %g3 |
| 279 | !stx %g2, [%g3] |
| 280 | !!===================== |
| 281 | !setx 0x0000000000000000, %g1, %g2 |
| 282 | !setx 0x9800000488, %g1, %g3 |
| 283 | !stx %g2, [%g3] |
| 284 | !!===================== |
| 285 | !setx 0x0000000000000000, %g1, %g2 |
| 286 | !setx 0x9300000c00, %g1, %g3 |
| 287 | !stx %g2, [%g3] |
| 288 | !!===================== |
| 289 | !setx 0x0000000000000000, %g1, %g2 |
| 290 | !setx 0x9300000e20, %g1, %g3 |
| 291 | !stx %g2, [%g3] |
| 292 | !!===================== |
| 293 | !setx 0x0000000000000000, %g1, %g2 |
| 294 | !setx 0x9300000e28, %g1, %g3 |
| 295 | !stx %g2, [%g3] |
| 296 | !!===================== |
| 297 | !setx 0x0000000000000000, %g1, %g2 |
| 298 | !setx 0x9300000e38, %g1, %g3 |
| 299 | !stx %g2, [%g3] |
| 300 | !!===================== |
| 301 | !setx 0x0000000000000008, %g1, %g2 |
| 302 | !setx 0x8503000018, %g1, %g3 |
| 303 | !stx %g2, [%g3] |
| 304 | !!===================== |
| 305 | !setx 0x0000000000000000, %g1, %g2 |
| 306 | !setx 0x9800000828, %g1, %g3 |
| 307 | !stx %g2, [%g3] |
| 308 | !!===================== |
| 309 | !setx 0x0000000000000000, %g1, %g2 |
| 310 | !setx 0x8503000028, %g1, %g3 |
| 311 | !stx %g2, [%g3] |
| 312 | !!===================== |
| 313 | !setx 0x0000000000000001, %g1, %g2 |
| 314 | !setx 0x8503000020, %g1, %g3 |
| 315 | !stx %g2, [%g3] |
| 316 | !!===================== |
| 317 | |
| 318 | /*********************************************************************** |
| 319 | Disable L2 Cache Visibility Port |
| 320 | ***********************************************************************/ |
| 321 | |
| 322 | setx 0x0000000000000000, %g1, %g2 |
| 323 | setx 0x9800001800, %g1, %g3 |
| 324 | stx %g2, [%g3] |
| 325 | !===================== |
| 326 | setx 0x0000000000000000, %g1, %g2 |
| 327 | setx 0x9800001820, %g1, %g3 |
| 328 | stx %g2, [%g3] |
| 329 | !===================== |
| 330 | setx 0x0000000000000000, %g1, %g2 |
| 331 | setx 0x9800001828, %g1, %g3 |
| 332 | stx %g2, [%g3] |
| 333 | !===================== |
| 334 | setx 0x0000000000000000, %g1, %g2 |
| 335 | setx 0x9800001830, %g1, %g3 |
| 336 | stx %g2, [%g3] |
| 337 | !===================== |
| 338 | setx 0x0000000000000000, %g1, %g2 |
| 339 | setx 0x9800001838, %g1, %g3 |
| 340 | stx %g2, [%g3] |
| 341 | !===================== |
| 342 | setx 0x0000000000000000, %g1, %g2 |
| 343 | setx 0x9800001840, %g1, %g3 |
| 344 | stx %g2, [%g3] |
| 345 | !===================== |
| 346 | |
| 347 | /*********************************************************************** |
| 348 | Disable IOBridge Visibility Ports |
| 349 | ***********************************************************************/ |
| 350 | |
| 351 | setx 0x0000000000000000, %g1, %g2 |
| 352 | setx 0x9800001000, %g1, %g3 |
| 353 | stx %g2, [%g3] |
| 354 | !===================== |
| 355 | setx 0x0000000000000000, %g1, %g2 |
| 356 | setx 0x9800002000, %g1, %g3 |
| 357 | stx %g2, [%g3] |
| 358 | !===================== |
| 359 | setx 0x0000000000000000, %g1, %g2 |
| 360 | setx 0x9800002008, %g1, %g3 |
| 361 | stx %g2, [%g3] |
| 362 | !===================== |
| 363 | setx 0x0000000000000000, %g1, %g2 |
| 364 | setx 0x9800002100, %g1, %g3 |
| 365 | stx %g2, [%g3] |
| 366 | !===================== |
| 367 | setx 0x0000000000000000, %g1, %g2 |
| 368 | setx 0x9800002140, %g1, %g3 |
| 369 | stx %g2, [%g3] |
| 370 | !===================== |
| 371 | setx 0x0000000000000000, %g1, %g2 |
| 372 | setx 0x9800002160, %g1, %g3 |
| 373 | stx %g2, [%g3] |
| 374 | !===================== |
| 375 | setx 0x0000000000000000, %g1, %g2 |
| 376 | setx 0x9800002180, %g1, %g3 |
| 377 | stx %g2, [%g3] |
| 378 | !===================== |
| 379 | setx 0x0000000000000000, %g1, %g2 |
| 380 | setx 0x98000021a0, %g1, %g3 |
| 381 | stx %g2, [%g3] |
| 382 | !===================== |
| 383 | setx 0x0000000000000000, %g1, %g2 |
| 384 | setx 0x9800002148, %g1, %g3 |
| 385 | stx %g2, [%g3] |
| 386 | !===================== |
| 387 | setx 0x0000000000000000, %g1, %g2 |
| 388 | setx 0x9800002168, %g1, %g3 |
| 389 | stx %g2, [%g3] |
| 390 | !===================== |
| 391 | setx 0x0000000000000000, %g1, %g2 |
| 392 | setx 0x9800002188, %g1, %g3 |
| 393 | stx %g2, [%g3] |
| 394 | !===================== |
| 395 | setx 0x0000000000000000, %g1, %g2 |
| 396 | setx 0x98000021a8, %g1, %g3 |
| 397 | stx %g2, [%g3] |
| 398 | !===================== |
| 399 | setx 0x0000000000000000, %g1, %g2 |
| 400 | setx 0x9800002150, %g1, %g3 |
| 401 | stx %g2, [%g3] |
| 402 | !===================== |
| 403 | setx 0x0000000000000000, %g1, %g2 |
| 404 | setx 0x9800002170, %g1, %g3 |
| 405 | stx %g2, [%g3] |
| 406 | !===================== |
| 407 | setx 0x0000000000000000, %g1, %g2 |
| 408 | setx 0x9800002190, %g1, %g3 |
| 409 | stx %g2, [%g3] |
| 410 | !===================== |
| 411 | setx 0x0000000000000000, %g1, %g2 |
| 412 | setx 0x98000021b0, %g1, %g3 |
| 413 | stx %g2, [%g3] |
| 414 | !===================== |
| 415 | |
| 416 | /*********************************************************************** |
| 417 | Configure jbi controller |
| 418 | ***********************************************************************/ |
| 419 | |
| 420 | setx 0x03fb303e00000001, %g1, %g2 |
| 421 | setx 0x8000000000, %g1, %g3 |
| 422 | stx %g2, [%g3] |
| 423 | !===================== |
| 424 | setx 0x000000007033fe0f, %g1, %g2 |
| 425 | setx 0x8000000008, %g1, %g3 |
| 426 | stx %g2, [%g3] |
| 427 | !===================== |
| 428 | setx 0x0000003fc0000000, %g1, %g2 |
| 429 | setx 0x80000100a0, %g1, %g3 |
| 430 | stx %g2, [%g3] |
| 431 | !===================== |
| 432 | setx 0x00000000fe0003ff, %g1, %g2 |
| 433 | setx 0x8000004100, %g1, %g3 |
| 434 | stx %g2, [%g3] |
| 435 | !===================== |
| 436 | |
| 437 | /*********************************************************************** |
| 438 | IOSYNC cycles to start sjm |
| 439 | ***********************************************************************/ |
| 440 | |
| 441 | setx 0xdeadbeefdeadbeef, %g1, %g2 |
| 442 | setx 0xcf00beef00, %g1, %g3 |
| 443 | stx %g2, [%g3] |
| 444 | !===================== |
| 445 | setx 0xdeadbeefdeadbeef, %g1, %g2 |
| 446 | setx 0xef00beef00, %g1, %g3 |
| 447 | stx %g2, [%g3] |
| 448 | |
| 449 | !============================= |
| 450 | done; |
| 451 | |
| 452 | #else |
| 453 | #ifdef DC_ON_OFF |
| 454 | |
| 455 | and %i0, 0x1, %i0 |
| 456 | brz %i0, on |
| 457 | nop |
| 458 | |
| 459 | mov 0xd, %i0 |
| 460 | ba finish_dc_on_off |
| 461 | stxa %l0, [%g0] 0x45 /* turn D-cache off */ |
| 462 | on: |
| 463 | mov 0xf, %i0 |
| 464 | stxa %i0, [%g0] 0x45 /* turn D-cache back on */ |
| 465 | |
| 466 | finish_dc_on_off: |
| 467 | done |
| 468 | |
| 469 | #else |
| 470 | stxa %i0, [%g0] 0x73; |
| 471 | done; |
| 472 | #endif |
| 473 | #endif |
| 474 | !============================================================================ |
| 475 | |
| 476 | #define ENABLE_T0_Fp_exception_ieee_754_0x21 |
| 477 | #define ENABLE_T0_Fp_exception_other_0x22 |
| 478 | #define ENABLE_T0_Fp_disabled_0x20 |
| 479 | #define ENABLE_T0_Illegal_instruction_0x10 |
| 480 | #define ENABLE_T1_Illegal_instruction_0x10 |
| 481 | #define ENABLE_HT0_Illegal_instruction_0x10 |
| 482 | #define ENABLE_HT1_Illegal_instruction_0x10 |
| 483 | #define ENABLE_T0_Clean_Window_0x24 |
| 484 | |
| 485 | #define H_T0_Trap_Instruction_0 |
| 486 | #define My_T0_Trap_Instruction_0 \ |
| 487 | ta 0x90; \ |
| 488 | done; |
| 489 | |
| 490 | #define H_HT0_HTrap_Instruction_0 intr0x190_custom_trap |
| 491 | #ifdef SJM |
| 492 | #define My_HT0_HTrap_Instruction_0 \ |
| 493 | setx intr0x190_custom_trap, %g1, %g2; \ |
| 494 | jmp %g2; nop |
| 495 | #else |
| 496 | #define My_HT0_HTrap_Instruction_0 \ |
| 497 | stxa %i0, [%g0] 0x73; \ |
| 498 | done; |
| 499 | #endif |
| 500 | |
| 501 | #define H_HT0_Interrupt_0x60 intr0x60_custom_trap |
| 502 | #define My_HT0_Interrupt_0x60 \ |
| 503 | ldxa [%g0] 0x72, %g2; \ |
| 504 | ldxa [%g0] 0x74, %g1; \ |
| 505 | retry; |
| 506 | |
| 507 | |
| 508 | #define THREAD_COUNT 8 |
| 509 | #define THREAD_STRIDE 1 |
| 510 | #include "hboot.s" |
| 511 | |
| 512 | !try later: |
| 513 | ! stxa %l6, [$8] (0x22 | ($2 & 0x9)) ! ASI is randomly set |
| 514 | !=========== |
| 515 | define(BST_INIT, ` |
| 516 | add $6, ($7 & 0xfff0), $8 ! 4-byte align the offset |
| 517 | stxa %l6, [$8] 0x22 ! ASI is randomly set |
| 518 | ') |
| 519 | |
| 520 | !try later: |
| 521 | !ldda [$8] (0x22 | ($2 & 0x9)), %l6 ! ASI is randomly set |
| 522 | !=========== |
| 523 | define(BLD_INIT, ` |
| 524 | add $6, ($7 & 0xfff0), $8 ! 4-byte align the offset |
| 525 | ldda [$8] 0x22, %l6 ! ASI is randomly set |
| 526 | ') |
| 527 | |
| 528 | define(CHECK_PROC_ID,` |
| 529 | check_cpu_id: |
| 530 | |
| 531 | wr %g0, 0x4, %fprs /* make sure fef is 1 */ |
| 532 | mov THREAD_STRIDE, %l2 |
| 533 | th_fork(thread,%l0) |
| 534 | |
| 535 | thread_0: |
| 536 | #ifdef SJM |
| 537 | ta 0x30 |
| 538 | #endif |
| 539 | mov 0, %g1 |
| 540 | udivx %g1, %l2, %g1 |
| 541 | ba entry_point; nop |
| 542 | |
| 543 | |
| 544 | thread_1: |
| 545 | mov 1, %g1 |
| 546 | udivx %g1, %l2, %g1 |
| 547 | ba entry_point; nop |
| 548 | |
| 549 | thread_2: |
| 550 | mov 2, %g1 |
| 551 | udivx %g1, %l2, %g1 |
| 552 | ba entry_point; nop |
| 553 | |
| 554 | thread_3: |
| 555 | mov 3, %g1 |
| 556 | udivx %g1, %l2, %g1 |
| 557 | ba entry_point; nop |
| 558 | |
| 559 | thread_4: |
| 560 | mov 4, %g1 |
| 561 | udivx %g1, %l2, %g1 |
| 562 | ba entry_point; nop |
| 563 | |
| 564 | thread_5: |
| 565 | mov 5, %g1 |
| 566 | udivx %g1, %l2, %g1 |
| 567 | ba entry_point; nop |
| 568 | |
| 569 | thread_6: |
| 570 | mov 6, %g1 |
| 571 | udivx %g1, %l2, %g1 |
| 572 | ba entry_point; nop |
| 573 | |
| 574 | thread_7: |
| 575 | mov 7, %g1 |
| 576 | udivx %g1, %l2, %g1 |
| 577 | ba entry_point; nop |
| 578 | |
| 579 | thread_8: |
| 580 | mov 8, %g1 |
| 581 | udivx %g1, %l2, %g1 |
| 582 | ba entry_point; nop |
| 583 | |
| 584 | thread_9: |
| 585 | mov 9, %g1 |
| 586 | udivx %g1, %l2, %g1 |
| 587 | ba entry_point; nop |
| 588 | |
| 589 | thread_10: |
| 590 | mov 10, %g1 |
| 591 | udivx %g1, %l2, %g1 |
| 592 | ba entry_point; nop |
| 593 | |
| 594 | thread_11: |
| 595 | mov 11, %g1 |
| 596 | udivx %g1, %l2, %g1 |
| 597 | ba entry_point; nop |
| 598 | |
| 599 | thread_12: |
| 600 | mov 12, %g1 |
| 601 | udivx %g1, %l2, %g1 |
| 602 | ba entry_point; nop |
| 603 | |
| 604 | thread_13: |
| 605 | mov 13, %g1 |
| 606 | udivx %g1, %l2, %g1 |
| 607 | ba entry_point; nop |
| 608 | |
| 609 | thread_14: |
| 610 | mov 14, %g1 |
| 611 | udivx %g1, %l2, %g1 |
| 612 | ba entry_point; nop |
| 613 | |
| 614 | thread_15: |
| 615 | mov 15, %g1 |
| 616 | udivx %g1, %l2, %g1 |
| 617 | ba entry_point; nop |
| 618 | |
| 619 | thread_16: |
| 620 | mov 16, %g1 |
| 621 | udivx %g1, %l2, %g1 |
| 622 | ba entry_point; nop |
| 623 | |
| 624 | thread_17: |
| 625 | mov 17, %g1 |
| 626 | udivx %g1, %l2, %g1 |
| 627 | ba entry_point; nop |
| 628 | |
| 629 | thread_18: |
| 630 | mov 18, %g1 |
| 631 | udivx %g1, %l2, %g1 |
| 632 | ba entry_point; nop |
| 633 | |
| 634 | thread_19: |
| 635 | mov 19, %g1 |
| 636 | udivx %g1, %l2, %g1 |
| 637 | ba entry_point; nop |
| 638 | |
| 639 | thread_20: |
| 640 | mov 20, %g1 |
| 641 | udivx %g1, %l2, %g1 |
| 642 | ba entry_point; nop |
| 643 | |
| 644 | thread_21: |
| 645 | mov 21, %g1 |
| 646 | udivx %g1, %l2, %g1 |
| 647 | ba entry_point; nop |
| 648 | |
| 649 | thread_22: |
| 650 | mov 22, %g1 |
| 651 | udivx %g1, %l2, %g1 |
| 652 | ba entry_point; nop |
| 653 | |
| 654 | thread_23: |
| 655 | mov 23, %g1 |
| 656 | udivx %g1, %l2, %g1 |
| 657 | ba entry_point; nop |
| 658 | |
| 659 | thread_24: |
| 660 | mov 24, %g1 |
| 661 | udivx %g1, %l2, %g1 |
| 662 | ba entry_point; nop |
| 663 | |
| 664 | thread_25: |
| 665 | mov 25, %g1 |
| 666 | udivx %g1, %l2, %g1 |
| 667 | ba entry_point; nop |
| 668 | |
| 669 | thread_26: |
| 670 | mov 26, %g1 |
| 671 | udivx %g1, %l2, %g1 |
| 672 | ba entry_point; nop |
| 673 | |
| 674 | |
| 675 | thread_27: |
| 676 | mov 27, %g1 |
| 677 | udivx %g1, %l2, %g1 |
| 678 | ba entry_point; nop |
| 679 | |
| 680 | thread_28: |
| 681 | mov 28, %g1 |
| 682 | udivx %g1, %l2, %g1 |
| 683 | ba entry_point; nop |
| 684 | |
| 685 | thread_29: |
| 686 | mov 29, %g1 |
| 687 | udivx %g1, %l2, %g1 |
| 688 | ba entry_point; nop |
| 689 | |
| 690 | thread_30: |
| 691 | mov 30, %g1 |
| 692 | udivx %g1, %l2, %g1 |
| 693 | ba entry_point; nop |
| 694 | |
| 695 | thread_31: |
| 696 | mov 31, %g1 |
| 697 | udivx %g1, %l2, %g1 |
| 698 | ba entry_point; nop |
| 699 | |
| 700 | thread_32: |
| 701 | mov 32, %g1 |
| 702 | udivx %g1, %l2, %g1 |
| 703 | ba entry_point; nop |
| 704 | |
| 705 | thread_33: |
| 706 | mov 33, %g1 |
| 707 | udivx %g1, %l2, %g1 |
| 708 | ba entry_point; nop |
| 709 | |
| 710 | thread_34: |
| 711 | mov 34, %g1 |
| 712 | udivx %g1, %l2, %g1 |
| 713 | ba entry_point; nop |
| 714 | |
| 715 | thread_35: |
| 716 | mov 35, %g1 |
| 717 | udivx %g1, %l2, %g1 |
| 718 | ba entry_point; nop |
| 719 | |
| 720 | thread_36: |
| 721 | mov 36, %g1 |
| 722 | udivx %g1, %l2, %g1 |
| 723 | ba entry_point; nop |
| 724 | |
| 725 | thread_37: |
| 726 | mov 37, %g1 |
| 727 | udivx %g1, %l2, %g1 |
| 728 | ba entry_point; nop |
| 729 | |
| 730 | thread_38: |
| 731 | mov 38, %g1 |
| 732 | udivx %g1, %l2, %g1 |
| 733 | ba entry_point; nop |
| 734 | |
| 735 | thread_39: |
| 736 | mov 39, %g1 |
| 737 | udivx %g1, %l2, %g1 |
| 738 | ba entry_point; nop |
| 739 | |
| 740 | thread_40: |
| 741 | mov 40, %g1 |
| 742 | udivx %g1, %l2, %g1 |
| 743 | ba entry_point; nop |
| 744 | |
| 745 | thread_41: |
| 746 | mov 41, %g1 |
| 747 | udivx %g1, %l2, %g1 |
| 748 | ba entry_point; nop |
| 749 | |
| 750 | thread_42: |
| 751 | mov 42, %g1 |
| 752 | udivx %g1, %l2, %g1 |
| 753 | ba entry_point; nop |
| 754 | |
| 755 | thread_43: |
| 756 | mov 43, %g1 |
| 757 | udivx %g1, %l2, %g1 |
| 758 | ba entry_point; nop |
| 759 | |
| 760 | thread_44: |
| 761 | mov 44, %g1 |
| 762 | udivx %g1, %l2, %g1 |
| 763 | ba entry_point; nop |
| 764 | |
| 765 | thread_45: |
| 766 | mov 45, %g1 |
| 767 | udivx %g1, %l2, %g1 |
| 768 | ba entry_point; nop |
| 769 | |
| 770 | thread_46: |
| 771 | mov 46, %g1 |
| 772 | udivx %g1, %l2, %g1 |
| 773 | ba entry_point; nop |
| 774 | |
| 775 | thread_47: |
| 776 | mov 47, %g1 |
| 777 | udivx %g1, %l2, %g1 |
| 778 | ba entry_point; nop |
| 779 | |
| 780 | thread_48: |
| 781 | mov 48, %g1 |
| 782 | udivx %g1, %l2, %g1 |
| 783 | ba entry_point; nop |
| 784 | |
| 785 | thread_49: |
| 786 | mov 49, %g1 |
| 787 | udivx %g1, %l2, %g1 |
| 788 | ba entry_point; nop |
| 789 | |
| 790 | thread_50: |
| 791 | mov 50, %g1 |
| 792 | udivx %g1, %l2, %g1 |
| 793 | ba entry_point; nop |
| 794 | |
| 795 | thread_51: |
| 796 | mov 51, %g1 |
| 797 | udivx %g1, %l2, %g1 |
| 798 | ba entry_point; nop |
| 799 | |
| 800 | thread_52: |
| 801 | mov 52, %g1 |
| 802 | udivx %g1, %l2, %g1 |
| 803 | ba entry_point; nop |
| 804 | |
| 805 | thread_53: |
| 806 | mov 53, %g1 |
| 807 | udivx %g1, %l2, %g1 |
| 808 | ba entry_point; nop |
| 809 | |
| 810 | thread_54: |
| 811 | mov 54, %g1 |
| 812 | udivx %g1, %l2, %g1 |
| 813 | ba entry_point; nop |
| 814 | |
| 815 | thread_55: |
| 816 | mov 55, %g1 |
| 817 | udivx %g1, %l2, %g1 |
| 818 | ba entry_point; nop |
| 819 | |
| 820 | thread_56: |
| 821 | mov 56, %g1 |
| 822 | udivx %g1, %l2, %g1 |
| 823 | ba entry_point; nop |
| 824 | |
| 825 | thread_57: |
| 826 | mov 57, %g1 |
| 827 | udivx %g1, %l2, %g1 |
| 828 | ba entry_point; nop |
| 829 | |
| 830 | thread_58: |
| 831 | mov 58, %g1 |
| 832 | udivx %g1, %l2, %g1 |
| 833 | ba entry_point; nop |
| 834 | |
| 835 | thread_59: |
| 836 | mov 59, %g1 |
| 837 | udivx %g1, %l2, %g1 |
| 838 | ba entry_point; nop |
| 839 | |
| 840 | thread_60: |
| 841 | mov 60, %g1 |
| 842 | udivx %g1, %l2, %g1 |
| 843 | ba entry_point; nop |
| 844 | |
| 845 | thread_61: |
| 846 | mov 61, %g1 |
| 847 | udivx %g1, %l2, %g1 |
| 848 | ba entry_point; nop |
| 849 | |
| 850 | thread_62: |
| 851 | mov 62, %g1 |
| 852 | udivx %g1, %l2, %g1 |
| 853 | ba entry_point; nop |
| 854 | |
| 855 | thread_63: |
| 856 | mov 63, %g1 |
| 857 | udivx %g1, %l2, %g1 |
| 858 | ba entry_point; nop |
| 859 | |
| 860 | entry_point: |
| 861 | #ifdef RTGPRIV |
| 862 | ta T_CHANGE_PRIV |
| 863 | #endif |
| 864 | |
| 865 | ') |
| 866 | ! --- Common Macro Definitions --- |
| 867 | ! |
| 868 | ! macros will be instantiated with these arguments |
| 869 | ! macro_name(P#, rand#, my_cpu#, PA_val, VA_val, VA_reg, VA_offset, \ |
| 870 | ! tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) |
| 871 | ! |
| 872 | ! P# - Pid, just in case one needs unique number |
| 873 | ! rand# - random number |
| 874 | ! my_cpu# - CPU id |
| 875 | ! PA_val - shared memory physisal address value |
| 876 | ! VA_val - shared memory virtual address value |
| 877 | ! VA_reg - register containing VA region base address |
| 878 | ! VA_offset - VA_reg + VA_offset will give correct VA address value |
| 879 | ! tmp_reg0-tmp_reg3 - integer registers for arbitrary use within the macro |
| 880 | ! tmp_reg0 & tmp_reg1 are even-odd register pair |
| 881 | ! |
| 882 | ! VA_val may be incorrect since VA will be determined at compile time by assembler |
| 883 | ! and may not available at diag generation time, but VA_reg+VA_offset is valid |
| 884 | ! |
| 885 | ! ex. SAMPLE(1, 1249, 0, 0x43400100, 0x100, %i1, 0x100, %l6, %l7, %o5, %l3) |
| 886 | ! |
| 887 | ! Sample macro 1: |
| 888 | ! load unsigned byte from the given shared addr into tmp_reg1 |
| 889 | ! the given shared addr is 4-byte aligned and we will randomly |
| 890 | ! pick one byte from the 4 bytes. |
| 891 | ! |
| 892 | ! define(SAMPLE, ` |
| 893 | ! ldub [$6+$7+($2 mod 4)], $8 |
| 894 | ! ') |
| 895 | ! |
| 896 | ! Can also use C-like macro definition format. |
| 897 | ! |
| 898 | ! Sample macro 2: |
| 899 | ! issue an "ldda" instruction to the randomly picked shared location |
| 900 | ! (aligned it to 16-byte boundary first) with a random ASI value among |
| 901 | ! 0x22, 0x23, 0x2a, and 0x2b (utilizing the provided "rand" value). |
| 902 | ! |
| 903 | ! #define BLD_INIT(Pid, rand, my_cpu, PA_val, \ |
| 904 | ! VA_val, VA_reg, VA_offset, \ |
| 905 | ! tmp_reg0, tmp_reg1, tmp_reg2, tmp_reg3) \ |
| 906 | ! add VA_reg, (VA_offset & 0xfff0), tmp_reg3; \ |
| 907 | ! ldda [tmp_reg2] (0x22 | (rand & 0x9)), tmp_reg0; |
| 908 | ! |
| 909 | ! --- |
| 910 | |
| 911 | ! Macro NOPTRAIN |
| 912 | ! Train of NOPs |
| 913 | |
| 914 | #define NOPTRAIN(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ |
| 915 | nop;\ |
| 916 | nop;\ |
| 917 | nop;\ |
| 918 | nop; |
| 919 | |
| 920 | |
| 921 | ! Macro STTRAIN4 |
| 922 | ! Train of total 4 of UW stores. |
| 923 | ! Note: doesn't use shared addresses |
| 924 | |
| 925 | #define STTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ |
| 926 | set 5120, tmp_reg1; \ |
| 927 | add %i0, tmp_reg1, tmp_reg1; \ |
| 928 | set rand, tmp_reg2; \ |
| 929 | stw tmp_reg2, [tmp_reg1]; \ |
| 930 | stw tmp_reg2, [tmp_reg1+4]; \ |
| 931 | stw tmp_reg2, [tmp_reg1+8]; \ |
| 932 | stw tmp_reg2, [tmp_reg1+16]; |
| 933 | |
| 934 | ! Macro STTRAIN8 |
| 935 | ! Train of total 8 of UW stores |
| 936 | |
| 937 | #define STTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ |
| 938 | set 5120, tmp_reg1; \ |
| 939 | add %i0, tmp_reg1, tmp_reg1; \ |
| 940 | set rand, tmp_reg2; \ |
| 941 | add tmp_reg2, rand % 4096, tmp_reg3; \ |
| 942 | stw tmp_reg2, [tmp_reg1]; \ |
| 943 | stw tmp_reg2, [tmp_reg1+4]; \ |
| 944 | stw tmp_reg2, [tmp_reg1+8]; \ |
| 945 | stw tmp_reg2, [tmp_reg1+12]; \ |
| 946 | stw tmp_reg3, [tmp_reg1+4]; \ |
| 947 | stw tmp_reg3, [tmp_reg1+12]; \ |
| 948 | stw tmp_reg3, [tmp_reg1]; \ |
| 949 | stw tmp_reg3, [tmp_reg1+8]; |
| 950 | |
| 951 | ! Macro LDTRAIN4 |
| 952 | ! Train of total 4 of UW Loads |
| 953 | ! Note the values of those loads inside the macro will not be analized, |
| 954 | ! even though the access are [possibly] made to the shared locations |
| 955 | |
| 956 | #define LDTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ |
| 957 | ld [%i0], tmp_reg1; \ |
| 958 | ld [%i1+4], tmp_reg1; \ |
| 959 | ld [%i2+8], tmp_reg1; \ |
| 960 | ld [%i3+12], tmp_reg1; |
| 961 | |
| 962 | ! Macro LDTRAIN8 |
| 963 | |
| 964 | #define LDTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ |
| 965 | ld [%i3], tmp_reg1; \ |
| 966 | ld [%i2+4], tmp_reg1; \ |
| 967 | ld [%i1+8], tmp_reg2; \ |
| 968 | ld [%i0+12], tmp_reg2; \ |
| 969 | ld [%i3+4], tmp_reg3; \ |
| 970 | ld [%i2], tmp_reg3; \ |
| 971 | ld [%i1+12], tmp_reg4; \ |
| 972 | ld [%i0+8], tmp_reg4; |
| 973 | |
| 974 | ! Macro PREFETCHTRAIN4 |
| 975 | |
| 976 | #define PREFETCHTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ |
| 977 | prefetch [%i0+4], 0; \ |
| 978 | prefetch [%i1+12], 0; \ |
| 979 | prefetch [%i2+8], 0; \ |
| 980 | prefetch [%i3], 0; |
| 981 | |
| 982 | ! Macro PREFETCHTRAIN8 |
| 983 | |
| 984 | #define PREFETCHTRAIN8(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ |
| 985 | prefetch [%i3], 0; \ |
| 986 | prefetch [%i2+4], 0; \ |
| 987 | prefetch [%i1+8], 0; \ |
| 988 | prefetch [%i0+12], 0; \ |
| 989 | prefetch [%i3+4], 1; \ |
| 990 | prefetch [%i2], 1; \ |
| 991 | prefetch [%i1+12], 1; \ |
| 992 | prefetch [%i0+8], 1; |
| 993 | |
| 994 | ! Macro CASTRAIN4 |
| 995 | ! This is an interesting macro that will probably create the write congessions |
| 996 | ! access to the shared locations (offsets from bases have to be adjusted) |
| 997 | ! the values of the locations are not changed, so it should not affect analysis |
| 998 | |
| 999 | #define CASTRAIN4(Pid, rand, my_cpu, PA_val, VA_val, VA_reg, VA_offset, tmp_reg1, tmp_reg2, tmp_reg3, tmp_reg4) \ |
| 1000 | set 128, tmp_reg1;\ |
| 1001 | add %i0, tmp_reg1, tmp_reg1;\ |
| 1002 | set 256, tmp_reg2;\ |
| 1003 | add %i1, tmp_reg2, tmp_reg2;\ |
| 1004 | ld [tmp_reg1], tmp_reg3;\ |
| 1005 | ld [tmp_reg2], tmp_reg4;\ |
| 1006 | cas [tmp_reg1], tmp_reg3, tmp_reg3;\ |
| 1007 | cas [tmp_reg1], tmp_reg3, tmp_reg3;\ |
| 1008 | cas [tmp_reg2], tmp_reg4, tmp_reg4;\ |
| 1009 | cas [tmp_reg2], tmp_reg4, tmp_reg4; |
| 1010 | |
| 1011 | |
| 1012 | define(EN_INTERRUPTS,` |
| 1013 | rdpr %pstate, $1 |
| 1014 | or $1, 0x002, $1 |
| 1015 | wrpr $1, %pstate |
| 1016 | ') |
| 1017 | |
| 1018 | define(DIS_INTERRUPTS,` |
| 1019 | rdpr %pstate, $1 |
| 1020 | and $1, 0xffd, $1 |
| 1021 | wrpr $1, %pstate ! set PSTATE.IE |
| 1022 | ') |
| 1023 | |
| 1024 | define(CHECK_DISPATCH_STATUS,` |
| 1025 | mov $1, $3 |
| 1026 | mulx $3, 2, $3 |
| 1027 | mov 3, $4 |
| 1028 | sllx $4, $3, $4 |
| 1029 | ldxa [%g0]ASI_INTR_DISPATCH_STATUS, $3 |
| 1030 | and $3, $4, $3 |
| 1031 | cmp %g0, $3 |
| 1032 | bne $2 |
| 1033 | ') |
| 1034 | |
| 1035 | define(CHECK_RECEIVE_STATUS,` |
| 1036 | ldxa [%g0]ASI_INTR_RECEIVE, $1 |
| 1037 | cmp %g0, $1 |
| 1038 | tne BAD_TRAP |
| 1039 | ') |
| 1040 | |
| 1041 | define(WRITE_INTR_DATA_REGS,` |
| 1042 | setx $1, $2, $3 |
| 1043 | add %g0, ASI_INTR_DATA0_W_VAL, $2 |
| 1044 | stxa $3, [$2]ASI_INTR_DATA0_W |
| 1045 | setx $1, $2, $3 |
| 1046 | add %g0, ASI_INTR_DATA1_W_VAL, $2 |
| 1047 | stxa $3, [$2]ASI_INTR_DATA1_W |
| 1048 | setx $1, $2, $3 |
| 1049 | add %g0, ASI_INTR_DATA2_W_VAL, $2 |
| 1050 | stxa $3, [$2]ASI_INTR_DATA2_W |
| 1051 | setx $1, $2, $3 |
| 1052 | add %g0, ASI_INTR_DATA3_W_VAL, $2 |
| 1053 | stxa $3, [$2]ASI_INTR_DATA3_W |
| 1054 | setx $1, $2, $3 |
| 1055 | add %g0, ASI_INTR_DATA4_W_VAL, $2 |
| 1056 | stxa $3, [$2]ASI_INTR_DATA4_W |
| 1057 | setx $1, $2, $3 |
| 1058 | add %g0, ASI_INTR_DATA5_W_VAL, $2 |
| 1059 | stxa $3, [$2]ASI_INTR_DATA5_W |
| 1060 | setx $1, $2, $3 |
| 1061 | add %g0, ASI_INTR_DATA6_W_VAL, $2 |
| 1062 | stxa $3, [$2]ASI_INTR_DATA6_W |
| 1063 | setx $1, $2, $3 |
| 1064 | add %g0, ASI_INTR_DATA7_W_VAL, $2 |
| 1065 | stxa $3, [$2]ASI_INTR_DATA7_W |
| 1066 | membar #Sync |
| 1067 | ') |
| 1068 | |
| 1069 | define(INTR_SET_DISPATCH_VECTOR,` |
| 1070 | or %g0,$1,$4 |
| 1071 | sllx $4, 29, $4 ! SID |
| 1072 | mov $4, $5 |
| 1073 | or %g0,$2,$4 |
| 1074 | sllx $4, 24, $4 ! BN pair |
| 1075 | or $5,$4,$5 |
| 1076 | or %g0,$3,$4 |
| 1077 | sllx $4, 14, $4 ! MID |
| 1078 | or $5,$4,$5 |
| 1079 | or $5,0x70,$5 ! VA[13:0] = 0x70 |
| 1080 | ') |
| 1081 | |
| 1082 | define(DSPCH_INTERRUPT,` |
| 1083 | stxa %g0, [$1]ASI_INTR_DISPATCH_W |
| 1084 | membar #Sync |
| 1085 | ') |
| 1086 | |
| 1087 | #define REGION0_ALIAS0_O 0x0 |
| 1088 | #define REGION1_ALIAS0_O 0x10000 |
| 1089 | #define REGION2_ALIAS0_O 0x20000 |
| 1090 | #define REGION3_ALIAS0_O 0x30000 |
| 1091 | #define REPLACEMENT0_ALIAS0_O 0x40000 |
| 1092 | |
| 1093 | |
| 1094 | !------------------------------------------------------------------------ |
| 1095 | |
| 1096 | .seg "data" |
| 1097 | ALIGN_PAGE_512K |
| 1098 | tsotool_unshared_data_start: |
| 1099 | !-- label names of res_buf must match with extract_loads_m64.pl -- |
| 1100 | .align 64 ! for self bcopy() |
| 1101 | res_buf_fp_p_0: |
| 1102 | .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 |
| 1103 | .align 64 ! for self bcopy() |
| 1104 | res_buf_int_p_0: |
| 1105 | .skip RESULTS_BUF_SIZE_PER_CPU_RTL/2 |
| 1106 | private_data_p0: |
| 1107 | .skip PRIVATE_DATA_AREA_PER_CPU_RTL |
| 1108 | stack_top_p0: |
| 1109 | .skip 2048 |
| 1110 | tsotool_unshared_data_end: |
| 1111 | ALIGN_PAGE_512K |
| 1112 | ! to prevent VAs from running over from this section into shared regions |
| 1113 | |
| 1114 | !------------------------------------------------------------------------ |
| 1115 | |
| 1116 | .seg "data" |
| 1117 | ! 4 shared memory regions, 0 alias(es) each (Alias 0 is normal VA) |
| 1118 | |
| 1119 | ALIGN_PAGE_8K |
| 1120 | REGION0_ALIAS0_START: |
| 1121 | .skip REGION_MAPPED_SIZE_RTL |
| 1122 | REGION0_ALIAS0_END: |
| 1123 | .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL |
| 1124 | |
| 1125 | ALIGN_PAGE_8K |
| 1126 | REGION1_ALIAS0_START: |
| 1127 | .skip REGION_MAPPED_SIZE_RTL |
| 1128 | REGION1_ALIAS0_END: |
| 1129 | .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL |
| 1130 | |
| 1131 | ALIGN_PAGE_8K |
| 1132 | REGION2_ALIAS0_START: |
| 1133 | .skip REGION_MAPPED_SIZE_RTL |
| 1134 | REGION2_ALIAS0_END: |
| 1135 | .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL |
| 1136 | |
| 1137 | ALIGN_PAGE_8K |
| 1138 | REGION3_ALIAS0_START: |
| 1139 | .skip REGION_MAPPED_SIZE_RTL |
| 1140 | REGION3_ALIAS0_END: |
| 1141 | .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL |
| 1142 | |
| 1143 | ALIGN_PAGE_8K |
| 1144 | REPLACEMENT0_ALIAS0_START: |
| 1145 | .skip REGION_MAPPED_SIZE_RTL |
| 1146 | REPLACEMENT0_ALIAS0_END: |
| 1147 | .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL |
| 1148 | |
| 1149 | ALIGN_PAGE_8K |
| 1150 | REPLACEMENT1_ALIAS0_START: |
| 1151 | .skip REGION_MAPPED_SIZE_RTL |
| 1152 | REPLACEMENT1_ALIAS0_END: |
| 1153 | .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL |
| 1154 | |
| 1155 | ALIGN_PAGE_8K |
| 1156 | REPLACEMENT2_ALIAS0_START: |
| 1157 | .skip REGION_MAPPED_SIZE_RTL |
| 1158 | REPLACEMENT2_ALIAS0_END: |
| 1159 | .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL |
| 1160 | |
| 1161 | ALIGN_PAGE_8K |
| 1162 | REPLACEMENT3_ALIAS0_START: |
| 1163 | .skip REGION_MAPPED_SIZE_RTL |
| 1164 | REPLACEMENT3_ALIAS0_END: |
| 1165 | .skip REGION_SIZE_RTL-REGION_MAPPED_SIZE_RTL |
| 1166 | |
| 1167 | .seg "text" |
| 1168 | ALIGN_PAGE_8K |
| 1169 | local_trap_handlers_start: |
| 1170 | |
| 1171 | .align 64 |
| 1172 | extern_interrupt_handler: |
| 1173 | stxa %g0, [%g0]ASI_INTR_RECEIVE |
| 1174 | retry |
| 1175 | |
| 1176 | local_trap_handlers_end: |
| 1177 | |
| 1178 | .global main |
| 1179 | .seg "text" |
| 1180 | ALIGN_PAGE_8K |
| 1181 | user_text_start: |
| 1182 | ba main |
| 1183 | nop |
| 1184 | user_text_end: |
| 1185 | |
| 1186 | ALIGN_PAGE_64K |
| 1187 | tsotool_text_start: |
| 1188 | main: |
| 1189 | mov 0, %o0 |
| 1190 | mov 0, %o1 |
| 1191 | CHECK_PROC_ID |
| 1192 | ! at this point, g1 should have CPU id (0, 1, 2, ...) |
| 1193 | set REGION0_ALIAS0_START, %o0 ! shared address 0 |
| 1194 | set REGION1_ALIAS0_START, %o1 ! shared address 1 |
| 1195 | set REGION2_ALIAS0_START, %o2 ! shared address 2 |
| 1196 | set REGION3_ALIAS0_START, %o3 ! shared address 3 |
| 1197 | cmp %g1, 0x0 |
| 1198 | be setup_p0 |
| 1199 | nop |
| 1200 | EXIT_BAD ! Should never reach here |
| 1201 | nop |
| 1202 | |
| 1203 | setup_p0: |
| 1204 | setx stack_top_p0, %g1, %l1 |
| 1205 | add %l1, 1024, %sp |
| 1206 | setx res_buf_fp_p_0, %g1, %o4 |
| 1207 | setx private_data_p0, %g1, %o5 |
| 1208 | setx func0, %g1, %l4 |
| 1209 | call %l4 |
| 1210 | nop |
| 1211 | EXIT_GOOD |
| 1212 | nop |
| 1213 | #define NO_REAL_CPUS_MINUS_1 0 |
| 1214 | |
| 1215 | !----------------- |
| 1216 | |
| 1217 | ! register usage: |
| 1218 | ! %i0 %i1 : base registers for first 2 regions |
| 1219 | ! %i2 %i3 : cache registers for 4 regions |
| 1220 | ! %i4 fixed pointer to per-cpu results area |
| 1221 | ! %l1 moving pointer to per-cpu FP results area |
| 1222 | ! %o7 moving pointer to per-cpu integer results area |
| 1223 | ! %i5 pointer to per-cpu private area |
| 1224 | ! %l0 holds lfsr, used as source of random bits |
| 1225 | ! %l2 loop count register |
| 1226 | ! %f16 running counter for unique fp store values |
| 1227 | ! %f17 holds increment value for fp counter |
| 1228 | ! %l4 running counter for unique integer store values (increment value is always 1) |
| 1229 | ! %l5 move-to register for load values (simulation only) |
| 1230 | ! %f30 move-to register for FP values (simulation only) |
| 1231 | ! %l3 %l6 %l7 %o5 : 4 temporary registers |
| 1232 | ! %o0 %o1 %o2 %o3 %o4 : 5 integer results buffer registers |
| 1233 | ! %f0-f15 FP results buffer registers |
| 1234 | ! %f32-f47 FP block load/store registers |
| 1235 | |
| 1236 | func0: |
| 1237 | ! 100 (dynamic) instruction sequence begins |
| 1238 | save %sp, -192, %sp |
| 1239 | |
| 1240 | ! Force %i0-%i3 to be 64-byte aligned |
| 1241 | add %i0, 63, %i0 |
| 1242 | andn %i0, 63, %i0 |
| 1243 | |
| 1244 | add %i1, 63, %i1 |
| 1245 | andn %i1, 63, %i1 |
| 1246 | |
| 1247 | add %i2, 63, %i2 |
| 1248 | andn %i2, 63, %i2 |
| 1249 | |
| 1250 | add %i3, 63, %i3 |
| 1251 | andn %i3, 63, %i3 |
| 1252 | |
| 1253 | add %i4, 63, %i4 |
| 1254 | andn %i4, 63, %i4 |
| 1255 | |
| 1256 | add %i5, 63, %i5 |
| 1257 | andn %i5, 63, %i5 |
| 1258 | |
| 1259 | |
| 1260 | ! Initialize pointer to FP load results area |
| 1261 | mov %i4, %l1 |
| 1262 | |
| 1263 | ! Initialize pointer to integer load results area |
| 1264 | sethi %hi(0x80000), %o7 |
| 1265 | or %o7, %lo(0x80000), %o7 |
| 1266 | add %o7, %l1, %o7 |
| 1267 | |
| 1268 | ! Initialize %f0-%f62 to 0xdeadbee0deadbee1 |
| 1269 | sethi %hi(0xdeadbee0), %l6 |
| 1270 | or %l6, %lo(0xdeadbee0), %l6 |
| 1271 | stw %l6, [%i5] |
| 1272 | sethi %hi(0xdeadbee1), %l6 |
| 1273 | or %l6, %lo(0xdeadbee1), %l6 |
| 1274 | stw %l6, [%i5+4] |
| 1275 | ldd [%i5], %f0 |
| 1276 | fmovd %f0, %f2 |
| 1277 | fmovd %f0, %f4 |
| 1278 | fmovd %f0, %f6 |
| 1279 | fmovd %f0, %f8 |
| 1280 | fmovd %f0, %f10 |
| 1281 | fmovd %f0, %f12 |
| 1282 | fmovd %f0, %f14 |
| 1283 | fmovd %f0, %f16 |
| 1284 | fmovd %f0, %f18 |
| 1285 | fmovd %f0, %f20 |
| 1286 | fmovd %f0, %f22 |
| 1287 | fmovd %f0, %f24 |
| 1288 | fmovd %f0, %f26 |
| 1289 | fmovd %f0, %f28 |
| 1290 | fmovd %f0, %f30 |
| 1291 | fmovd %f0, %f32 |
| 1292 | fmovd %f0, %f34 |
| 1293 | fmovd %f0, %f36 |
| 1294 | fmovd %f0, %f38 |
| 1295 | fmovd %f0, %f40 |
| 1296 | fmovd %f0, %f42 |
| 1297 | fmovd %f0, %f44 |
| 1298 | fmovd %f0, %f46 |
| 1299 | fmovd %f0, %f48 |
| 1300 | fmovd %f0, %f50 |
| 1301 | fmovd %f0, %f52 |
| 1302 | fmovd %f0, %f54 |
| 1303 | fmovd %f0, %f56 |
| 1304 | fmovd %f0, %f58 |
| 1305 | fmovd %f0, %f60 |
| 1306 | fmovd %f0, %f62 |
| 1307 | |
| 1308 | ! Signature for extract_loads script to start extracting load values for this stream |
| 1309 | sethi %hi(0x00deade1), %l6 |
| 1310 | or %l6, %lo(0x00deade1), %l6 |
| 1311 | stw %l6, [%i5] |
| 1312 | ld [%i5], %f16 |
| 1313 | |
| 1314 | ! Initialize running integer counter in register %l4 |
| 1315 | sethi %hi(0x1), %l4 |
| 1316 | or %l4, %lo(0x1), %l4 |
| 1317 | |
| 1318 | ! Initialize running FP counter in register %f16 |
| 1319 | sethi %hi(0x3f800001), %l6 |
| 1320 | or %l6, %lo(0x3f800001), %l6 |
| 1321 | stw %l6, [%i5] |
| 1322 | ld [%i5], %f16 |
| 1323 | |
| 1324 | ! Initialize FP counter increment value in register %f17 (constant) |
| 1325 | sethi %hi(0x34000000), %l6 |
| 1326 | or %l6, %lo(0x34000000), %l6 |
| 1327 | stw %l6, [%i5] |
| 1328 | ld [%i5], %f17 |
| 1329 | |
| 1330 | ! Initialize LFSR to 0x75ef^4 |
| 1331 | sethi %hi(0x75ef), %l0 |
| 1332 | or %l0, %lo(0x75ef), %l0 |
| 1333 | mulx %l0, %l0, %l0 |
| 1334 | mulx %l0, %l0, %l0 |
| 1335 | |
| 1336 | !-- init shared addrs 0 to 15 --- |
| 1337 | stx %g0, [%i0+0] |
| 1338 | stx %g0, [%i0+8] |
| 1339 | stx %g0, [%i0+32] |
| 1340 | stx %g0, [%i0+64] |
| 1341 | stx %g0, [%i1+72] |
| 1342 | stx %g0, [%i1+80] |
| 1343 | stx %g0, [%i1+256] |
| 1344 | stx %g0, [%i1+512] |
| 1345 | sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 |
| 1346 | add %i0, %i3, %i3 |
| 1347 | stx %g0, [%i3+32] |
| 1348 | stx %g0, [%i3+64] |
| 1349 | sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 |
| 1350 | add %i0, %i2, %i2 |
| 1351 | stx %g0, [%i2+0] |
| 1352 | stx %g0, [%i2+64] |
| 1353 | stx %g0, [%i2+128] |
| 1354 | stx %g0, [%i2+192] |
| 1355 | |
| 1356 | ! use untouched cache-line (offset 4K) in replacement area for sync |
| 1357 | ! need to do atomic ops, so need CV=1 (guarunteed in replacement area) |
| 1358 | sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i3 |
| 1359 | add %i0, %i3, %i3 |
| 1360 | sub %i3, -4096, %l7 |
| 1361 | |
| 1362 | sethi %hi(0x10000), %l6 ! for sync time-out |
| 1363 | !-- master of sync_init --- |
| 1364 | or %g0, NO_REAL_CPUS_MINUS_1, %o5 |
| 1365 | stw %o5, [%l7] |
| 1366 | membar #Sync |
| 1367 | sync_init_0: |
| 1368 | brnz,pt %l6, 1f |
| 1369 | sub %l6, 1, %l6 ! delay slot |
| 1370 | EXIT_BAD |
| 1371 | 1: |
| 1372 | brnz,pt %o5, sync_init_0 |
| 1373 | lduw [%l7], %o5 ! delay slot |
| 1374 | !-- end of sync_init --- |
| 1375 | |
| 1376 | |
| 1377 | BEGIN_NODES0: ! Test istream for CPU 0 begins |
| 1378 | |
| 1379 | P1: !_QWST [6] (maybe <- 0x3f800001) (FP) (Loop entry) (Loop exit) |
| 1380 | sethi %hi(0x1), %l2 |
| 1381 | or %l2, %lo(0x1), %l2 |
| 1382 | loop_entry_0_0: |
| 1383 | ! preparing store val #0, next val will be in f20 |
| 1384 | fmovs %f16, %f20 |
| 1385 | fadds %f16, %f17, %f16 |
| 1386 | ! preparing store val #1, next val will be in f21 |
| 1387 | fmovs %f16, %f21 |
| 1388 | fadds %f16, %f17, %f16 |
| 1389 | stq %f20, [%i1 + 80] |
| 1390 | loop_exit_0_0: |
| 1391 | sub %l2, 1, %l2 |
| 1392 | cmp %l2, 0 |
| 1393 | bg loop_entry_0_0 |
| 1394 | nop |
| 1395 | |
| 1396 | P2: !_PREFETCH [2] (Int) (Loop entry) |
| 1397 | sethi %hi(0x2), %l2 |
| 1398 | or %l2, %lo(0x2), %l2 |
| 1399 | loop_entry_0_1: |
| 1400 | prefetch [%i0 + 12], 1 |
| 1401 | |
| 1402 | P3: !_PREFETCH [11] (Int) |
| 1403 | sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 |
| 1404 | add %i0, %i2, %i2 |
| 1405 | prefetch [%i2 + 64], 1 |
| 1406 | |
| 1407 | P4: !_PREFETCH [1] (Int) (LE) |
| 1408 | wr %g0, 0x88, %asi |
| 1409 | prefetcha [%i0 + 4] %asi, 1 |
| 1410 | |
| 1411 | P5: !_PREFETCH [2] (Int) |
| 1412 | prefetch [%i0 + 12], 1 |
| 1413 | |
| 1414 | P6: !_QWST [2] (maybe <- 0x3f800003) (FP) |
| 1415 | ! preparing store val #0, next val will be in f20 |
| 1416 | fmovs %f16, %f20 |
| 1417 | fadds %f16, %f17, %f16 |
| 1418 | ! preparing store val #1, next val will be in f21 |
| 1419 | fmovs %f16, %f21 |
| 1420 | fadds %f16, %f17, %f16 |
| 1421 | ! preparing store val #2, next val will be in f23 |
| 1422 | fmovs %f16, %f23 |
| 1423 | fadds %f16, %f17, %f16 |
| 1424 | stq %f20, [%i0 + 0] |
| 1425 | |
| 1426 | P7: !_QWST [12] (maybe <- 0x3f800006) (FP) |
| 1427 | sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 |
| 1428 | add %i0, %i3, %i3 |
| 1429 | ! preparing store val #0, next val will be in f20 |
| 1430 | fmovs %f16, %f20 |
| 1431 | fadds %f16, %f17, %f16 |
| 1432 | stq %f20, [%i3 + 0] |
| 1433 | |
| 1434 | P8: !_PREFETCH [9] (Int) |
| 1435 | prefetch [%i1 + 512], 1 |
| 1436 | |
| 1437 | P9: !_PREFETCH [6] (Int) (Loop exit) |
| 1438 | prefetch [%i1 + 80], 1 |
| 1439 | loop_exit_0_1: |
| 1440 | sub %l2, 1, %l2 |
| 1441 | cmp %l2, 0 |
| 1442 | bg loop_entry_0_1 |
| 1443 | nop |
| 1444 | |
| 1445 | P10: !_QWST [7] (maybe <- 0x3f800007) (FP) (Loop entry) |
| 1446 | sethi %hi(0x3), %l2 |
| 1447 | or %l2, %lo(0x3), %l2 |
| 1448 | loop_entry_0_2: |
| 1449 | ! preparing store val #0, next val will be in f20 |
| 1450 | fmovs %f16, %f20 |
| 1451 | fadds %f16, %f17, %f16 |
| 1452 | ! preparing store val #1, next val will be in f21 |
| 1453 | fmovs %f16, %f21 |
| 1454 | fadds %f16, %f17, %f16 |
| 1455 | stq %f20, [%i1 + 80] |
| 1456 | |
| 1457 | P11: !_PREFETCH [12] (Int) |
| 1458 | sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 |
| 1459 | add %i0, %i2, %i2 |
| 1460 | prefetch [%i2 + 0], 1 |
| 1461 | |
| 1462 | P12: !_QWST [13] (maybe <- 0x3f800009) (FP) |
| 1463 | ! preparing store val #0, next val will be in f20 |
| 1464 | fmovs %f16, %f20 |
| 1465 | fadds %f16, %f17, %f16 |
| 1466 | stq %f20, [%i2 + 64] |
| 1467 | |
| 1468 | P13: !_PREFETCH [2] (Int) (Branch target of P48) |
| 1469 | prefetch [%i0 + 12], 1 |
| 1470 | ba P14 |
| 1471 | nop |
| 1472 | |
| 1473 | TARGET48: |
| 1474 | ba RET48 |
| 1475 | nop |
| 1476 | |
| 1477 | |
| 1478 | P14: !_PREFETCH [5] (Int) |
| 1479 | prefetch [%i1 + 76], 1 |
| 1480 | |
| 1481 | P15: !_PREFETCH [5] (Int) |
| 1482 | prefetch [%i1 + 76], 1 |
| 1483 | |
| 1484 | P16: !_QWST [7] (maybe <- 0x3f80000a) (FP) |
| 1485 | ! preparing store val #0, next val will be in f20 |
| 1486 | fmovs %f16, %f20 |
| 1487 | fadds %f16, %f17, %f16 |
| 1488 | ! preparing store val #1, next val will be in f21 |
| 1489 | fmovs %f16, %f21 |
| 1490 | fadds %f16, %f17, %f16 |
| 1491 | stq %f20, [%i1 + 80] |
| 1492 | |
| 1493 | P17: !_PREFETCH [11] (Int) (Loop exit) |
| 1494 | sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 |
| 1495 | add %i0, %i3, %i3 |
| 1496 | prefetch [%i3 + 64], 1 |
| 1497 | loop_exit_0_2: |
| 1498 | sub %l2, 1, %l2 |
| 1499 | cmp %l2, 0 |
| 1500 | bg loop_entry_0_2 |
| 1501 | nop |
| 1502 | |
| 1503 | P18: !_QWST [0] (maybe <- 0x3f80000c) (FP) (Loop entry) |
| 1504 | sethi %hi(0x2), %l2 |
| 1505 | or %l2, %lo(0x2), %l2 |
| 1506 | loop_entry_0_3: |
| 1507 | ! preparing store val #0, next val will be in f20 |
| 1508 | fmovs %f16, %f20 |
| 1509 | fadds %f16, %f17, %f16 |
| 1510 | ! preparing store val #1, next val will be in f21 |
| 1511 | fmovs %f16, %f21 |
| 1512 | fadds %f16, %f17, %f16 |
| 1513 | ! preparing store val #2, next val will be in f23 |
| 1514 | fmovs %f16, %f23 |
| 1515 | fadds %f16, %f17, %f16 |
| 1516 | stq %f20, [%i0 + 0] |
| 1517 | |
| 1518 | P19: !_QWST [12] (maybe <- 0x3f80000f) (FP) |
| 1519 | sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 |
| 1520 | add %i0, %i2, %i2 |
| 1521 | ! preparing store val #0, next val will be in f20 |
| 1522 | fmovs %f16, %f20 |
| 1523 | fadds %f16, %f17, %f16 |
| 1524 | stq %f20, [%i2 + 0] |
| 1525 | |
| 1526 | P20: !_PREFETCH [7] (Int) |
| 1527 | prefetch [%i1 + 84], 1 |
| 1528 | |
| 1529 | P21: !_QWST [15] (maybe <- 0x3f800010) (FP) |
| 1530 | ! preparing store val #0, next val will be in f20 |
| 1531 | fmovs %f16, %f20 |
| 1532 | fadds %f16, %f17, %f16 |
| 1533 | stq %f20, [%i2 + 192] |
| 1534 | |
| 1535 | P22: !_PREFETCH [0] (Int) |
| 1536 | prefetch [%i0 + 0], 1 |
| 1537 | |
| 1538 | P23: !_PREFETCH [4] (Int) |
| 1539 | prefetch [%i0 + 64], 1 |
| 1540 | |
| 1541 | P24: !_PREFETCH [15] (Int) |
| 1542 | prefetch [%i2 + 192], 1 |
| 1543 | |
| 1544 | P25: !_PREFETCH [1] (Int) |
| 1545 | prefetch [%i0 + 4], 1 |
| 1546 | |
| 1547 | P26: !_QWST [3] (maybe <- 0x3f800011) (FP) (Loop exit) (Branch target of P78) |
| 1548 | ! preparing store val #0, next val will be in f20 |
| 1549 | fmovs %f16, %f20 |
| 1550 | fadds %f16, %f17, %f16 |
| 1551 | stq %f20, [%i0 + 32] |
| 1552 | loop_exit_0_3: |
| 1553 | sub %l2, 1, %l2 |
| 1554 | cmp %l2, 0 |
| 1555 | bg loop_entry_0_3 |
| 1556 | nop |
| 1557 | ba P27 |
| 1558 | nop |
| 1559 | |
| 1560 | TARGET78: |
| 1561 | ba RET78 |
| 1562 | nop |
| 1563 | |
| 1564 | |
| 1565 | P27: !_QWST [5] (maybe <- 0x3f800012) (FP) (Loop entry) |
| 1566 | sethi %hi(0x1), %l2 |
| 1567 | or %l2, %lo(0x1), %l2 |
| 1568 | loop_entry_0_4: |
| 1569 | ! preparing store val #0, next val will be in f23 |
| 1570 | fmovs %f16, %f23 |
| 1571 | fadds %f16, %f17, %f16 |
| 1572 | stq %f20, [%i1 + 64] |
| 1573 | |
| 1574 | P28: !_QWST [0] (maybe <- 0x3f800013) (FP) |
| 1575 | ! preparing store val #0, next val will be in f20 |
| 1576 | fmovs %f16, %f20 |
| 1577 | fadds %f16, %f17, %f16 |
| 1578 | ! preparing store val #1, next val will be in f21 |
| 1579 | fmovs %f16, %f21 |
| 1580 | fadds %f16, %f17, %f16 |
| 1581 | ! preparing store val #2, next val will be in f23 |
| 1582 | fmovs %f16, %f23 |
| 1583 | fadds %f16, %f17, %f16 |
| 1584 | stq %f20, [%i0 + 0] |
| 1585 | |
| 1586 | P29: !_QWST [12] (maybe <- 0x3f800016) (FP) |
| 1587 | sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 |
| 1588 | add %i0, %i3, %i3 |
| 1589 | ! preparing store val #0, next val will be in f20 |
| 1590 | fmovs %f16, %f20 |
| 1591 | fadds %f16, %f17, %f16 |
| 1592 | stq %f20, [%i3 + 0] |
| 1593 | |
| 1594 | P30: !_LD [14] (Int) |
| 1595 | lduw [%i3 + 128], %o0 |
| 1596 | ! move %o0(lower) -> %o0(upper) |
| 1597 | sllx %o0, 32, %o0 |
| 1598 | |
| 1599 | P31: !_PREFETCH [1] (Int) |
| 1600 | prefetch [%i0 + 4], 1 |
| 1601 | |
| 1602 | P32: !_PREFETCH [14] (Int) |
| 1603 | prefetch [%i3 + 128], 1 |
| 1604 | |
| 1605 | P33: !_PREFETCH [14] (Int) |
| 1606 | prefetch [%i3 + 128], 1 |
| 1607 | |
| 1608 | P34: !_QWST [7] (maybe <- 0x3f800017) (FP) |
| 1609 | ! preparing store val #0, next val will be in f20 |
| 1610 | fmovs %f16, %f20 |
| 1611 | fadds %f16, %f17, %f16 |
| 1612 | ! preparing store val #1, next val will be in f21 |
| 1613 | fmovs %f16, %f21 |
| 1614 | fadds %f16, %f17, %f16 |
| 1615 | stq %f20, [%i1 + 80] |
| 1616 | |
| 1617 | P35: !_REPLACEMENT [1] (Int) |
| 1618 | sethi %hi(REPLACEMENT0_ALIAS0_O-REGION0_ALIAS0_O), %i2 |
| 1619 | add %i0, %i2, %i2 |
| 1620 | sethi %hi(0x10000), %l7 |
| 1621 | ld [%i2+4], %l3 |
| 1622 | st %l3, [%i2+4] |
| 1623 | add %i2, %l7, %o5 |
| 1624 | ld [%o5+4], %l3 |
| 1625 | st %l3, [%o5+4] |
| 1626 | add %o5, %l7, %o5 |
| 1627 | ld [%o5+4], %l3 |
| 1628 | st %l3, [%o5+4] |
| 1629 | add %o5, %l7, %o5 |
| 1630 | ld [%o5+4], %l3 |
| 1631 | st %l3, [%o5+4] |
| 1632 | |
| 1633 | P36: !_PREFETCH [0] (Int) |
| 1634 | prefetch [%i0 + 0], 1 |
| 1635 | |
| 1636 | P37: !_QWST [3] (maybe <- 0x3f800019) (FP) |
| 1637 | ! preparing store val #0, next val will be in f20 |
| 1638 | fmovs %f16, %f20 |
| 1639 | fadds %f16, %f17, %f16 |
| 1640 | stq %f20, [%i0 + 32] |
| 1641 | |
| 1642 | P38: !_QWST [10] (maybe <- 0x3f80001a) (FP) |
| 1643 | sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i3 |
| 1644 | add %i0, %i3, %i3 |
| 1645 | ! preparing store val #0, next val will be in f20 |
| 1646 | fmovs %f16, %f20 |
| 1647 | fadds %f16, %f17, %f16 |
| 1648 | stq %f20, [%i3 + 32] |
| 1649 | |
| 1650 | P39: !_QWST [1] (maybe <- 0x3f80001b) (FP) |
| 1651 | ! preparing store val #0, next val will be in f20 |
| 1652 | fmovs %f16, %f20 |
| 1653 | fadds %f16, %f17, %f16 |
| 1654 | ! preparing store val #1, next val will be in f21 |
| 1655 | fmovs %f16, %f21 |
| 1656 | fadds %f16, %f17, %f16 |
| 1657 | ! preparing store val #2, next val will be in f23 |
| 1658 | fmovs %f16, %f23 |
| 1659 | fadds %f16, %f17, %f16 |
| 1660 | stq %f20, [%i0 + 0] |
| 1661 | |
| 1662 | P40: !_QWST [6] (maybe <- 0x3f80001e) (FP) |
| 1663 | ! preparing store val #0, next val will be in f20 |
| 1664 | fmovs %f16, %f20 |
| 1665 | fadds %f16, %f17, %f16 |
| 1666 | ! preparing store val #1, next val will be in f21 |
| 1667 | fmovs %f16, %f21 |
| 1668 | fadds %f16, %f17, %f16 |
| 1669 | stq %f20, [%i1 + 80] |
| 1670 | |
| 1671 | P41: !_LD [2] (Int) |
| 1672 | lduw [%i0 + 12], %l7 |
| 1673 | ! move %l7(lower) -> %o0(lower) |
| 1674 | or %l7, %o0, %o0 |
| 1675 | |
| 1676 | P42: !_LD [2] (Int) |
| 1677 | lduw [%i0 + 12], %o1 |
| 1678 | ! move %o1(lower) -> %o1(upper) |
| 1679 | sllx %o1, 32, %o1 |
| 1680 | |
| 1681 | P43: !_LD [9] (Int) |
| 1682 | lduw [%i1 + 512], %l7 |
| 1683 | ! move %l7(lower) -> %o1(lower) |
| 1684 | or %l7, %o1, %o1 |
| 1685 | |
| 1686 | P44: !_LD [9] (Int) |
| 1687 | lduw [%i1 + 512], %o2 |
| 1688 | ! move %o2(lower) -> %o2(upper) |
| 1689 | sllx %o2, 32, %o2 |
| 1690 | |
| 1691 | P45: !_LD [0] (Int) |
| 1692 | lduw [%i0 + 0], %l7 |
| 1693 | ! move %l7(lower) -> %o2(lower) |
| 1694 | or %l7, %o2, %o2 |
| 1695 | |
| 1696 | P46: !_LD [13] (Int) |
| 1697 | sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i2 |
| 1698 | add %i0, %i2, %i2 |
| 1699 | lduw [%i2 + 64], %o3 |
| 1700 | ! move %o3(lower) -> %o3(upper) |
| 1701 | sllx %o3, 32, %o3 |
| 1702 | |
| 1703 | P47: !_LD [15] (Int) |
| 1704 | lduw [%i2 + 192], %l7 |
| 1705 | ! move %l7(lower) -> %o3(lower) |
| 1706 | or %l7, %o3, %o3 |
| 1707 | |
| 1708 | P48: !_LD [3] (Int) (CBR) |
| 1709 | lduw [%i0 + 32], %o4 |
| 1710 | ! move %o4(lower) -> %o4(upper) |
| 1711 | sllx %o4, 32, %o4 |
| 1712 | |
| 1713 | ! cbranch |
| 1714 | andcc %l0, 1, %g0 |
| 1715 | be,pn %xcc, TARGET48 |
| 1716 | nop |
| 1717 | RET48: |
| 1718 | |
| 1719 | ! lfsr step begin |
| 1720 | srlx %l0, 1, %l6 |
| 1721 | xnor %l6, %l0, %l6 |
| 1722 | sllx %l6, 63, %l6 |
| 1723 | or %l6, %l0, %l0 |
| 1724 | srlx %l0, 1, %l0 |
| 1725 | |
| 1726 | |
| 1727 | P49: !_LD [6] (Int) (Loop exit) |
| 1728 | lduw [%i1 + 80], %o5 |
| 1729 | ! move %o5(lower) -> %o4(lower) |
| 1730 | or %o5, %o4, %o4 |
| 1731 | !---- flushing int results buffer---- |
| 1732 | mov %o0, %l5 |
| 1733 | mov %o1, %l5 |
| 1734 | mov %o2, %l5 |
| 1735 | mov %o3, %l5 |
| 1736 | mov %o4, %l5 |
| 1737 | loop_exit_0_4: |
| 1738 | sub %l2, 1, %l2 |
| 1739 | cmp %l2, 0 |
| 1740 | bg loop_entry_0_4 |
| 1741 | nop |
| 1742 | |
| 1743 | P50: !_QWST [3] (maybe <- 0x3f800020) (FP) (Loop entry) |
| 1744 | sethi %hi(0x1), %l2 |
| 1745 | or %l2, %lo(0x1), %l2 |
| 1746 | loop_entry_0_5: |
| 1747 | ! preparing store val #0, next val will be in f20 |
| 1748 | fmovs %f16, %f20 |
| 1749 | fadds %f16, %f17, %f16 |
| 1750 | stq %f20, [%i0 + 32] |
| 1751 | |
| 1752 | P51: !_LD [4] (Int) |
| 1753 | lduw [%i0 + 64], %o0 |
| 1754 | ! move %o0(lower) -> %o0(upper) |
| 1755 | sllx %o0, 32, %o0 |
| 1756 | |
| 1757 | P52: !_QWST [9] (maybe <- 0x3f800021) (FP) |
| 1758 | ! preparing store val #0, next val will be in f20 |
| 1759 | fmovs %f16, %f20 |
| 1760 | fadds %f16, %f17, %f16 |
| 1761 | stq %f20, [%i1 + 512] |
| 1762 | |
| 1763 | P53: !_QWST [3] (maybe <- 0x3f800022) (FP) |
| 1764 | ! preparing store val #0, next val will be in f20 |
| 1765 | fmovs %f16, %f20 |
| 1766 | fadds %f16, %f17, %f16 |
| 1767 | stq %f20, [%i0 + 32] |
| 1768 | |
| 1769 | P54: !_QWST [12] (maybe <- 0x3f800023) (FP) |
| 1770 | sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 |
| 1771 | add %i0, %i3, %i3 |
| 1772 | ! preparing store val #0, next val will be in f20 |
| 1773 | fmovs %f16, %f20 |
| 1774 | fadds %f16, %f17, %f16 |
| 1775 | stq %f20, [%i3 + 0] |
| 1776 | |
| 1777 | P55: !_PREFETCH [9] (Int) |
| 1778 | prefetch [%i1 + 512], 1 |
| 1779 | |
| 1780 | P56: !_LD [6] (Int) |
| 1781 | lduw [%i1 + 80], %l3 |
| 1782 | ! move %l3(lower) -> %o0(lower) |
| 1783 | or %l3, %o0, %o0 |
| 1784 | |
| 1785 | P57: !_LD [5] (Int) |
| 1786 | lduw [%i1 + 76], %o1 |
| 1787 | ! move %o1(lower) -> %o1(upper) |
| 1788 | sllx %o1, 32, %o1 |
| 1789 | |
| 1790 | P58: !_LD [10] (Int) |
| 1791 | sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 |
| 1792 | add %i0, %i2, %i2 |
| 1793 | lduw [%i2 + 32], %l3 |
| 1794 | ! move %l3(lower) -> %o1(lower) |
| 1795 | or %l3, %o1, %o1 |
| 1796 | |
| 1797 | P59: !_LD [8] (Int) (LE) |
| 1798 | wr %g0, 0x88, %asi |
| 1799 | lduwa [%i1 + 256] %asi, %o2 |
| 1800 | ! move %o2(lower) -> %o2(upper) |
| 1801 | sllx %o2, 32, %o2 |
| 1802 | |
| 1803 | P60: !_LD [15] (Int) |
| 1804 | lduw [%i3 + 192], %l3 |
| 1805 | ! move %l3(lower) -> %o2(lower) |
| 1806 | or %l3, %o2, %o2 |
| 1807 | |
| 1808 | P61: !_LD [9] (Int) |
| 1809 | lduw [%i1 + 512], %o3 |
| 1810 | ! move %o3(lower) -> %o3(upper) |
| 1811 | sllx %o3, 32, %o3 |
| 1812 | |
| 1813 | P62: !_LD [0] (Int) |
| 1814 | lduw [%i0 + 0], %l3 |
| 1815 | ! move %l3(lower) -> %o3(lower) |
| 1816 | or %l3, %o3, %o3 |
| 1817 | |
| 1818 | P63: !_LD [8] (Int) |
| 1819 | lduw [%i1 + 256], %o4 |
| 1820 | ! move %o4(lower) -> %o4(upper) |
| 1821 | sllx %o4, 32, %o4 |
| 1822 | |
| 1823 | P64: !_LD [0] (Int) (Loop exit) |
| 1824 | lduw [%i0 + 0], %l3 |
| 1825 | ! move %l3(lower) -> %o4(lower) |
| 1826 | or %l3, %o4, %o4 |
| 1827 | !---- flushing int results buffer---- |
| 1828 | mov %o0, %l5 |
| 1829 | mov %o1, %l5 |
| 1830 | mov %o2, %l5 |
| 1831 | mov %o3, %l5 |
| 1832 | mov %o4, %l5 |
| 1833 | loop_exit_0_5: |
| 1834 | sub %l2, 1, %l2 |
| 1835 | cmp %l2, 0 |
| 1836 | bg loop_entry_0_5 |
| 1837 | nop |
| 1838 | |
| 1839 | P65: !_PREFETCH [3] (Int) (Loop entry) |
| 1840 | sethi %hi(0x1), %l2 |
| 1841 | or %l2, %lo(0x1), %l2 |
| 1842 | loop_entry_0_6: |
| 1843 | prefetch [%i0 + 32], 1 |
| 1844 | |
| 1845 | P66: !_QWST [3] (maybe <- 0x3f800024) (FP) |
| 1846 | ! preparing store val #0, next val will be in f20 |
| 1847 | fmovs %f16, %f20 |
| 1848 | fadds %f16, %f17, %f16 |
| 1849 | stq %f20, [%i0 + 32] |
| 1850 | |
| 1851 | P67: !_QWST [14] (maybe <- 0x3f800025) (FP) (Loop exit) |
| 1852 | sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 |
| 1853 | add %i0, %i3, %i3 |
| 1854 | ! preparing store val #0, next val will be in f20 |
| 1855 | fmovs %f16, %f20 |
| 1856 | fadds %f16, %f17, %f16 |
| 1857 | stq %f20, [%i3 + 128] |
| 1858 | loop_exit_0_6: |
| 1859 | sub %l2, 1, %l2 |
| 1860 | cmp %l2, 0 |
| 1861 | bg loop_entry_0_6 |
| 1862 | nop |
| 1863 | |
| 1864 | P68: !_MEMBAR (Int) |
| 1865 | membar #StoreLoad |
| 1866 | |
| 1867 | P69: !_LD [0] (Int) |
| 1868 | lduw [%i0 + 0], %o0 |
| 1869 | ! move %o0(lower) -> %o0(upper) |
| 1870 | sllx %o0, 32, %o0 |
| 1871 | |
| 1872 | P70: !_LD [1] (Int) |
| 1873 | lduw [%i0 + 4], %l3 |
| 1874 | ! move %l3(lower) -> %o0(lower) |
| 1875 | or %l3, %o0, %o0 |
| 1876 | |
| 1877 | P71: !_LD [2] (Int) (LE) |
| 1878 | wr %g0, 0x88, %asi |
| 1879 | lduwa [%i0 + 12] %asi, %o1 |
| 1880 | ! move %o1(lower) -> %o1(upper) |
| 1881 | sllx %o1, 32, %o1 |
| 1882 | |
| 1883 | P72: !_LD [3] (FP) |
| 1884 | ld [%i0 + 32], %f0 |
| 1885 | ! 1 addresses covered |
| 1886 | |
| 1887 | P73: !_LD [4] (Int) |
| 1888 | lduw [%i0 + 64], %l3 |
| 1889 | ! move %l3(lower) -> %o1(lower) |
| 1890 | or %l3, %o1, %o1 |
| 1891 | |
| 1892 | P74: !_LD [5] (Int) |
| 1893 | lduw [%i1 + 76], %o2 |
| 1894 | ! move %o2(lower) -> %o2(upper) |
| 1895 | sllx %o2, 32, %o2 |
| 1896 | |
| 1897 | P75: !_LD [6] (FP) |
| 1898 | ld [%i1 + 80], %f1 |
| 1899 | ! 1 addresses covered |
| 1900 | |
| 1901 | P76: !_LD [7] (Int) |
| 1902 | lduw [%i1 + 84], %l3 |
| 1903 | ! move %l3(lower) -> %o2(lower) |
| 1904 | or %l3, %o2, %o2 |
| 1905 | |
| 1906 | P77: !_LD [8] (FP) |
| 1907 | ld [%i1 + 256], %f2 |
| 1908 | ! 1 addresses covered |
| 1909 | |
| 1910 | P78: !_LD [9] (Int) (CBR) |
| 1911 | lduw [%i1 + 512], %o3 |
| 1912 | ! move %o3(lower) -> %o3(upper) |
| 1913 | sllx %o3, 32, %o3 |
| 1914 | |
| 1915 | ! cbranch |
| 1916 | andcc %l0, 1, %g0 |
| 1917 | be,pn %xcc, TARGET78 |
| 1918 | nop |
| 1919 | RET78: |
| 1920 | |
| 1921 | ! lfsr step begin |
| 1922 | srlx %l0, 1, %o5 |
| 1923 | xnor %o5, %l0, %o5 |
| 1924 | sllx %o5, 63, %o5 |
| 1925 | or %o5, %l0, %l0 |
| 1926 | srlx %l0, 1, %l0 |
| 1927 | |
| 1928 | |
| 1929 | P79: !_LD [10] (Int) |
| 1930 | sethi %hi(REGION2_ALIAS0_O-REGION0_ALIAS0_O), %i2 |
| 1931 | add %i0, %i2, %i2 |
| 1932 | lduw [%i2 + 32], %l6 |
| 1933 | ! move %l6(lower) -> %o3(lower) |
| 1934 | or %l6, %o3, %o3 |
| 1935 | |
| 1936 | P80: !_LD [11] (Int) |
| 1937 | lduw [%i2 + 64], %o4 |
| 1938 | ! move %o4(lower) -> %o4(upper) |
| 1939 | sllx %o4, 32, %o4 |
| 1940 | |
| 1941 | P81: !_LD [12] (Int) |
| 1942 | sethi %hi(REGION3_ALIAS0_O-REGION0_ALIAS0_O), %i3 |
| 1943 | add %i0, %i3, %i3 |
| 1944 | lduw [%i3 + 0], %l6 |
| 1945 | ! move %l6(lower) -> %o4(lower) |
| 1946 | or %l6, %o4, %o4 |
| 1947 | !---- flushing int results buffer---- |
| 1948 | mov %o0, %l5 |
| 1949 | mov %o1, %l5 |
| 1950 | mov %o2, %l5 |
| 1951 | mov %o3, %l5 |
| 1952 | mov %o4, %l5 |
| 1953 | |
| 1954 | P82: !_LD [13] (Int) |
| 1955 | lduw [%i3 + 64], %o0 |
| 1956 | ! move %o0(lower) -> %o0(upper) |
| 1957 | sllx %o0, 32, %o0 |
| 1958 | |
| 1959 | P83: !_LD [14] (Int) |
| 1960 | lduw [%i3 + 128], %l6 |
| 1961 | ! move %l6(lower) -> %o0(lower) |
| 1962 | or %l6, %o0, %o0 |
| 1963 | |
| 1964 | P84: !_LD [15] (Int) |
| 1965 | lduw [%i3 + 192], %o1 |
| 1966 | ! move %o1(lower) -> %o1(upper) |
| 1967 | sllx %o1, 32, %o1 |
| 1968 | |
| 1969 | END_NODES0: ! Test istream for CPU 0 ends |
| 1970 | sethi %hi(0xdead0e0f), %l3 |
| 1971 | or %l3, %lo(0xdead0e0f), %l3 |
| 1972 | ! move %l3(lower) -> %o1(lower) |
| 1973 | or %l3, %o1, %o1 |
| 1974 | stw %l3, [%i5] |
| 1975 | ld [%i5], %f3 |
| 1976 | !---- flushing int results buffer---- |
| 1977 | mov %o0, %l5 |
| 1978 | mov %o1, %l5 |
| 1979 | !---- flushing fp results buffer to %f30 ---- |
| 1980 | fmovd %f0, %f30 |
| 1981 | fmovd %f2, %f30 |
| 1982 | |
| 1983 | restore |
| 1984 | retl |
| 1985 | nop |
| 1986 | tsotool_text_end: |
| 1987 | |
| 1988 | |
| 1989 | !#0 N1 P1 QWST 6 0x3f800001 FP BE Pri |
| 1990 | !#0 N2 P1 QWST 7 0x3f800002 FP BE Pri |
| 1991 | !#A N1 N2 |
| 1992 | !#0 N7 P6 QWST 0 0x3f800003 FP BE Pri |
| 1993 | !#0 N8 P6 QWST 1 0x3f800004 FP BE Pri |
| 1994 | !#A N7 N8 |
| 1995 | !#0 N9 P6 QWST 2 0x3f800005 FP BE Pri |
| 1996 | !#0 N10 P7 QWST 12 0x3f800006 FP BE Pri |
| 1997 | !#0 N17 P6 QWST 0 0x3f800007 FP BE Pri |
| 1998 | !#0 N18 P6 QWST 1 0x3f800008 FP BE Pri |
| 1999 | !#A N17 N18 |
| 2000 | !#0 N19 P6 QWST 2 0x3f800009 FP BE Pri |
| 2001 | !#0 N20 P7 QWST 12 0x3f80000a FP BE Pri |
| 2002 | !#0 N23 P10 QWST 6 0x3f80000b FP BE Pri |
| 2003 | !#0 N24 P10 QWST 7 0x3f80000c FP BE Pri |
| 2004 | !#A N23 N24 |
| 2005 | !#0 N26 P12 QWST 13 0x3f80000d FP BE Pri |
| 2006 | !#0 N30 P16 QWST 6 0x3f80000e FP BE Pri |
| 2007 | !#0 N31 P16 QWST 7 0x3f80000f FP BE Pri |
| 2008 | !#A N30 N31 |
| 2009 | !#0 N33 P10 QWST 6 0x3f800010 FP BE Pri |
| 2010 | !#0 N34 P10 QWST 7 0x3f800011 FP BE Pri |
| 2011 | !#A N33 N34 |
| 2012 | !#0 N36 P12 QWST 13 0x3f800012 FP BE Pri |
| 2013 | !#0 N40 P16 QWST 6 0x3f800013 FP BE Pri |
| 2014 | !#0 N41 P16 QWST 7 0x3f800014 FP BE Pri |
| 2015 | !#A N40 N41 |
| 2016 | !#0 N43 P10 QWST 6 0x3f800015 FP BE Pri |
| 2017 | !#0 N44 P10 QWST 7 0x3f800016 FP BE Pri |
| 2018 | !#A N43 N44 |
| 2019 | !#0 N46 P12 QWST 13 0x3f800017 FP BE Pri |
| 2020 | !#0 N50 P16 QWST 6 0x3f800018 FP BE Pri |
| 2021 | !#0 N51 P16 QWST 7 0x3f800019 FP BE Pri |
| 2022 | !#A N50 N51 |
| 2023 | !#0 N53 P18 QWST 0 0x3f80001a FP BE Pri |
| 2024 | !#0 N54 P18 QWST 1 0x3f80001b FP BE Pri |
| 2025 | !#A N53 N54 |
| 2026 | !#0 N55 P18 QWST 2 0x3f80001c FP BE Pri |
| 2027 | !#0 N56 P19 QWST 12 0x3f80001d FP BE Pri |
| 2028 | !#0 N58 P21 QWST 15 0x3f80001e FP BE Pri |
| 2029 | !#0 N63 P26 QWST 3 0x3f80001f FP BE Pri |
| 2030 | !#0 N64 P18 QWST 0 0x3f800020 FP BE Pri |
| 2031 | !#0 N65 P18 QWST 1 0x3f800021 FP BE Pri |
| 2032 | !#A N64 N65 |
| 2033 | !#0 N66 P18 QWST 2 0x3f800022 FP BE Pri |
| 2034 | !#0 N67 P19 QWST 12 0x3f800023 FP BE Pri |
| 2035 | !#0 N69 P21 QWST 15 0x3f800024 FP BE Pri |
| 2036 | !#0 N74 P26 QWST 3 0x3f800025 FP BE Pri |
| 2037 | !#0 N75 P27 QWST 5 0x3f800026 FP BE Pri |
| 2038 | !#0 N76 P28 QWST 0 0x3f800027 FP BE Pri |
| 2039 | !#0 N77 P28 QWST 1 0x3f800028 FP BE Pri |
| 2040 | !#A N76 N77 |
| 2041 | !#0 N78 P28 QWST 2 0x3f800029 FP BE Pri |
| 2042 | !#0 N79 P29 QWST 12 0x3f80002a FP BE Pri |
| 2043 | !#0 N80 P30 LD 14 -1 Int BE Pri |
| 2044 | !#0 N84 P34 QWST 6 0x3f80002b FP BE Pri |
| 2045 | !#0 N85 P34 QWST 7 0x3f80002c FP BE Pri |
| 2046 | !#A N84 N85 |
| 2047 | !#0 N88 P37 QWST 3 0x3f80002d FP BE Pri |
| 2048 | !#0 N89 P38 QWST 10 0x3f80002e FP BE Pri |
| 2049 | !#0 N90 P39 QWST 0 0x3f80002f FP BE Pri |
| 2050 | !#0 N91 P39 QWST 1 0x3f800030 FP BE Pri |
| 2051 | !#A N90 N91 |
| 2052 | !#0 N92 P39 QWST 2 0x3f800031 FP BE Pri |
| 2053 | !#0 N93 P40 QWST 6 0x3f800032 FP BE Pri |
| 2054 | !#0 N94 P40 QWST 7 0x3f800033 FP BE Pri |
| 2055 | !#A N93 N94 |
| 2056 | !#0 N95 P41 LD 2 -1 Int BE Pri |
| 2057 | !#0 N96 P42 LD 2 -1 Int BE Pri |
| 2058 | !#0 N97 P43 LD 9 -1 Int BE Pri |
| 2059 | !#0 N98 P44 LD 9 -1 Int BE Pri |
| 2060 | !#0 N99 P45 LD 0 -1 Int BE Pri |
| 2061 | !#0 N100 P46 LD 13 -1 Int BE Pri |
| 2062 | !#0 N101 P47 LD 15 -1 Int BE Pri |
| 2063 | !#0 N102 P48 LD 3 -1 Int BE Pri |
| 2064 | !#0 N103 P49 LD 6 -1 Int BE Pri |
| 2065 | !#0 N104 P50 QWST 3 0x3f800034 FP BE Pri |
| 2066 | !#0 N105 P51 LD 4 -1 Int BE Pri |
| 2067 | !#0 N106 P52 QWST 9 0x3f800035 FP BE Pri |
| 2068 | !#0 N107 P53 QWST 3 0x3f800036 FP BE Pri |
| 2069 | !#0 N108 P54 QWST 12 0x3f800037 FP BE Pri |
| 2070 | !#0 N110 P56 LD 6 -1 Int BE Pri |
| 2071 | !#0 N111 P57 LD 5 -1 Int BE Pri |
| 2072 | !#0 N112 P58 LD 10 -1 Int BE Pri |
| 2073 | !#0 N113 P59 LD 8 -1 Int LE Pri |
| 2074 | !#0 N114 P60 LD 15 -1 Int BE Pri |
| 2075 | !#0 N115 P61 LD 9 -1 Int BE Pri |
| 2076 | !#0 N116 P62 LD 0 -1 Int BE Pri |
| 2077 | !#0 N117 P63 LD 8 -1 Int BE Pri |
| 2078 | !#0 N118 P64 LD 0 -1 Int BE Pri |
| 2079 | !#0 N120 P66 QWST 3 0x3f800038 FP BE Pri |
| 2080 | !#0 N121 P67 QWST 14 0x3f800039 FP BE Pri |
| 2081 | !#0 N122 P68 MEMBAR |
| 2082 | !#0 N123 P69 LD 0 -1 Int BE Pri |
| 2083 | !#0 N124 P70 LD 1 -1 Int BE Pri |
| 2084 | !#0 N125 P71 LD 2 -1 Int LE Pri |
| 2085 | !#0 N126 P72 LD 3 -1 FP BE Pri |
| 2086 | !#0 N127 P73 LD 4 -1 Int BE Pri |
| 2087 | !#0 N128 P74 LD 5 -1 Int BE Pri |
| 2088 | !#0 N129 P75 LD 6 -1 FP BE Pri |
| 2089 | !#0 N130 P76 LD 7 -1 Int BE Pri |
| 2090 | !#0 N131 P77 LD 8 -1 FP BE Pri |
| 2091 | !#0 N132 P78 LD 9 -1 Int BE Pri |
| 2092 | !#0 N133 P79 LD 10 -1 Int BE Pri |
| 2093 | !#0 N134 P80 LD 11 -1 Int BE Pri |
| 2094 | !#0 N135 P81 LD 12 -1 Int BE Pri |
| 2095 | !#0 N136 P82 LD 13 -1 Int BE Pri |
| 2096 | !#0 N137 P83 LD 14 -1 Int BE Pri |
| 2097 | !#0 N138 P84 LD 15 -1 Int BE Pri |