| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: err_mra_diag.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MY_HP_TEXT_PA 0x1050000000 |
| 39 | #define MY_HP_DATA_PA 0x1050001000 |
| 40 | |
| 41 | #define ASI_PRIMARY_CONTEXT_0 0x21 |
| 42 | #define ASI_ITLB_DATA_IN_REG 0x54 |
| 43 | #define ASI_DMMU_TAG_ACCESS 0x58 |
| 44 | #define ASI_DTLB_DATA_IN_REG 0x5c |
| 45 | #define ASI_DMMU_SFAR 0x58 |
| 46 | |
| 47 | |
| 48 | #define MY_USER_TEXT_VA000 0x7a000000 |
| 49 | #define MY_USER_TEXT_RA000 0x7b000000 |
| 50 | #define MY_USER_TEXT_PA000 0x107b000000 |
| 51 | #define MY_USER_TEXT_VA001 0x7a010000 |
| 52 | #define MY_USER_TEXT_RA001 0x7b010000 |
| 53 | #define MY_USER_TEXT_PA001 0x107b010000 |
| 54 | #define MY_USER_TEXT_VA002 0x7a020000 |
| 55 | #define MY_USER_TEXT_RA002 0x7b020000 |
| 56 | #define MY_USER_TEXT_PA002 0x107b020000 |
| 57 | #define MY_USER_TEXT_VA003 0x7a030000 |
| 58 | #define MY_USER_TEXT_RA003 0x7b030000 |
| 59 | #define MY_USER_TEXT_PA003 0x107b030000 |
| 60 | #define MY_USER_TEXT_VA004 0x7a040000 |
| 61 | #define MY_USER_TEXT_RA004 0x7b040000 |
| 62 | #define MY_USER_TEXT_PA004 0x107b040000 |
| 63 | #define MY_USER_TEXT_VA005 0x7a050000 |
| 64 | #define MY_USER_TEXT_RA005 0x7b050000 |
| 65 | #define MY_USER_TEXT_PA005 0x107b050000 |
| 66 | |
| 67 | #define MY_USER_DATA_VA000 0x6a000000 |
| 68 | #define MY_USER_DATA_RA000 0x6b000000 |
| 69 | #define MY_USER_DATA_PA000 0x106b000000 |
| 70 | #define MY_USER_DATA_VA001 0x6a010000 |
| 71 | #define MY_USER_DATA_RA001 0x6b010000 |
| 72 | #define MY_USER_DATA_PA001 0x106b010000 |
| 73 | #define MY_USER_DATA_VA002 0x6a020000 |
| 74 | #define MY_USER_DATA_RA002 0x6b020000 |
| 75 | #define MY_USER_DATA_PA002 0x106b020000 |
| 76 | #define MY_USER_DATA_VA003 0x6a030000 |
| 77 | #define MY_USER_DATA_RA003 0x6b030000 |
| 78 | #define MY_USER_DATA_PA003 0x106b030000 |
| 79 | #define MY_USER_DATA_VA004 0x6a040000 |
| 80 | #define MY_USER_DATA_RA004 0x6b040000 |
| 81 | #define MY_USER_DATA_PA004 0x106b040000 |
| 82 | #define MY_USER_DATA_VA005 0x6a050000 |
| 83 | #define MY_USER_DATA_RA005 0x6b050000 |
| 84 | #define MY_USER_DATA_PA005 0x106b050000 |
| 85 | |
| 86 | #define IMDU_ERR_EN 0xa0000000 |
| 87 | #define IMTU_ERR_EN 0x90000000 |
| 88 | #define DMDU_ERR_EN 0x88000000 |
| 89 | #define DMTU_ERR_EN 0x84000000 |
| 90 | #define IRCU_ERR_EN 0x82000000 |
| 91 | #define FRCU_ERR_EN 0x81000000 |
| 92 | #define SCAU_ERR_EN 0x80800000 |
| 93 | #define TCCU_ERR_EN 0x80400000 |
| 94 | #define TSAU_ERR_EN 0x80200000 |
| 95 | #define MRAU_ERR_EN 0x80100000 |
| 96 | #define STAU_ERR_EN 0x80080000 |
| 97 | #define STDU_ERR_EN 0x80020000 |
| 98 | |
| 99 | #define ASI_DESR 0x4c |
| 100 | #define ASI_DFESR 0x4c |
| 101 | #define DFESR_VA 0x8 |
| 102 | #define ASI_DSFSR 0x58 |
| 103 | #define ASI_ISFSR 0x50 |
| 104 | #define SFSR_VA 0x18 |
| 105 | #define ASI_SFAR 0x58 |
| 106 | #define SFAR_VA 0x20 |
| 107 | #define ASI_ERR_INJ 0x43 |
| 108 | #define ASI_CETER 0x4C |
| 109 | #define CETER_VA 0x18 |
| 110 | #define ASI_CERER 0x4C |
| 111 | #define CERER_VA 0x10 |
| 112 | |
| 113 | #define CERER_SBDPC 0x400 |
| 114 | #define CETER_DHCCE 0x1000000000000000 |
| 115 | #define CETER_DE 0x2000000000000000 |
| 116 | #define CETER_PSCCE 0x4000000000000000 |
| 117 | #define MRAU_ERR_TYPE 0x7 |
| 118 | |
| 119 | #define MAIN_PAGE_HV_ALSO |
| 120 | |
| 121 | #define My_HT0_Mem_Address_Not_Aligned_0x34 \ |
| 122 | add %g0, CERER_VA, %g3; \ |
| 123 | set SCAU_ERR_EN, %l1; \ |
| 124 | or %l1, %l2, %l1 ;\ |
| 125 | stxa %l1, [%g0]ASI_ERR_INJ;\ |
| 126 | done;nop |
| 127 | |
| 128 | #define H_HT0_Internal_Processor_Error_0x29 |
| 129 | #define SUN_H_HT0_Internal_Processor_Error_0x29 \ |
| 130 | ba INT_PROC_ERR_HANDLER; \ |
| 131 | nop;nop;nop;nop;nop;nop;nop |
| 132 | #include "hboot.s" |
| 133 | |
| 134 | /************************************************************************ |
| 135 | Test case: |
| 136 | ************************************************************************/ |
| 137 | |
| 138 | .text |
| 139 | .global main |
| 140 | |
| 141 | main: /* test begin */ |
| 142 | ta T_CHANGE_HPRIV |
| 143 | |
| 144 | !! set CERER.MRAU |
| 145 | setx 0x200000000, %g1, %o2 !! enable mra errs |
| 146 | add %g0, CERER_VA, %g3 !!g3 has cerer va |
| 147 | |
| 148 | stxa %o2, [%g3]ASI_CERER |
| 149 | |
| 150 | !! set CETER.PSCCE |
| 151 | setx CETER_PSCCE, %l0, %o2 |
| 152 | add %g0, CETER_VA, %g3 |
| 153 | stxa %o2, [%g3]ASI_CETER |
| 154 | |
| 155 | add %g0, 1, %l2 !! mask |
| 156 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %i1 |
| 157 | |
| 158 | !! Enable error injection |
| 159 | set MRAU_ERR_EN, %l1 |
| 160 | or %l1, %l2, %l1 ! set mask bit 0 to 1 |
| 161 | stxa %l1, [%g0]ASI_ERR_INJ |
| 162 | |
| 163 | mov %g0, %l1 |
| 164 | mov %g0, %l3 |
| 165 | mov %g0, %l4 |
| 166 | setx user_code_begin_000, %g1, %g2 |
| 167 | jmp %g2 |
| 168 | nop |
| 169 | EXIT_BAD |
| 170 | |
| 171 | /************************************************************************ |
| 172 | Test case data start |
| 173 | ************************************************************************/ |
| 174 | .data |
| 175 | .global user_data_start |
| 176 | user_data_start: |
| 177 | .word 0x12345678 |
| 178 | .word 0x9a9b9c9d |
| 179 | .word 0x00000000 |
| 180 | .word 0xffffffff |
| 181 | .word 0x12345678 |
| 182 | .word 0x9a9b9c9d |
| 183 | .word 0x00000000 |
| 184 | .word 0xffffffff |
| 185 | |
| 186 | !#*********************************************************************** |
| 187 | |
| 188 | SECTION .My_User_Section_4v000 TEXT_VA=MY_USER_TEXT_VA000, DATA_VA=MY_USER_DATA_VA000 |
| 189 | attr_text { |
| 190 | Name = .My_User_Section_4v000, |
| 191 | part_0_ctx_nonzero_tsb_config_2, |
| 192 | VA = MY_USER_TEXT_VA000, |
| 193 | RA = MY_USER_TEXT_RA000, |
| 194 | PA = ra2pa(MY_USER_TEXT_RA000, 0), |
| 195 | TTE_Context = PCONTEXT, |
| 196 | TTE_V = 1, |
| 197 | TTE_NFO = 0, |
| 198 | TTE_L = 0, |
| 199 | TTE_Soft = 0, |
| 200 | TTE_IE = 0, |
| 201 | TTE_E = 0, |
| 202 | TTE_CP = 1, |
| 203 | TTE_CV = 0, |
| 204 | TTE_P = 0, |
| 205 | TTE_EP = 1, |
| 206 | TTE_W = 0, |
| 207 | TTE_SW1 = 0, |
| 208 | TTE_SW0 = 0, |
| 209 | TTE_RSVD1 = 0, |
| 210 | TTE_Size = 0, |
| 211 | } |
| 212 | attr_text { |
| 213 | NAME = .My_User_Section_4v000, |
| 214 | hypervisor |
| 215 | } |
| 216 | !Inject error in all the registers of MRA in a loop. Inject error in register 0. |
| 217 | !Access that register to ensure error is detected. Do it for both ld and |
| 218 | !store accesses. |
| 219 | ! |
| 220 | .text |
| 221 | .global user_code_begin_000 |
| 222 | user_code_begin_000: |
| 223 | add %g0, 1, %l1 |
| 224 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i2 |
| 225 | stxa %i2, [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG |
| 226 | |
| 227 | mov %i2, %i3 |
| 228 | mov %i1, %i4 |
| 229 | brnz,a %l4, .+20 |
| 230 | stxa %g0, [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG !! The err handelr does a done |
| 231 | !! for store. With retry we will |
| 232 | !! end up in infinite loop as |
| 233 | !!err injection is on. |
| 234 | |
| 235 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2 !! err is precise |
| 236 | cmp %g2, %i2 |
| 237 | bne FAIL |
| 238 | brz %i0, FAIL |
| 239 | add %i1, 8, %i1 |
| 240 | and %i1, 0x8, %l5 |
| 241 | brz,a %l5, .+8 |
| 242 | add %l3, 1, %l3 !! inc l3 if bit 8 is zero. l3 has expected MRA index |
| 243 | cmp %i1, 0x48 |
| 244 | ble user_code_begin_000 |
| 245 | mov %g0, %i0 |
| 246 | |
| 247 | brnz %l4, .+24 |
| 248 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %i1 |
| 249 | mov %g0, %l3 |
| 250 | add %g0, 1, %l4 |
| 251 | ba user_code_begin_000 |
| 252 | nop |
| 253 | |
| 254 | add %g0, ASI_MMU_REAL_RANGE_0, %i1 |
| 255 | add %g0, 0x4, %l3 |
| 256 | mov %g0, %l4 |
| 257 | |
| 258 | CHK_RANGE_REG: |
| 259 | add %g0, 1, %l1 |
| 260 | ldxa [%i1]ASI_MMU_REAL_RANGE, %i2 |
| 261 | stxa %i2, [%i1]ASI_MMU_REAL_RANGE |
| 262 | mov %i2, %i3 |
| 263 | mov %i1, %i4 |
| 264 | brnz,a %l4, .+20 |
| 265 | stxa %g0, [%i1]ASI_MMU_REAL_RANGE |
| 266 | ldxa [%i1]ASI_MMU_REAL_RANGE, %g2 !! err is precise |
| 267 | cmp %g2, %i2 |
| 268 | bne FAIL |
| 269 | cmp %i0, %l1 |
| 270 | bne FAIL |
| 271 | mov %g0, %i0 |
| 272 | |
| 273 | add %i1, 8, %i1 |
| 274 | cmp %i1, 0x120 |
| 275 | ble CHK_RANGE_REG |
| 276 | add %l3, 1, %l3 |
| 277 | |
| 278 | brnz %l4, .+24 |
| 279 | add %g0, ASI_MMU_REAL_RANGE_0, %i1 |
| 280 | add %g0, 0x4, %l3 |
| 281 | add %g0, 1, %l4 |
| 282 | ba CHK_RANGE_REG |
| 283 | nop |
| 284 | |
| 285 | add %g0, ASI_MMU_PHYSICAL_OFFSET_0, %i1 |
| 286 | add %g0, 0x4, %l3 |
| 287 | mov %g0, %l4 |
| 288 | |
| 289 | CHK_PHY_OFFSET: |
| 290 | add %g0, 1, %l1 |
| 291 | ldxa [%i1]ASI_MMU_PHYSICAL_OFFSET, %i2 |
| 292 | stxa %i2, [%i1]ASI_MMU_PHYSICAL_OFFSET |
| 293 | mov %i2, %i3 |
| 294 | mov %i1, %i4 |
| 295 | brnz,a %l4, .+20 |
| 296 | stxa %g0, [%i1]ASI_MMU_PHYSICAL_OFFSET |
| 297 | ldxa [%i1]ASI_MMU_PHYSICAL_OFFSET, %g2 !! err is precise |
| 298 | cmp %g2, %i2 |
| 299 | bne FAIL |
| 300 | cmp %i0, %l1 |
| 301 | bne FAIL |
| 302 | mov %g0, %i0 |
| 303 | |
| 304 | add %i1, 8, %i1 |
| 305 | cmp %i1, 0x220 |
| 306 | ble CHK_PHY_OFFSET |
| 307 | add %l3, 1, %l3 |
| 308 | |
| 309 | brnz %l4, .+24 |
| 310 | add %g0, ASI_MMU_PHYSICAL_OFFSET_0, %i1 |
| 311 | add %g0, 0x4, %l3 |
| 312 | add %g0, 1, %l4 |
| 313 | ba CHK_PHY_OFFSET |
| 314 | nop |
| 315 | |
| 316 | /* |
| 317 | EXIT_GOOD |
| 318 | nop |
| 319 | */ |
| 320 | setx user_code_begin_001, %g1, %g2 |
| 321 | jmp %g2 |
| 322 | nop |
| 323 | |
| 324 | FAIL: |
| 325 | EXIT_BAD |
| 326 | |
| 327 | attr_data { |
| 328 | Name = .My_User_Section_4v000, |
| 329 | part_0_ctx_nonzero_tsb_config_1, |
| 330 | VA = MY_USER_DATA_VA000, |
| 331 | RA = MY_USER_DATA_RA000, |
| 332 | PA = ra2pa(MY_USER_DATA_RA000, 0), |
| 333 | TTE_Context = PCONTEXT, |
| 334 | TTE_V = 1, |
| 335 | TTE_NFO = 0, |
| 336 | TTE_L = 0, |
| 337 | TTE_Soft = 0, |
| 338 | TTE_IE = 0, |
| 339 | TTE_E = 0, |
| 340 | TTE_CP = 1, |
| 341 | TTE_CV = 0, |
| 342 | TTE_P = 0, |
| 343 | TTE_EP = 0, |
| 344 | TTE_W = 1, |
| 345 | TTE_SW1 = 0, |
| 346 | TTE_SW0 = 0, |
| 347 | TTE_RSVD1 = 0, |
| 348 | TTE_Size = 0, |
| 349 | } |
| 350 | attr_data { |
| 351 | NAME = .My_User_Section_4v000, |
| 352 | hypervisor |
| 353 | } |
| 354 | .data |
| 355 | .global user_data_begin_000 |
| 356 | user_data_begin_000: |
| 357 | .xword 0xe0066361bd9fcb86 |
| 358 | .xword 0xea22901c101f6f52 |
| 359 | .xword 0x806faa2171350467 |
| 360 | .xword 0xff54f2cd06a0d342 |
| 361 | .xword 0x566bff718cddb905 |
| 362 | .xword 0x6d367bc4d165d37a |
| 363 | .xword 0x5efc42b18f920522 |
| 364 | .xword 0x584c92dec4bc66de |
| 365 | |
| 366 | .xword 0xed9efe0d05896ce1 |
| 367 | |
| 368 | .xword 0xf9d45b94972117c8 |
| 369 | |
| 370 | .xword 0xd0c647618c9e43f3 |
| 371 | |
| 372 | .xword 0xfe04ead3b77c2d11 |
| 373 | |
| 374 | .xword 0x06d2d7f29e76397c |
| 375 | |
| 376 | .xword 0x234c366110eddd38 |
| 377 | |
| 378 | .xword 0xa80656d4288044bc |
| 379 | |
| 380 | .xword 0x12e763fbd8e2970d |
| 381 | |
| 382 | .xword 0x7320217fab3eae0e |
| 383 | |
| 384 | .xword 0x38683cebedefb5af |
| 385 | |
| 386 | |
| 387 | SECTION .My_User_Section_4v001 TEXT_VA=MY_USER_TEXT_VA001, DATA_VA=MY_USER_DATA_VA001 |
| 388 | attr_text { |
| 389 | Name = .My_User_Section_4v001, |
| 390 | part_0_ctx_nonzero_tsb_config_2, |
| 391 | VA = MY_USER_TEXT_VA001, |
| 392 | RA = MY_USER_TEXT_RA001, |
| 393 | PA = ra2pa(MY_USER_TEXT_RA001, 0), |
| 394 | TTE_Context = PCONTEXT, |
| 395 | TTE_V = 1, |
| 396 | TTE_NFO = 0, |
| 397 | TTE_L = 0, |
| 398 | TTE_Soft = 0, |
| 399 | TTE_IE = 0, |
| 400 | TTE_E = 0, |
| 401 | TTE_CP = 1, |
| 402 | TTE_CV = 0, |
| 403 | TTE_P = 0, |
| 404 | TTE_EP = 1, |
| 405 | TTE_W = 0, |
| 406 | TTE_SW1 = 0, |
| 407 | TTE_SW0 = 0, |
| 408 | TTE_RSVD1 = 0, |
| 409 | TTE_Size = 0, |
| 410 | } |
| 411 | attr_text { |
| 412 | NAME = .My_User_Section_4v001, |
| 413 | hypervisor |
| 414 | } |
| 415 | !! Each MRA entry has two registers. For eg. entry 0, has z_tsb_config_0 and z_tsb_config_1.!!Inject error in z_tsb_config_0 and access z_tsb_config_1. |
| 416 | |
| 417 | !! Then chk the above case for stores also. |
| 418 | !! Err is injected in register 1, do a store to regsiter 2 and ensure that the store |
| 419 | !! is not committed. |
| 420 | !! In case of stores, the trap handler ensures that the store is not committed and also |
| 421 | !! clears the error. |
| 422 | |
| 423 | .text |
| 424 | .global user_code_begin_001 |
| 425 | user_code_begin_001: |
| 426 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %i1 |
| 427 | mov %g0, %l3 |
| 428 | mov %g0, %l4 |
| 429 | |
| 430 | CHK_TSB_CFG_1: |
| 431 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i2 |
| 432 | add %i1, 8, %i4 |
| 433 | ldxa [%i4]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i3 |
| 434 | |
| 435 | stxa %i2, [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG |
| 436 | !! If l4 is 1 then chk the error with store, else it is with ld. |
| 437 | brnz,a %l4, .+20 |
| 438 | stxa %g0, [%i4]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG |
| 439 | ldxa [%i4]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2 !! err is precise |
| 440 | cmp %g2, %i3 |
| 441 | bne FAIL |
| 442 | |
| 443 | cmp %i0, %l1 |
| 444 | bne FAIL |
| 445 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2 |
| 446 | cmp %g2, %i2 |
| 447 | bne FAIL |
| 448 | |
| 449 | add %i1, 0x10, %i1 |
| 450 | add %l3, 1, %l3 !! inc l3 if bit 8 is zero. l3 has expected MRA index |
| 451 | cmp %i1, 0x40 |
| 452 | ble CHK_TSB_CFG_1 |
| 453 | mov %g0, %i0 |
| 454 | |
| 455 | brnz %l4, .+24 |
| 456 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %i1 |
| 457 | mov %g0, %l3 |
| 458 | add %g0, 1, %l4 |
| 459 | ba CHK_TSB_CFG_1 |
| 460 | nop |
| 461 | |
| 462 | add %g0, ASI_MMU_REAL_RANGE_0, %i1 |
| 463 | add %g0, 0x4, %l3 |
| 464 | mov %g0, %l4 |
| 465 | |
| 466 | CHK_RANGE_REG_1: |
| 467 | ldxa [%i1]ASI_MMU_REAL_RANGE, %i2 |
| 468 | add %i1, 0x100, %i4 !! g2 has phy offset register |
| 469 | ldxa [%i4]ASI_MMU_PHYSICAL_OFFSET, %i3 |
| 470 | stxa %i2, [%i1]ASI_MMU_REAL_RANGE |
| 471 | !! If l4 is 1 then chk the error with store, else it is with ld. |
| 472 | brnz,a %l4, .+20 |
| 473 | stxa %g0, [%i4]ASI_MMU_PHYSICAL_OFFSET |
| 474 | ldxa [%i4]ASI_MMU_PHYSICAL_OFFSET, %g2 !! err is precise |
| 475 | cmp %g2, %i3 |
| 476 | bne FAIL |
| 477 | |
| 478 | cmp %i0, %l1 |
| 479 | bne FAIL |
| 480 | mov %g0, %i0 |
| 481 | ldxa [%i1]ASI_MMU_REAL_RANGE, %g2 |
| 482 | cmp %g2, %i2 |
| 483 | bne FAIL |
| 484 | |
| 485 | add %i1, 8, %i1 |
| 486 | cmp %i1, 0x120 |
| 487 | ble CHK_RANGE_REG_1 |
| 488 | add %l3, 1, %l3 |
| 489 | |
| 490 | brnz %l4, .+24 |
| 491 | add %g0, ASI_MMU_REAL_RANGE_0, %i1 |
| 492 | add %g0, 0x4, %l3 |
| 493 | add %g0, 1, %l4 |
| 494 | ba CHK_RANGE_REG_1 |
| 495 | |
| 496 | setx user_code_begin_002, %g1, %g2 |
| 497 | jmp %g2 |
| 498 | nop |
| 499 | FAIL: |
| 500 | EXIT_BAD |
| 501 | nop |
| 502 | |
| 503 | attr_data { |
| 504 | Name = .My_User_Section_4v001, |
| 505 | part_0_ctx_nonzero_tsb_config_1, |
| 506 | VA = MY_USER_DATA_VA001, |
| 507 | RA = MY_USER_DATA_RA001, |
| 508 | PA = ra2pa(MY_USER_DATA_RA001, 0), |
| 509 | TTE_Context = PCONTEXT, |
| 510 | TTE_V = 1, |
| 511 | TTE_NFO = 0, |
| 512 | TTE_L = 0, |
| 513 | TTE_Soft = 0, |
| 514 | TTE_IE = 0, |
| 515 | TTE_E = 0, |
| 516 | TTE_CP = 1, |
| 517 | TTE_CV = 0, |
| 518 | TTE_P = 0, |
| 519 | TTE_EP = 0, |
| 520 | TTE_W = 1, |
| 521 | TTE_SW1 = 0, |
| 522 | TTE_SW0 = 0, |
| 523 | TTE_RSVD1 = 0, |
| 524 | TTE_Size = 0, |
| 525 | } |
| 526 | attr_data { |
| 527 | NAME = .My_User_Section_4v001, |
| 528 | hypervisor |
| 529 | } |
| 530 | .data |
| 531 | .global user_data_begin_001 |
| 532 | user_data_begin_001: |
| 533 | .xword 0xfa474991f13e3460 |
| 534 | .xword 0x1446415baecf3609 |
| 535 | .xword 0xe3215e901114ad4b |
| 536 | .xword 0xf91d897e92d1ee95 |
| 537 | .xword 0x33458a48805d888b |
| 538 | .xword 0x7f5a3ddb7d8e3c23 |
| 539 | .xword 0xaa80311fb1e17e79 |
| 540 | .xword 0x0f59d0e1ac35dbd4 |
| 541 | .xword 0x057c893bc8fc1e7e |
| 542 | .xword 0xcfb9e3a29c786cc0 |
| 543 | .xword 0x7257becb4609969e |
| 544 | .xword 0x4b1896677e83abae |
| 545 | .xword 0xc2e35a285574f037 |
| 546 | .xword 0x2e42eb5835020e2e |
| 547 | .xword 0x90775b99929f43cc |
| 548 | .xword 0x9fac4ae85a4ecd4e |
| 549 | |
| 550 | .word 0x10731 |
| 551 | .word 0xd027 |
| 552 | .word 0x1350e |
| 553 | .word 0x10e9d |
| 554 | |
| 555 | |
| 556 | SECTION .My_User_Section_4v002 TEXT_VA=MY_USER_TEXT_VA002, DATA_VA=MY_USER_DATA_VA002 |
| 557 | attr_text { |
| 558 | Name = .My_User_Section_4v002, |
| 559 | part_0_ctx_nonzero_tsb_config_2, |
| 560 | VA = MY_USER_TEXT_VA002, |
| 561 | RA = MY_USER_TEXT_RA002, |
| 562 | PA = ra2pa(MY_USER_TEXT_RA002, 0), |
| 563 | TTE_Context = PCONTEXT, |
| 564 | TTE_V = 1, |
| 565 | TTE_NFO = 0, |
| 566 | TTE_L = 0, |
| 567 | TTE_Soft = 0, |
| 568 | TTE_IE = 0, |
| 569 | TTE_E = 0, |
| 570 | TTE_CP = 1, |
| 571 | TTE_CV = 0, |
| 572 | TTE_P = 0, |
| 573 | TTE_EP = 1, |
| 574 | TTE_W = 0, |
| 575 | TTE_SW1 = 0, |
| 576 | TTE_SW0 = 0, |
| 577 | TTE_RSVD1 = 0, |
| 578 | TTE_Size = 0, |
| 579 | } |
| 580 | attr_text { |
| 581 | NAME = .My_User_Section_4v002, |
| 582 | hypervisor |
| 583 | } |
| 584 | !! Each MRA entry has two registers. For eg. entry 0, has z_tsb_config_0 and z_tsb_config_1.!!Inject error in z_tsb_config_1 and access z_tsb_config_0. |
| 585 | .text |
| 586 | .text |
| 587 | .global user_code_begin_002 |
| 588 | user_code_begin_002: |
| 589 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %i1 |
| 590 | add %i1, 8, %i1 |
| 591 | mov %g0, %l3 |
| 592 | mov %g0, %l4 |
| 593 | |
| 594 | CHK_TSB_CFG_2: |
| 595 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i2 |
| 596 | sub %i1, 8, %i4 |
| 597 | ldxa [%i4]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i3 |
| 598 | |
| 599 | stxa %i2, [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG |
| 600 | !! If l4 is 1 then chk the error with store, else it is with ld. |
| 601 | brnz,a %l4, .+20 |
| 602 | stxa %g0, [%i4]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG |
| 603 | ldxa [%i4]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2 !! err is precise |
| 604 | cmp %g2, %i3 |
| 605 | bne FAIL |
| 606 | cmp %i0, %l1 |
| 607 | bne FAIL |
| 608 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2 |
| 609 | cmp %g2, %i2 |
| 610 | bne FAIL |
| 611 | |
| 612 | add %i1, 0x10, %i1 |
| 613 | add %l3, 1, %l3 !! inc l3 if bit 8 is zero. l3 has expected MRA index |
| 614 | cmp %i1, 0x48 |
| 615 | ble CHK_TSB_CFG_2 |
| 616 | mov %g0, %i0 |
| 617 | |
| 618 | brnz %l4, .+28 |
| 619 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %i1 |
| 620 | add %i1, 8, %i1 |
| 621 | mov %g0, %l3 |
| 622 | add %g0, 1, %l4 |
| 623 | ba CHK_TSB_CFG_2 |
| 624 | nop |
| 625 | |
| 626 | add %g0, ASI_MMU_PHYSICAL_OFFSET_0, %i1 |
| 627 | add %g0, 0x4, %l3 |
| 628 | mov %g0, %l4 |
| 629 | |
| 630 | CHK_RANGE_REG_2: |
| 631 | ldxa [%i1]ASI_MMU_PHYSICAL_OFFSET, %i2 |
| 632 | sub %i1, 0x100, %i4 |
| 633 | ldxa [%i4]ASI_MMU_REAL_RANGE, %i3 |
| 634 | stxa %i2, [%i1]ASI_MMU_PHYSICAL_OFFSET |
| 635 | !! If l4 is 1 then chk the error with store, else it is with ld. |
| 636 | brnz,a %l4, .+20 |
| 637 | stxa %g0, [%i4]ASI_MMU_REAL_RANGE |
| 638 | ldxa [%i4]ASI_MMU_REAL_RANGE, %g2 !! err is precise |
| 639 | cmp %g2, %i3 |
| 640 | bne FAIL |
| 641 | cmp %i0, %l1 |
| 642 | bne FAIL |
| 643 | mov %g0, %i0 |
| 644 | ldxa [%i1]ASI_MMU_REAL_RANGE, %g2 |
| 645 | cmp %g2, %i2 |
| 646 | bne FAIL |
| 647 | |
| 648 | add %i1, 8, %i1 |
| 649 | cmp %i1, 0x220 |
| 650 | ble CHK_RANGE_REG_2 |
| 651 | add %l3, 1, %l3 |
| 652 | |
| 653 | brnz %l4, .+24 |
| 654 | add %g0, ASI_MMU_PHYSICAL_OFFSET_0, %i1 |
| 655 | add %g0, 0x4, %l3 |
| 656 | add %g0, 1, %l4 |
| 657 | ba CHK_RANGE_REG_2 |
| 658 | nop |
| 659 | |
| 660 | setx user_code_begin_003, %g1, %g2 |
| 661 | jmp %g2 |
| 662 | nop |
| 663 | |
| 664 | FAIL: |
| 665 | EXIT_BAD |
| 666 | nop |
| 667 | |
| 668 | attr_data { |
| 669 | Name = .My_User_Section_4v002, |
| 670 | part_0_ctx_nonzero_tsb_config_1, |
| 671 | VA = MY_USER_DATA_VA002, |
| 672 | RA = MY_USER_DATA_RA002, |
| 673 | PA = ra2pa(MY_USER_DATA_RA002, 0), |
| 674 | TTE_Context = PCONTEXT, |
| 675 | TTE_V = 1, |
| 676 | TTE_NFO = 0, |
| 677 | TTE_L = 0, |
| 678 | TTE_Soft = 0, |
| 679 | TTE_IE = 0, |
| 680 | TTE_E = 0, |
| 681 | TTE_CP = 1, |
| 682 | TTE_CV = 0, |
| 683 | TTE_P = 0, |
| 684 | TTE_EP = 0, |
| 685 | TTE_W = 1, |
| 686 | TTE_SW1 = 0, |
| 687 | TTE_SW0 = 0, |
| 688 | TTE_RSVD1 = 0, |
| 689 | TTE_Size = 0, |
| 690 | } |
| 691 | attr_data { |
| 692 | NAME = .My_User_Section_4v002, |
| 693 | hypervisor |
| 694 | } |
| 695 | .data |
| 696 | .global user_data_begin_002 |
| 697 | user_data_begin_002: |
| 698 | .xword 0x050a211e918857f3 |
| 699 | .xword 0x7980bbbf09b95bba |
| 700 | .xword 0x55f410e2b57433f6 |
| 701 | .xword 0x106c3aa95e2aa3c3 |
| 702 | .xword 0xbcb980bc1bb072d8 |
| 703 | .xword 0x63da435c10b717dd |
| 704 | .xword 0x375d99be87bef073 |
| 705 | .xword 0x03a5206ac6d08fd2 |
| 706 | .xword 0xfa474991f13e3460 |
| 707 | .xword 0x1446415baecf3609 |
| 708 | .xword 0xe3215e901114ad4b |
| 709 | .xword 0xf91d897e92d1ee95 |
| 710 | .xword 0x33458a48805d888b |
| 711 | .xword 0x7f5a3ddb7d8e3c23 |
| 712 | .xword 0xaa80311fb1e17e79 |
| 713 | .xword 0x0f59d0e1ac35dbd4 |
| 714 | |
| 715 | .word 0x1eb9 |
| 716 | .word 0x43ec |
| 717 | .word 0xc619 |
| 718 | .word 0x11a06 |
| 719 | |
| 720 | |
| 721 | SECTION .My_User_Section_4v003 TEXT_VA=MY_USER_TEXT_VA003, DATA_VA=MY_USER_DATA_VA003 |
| 722 | attr_text { |
| 723 | Name = .My_User_Section_4v003, |
| 724 | part_0_ctx_nonzero_tsb_config_2, |
| 725 | VA = MY_USER_TEXT_VA003, |
| 726 | RA = MY_USER_TEXT_RA003, |
| 727 | PA = ra2pa(MY_USER_TEXT_RA003, 0), |
| 728 | TTE_Context = PCONTEXT, |
| 729 | TTE_V = 1, |
| 730 | TTE_NFO = 0, |
| 731 | TTE_L = 0, |
| 732 | TTE_Soft = 0, |
| 733 | TTE_IE = 0, |
| 734 | TTE_E = 0, |
| 735 | TTE_CP = 1, |
| 736 | TTE_CV = 0, |
| 737 | TTE_P = 0, |
| 738 | TTE_EP = 1, |
| 739 | TTE_W = 0, |
| 740 | TTE_SW1 = 0, |
| 741 | TTE_SW0 = 0, |
| 742 | TTE_RSVD1 = 0, |
| 743 | TTE_Size = 0, |
| 744 | } |
| 745 | attr_text { |
| 746 | NAME = .My_User_Section_4v003, |
| 747 | hypervisor |
| 748 | } |
| 749 | !! Each MRA entry has two registers. For eg. entry 0, has z_tsb_config_0 and z_tsb_config_1.!! Inject err in register 0. access register 1. Go to trap handler and wr to register 1. |
| 750 | !! Check that the error is cleared in register 0 also. |
| 751 | !! Do the above thing for reverse case too. |
| 752 | |
| 753 | |
| 754 | !! Chk that err is inot detected if mrau is 0. |
| 755 | !! err is not dteceted in ceter.pscce is 0. |
| 756 | |
| 757 | .text |
| 758 | .global user_code_begin_003 |
| 759 | user_code_begin_003: |
| 760 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %i1 |
| 761 | add %i1, 8, %i1 |
| 762 | mov %g0, %l3 |
| 763 | mov %g0, %l4 |
| 764 | |
| 765 | CHK_TSB_CFG_3: |
| 766 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i2 |
| 767 | sub %i1, 8, %i4 |
| 768 | ldxa [%i4]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i3 |
| 769 | |
| 770 | stxa %i3, [%i4]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG !! err in entry 0. |
| 771 | ldxa [%i4]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2 !! read entry 0. |
| 772 | cmp %g2, %i3 |
| 773 | bne FAIL |
| 774 | cmp %i0, %l1 |
| 775 | bne FAIL |
| 776 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2 |
| 777 | cmp %g2, %i2 |
| 778 | bne FAIL |
| 779 | |
| 780 | add %i1, 0x10, %i1 |
| 781 | add %l3, 1, %l3 |
| 782 | cmp %i1, 0x48 |
| 783 | ble CHK_TSB_CFG_3 |
| 784 | mov %g0, %i0 |
| 785 | |
| 786 | add %g0, ASI_MMU_PHYSICAL_OFFSET_0, %i1 |
| 787 | add %g0, 0x4, %l3 |
| 788 | |
| 789 | CHK_RANGE_REG_3: |
| 790 | ldxa [%i1]ASI_MMU_PHYSICAL_OFFSET, %i2 |
| 791 | sub %i1, 0x100, %i4 |
| 792 | ldxa [%i4]ASI_MMU_REAL_RANGE, %i3 |
| 793 | stxa %i3, [%i4]ASI_MMU_REAL_RANGE |
| 794 | ldxa [%i4]ASI_MMU_REAL_RANGE, %g2 !! err is precise |
| 795 | cmp %g2, %i3 |
| 796 | bne FAIL |
| 797 | cmp %i0, %l1 |
| 798 | bne FAIL |
| 799 | mov %g0, %i0 |
| 800 | ldxa [%i1]ASI_MMU_PHYSICAL_OFFSET, %g2 |
| 801 | cmp %g2, %i2 |
| 802 | bne FAIL |
| 803 | |
| 804 | add %i1, 8, %i1 |
| 805 | cmp %i1, 0x220 |
| 806 | ble CHK_RANGE_REG_3 |
| 807 | add %l3, 1, %l3 |
| 808 | |
| 809 | !! Try the reverse case. |
| 810 | !! Inject err in register 1. access register 1. Go to trap handler and wr to register 0. |
| 811 | !! Check that the error is cleared in register 1 also. |
| 812 | !! Do the above thing for reverse case too. |
| 813 | |
| 814 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %i1 |
| 815 | add %g0, 0, %l3 |
| 816 | |
| 817 | CHK_TSB_CFG_4: |
| 818 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i2 |
| 819 | add %i1, 8, %i4 |
| 820 | ldxa [%i4]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i3 |
| 821 | |
| 822 | stxa %i3, [%i4]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG !! err in entry 1. |
| 823 | ldxa [%i4]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2 !! read entry 1. |
| 824 | cmp %g2, %i3 |
| 825 | bne FAIL |
| 826 | cmp %i0, %l1 |
| 827 | bne FAIL |
| 828 | mov %g0, %i0 |
| 829 | mov %g0, %l1 |
| 830 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2 |
| 831 | cmp %i0, %l1 !! chk trap is not taken here |
| 832 | bne FAIL |
| 833 | cmp %g2, %i2 |
| 834 | bne FAIL |
| 835 | |
| 836 | add %i1, 0x10, %i1 |
| 837 | add %l3, 1, %l3 |
| 838 | cmp %i1, 0x40 |
| 839 | ble CHK_TSB_CFG_4 |
| 840 | add %g0, 1, %l1 |
| 841 | |
| 842 | add %g0, ASI_MMU_REAL_RANGE_0, %i1 |
| 843 | add %g0, 0x4, %l3 |
| 844 | |
| 845 | CHK_RANGE_REG_4: |
| 846 | ldxa [%i1]ASI_MMU_REAL_RANGE, %i2 |
| 847 | add %i1, 0x100, %i4 |
| 848 | ldxa [%i4]ASI_MMU_PHYSICAL_OFFSET, %i3 |
| 849 | stxa %i3, [%i4]ASI_MMU_PHYSICAL_OFFSET |
| 850 | ldxa [%i4]ASI_MMU_PHYSICAL_OFFSET, %g2 !! err is precise |
| 851 | cmp %g2, %i3 |
| 852 | bne FAIL |
| 853 | cmp %i0, %l1 |
| 854 | bne FAIL |
| 855 | mov %g0, %i0 |
| 856 | mov %g0, %l1 |
| 857 | ldxa [%i1]ASI_MMU_REAL_RANGE, %g2 !no trap here. |
| 858 | cmp %i0, %l1 |
| 859 | bne FAIL |
| 860 | cmp %g2, %i2 |
| 861 | bne FAIL |
| 862 | |
| 863 | add %l3, 1, %l3 |
| 864 | add %i1, 8, %i1 |
| 865 | cmp %i1, 0x120 |
| 866 | ble CHK_RANGE_REG_4 |
| 867 | add %g0, 1, %l1 |
| 868 | |
| 869 | setx user_code_begin_004, %g1, %g2 |
| 870 | jmp %g2 |
| 871 | nop |
| 872 | |
| 873 | FAIL: |
| 874 | EXIT_BAD |
| 875 | nop |
| 876 | |
| 877 | attr_data { |
| 878 | Name = .My_User_Section_4v003, |
| 879 | part_0_ctx_nonzero_tsb_config_1, |
| 880 | VA = MY_USER_DATA_VA003, |
| 881 | RA = MY_USER_DATA_RA003, |
| 882 | PA = ra2pa(MY_USER_DATA_RA003, 0), |
| 883 | TTE_Context = PCONTEXT, |
| 884 | TTE_V = 1, |
| 885 | TTE_NFO = 0, |
| 886 | TTE_L = 0, |
| 887 | TTE_Soft = 0, |
| 888 | TTE_IE = 0, |
| 889 | TTE_E = 0, |
| 890 | TTE_CP = 1, |
| 891 | TTE_CV = 0, |
| 892 | TTE_P = 0, |
| 893 | TTE_EP = 0, |
| 894 | TTE_W = 1, |
| 895 | TTE_SW1 = 0, |
| 896 | TTE_SW0 = 0, |
| 897 | TTE_RSVD1 = 0, |
| 898 | TTE_Size = 0, |
| 899 | } |
| 900 | attr_data { |
| 901 | NAME = .My_User_Section_4v003, |
| 902 | hypervisor |
| 903 | } |
| 904 | .data |
| 905 | .global user_data_begin_003 |
| 906 | user_data_begin_003: |
| 907 | .xword 0xca12fd23b5b1b1d6 |
| 908 | .xword 0x3428a18f797bd42a |
| 909 | .xword 0x0d0630dd16ca2db5 |
| 910 | .xword 0x281c49cf3f51a83f |
| 911 | .xword 0x8fc66b8940c55c03 |
| 912 | .xword 0xfd6f2a2b60aee94c |
| 913 | .xword 0xec72846b0261894e |
| 914 | .xword 0xf1bd6c544120f822 |
| 915 | |
| 916 | .xword 0xefc4e1f1b35853fc |
| 917 | .xword 0xe790a0c1689eb683 |
| 918 | .xword 0x88c650f170c41710 |
| 919 | .xword 0x614126cf9fc8dca3 |
| 920 | .xword 0x4be2f60911e465ce |
| 921 | .xword 0x4e22352a0c29c95c |
| 922 | .xword 0xf18efdf01ce79e24 |
| 923 | .xword 0x294aaa56144d7cf1 |
| 924 | |
| 925 | .word 0xdfaa |
| 926 | .word 0x39a9 |
| 927 | .word 0xb967 |
| 928 | .word 0x280c |
| 929 | |
| 930 | |
| 931 | SECTION .My_User_Section_4v004 TEXT_VA=MY_USER_TEXT_VA004, DATA_VA=MY_USER_DATA_VA004 |
| 932 | attr_text { |
| 933 | Name = .My_User_Section_4v004, |
| 934 | part_0_ctx_nonzero_tsb_config_2, |
| 935 | VA = MY_USER_TEXT_VA004, |
| 936 | RA = MY_USER_TEXT_RA004, |
| 937 | PA = ra2pa(MY_USER_TEXT_RA004, 0), |
| 938 | TTE_Context = PCONTEXT, |
| 939 | TTE_V = 1, |
| 940 | TTE_NFO = 0, |
| 941 | TTE_L = 0, |
| 942 | TTE_Soft = 0, |
| 943 | TTE_IE = 0, |
| 944 | TTE_E = 0, |
| 945 | TTE_CP = 1, |
| 946 | TTE_CV = 0, |
| 947 | TTE_P = 0, |
| 948 | TTE_EP = 1, |
| 949 | TTE_W = 0, |
| 950 | TTE_SW1 = 0, |
| 951 | TTE_SW0 = 0, |
| 952 | TTE_RSVD1 = 0, |
| 953 | TTE_Size = 0, |
| 954 | } |
| 955 | attr_text { |
| 956 | NAME = .My_User_Section_4v004, |
| 957 | hypervisor |
| 958 | } |
| 959 | |
| 960 | !! Inject err in all the entries . Clear cerer.mrau. Chk trap is not taken, |
| 961 | !! Set cerer.mrau but set ceter.pscce, chk trap is not taken. |
| 962 | !! Now set both cerer and ceter bits and chk trap is taken. |
| 963 | !! Checks stores are committed if error detection is turned off |
| 964 | |
| 965 | |
| 966 | .text |
| 967 | .global user_code_begin_004 |
| 968 | user_code_begin_004: |
| 969 | setx user_data_begin_004, %g1, %g2 |
| 970 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %i1 |
| 971 | mov %g0, %l4 |
| 972 | mov %g0, %l3 |
| 973 | mov %g0, %o0 |
| 974 | |
| 975 | LD_TSB_CFG_5: |
| 976 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i2 |
| 977 | stxa %i2, [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG !err injected |
| 978 | stx %i2, [%g2 + %o0] !store data |
| 979 | |
| 980 | add %i1, 0x10, %i1 |
| 981 | cmp %i1, 0x40 |
| 982 | ble LD_TSB_CFG_5 |
| 983 | add %o0, 0x10, %o0 |
| 984 | |
| 985 | add %g0, ASI_MMU_REAL_RANGE_0, %i1 |
| 986 | add %g0, 0x4, %l3 |
| 987 | LD_RANGE_REG_5: |
| 988 | ldxa [%i1]ASI_MMU_REAL_RANGE, %i2 |
| 989 | stxa %i2, [%i1]ASI_MMU_REAL_RANGE |
| 990 | stx %i2, [%g2 + %o0] !store data |
| 991 | |
| 992 | add %i1, 8, %i1 |
| 993 | cmp %i1, 0x120 |
| 994 | ble LD_RANGE_REG_5 |
| 995 | add %o0, 0x10, %o0 |
| 996 | |
| 997 | !! now clear cerer.mrau. The err shd not be detected. |
| 998 | !! Access 2nd register in all the entries. WRite to 0. |
| 999 | |
| 1000 | add %g0, CERER_VA, %g3 |
| 1001 | stxa %g0, [%g3]ASI_CERER |
| 1002 | add %g0, 8, %o0 |
| 1003 | |
| 1004 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %i1 |
| 1005 | add %i1, 8, %i1 |
| 1006 | mov %g0, %l1 |
| 1007 | mov %g0, %i0 |
| 1008 | |
| 1009 | ST_TSB_CFG_5: |
| 1010 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i2 |
| 1011 | stx %i2, [%g2 + %o0] !store data |
| 1012 | stxa %g0, [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG |
| 1013 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i2 |
| 1014 | cmp %i2, %g0 ! store shd be committed |
| 1015 | bne FAIL |
| 1016 | |
| 1017 | cmp %i0, %l1 |
| 1018 | bne FAIL |
| 1019 | |
| 1020 | add %i1, 0x10, %i1 |
| 1021 | cmp %i1, 0x48 |
| 1022 | ble ST_TSB_CFG_5 |
| 1023 | add %o0, 0x10, %o0 |
| 1024 | |
| 1025 | add %g0, ASI_MMU_PHYSICAL_OFFSET_0, %i1 |
| 1026 | |
| 1027 | ST_RANGE_REG_5: |
| 1028 | ldxa [%i1]ASI_MMU_PHYSICAL_OFFSET, %i2 |
| 1029 | stx %i2, [%g2 + %o0] !store data |
| 1030 | stxa %g0, [%i1]ASI_MMU_PHYSICAL_OFFSET |
| 1031 | ldxa [%i1]ASI_MMU_PHYSICAL_OFFSET, %i2 |
| 1032 | cmp %i2, %g0 ! store shd be committed |
| 1033 | bne FAIL |
| 1034 | |
| 1035 | cmp %i0, %l1 |
| 1036 | bne FAIL |
| 1037 | |
| 1038 | add %i1, 0x8, %i1 |
| 1039 | cmp %i1, 0x220 |
| 1040 | ble ST_RANGE_REG_5 |
| 1041 | add %o0, 0x10, %o0 |
| 1042 | |
| 1043 | !! Now set cerer.mrau but clear ceter.pscce. Err shd not be detected. |
| 1044 | !! Access 1st register in all the entries. WRite to 0. |
| 1045 | |
| 1046 | setx 0x200000000, %g1, %o2 !! enable mra errs |
| 1047 | stxa %o2, [%g3]ASI_CERER |
| 1048 | |
| 1049 | !! clear CETER.PSCCE |
| 1050 | add %g0, CETER_VA, %g3 |
| 1051 | stxa %g3, [%g3]ASI_CETER |
| 1052 | |
| 1053 | |
| 1054 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %i1 |
| 1055 | mov %g0, %l1 |
| 1056 | mov %g0, %i0 |
| 1057 | |
| 1058 | ST_TSB_CFG_6: |
| 1059 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i2 |
| 1060 | stxa %g0, [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG |
| 1061 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %i2 |
| 1062 | cmp %i2, %g0 ! store shd be committed |
| 1063 | bne FAIL |
| 1064 | |
| 1065 | cmp %i0, %l1 |
| 1066 | bne FAIL |
| 1067 | |
| 1068 | add %i1, 0x10, %i1 |
| 1069 | cmp %i1, 0x40 |
| 1070 | ble ST_TSB_CFG_6 |
| 1071 | nop |
| 1072 | |
| 1073 | add %g0, ASI_MMU_REAL_RANGE_0, %i1 |
| 1074 | add %g0, 0x4, %l3 |
| 1075 | ST_RANGE_REG_6: |
| 1076 | ldxa [%i1]ASI_MMU_REAL_RANGE, %i2 |
| 1077 | stxa %g0, [%i1]ASI_MMU_REAL_RANGE |
| 1078 | ldxa [%i1]ASI_MMU_REAL_RANGE, %i2 |
| 1079 | cmp %i2, %g0 ! store shd be committed |
| 1080 | bne FAIL |
| 1081 | |
| 1082 | cmp %i0, %l1 |
| 1083 | bne FAIL |
| 1084 | |
| 1085 | add %i1, 0x8, %i1 |
| 1086 | cmp %i1, 0x120 |
| 1087 | ble ST_RANGE_REG_6 |
| 1088 | nop |
| 1089 | |
| 1090 | !! now set both the ceter and cerer bits and see error is detected. |
| 1091 | !! At this time all the MRA entries have errors, and contain 0. |
| 1092 | setx CETER_PSCCE, %l0, %o2 |
| 1093 | stxa %o2, [%g3]ASI_CETER |
| 1094 | |
| 1095 | add %g0, ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %i1 |
| 1096 | mov %g0, %l4 |
| 1097 | mov %g0, %o0 |
| 1098 | mov %g0, %l3 |
| 1099 | add %g0, 1, %l1 |
| 1100 | LD_TSB_CFG_6: |
| 1101 | mov %g0, %i2 |
| 1102 | add %i1, 8, %i4 |
| 1103 | mov %g0, %i3 !above 3 insts reqd. for the trap handler to work |
| 1104 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3 |
| 1105 | cmp %g3, 0 |
| 1106 | bne FAIL |
| 1107 | cmp %i0, %l1 |
| 1108 | bne FAIL |
| 1109 | mov %g0, %i0 |
| 1110 | |
| 1111 | add %i1, 0x10, %i1 |
| 1112 | cmp %i1, 0x40 |
| 1113 | ble LD_TSB_CFG_6 |
| 1114 | add %l3, 1, %l3 |
| 1115 | |
| 1116 | add %g0, ASI_MMU_REAL_RANGE_0, %i1 |
| 1117 | add %g0, 0x4, %l3 |
| 1118 | mov %g0, %l4 |
| 1119 | |
| 1120 | LD_RANGE_REG_6: |
| 1121 | mov %g0, %i2 |
| 1122 | add %i1, 0x100, %i4 |
| 1123 | mov %g0, %i3 |
| 1124 | stxa %i2, [%i1]ASI_MMU_REAL_RANGE |
| 1125 | cmp %i0, %l1 |
| 1126 | bne FAIL |
| 1127 | mov %g0, %i0 |
| 1128 | |
| 1129 | add %i1, 8, %i1 |
| 1130 | cmp %i1, 0x120 |
| 1131 | ble LD_RANGE_REG_6 |
| 1132 | add %l3, 1, %l3 |
| 1133 | |
| 1134 | EXIT_GOOD |
| 1135 | nop |
| 1136 | |
| 1137 | |
| 1138 | FAIL: EXIT_BAD |
| 1139 | nop |
| 1140 | |
| 1141 | attr_data { |
| 1142 | Name = .My_User_Section_4v004, |
| 1143 | part_0_ctx_nonzero_tsb_config_1, |
| 1144 | VA = MY_USER_DATA_VA004, |
| 1145 | RA = MY_USER_DATA_RA004, |
| 1146 | PA = ra2pa(MY_USER_DATA_RA004, 0), |
| 1147 | TTE_Context = PCONTEXT, |
| 1148 | TTE_V = 1, |
| 1149 | TTE_NFO = 0, |
| 1150 | TTE_L = 0, |
| 1151 | TTE_Soft = 0, |
| 1152 | TTE_IE = 0, |
| 1153 | TTE_E = 0, |
| 1154 | TTE_CP = 1, |
| 1155 | TTE_CV = 0, |
| 1156 | TTE_P = 0, |
| 1157 | TTE_EP = 0, |
| 1158 | TTE_W = 1, |
| 1159 | TTE_SW1 = 0, |
| 1160 | TTE_SW0 = 0, |
| 1161 | TTE_RSVD1 = 0, |
| 1162 | TTE_Size = 0, |
| 1163 | } |
| 1164 | attr_data { |
| 1165 | NAME = .My_User_Section_4v004, |
| 1166 | hypervisor |
| 1167 | } |
| 1168 | .data |
| 1169 | .global user_data_begin_004 |
| 1170 | user_data_begin_004: |
| 1171 | .xword 0xefc4e1f1b35853fc |
| 1172 | .xword 0xe790a0c1689eb683 |
| 1173 | .xword 0x88c650f170c41710 |
| 1174 | .xword 0x614126cf9fc8dca3 |
| 1175 | .xword 0x4be2f60911e465ce |
| 1176 | .xword 0x4e22352a0c29c95c |
| 1177 | .xword 0xf18efdf01ce79e24 |
| 1178 | .xword 0x294aaa56144d7cf1 |
| 1179 | .xword 0xe0066361bd9fcb86 |
| 1180 | .xword 0xea22901c101f6f52 |
| 1181 | .xword 0x806faa2171350467 |
| 1182 | .xword 0xff54f2cd06a0d342 |
| 1183 | .xword 0x566bff718cddb905 |
| 1184 | .xword 0x6d367bc4d165d37a |
| 1185 | .xword 0x5efc42b18f920522 |
| 1186 | .xword 0x584c92dec4bc66de |
| 1187 | .word 0x4069 |
| 1188 | .word 0x41ed |
| 1189 | .word 0x14c07 |
| 1190 | .word 0x29de |
| 1191 | |
| 1192 | |
| 1193 | SECTION .My_User_Section_4v005 TEXT_VA=MY_USER_TEXT_VA005, DATA_VA=MY_USER_DATA_VA005 |
| 1194 | attr_text { |
| 1195 | Name = .My_User_Section_4v005, |
| 1196 | part_0_ctx_nonzero_tsb_config_3, |
| 1197 | VA = MY_USER_TEXT_VA005, |
| 1198 | RA = MY_USER_TEXT_RA005, |
| 1199 | PA = ra2pa(MY_USER_TEXT_RA005, 0), |
| 1200 | TTE_Context = PCONTEXT, |
| 1201 | TTE_V = 1, |
| 1202 | TTE_NFO = 0, |
| 1203 | TTE_L = 0, |
| 1204 | TTE_Soft = 0, |
| 1205 | TTE_IE = 0, |
| 1206 | TTE_E = 0, |
| 1207 | TTE_CP = 1, |
| 1208 | TTE_CV = 0, |
| 1209 | TTE_P = 0, |
| 1210 | TTE_EP = 1, |
| 1211 | TTE_W = 0, |
| 1212 | TTE_SW1 = 0, |
| 1213 | TTE_SW0 = 0, |
| 1214 | TTE_RSVD1 = 0, |
| 1215 | TTE_Size = 0, |
| 1216 | } |
| 1217 | attr_text { |
| 1218 | NAME = .My_User_Section_4v005, |
| 1219 | hypervisor |
| 1220 | } |
| 1221 | .text |
| 1222 | .global user_code_begin_005 |
| 1223 | user_code_begin_005: |
| 1224 | |
| 1225 | add %g0, 1, %l3 |
| 1226 | |
| 1227 | |
| 1228 | attr_data { |
| 1229 | Name = .My_User_Section_4v005, |
| 1230 | part_0_ctx_nonzero_tsb_config_1, |
| 1231 | VA = MY_USER_DATA_VA005, |
| 1232 | RA = MY_USER_DATA_RA005, |
| 1233 | PA = ra2pa(MY_USER_DATA_RA005, 0), |
| 1234 | TTE_Context = PCONTEXT, |
| 1235 | TTE_V = 1, |
| 1236 | TTE_NFO = 0, |
| 1237 | TTE_L = 0, |
| 1238 | TTE_Soft = 0, |
| 1239 | TTE_IE = 0, |
| 1240 | TTE_E = 0, |
| 1241 | TTE_CP = 1, |
| 1242 | TTE_CV = 0, |
| 1243 | TTE_P = 0, |
| 1244 | TTE_EP = 0, |
| 1245 | TTE_W = 1, |
| 1246 | TTE_SW1 = 0, |
| 1247 | TTE_SW0 = 0, |
| 1248 | TTE_RSVD1 = 0, |
| 1249 | TTE_Size = 0, |
| 1250 | } |
| 1251 | attr_data { |
| 1252 | NAME = .My_User_Section_4v005, |
| 1253 | hypervisor |
| 1254 | } |
| 1255 | .data |
| 1256 | .global user_data_begin_005 |
| 1257 | user_data_begin_005: |
| 1258 | .xword 0xefc4e1f1b35853fc |
| 1259 | .xword 0xe790a0c1689eb683 |
| 1260 | .xword 0x88c650f170c41710 |
| 1261 | .xword 0x614126cf9fc8dca3 |
| 1262 | .xword 0x4be2f60911e465ce |
| 1263 | .xword 0x4e22352a0c29c95c |
| 1264 | .xword 0xf18efdf01ce79e24 |
| 1265 | .xword 0x294aaa56144d7cf1 |
| 1266 | .xword 0xe0066361bd9fcb86 |
| 1267 | .xword 0xea22901c101f6f52 |
| 1268 | .xword 0x806faa2171350467 |
| 1269 | .xword 0xff54f2cd06a0d342 |
| 1270 | .xword 0x566bff718cddb905 |
| 1271 | .xword 0x6d367bc4d165d37a |
| 1272 | .xword 0x5efc42b18f920522 |
| 1273 | .xword 0x4be2f60911e465ce |
| 1274 | .xword 0x4e22352a0c29c95c |
| 1275 | .xword 0xf18efdf01ce79e24 |
| 1276 | .word 0xf93b |
| 1277 | .word 0xe34b |
| 1278 | .word 0x127e6 |
| 1279 | .word 0xd915 |
| 1280 | |
| 1281 | .global INT_PROC_ERR_HANDLER |
| 1282 | |
| 1283 | SECTION .HTRAPS |
| 1284 | .text |
| 1285 | |
| 1286 | INT_PROC_ERR_HANDLER: |
| 1287 | CHK_ERR_TYP: |
| 1288 | add %g0, SFSR_VA, %g1 |
| 1289 | ldxa [%g1]ASI_DSFSR, %o1 !! read the DSFSR |
| 1290 | stxa %g0, [%g1]ASI_DSFSR !! clear the dsfsr |
| 1291 | and %o1, 0xF, %o1 |
| 1292 | cmp %o1, MRAU_ERR_TYPE |
| 1293 | bne FAIL |
| 1294 | CHK_INDEX: |
| 1295 | add %g0, SFAR_VA, %g1 |
| 1296 | ldxa [%g1]ASI_SFAR, %o1 !! read the DSFAR |
| 1297 | and %o1, 0x7, %o2 |
| 1298 | cmp %l3, %o2 !! l3 has the expected index |
| 1299 | bne FAIL |
| 1300 | |
| 1301 | TURN_OFF_ERR_INJ: |
| 1302 | !!turn off error |
| 1303 | stxa %g0, [%g0]ASI_ERR_INJ |
| 1304 | !! do a normal wr to clear the err |
| 1305 | |
| 1306 | TURN_OFF_ERR_DETECTION: |
| 1307 | add %g0, CERER_VA, %g3 |
| 1308 | stxa %g0, [%g3]ASI_CERER |
| 1309 | |
| 1310 | CLEAR_ERR: |
| 1311 | and %i1, 0x200, %o1 |
| 1312 | brz,a %o1, .+24 |
| 1313 | nop |
| 1314 | ldxa [%i1]ASI_MMU_PHYSICAL_OFFSET, %g4 |
| 1315 | ldxa [%i4]ASI_MMU_PHYSICAL_OFFSET, %g5 |
| 1316 | stxa %i2, [%i1]ASI_MMU_PHYSICAL_OFFSET |
| 1317 | ba ENABLE_ERR_INJ |
| 1318 | |
| 1319 | and %i1, 0x100, %o1 |
| 1320 | brz,a %o1, .+24 |
| 1321 | nop |
| 1322 | ldxa [%i1]ASI_MMU_REAL_RANGE, %g4 |
| 1323 | ldxa [%i4]ASI_MMU_REAL_RANGE, %g5 |
| 1324 | stxa %i2, [%i1]ASI_MMU_REAL_RANGE |
| 1325 | ba ENABLE_ERR_INJ |
| 1326 | nop |
| 1327 | |
| 1328 | ldxa [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g4 |
| 1329 | ldxa [%i4]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g5 |
| 1330 | stxa %i2, [%i1]ASI_MMU_ZERO_CONTEXT_TSB_CONFIG |
| 1331 | |
| 1332 | |
| 1333 | ENABLE_ERR_INJ: |
| 1334 | cmp %g4, %i2 |
| 1335 | bne FAIL |
| 1336 | cmp %g5, %i3 |
| 1337 | bne FAIL |
| 1338 | !! enable error injection |
| 1339 | set MRAU_ERR_EN, %g1 |
| 1340 | or %g1, %l2, %g1 ! set mask bit 0 to 1 |
| 1341 | stxa %g1, [%g0]ASI_ERR_INJ |
| 1342 | |
| 1343 | ENABLE_ERR_DETECTION: |
| 1344 | setx 0x200000000, %g1, %o2 !! enable mra errs |
| 1345 | stxa %o2, [%g3]ASI_CERER |
| 1346 | |
| 1347 | add %g0, 1, %i0 |
| 1348 | brz,a %l4, .+8 |
| 1349 | retry |
| 1350 | done ! in case of stxa, errors are corrected by trap handler so no need to do |
| 1351 | ! a retry. As doing a retry will write bogus data in MRA entry. |
| 1352 | |
| 1353 | PASS: EXIT_GOOD |
| 1354 | nop |
| 1355 | |
| 1356 | FAIL: EXIT_BAD |
| 1357 | nop |