| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: isa3_1215ivtrap2.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define PORTABLE_CORE |
| 39 | |
| 40 | #define MAIN_PAGE_HV_ALSO |
| 41 | #define MAIN_PAGE_NUCLEUS_ALSO |
| 42 | |
| 43 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 44 | !Override trap handler definitions |
| 45 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
| 46 | |
| 47 | #include "asi_s.h" |
| 48 | |
| 49 | ! Interrupt trap handler |
| 50 | ! Compare ASI_SWVR_INTR_R with %l1 (TID) |
| 51 | |
| 52 | #define H_HT0_Interrupt_0x60 |
| 53 | #define My_HT0_Interrupt_0x60 \ |
| 54 | ba trap_0x60_ext;\ |
| 55 | nop;nop;nop;nop;nop;nop;nop |
| 56 | |
| 57 | |
| 58 | #define THREAD_COUNT 8 |
| 59 | #define THREAD_STRIDE 1 |
| 60 | #include "hboot.s" |
| 61 | |
| 62 | /************************************************************************ |
| 63 | Test case code start |
| 64 | ************************************************************************/ |
| 65 | |
| 66 | .text |
| 67 | .global main |
| 68 | |
| 69 | main: /* test begin */ |
| 70 | |
| 71 | th_fork(main_t); |
| 72 | |
| 73 | EXIT_BAD |
| 74 | |
| 75 | main_t_0: |
| 76 | |
| 77 | ! signal that thread has gotten here (started). |
| 78 | mov 0xff, %g2 |
| 79 | setx user_data_start, %g1, %l7 |
| 80 | stb %g2, [%l7 + %o1] |
| 81 | |
| 82 | ! master waits for other threads to be ready |
| 83 | setx user_data_start, %g1, %l7 |
| 84 | master_waiting: |
| 85 | ldx [%l7], %g2 |
| 86 | cmp %g2, 0xffffffffffffffff |
| 87 | bne master_waiting |
| 88 | nop |
| 89 | |
| 90 | |
| 91 | ta T_CHANGE_HPRIV |
| 92 | |
| 93 | rdpr %pstate, %g1 |
| 94 | wrpr %g1, 2, %pstate |
| 95 | |
| 96 | park_threads: |
| 97 | ! Park all threads .. |
| 98 | mov 1, %g1 |
| 99 | mov 0x50, %g2 |
| 100 | stxa %g1,[%g2]0x41 |
| 101 | |
| 102 | ! Save %l2 = TID+1 |
| 103 | ! Save %l4 as expected receive vector |
| 104 | ! |
| 105 | add %o1,1, %l2 |
| 106 | mov 1, %g1 |
| 107 | sllx %g1, %l2, %l4 |
| 108 | |
| 109 | clear_intr_recv: |
| 110 | stxa %g0, [%g0] ASI_SWVR_INTR_RECEIVE |
| 111 | mov 7, %l1 ! TID |
| 112 | |
| 113 | gen_next_intr: |
| 114 | sllx %l1, 8, %l3 ! Send TID+1 as vector |
| 115 | or %l3, %l1, %l3 |
| 116 | inc %l3 |
| 117 | |
| 118 | send_int: |
| 119 | stxa %l3, [%g0] ASI_SWVR_INTR_W |
| 120 | brnz %l1, gen_next_intr |
| 121 | dec %l1 |
| 122 | |
| 123 | unpark_threads: |
| 124 | ! Unpark all threads .. |
| 125 | not %g0, %g1 |
| 126 | mov 0x50, %g2 |
| 127 | stxa %g1,[%g2]0x41 |
| 128 | |
| 129 | rdpr %pstate, %g1 |
| 130 | wrpr %g1, 2, %pstate |
| 131 | |
| 132 | mov 1000, %g1 |
| 133 | loop_wait_for_awhile: |
| 134 | bnz loop_wait_for_awhile |
| 135 | dec %g1 |
| 136 | |
| 137 | EXIT_BAD |
| 138 | |
| 139 | main_t_1: |
| 140 | main_t_2: |
| 141 | main_t_3: |
| 142 | main_t_4: |
| 143 | main_t_5: |
| 144 | main_t_6: |
| 145 | main_t_7: |
| 146 | |
| 147 | ! Save %l2 = TID+1 |
| 148 | ! Save %l4 as expected receive vector |
| 149 | add %o1,1, %l2 |
| 150 | mov 1, %g1 |
| 151 | sllx %g1, %l2, %l4 |
| 152 | |
| 153 | ! signal that thread has gotten here (started). |
| 154 | mov 0xff, %g2 |
| 155 | setx user_data_start, %g1, %l7 |
| 156 | stb %g2, [%l7 + %o1] |
| 157 | |
| 158 | loop_wait_for_int: |
| 159 | mov 0, %g1 |
| 160 | b loop_wait_for_int |
| 161 | add %g1, 1, %g1 |
| 162 | |
| 163 | |
| 164 | /************************************************************************ |
| 165 | Test case data start |
| 166 | ************************************************************************/ |
| 167 | .data |
| 168 | user_data_start: |
| 169 | .word 0xB52E8698 |
| 170 | .end |
| 171 | |
| 172 | |
| 173 | SECTION .HTRAPS |
| 174 | .text |
| 175 | |
| 176 | trap_0x60_ext: |
| 177 | ldxa [%g0] ASI_SWVR_INTR_RECEIVE, %g1 ;\ |
| 178 | cmp %g1, %l4 ;\ |
| 179 | tne T_BAD_TRAP ;\ |
| 180 | ldxa [%g0] ASI_SWVR_INTR_R, %g2 ;\ |
| 181 | cmp %g2, %l2 ;\ |
| 182 | tne T_BAD_TRAP ;\ |
| 183 | ldxa [%g0] ASI_SWVR_INTR_RECEIVE, %g1 ;\ |
| 184 | cmp %g1, %l4 ;\ |
| 185 | te T_BAD_TRAP ;\ |
| 186 | ta T_GOOD_TRAP; \ |
| 187 | nop; |
| 188 | |