| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: warm_rst_protect_chkr.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module warm_protect_chkr(); |
| 36 | |
| 37 | //RST |
| 38 | |
| 39 | reg wrm_rst_chk_off; |
| 40 | initial begin // { |
| 41 | if ($test$plusargs("WRM_PROTECT_CHK_OFF")) |
| 42 | wrm_rst_chk_off <= 1; |
| 43 | else |
| 44 | wrm_rst_chk_off <= 0; |
| 45 | end //} |
| 46 | |
| 47 | // 0in disable_checker wrm_rst_chk_off -name wrm_protect* |
| 48 | |
| 49 | /* 0in constant |
| 50 | -var `RST.rst_fsm_ctl.reset_source_q |
| 51 | -active (`RST.rst_wmr_protect ) |
| 52 | -clock `RST.ccu_rst_sys_clk |
| 53 | -name wrm_protect_rst_reset_source_q |
| 54 | -module rst |
| 55 | -group rst_chkr |
| 56 | */ |
| 57 | |
| 58 | /*Need to take care in directed diag 0in constant |
| 59 | -var `RST.rst_fsm_ctl.reset_gen_q |
| 60 | -active (`RST.rst_wmr_protect ) |
| 61 | -clock `RST.ccu_rst_sys_clk |
| 62 | -name wrm_protect_rst_reset_gen_q |
| 63 | -module rst |
| 64 | -group rst_chkr |
| 65 | */ |
| 66 | |
| 67 | /* 0in constant |
| 68 | -var `RST.rst_fsm_ctl.rset_stat_q |
| 69 | -active (`RST.rst_wmr_protect ) |
| 70 | -clock `RST.ccu_rst_sys_clk |
| 71 | -name wrm_protect_rst_rset_stat_q |
| 72 | -module rst |
| 73 | -group rst_chkr |
| 74 | */ |
| 75 | |
| 76 | /*Need to take care in directed diag 0in constant |
| 77 | -var `RST.rst_fsm_ctl.ssys_reset_q |
| 78 | -active (`RST.rst_wmr_protect ) |
| 79 | -clock `RST.ccu_rst_sys_clk |
| 80 | -name wrm_protect_rst_ssys_reset_q |
| 81 | -module rst |
| 82 | -group rst_chkr |
| 83 | */ |
| 84 | |
| 85 | // NCU |
| 86 | |
| 87 | /* 0in constant |
| 88 | -var `TOP.cpu.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_sernum |
| 89 | -active (`RST.rst_wmr_protect ) |
| 90 | -clock `RST.ccu_rst_sys_clk |
| 91 | -name wrm_protect_ncu_sernum |
| 92 | -module ncu |
| 93 | -group rst_chkr |
| 94 | */ |
| 95 | |
| 96 | /* 0in constant |
| 97 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_fusestat |
| 98 | -active (`RST.rst_wmr_protect ) |
| 99 | -clock `RST.ccu_rst_sys_clk |
| 100 | -name wrm_protect_ncu_fusestat |
| 101 | -module ncu |
| 102 | -group rst_chkr |
| 103 | */ |
| 104 | |
| 105 | /* 0in constant |
| 106 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_coreavail |
| 107 | -active (`RST.rst_wmr_protect ) |
| 108 | -clock `RST.ccu_rst_sys_clk |
| 109 | -name wrm_protect_ncu_coreavail |
| 110 | -module ncu |
| 111 | -group rst_chkr |
| 112 | */ |
| 113 | |
| 114 | /* 0in constant |
| 115 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_bankavail |
| 116 | -active (`RST.rst_wmr_protect ) |
| 117 | -clock `RST.ccu_rst_sys_clk |
| 118 | -name wrm_protect_ncu_bankavail |
| 119 | -module ncu |
| 120 | -group rst_chkr |
| 121 | */ |
| 122 | |
| 123 | /* 0in constant |
| 124 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_bank_en |
| 125 | -active (`RST.rst_wmr_protect ) |
| 126 | -clock `RST.ccu_rst_sys_clk |
| 127 | -name wrm_protect_ncu_bank_en |
| 128 | -module ncu |
| 129 | -group rst_chkr |
| 130 | */ |
| 131 | |
| 132 | |
| 133 | /* 0in constant |
| 134 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_l2idxhs_en |
| 135 | -active (`RST.rst_wmr_protect ) |
| 136 | -clock `RST.ccu_rst_sys_clk |
| 137 | -name wrm_protect_ncu_l2idxhs_en |
| 138 | -module ncu |
| 139 | -group rst_chkr |
| 140 | */ |
| 141 | |
| 142 | |
| 143 | /* 0in constant |
| 144 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_per |
| 145 | -active (`RST.rst_wmr_protect ) |
| 146 | -clock `RST.ccu_rst_sys_clk |
| 147 | -name wrm_protect_ncu_per |
| 148 | -module ncu |
| 149 | -group rst_chkr |
| 150 | */ |
| 151 | |
| 152 | /* 0in constant |
| 153 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_esr |
| 154 | -active (`RST.rst_wmr_protect ) |
| 155 | -clock `RST.ccu_rst_sys_clk |
| 156 | -name wrm_protect_ncu_esr |
| 157 | -module ncu |
| 158 | -group rst_chkr |
| 159 | */ |
| 160 | |
| 161 | /* 0in constant |
| 162 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_err_steering |
| 163 | -active (`RST.rst_wmr_protect ) |
| 164 | -clock `RST.ccu_rst_sys_clk |
| 165 | -name wrm_protect_ncu_creg_err_steering |
| 166 | -module ncu |
| 167 | -group rst_chkr |
| 168 | */ |
| 169 | |
| 170 | /* 0in constant |
| 171 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_ncusyn |
| 172 | -active (`RST.rst_wmr_protect ) |
| 173 | -clock `RST.ccu_rst_sys_clk |
| 174 | -name wrm_protect_ncu_creg_ncusyn |
| 175 | -module ncu |
| 176 | -group rst_chkr |
| 177 | */ |
| 178 | |
| 179 | /* 0in constant |
| 180 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_ncu_scksel |
| 181 | -active (`RST.rst_wmr_protect ) |
| 182 | -clock `RST.ccu_rst_sys_clk |
| 183 | -name wrm_protect_creg_ncu_scksel |
| 184 | -module ncu |
| 185 | -group rst_chkr |
| 186 | */ |
| 187 | |
| 188 | /* 0in constant |
| 189 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_siisyn |
| 190 | -active (`RST.rst_wmr_protect ) |
| 191 | -clock `RST.ccu_rst_sys_clk |
| 192 | -name wrm_protect_ncu_creg_siisyn |
| 193 | -module ncu |
| 194 | -group rst_chkr |
| 195 | */ |
| 196 | |
| 197 | /*Review path 0in constant |
| 198 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.asi_coreavail |
| 199 | -active (`RST.rst_wmr_protect ) |
| 200 | -clock `RST.ccu_rst_sys_clk |
| 201 | -name wrm_protect_ncu_asi_coreavail |
| 202 | -module ncu |
| 203 | -group rst_chkr |
| 204 | */ |
| 205 | |
| 206 | /*Review path 0in constant |
| 207 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.asi_core_enable |
| 208 | -active (`RST.rst_wmr_protect ) |
| 209 | -clock `RST.ccu_rst_sys_clk |
| 210 | -name wrm_protect_ncu_asi_core_enable |
| 211 | -module ncu |
| 212 | -group rst_chkr |
| 213 | */ |
| 214 | |
| 215 | /* 0in constant |
| 216 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_cmp_tick_enable |
| 217 | -active (`RST.rst_wmr_protect ) |
| 218 | -clock `RST.ccu_rst_sys_clk |
| 219 | -name wrm_protect_ncu_creg_cmp_tick_enable |
| 220 | -module ncu |
| 221 | -group rst_chkr |
| 222 | */ |
| 223 | |
| 224 | /* 0in constant |
| 225 | -var `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_wmr_vec_mask |
| 226 | -active (`RST.rst_wmr_protect ) |
| 227 | -clock `RST.ccu_rst_sys_clk |
| 228 | -name wrm_protect_ncu_creg_wmr_vec_mask |
| 229 | -module ncu |
| 230 | -group rst_chkr |
| 231 | */ |
| 232 | |
| 233 | // TCU |
| 234 | // MBIST Mode register |
| 235 | /* 0in constant |
| 236 | -var `CPU.tcu.mbist_ctl.csr_mbist_mode_reg.dout |
| 237 | -active (`RST.rst_wmr_protect ) |
| 238 | -clock `RST.ccu_rst_sys_clk |
| 239 | -name wrm_protect_tcu_mbist_mode_reg |
| 240 | -module tcu |
| 241 | -group rst_chkr |
| 242 | */ |
| 243 | |
| 244 | // MBIST bypass reg |
| 245 | /* 0in constant |
| 246 | -var `CPU.tcu.mbist_ctl.csr_mbist_bypass_reg.dout |
| 247 | -active (`RST.rst_wmr_protect ) |
| 248 | -clock `RST.ccu_rst_sys_clk |
| 249 | -name wrm_protect_tcu_lower_mbist_bypass_reg |
| 250 | -module tcu |
| 251 | -group rst_chkr |
| 252 | */ |
| 253 | |
| 254 | // MBIST RESULTS done/fail bit(2) |
| 255 | // Comment0in constant |
| 256 | // -var `CPU.tcu.mbist_ctl.mbist_done_fail_reg.dout |
| 257 | // -active (`RST.rst_wmr_protect ) |
| 258 | // -clock `RST.ccu_rst_sys_clk |
| 259 | // -name wrm_protect_tcu_mbist_done_fail |
| 260 | // -module tcu |
| 261 | // -group rst_chkr |
| 262 | |
| 263 | // MBIST done reg |
| 264 | // Comment0in constant |
| 265 | // -var `CPU.tcu.mbist_ctl.mbist_done_reg.dout |
| 266 | // -active (`RST.rst_wmr_protect ) |
| 267 | // -clock `RST.ccu_rst_sys_clk |
| 268 | // -name wrm_protect_tcu_lower_mbist_done_reg |
| 269 | // -module tcu |
| 270 | // -group rst_chkr |
| 271 | // |
| 272 | |
| 273 | // MBIST fail reg |
| 274 | // Comment0in constant |
| 275 | // -var `CPU.tcu.mbist_ctl.mbist_fail_reg.dout |
| 276 | // -active (`RST.rst_wmr_protect ) |
| 277 | // -clock `RST.ccu_rst_sys_clk |
| 278 | // -name wrm_protect_tcu_lower_mbist_fail_reg |
| 279 | // -module tcu |
| 280 | // -group rst_chkr |
| 281 | // |
| 282 | |
| 283 | // LBIST Mode reg |
| 284 | /* 0in constant |
| 285 | -var `CPU.tcu.mbist_ctl.csr_lbist_mode_reg.dout |
| 286 | -active (`RST.rst_wmr_protect ) |
| 287 | -clock `RST.ccu_rst_sys_clk |
| 288 | -name wrm_protect_tcu_lbist_mode_reg |
| 289 | -module tcu |
| 290 | -group rst_chkr |
| 291 | */ |
| 292 | |
| 293 | // LBIST bypass reg |
| 294 | /* 0in constant |
| 295 | -var `CPU.tcu.mbist_ctl.csr_lbist_bypass_reg.dout |
| 296 | -active (`RST.rst_wmr_protect ) |
| 297 | -clock `RST.ccu_rst_sys_clk |
| 298 | -name wrm_protect_tcu_lbist_bypass_reg |
| 299 | -module tcu |
| 300 | -group rst_chkr |
| 301 | */ |
| 302 | |
| 303 | /* LBIST done reg |
| 304 | 0in constant |
| 305 | -var `CPU.tcu.mbist_ctl.tcu_lb_tcu_done_reg.dout |
| 306 | -active (`RST.rst_wmr_protect ) |
| 307 | -clock `RST.ccu_rst_sys_clk |
| 308 | -name wrm_protect_tcu_lbist_done_reg |
| 309 | -module tcu |
| 310 | -group rst_chkr |
| 311 | */ |
| 312 | |
| 313 | // Debug control reg (DCR) |
| 314 | // comment0in constant |
| 315 | // -var `CPU.tcu.regs_ctl.dbg_ctl.dbg_tcudcr_reg.dout |
| 316 | // -active (`RST.rst_wmr_protect ) |
| 317 | // -clock `RST.ccu_rst_sys_clk |
| 318 | // -name wrm_protect_tcu_debug_ctrl_reg |
| 319 | // -module tcu |
| 320 | // -group rst_chkr |
| 321 | |
| 322 | /* Pulse TRIGOUT pin |
| 323 | 0in constant |
| 324 | -var `CPU.tcu.regs_ctl.dbg_ctl.dbg_trigout_reg.dout |
| 325 | -active (`RST.rst_wmr_protect ) |
| 326 | -clock `RST.ccu_rst_sys_clk |
| 327 | -name wrm_protect_tcu_pulse_trigout |
| 328 | -module tcu |
| 329 | -group rst_chkr |
| 330 | */ |
| 331 | |
| 332 | // peu enable for test config bus |
| 333 | /* 0in constant |
| 334 | -var `CPU.tcu.mbist_ctl.csr_peu_entestcfg_reg.dout |
| 335 | -active (`RST.rst_wmr_protect ) |
| 336 | -clock `RST.ccu_rst_sys_clk |
| 337 | -name wrm_protect_tcu_peu_test_config |
| 338 | -module tcu |
| 339 | -group rst_chkr |
| 340 | */ |
| 341 | |
| 342 | // CLKSTP_DELAY |
| 343 | /* 0in constant |
| 344 | -var `CPU.tcu.sigmux_ctl.tcusig_cntdly_reg.dout |
| 345 | -active (`RST.rst_wmr_protect ) |
| 346 | -clock `RST.ccu_rst_sys_clk |
| 347 | -name wrm_protect_tcu_cntdly |
| 348 | -module tcu |
| 349 | -group rst_chkr |
| 350 | */ |
| 351 | |
| 352 | // CYCLE_COUNTER |
| 353 | // Comment0in constant |
| 354 | // -var `CPU.tcu.regs_ctl.dbg_ctl.dbg_cyccnt_reg.dout |
| 355 | // -active (`RST.rst_wmr_protect ) |
| 356 | // -clock `RST.ccu_rst_sys_clk |
| 357 | // -name wrm_protect_tcu_cycle_cnt |
| 358 | // -module tcu |
| 359 | // -group rst_chkr |
| 360 | // Tom Z email dated Nov 28 2005 |
| 361 | |
| 362 | // DEBUG EVENT COUNTER |
| 363 | // Comment0in constant |
| 364 | // -var `CPU.tcu.regs_ctl.dbg_ctl.dbg_decnt_reg.dout |
| 365 | // -active (`RST.rst_wmr_protect ) |
| 366 | // -clock `RST.ccu_rst_sys_clk |
| 367 | // -name wrm_protect_tcu_dbg_event_cnt |
| 368 | // -module tcu |
| 369 | // -group rst_chkr |
| 370 | // |
| 371 | |
| 372 | // MBIST_START |
| 373 | // 0IN constant |
| 374 | // -var `CPU.tcu.mbist_ctl.csr_mbist_start_reg.dout |
| 375 | // -active (`RST.rst_wmr_protect ) |
| 376 | // -clock `RST.ccu_rst_sys_clk |
| 377 | // -name wrm_protect_tcu_mbist_start |
| 378 | // -module tcu |
| 379 | // -group rst_chkr |
| 380 | // Tom Z email SENT dated Nov 28 2005 |
| 381 | |
| 382 | // MBIST_ABORT |
| 383 | // Comment0in constant |
| 384 | // -var `CPU.tcu.mbist_ctl.csr_mbist_abort_reg.dout |
| 385 | // -active (`RST.rst_wmr_protect ) |
| 386 | // -clock `RST.ccu_rst_sys_clk |
| 387 | // -name wrm_protect_tcu_mbist_abort |
| 388 | // -module tcu |
| 389 | // -group rst_chkr |
| 390 | |
| 391 | // MBIST_START_WMR |
| 392 | // Comment0in constant |
| 393 | // -var `CPU.tcu.mbist_ctl.csr_mbist_start_wmr_reg.dout |
| 394 | // -active (`RST.rst_wmr_protect ) |
| 395 | // -clock `RST.ccu_rst_sys_clk |
| 396 | // -name wrm_protect_tcu_mbist_start_wmr |
| 397 | // -module tcu |
| 398 | // -group rst_chkr |
| 399 | |
| 400 | // LBIST_START |
| 401 | /* 0in constant |
| 402 | -var `CPU.tcu.mbist_ctl.csr_lbist_start_reg.dout |
| 403 | -active (`RST.rst_wmr_protect ) |
| 404 | -clock `RST.ccu_rst_sys_clk |
| 405 | -name wrm_protect_tcu_lbist_start |
| 406 | -module tcu |
| 407 | -group rst_chkr |
| 408 | */ |
| 409 | |
| 410 | // DB0 ...No Warm protect registers |
| 411 | //DB1 |
| 412 | |
| 413 | //N2 Debug Port configuration Register 0x86_0000_0000 |
| 414 | /* 0in constant |
| 415 | -var `CPU.dbg1.dbg1_csr.ff_dbg_config.dout |
| 416 | -active (`RST.rst_wmr_protect ) |
| 417 | -clock `RST.ccu_rst_sys_clk |
| 418 | -name wrm_protect_dbg1_debug_port_config |
| 419 | -module db1 |
| 420 | -group rst_chkr |
| 421 | */ |
| 422 | |
| 423 | |
| 424 | //N2 I/O Quiesce control register bits 1:0 0x86_0000_0008 |
| 425 | /* 0in constant |
| 426 | -var `CPU.dbg1.dbg1_csr.ff_io_quiesce.dout[0] |
| 427 | -active (`RST.rst_wmr_protect ) |
| 428 | -clock `RST.ccu_rst_sys_clk |
| 429 | -name wrm_protect_dbg1_io_quiesce_control_0 |
| 430 | -module db1 |
| 431 | -group rst_chkr |
| 432 | */ |
| 433 | |
| 434 | //N2 I/O Quiesce control register bits 1:0 0x86_0000_0008 |
| 435 | /* 0in constant |
| 436 | -var `CPU.dbg1.dbg1_csr.ff_io_quiesce.dout[1] |
| 437 | -active (`RST.rst_wmr_protect ) |
| 438 | -clock `RST.ccu_rst_sys_clk |
| 439 | -name wrm_protect_dbg1_io_quiesce_control_1 |
| 440 | -module db1 |
| 441 | -group rst_chkr |
| 442 | */ |
| 443 | |
| 444 | |
| 445 | `ifndef TCU_SAT |
| 446 | // SPC |
| 447 | |
| 448 | // MCU |
| 449 | |
| 450 | // TO ENABLE : DRAM CAS Address Width Register |
| 451 | /* 0in constant |
| 452 | -var `CPU.mcu0.drif.pff_cas_addr_bits.dout |
| 453 | -active (`RST.rst_wmr_protect ) |
| 454 | -clock `RST.ccu_rst_sys_clk |
| 455 | -name wrm_protect_mcu_dram_cas_addr_width |
| 456 | -module mcu |
| 457 | -group rst_chkr |
| 458 | */ |
| 459 | |
| 460 | // : DRAM RAS Address Width Register |
| 461 | /* 0in constant |
| 462 | -var `CPU.mcu0.drif.pff_ras_addr_bits.dout |
| 463 | -active (`RST.rst_wmr_protect ) |
| 464 | -clock `RST.ccu_rst_sys_clk |
| 465 | -name wrm_protect_mcu_dram_ras_addr_width |
| 466 | -module mcu |
| 467 | -group rst_chkr |
| 468 | */ |
| 469 | |
| 470 | // :DRAM CAS Latency Register 0x84_0000_0010 |
| 471 | /* 0in constant |
| 472 | -var `CPU.mcu0.drif.pff_mode_reg.dout |
| 473 | -active (`RST.rst_wmr_protect ) |
| 474 | -clock `RST.ccu_rst_sys_clk |
| 475 | -name wrm_protect_mcu_dram_cas_latency |
| 476 | -module mcu |
| 477 | -group rst_chkr |
| 478 | */ |
| 479 | |
| 480 | // : DRAM Scrub Frequency Register |
| 481 | /* 0in constant |
| 482 | -var `CPU.mcu0.drif.pff_freq_scrub.dout |
| 483 | -active (`RST.rst_wmr_protect ) |
| 484 | -clock `RST.ccu_rst_sys_clk |
| 485 | -name wrm_protect_mcu_dram_scrub_freq |
| 486 | -module mcu |
| 487 | -group rst_chkr |
| 488 | */ |
| 489 | |
| 490 | //:DRAM Refresh Frequency Register 0x84_0000_0020 |
| 491 | /* 0in constant |
| 492 | -var `CPU.mcu0.drif.pff_ref_freq.dout |
| 493 | -active (`RST.rst_wmr_protect ) |
| 494 | -clock `RST.ccu_rst_sys_clk |
| 495 | -name wrm_protect_mcu_dram_refresh_freq |
| 496 | -module mcu |
| 497 | -group rst_chkr |
| 498 | */ |
| 499 | |
| 500 | //:DRAM Open Bank Max Register 0x84_0000_0028 |
| 501 | /* 0in constant |
| 502 | -var `CPU.mcu0.drif.pff_max_banks_open.dout |
| 503 | -active (`RST.rst_wmr_protect ) |
| 504 | -clock `RST.ccu_rst_sys_clk |
| 505 | -name wrm_protect_mcu_dram_open_bank_max |
| 506 | -module mcu |
| 507 | -group rst_chkr |
| 508 | */ |
| 509 | |
| 510 | //:DRAM Scrub Enable Register 0x84_0000_0040 |
| 511 | /* 0in constant |
| 512 | -var `CPU.mcu0.drif.pff_data_scrub.dout |
| 513 | -active (`RST.rst_wmr_protect ) |
| 514 | -clock `RST.ccu_rst_sys_clk |
| 515 | -name wrm_protect_mcu_dram_scrub_enable |
| 516 | -module mcu |
| 517 | -group rst_chkr |
| 518 | */ |
| 519 | |
| 520 | //:DRAM Programmable Time Counter Register 0x84_0000_0048 |
| 521 | /* 0in constant |
| 522 | -var `CPU.mcu0.drif.pff_max_time.dout |
| 523 | -active (`RST.rst_wmr_protect ) |
| 524 | -clock `RST.ccu_rst_sys_clk |
| 525 | -name wrm_protect_mcu_dram_programmable_time_counter |
| 526 | -module mcu |
| 527 | -group rst_chkr |
| 528 | */ |
| 529 | |
| 530 | // : DRAM RAS to RAS Different Bank Delay Register 0x84_0000_0080 |
| 531 | /* 0in constant |
| 532 | -var `CPU.mcu0.drif.pff_rrd_reg.dout |
| 533 | -active (`RST.rst_wmr_protect ) |
| 534 | -clock `RST.ccu_rst_sys_clk |
| 535 | -name wrm_protect_mcu_dram_rastoras_bank_delay |
| 536 | -module mcu |
| 537 | -group rst_chkr |
| 538 | */ |
| 539 | |
| 540 | //:DRAM RAS to RAS Same Bank Delay Register 0x84_0000_0088 |
| 541 | /* 0in constant |
| 542 | -var `CPU.mcu0.drif.pff_rc_reg.dout |
| 543 | -active (`RST.rst_wmr_protect ) |
| 544 | -clock `RST.ccu_rst_sys_clk |
| 545 | -name wrm_protect_mcu_dram_rastoras_same_bank_delay |
| 546 | -module mcu |
| 547 | -group rst_chkr |
| 548 | */ |
| 549 | |
| 550 | // :DRAM RAS to CAS Delay Register 0x84_0000_0090 |
| 551 | /* 0in constant |
| 552 | -var `CPU.mcu0.drif.pff_rcd_reg.dout |
| 553 | -active (`RST.rst_wmr_protect ) |
| 554 | -clock `RST.ccu_rst_sys_clk |
| 555 | -name wrm_protect_mcu_dram_rastocas_delay |
| 556 | -module mcu |
| 557 | -group rst_chkr |
| 558 | */ |
| 559 | |
| 560 | //:DRAM Write to Read CAS Delay Register 0x84_0000_0098 |
| 561 | /* 0in constant |
| 562 | -var `CPU.mcu0.drif.pff_wtr_reg.dout |
| 563 | -active (`RST.rst_wmr_protect ) |
| 564 | -clock `RST.ccu_rst_sys_clk |
| 565 | -name wrm_protect_mcu_dram_writetoread_cas_delay |
| 566 | -module mcu |
| 567 | -group rst_chkr |
| 568 | */ |
| 569 | |
| 570 | //:DRAM Read to Write CAS Delay Register 0x84_0000_00a0 |
| 571 | /* 0in constant |
| 572 | -var `CPU.mcu0.drif.pff_rtw_reg.dout |
| 573 | -active (`RST.rst_wmr_protect ) |
| 574 | -clock `RST.ccu_rst_sys_clk |
| 575 | -name wrm_protect_mcu_dram_readtowrite_cas_delay |
| 576 | -module mcu |
| 577 | -group rst_chkr |
| 578 | */ |
| 579 | |
| 580 | //:DRAM internal Read to Precharge Delay Register 0x84_0000_00a8 |
| 581 | /* 0in constant |
| 582 | -var `CPU.mcu0.drif.pff_rtp_reg.dout |
| 583 | -active (`RST.rst_wmr_protect ) |
| 584 | -clock `RST.ccu_rst_sys_clk |
| 585 | -name wrm_protect_mcu_dram_internal_readtoprecharge_delay |
| 586 | -module mcu |
| 587 | -group rst_chkr |
| 588 | */ |
| 589 | |
| 590 | //:DRAM Active to Precharge Delay Register 0x84_0000_00b0 |
| 591 | /* 0in constant |
| 592 | -var `CPU.mcu0.drif.pff_ras_reg.dout |
| 593 | -active (`RST.rst_wmr_protect ) |
| 594 | -clock `RST.ccu_rst_sys_clk |
| 595 | -name wrm_protect_mcu_dram_active_to_precharge_delay |
| 596 | -module mcu |
| 597 | -group rst_chkr |
| 598 | */ |
| 599 | |
| 600 | //:DRAM Precharge Command Period Register 0x84_0000_00b8 |
| 601 | /* 0in constant |
| 602 | -var `CPU.mcu0.drif.pff_rp_reg.dout |
| 603 | -active (`RST.rst_wmr_protect ) |
| 604 | -clock `RST.ccu_rst_sys_clk |
| 605 | -name wrm_protect_mcu_dram_precharge_command_period |
| 606 | -module mcu |
| 607 | -group rst_chkr |
| 608 | */ |
| 609 | |
| 610 | //:DRAM Write Recovery Period Register 0x84_0000_00c0 |
| 611 | /* 0in constant |
| 612 | -var `CPU.mcu0.drif.pff_wr_reg.dout |
| 613 | -active (`RST.rst_wmr_protect ) |
| 614 | -clock `RST.ccu_rst_sys_clk |
| 615 | -name wrm_protect_mcu_dram_write_recovery_period |
| 616 | -module mcu |
| 617 | -group rst_chkr |
| 618 | */ |
| 619 | |
| 620 | //:DRAM Autorefresh to Active Period Register 0x84_0000_00c8 |
| 621 | /* 0in constant |
| 622 | -var `CPU.mcu0.drif.pff_rfc_reg.dout |
| 623 | -active (`RST.rst_wmr_protect ) |
| 624 | -clock `RST.ccu_rst_sys_clk |
| 625 | -name wrm_protect_mcu_dram_autorefresh_active_period |
| 626 | -module mcu |
| 627 | -group rst_chkr |
| 628 | */ |
| 629 | |
| 630 | //:DRAM Mode Register Set Command Period Register 0x84_0000_00d0 |
| 631 | /* 0in constant |
| 632 | -var `CPU.mcu0.drif.pff_mrd_reg.dout |
| 633 | -active (`RST.rst_wmr_protect ) |
| 634 | -clock `RST.ccu_rst_sys_clk |
| 635 | -name wrm_protect_mcu_dram_mode_reg_set_command_period |
| 636 | -module mcu |
| 637 | -group rst_chkr |
| 638 | */ |
| 639 | |
| 640 | //:DRAM Four Activate Window Register 0x84_0000_00d8 |
| 641 | /* 0in constant |
| 642 | -var `CPU.mcu0.drif.pff_faw_reg.dout |
| 643 | -active (`RST.rst_wmr_protect ) |
| 644 | -clock `RST.ccu_rst_sys_clk |
| 645 | -name wrm_protect_mcu_dram_four_activate_window |
| 646 | -module mcu |
| 647 | -group rst_chkr |
| 648 | */ |
| 649 | |
| 650 | //:DRAM Internal Write to Read Command Delay Register 0x84_0000_00e0 |
| 651 | /* 0in constant |
| 652 | -var `CPU.mcu0.drif.pff_iwtr_reg.dout |
| 653 | -active (`RST.rst_wmr_protect ) |
| 654 | -clock `RST.ccu_rst_sys_clk |
| 655 | -name wrm_protect_mcu_dram_internal_writetoread_delay |
| 656 | -module mcu |
| 657 | -group rst_chkr |
| 658 | */ |
| 659 | |
| 660 | //:DRAM Precharge Wait Register During Power Up |
| 661 | // Section 25.11.21 PRM 1.1, this register is obsolete and no more warm protected |
| 662 | // INVALID0in constant |
| 663 | // -var `CPU.mcu0.drif.ff_precharge_wait.dout |
| 664 | // -active (`RST.rst_wmr_protect ) |
| 665 | // -clock `RST.ccu_rst_sys_clk |
| 666 | // -name wrm_protect_mcu_dram_precharge_wait_poweron |
| 667 | // -module mcu |
| 668 | // -group rst_chkr |
| 669 | // |
| 670 | |
| 671 | // : DRAM DIMM Stacked Register |
| 672 | /* 0in constant |
| 673 | -var `CPU.mcu0.drif.pff_stacked_dimm.dout |
| 674 | -active (`RST.rst_wmr_protect ) |
| 675 | -clock `RST.ccu_rst_sys_clk |
| 676 | -name wrm_protect_mcu_dram_stacked_dimm |
| 677 | -module mcu |
| 678 | -group rst_chkr |
| 679 | */ |
| 680 | // : DRAM Extended Mode (1) Register |
| 681 | /* 0in constant |
| 682 | -var `CPU.mcu0.drif.pff_ext_mode_reg1.dout |
| 683 | -active (`RST.rst_wmr_protect ) |
| 684 | -clock `RST.ccu_rst_sys_clk |
| 685 | -name wrm_protect_mcu_dram_ext_mode_1 |
| 686 | -module mcu |
| 687 | -group rst_chkr |
| 688 | */ |
| 689 | |
| 690 | // : DRAM Extended Mode (2) Register |
| 691 | /* 0in constant |
| 692 | -var `CPU.mcu0.drif.pff_ext_mode_reg2.dout |
| 693 | -active (`RST.rst_wmr_protect ) |
| 694 | -clock `RST.ccu_rst_sys_clk |
| 695 | -name wrm_protect_mcu_dram_ext_mode_2 |
| 696 | -module mcu |
| 697 | -group rst_chkr |
| 698 | */ |
| 699 | |
| 700 | // : DRAM Extended Mode (3) Register |
| 701 | /* 0in constant |
| 702 | -var `CPU.mcu0.drif.pff_ext_mode_reg3.dout |
| 703 | -active (`RST.rst_wmr_protect ) |
| 704 | -clock `RST.ccu_rst_sys_clk |
| 705 | -name wrm_protect_mcu_dram_ext_mode_3 |
| 706 | -module mcu |
| 707 | -group rst_chkr |
| 708 | */ |
| 709 | |
| 710 | // : DRAM 8 Bank Mode Register |
| 711 | /* 0in constant |
| 712 | -var `CPU.mcu0.drif.pff_eight_bank_present.dout |
| 713 | -active (`RST.rst_wmr_protect ) |
| 714 | -clock `RST.ccu_rst_sys_clk |
| 715 | -name wrm_protect_mcu_dram_8_bank_mode |
| 716 | -module mcu |
| 717 | -group rst_chkr |
| 718 | */ |
| 719 | |
| 720 | // : DRAM Branch Disabled Register |
| 721 | /* 0in constant |
| 722 | -var `CPU.mcu0.drif.pff_branch_disabled.dout |
| 723 | -active (`RST.rst_wmr_protect ) |
| 724 | -clock `RST.ccu_rst_sys_clk |
| 725 | -name wrm_protect_mcu_dram_branch_disabled |
| 726 | -module mcu |
| 727 | -group rst_chkr |
| 728 | */ |
| 729 | |
| 730 | // : DRAM Select Low Order Address Bits Register |
| 731 | /* 0in constant |
| 732 | -var `CPU.mcu0.drif.pff_bank_low_sel.dout |
| 733 | -active (`RST.rst_wmr_protect ) |
| 734 | -clock `RST.ccu_rst_sys_clk |
| 735 | -name wrm_protect_mcu_dram_select_low_order_addr_bits |
| 736 | -module mcu |
| 737 | -group rst_chkr |
| 738 | */ |
| 739 | |
| 740 | // : DRAM Single Channel Mode Register 0x84_0000_0148 |
| 741 | /* 0in constant |
| 742 | -var `CPU.mcu0.drif.pff_single_channel_mode.dout |
| 743 | -active (`RST.rst_wmr_protect ) |
| 744 | -clock `RST.ccu_rst_sys_clk |
| 745 | -name wrm_protect_mcu_dram_single_channel_mode |
| 746 | -module mcu |
| 747 | -group rst_chkr |
| 748 | */ |
| 749 | |
| 750 | // : DRAM DIMMs Present Register |
| 751 | /* 0in constant |
| 752 | -var `CPU.mcu0.drif.pff_dimms_present.dout |
| 753 | -active (`RST.rst_wmr_protect ) |
| 754 | -clock `RST.ccu_rst_sys_clk |
| 755 | -name wrm_protect_mcu_dram_dimms_present |
| 756 | -module mcu |
| 757 | -group rst_chkr |
| 758 | */ |
| 759 | |
| 760 | // : DRAM Fail-Over Status Register |
| 761 | /* 0in constant |
| 762 | -var `CPU.mcu0.drif.pff_fail_over_mode.dout |
| 763 | -active (`RST.rst_wmr_protect ) |
| 764 | -clock `RST.ccu_rst_sys_clk |
| 765 | -name wrm_protect_mcu_dram_fail_over_status |
| 766 | -module mcu |
| 767 | -group rst_chkr |
| 768 | */ |
| 769 | |
| 770 | // : DRAM Fail-Over Mask Register |
| 771 | /* 0in constant |
| 772 | -var `CPU.mcu0.drif.pff_fail_over_mask.dout |
| 773 | -active (`RST.rst_wmr_protect ) |
| 774 | -clock `RST.ccu_rst_sys_clk |
| 775 | -name wrm_protect_mcu_dram_fail_over_mask |
| 776 | -module mcu |
| 777 | -group rst_chkr |
| 778 | */ |
| 779 | |
| 780 | //:DRAM Debug Trigger Enable Register 0x84_0000_0230 |
| 781 | /* 0in constant |
| 782 | -var `CPU.mcu0.rdpctl.pff_dbg_trig.dout |
| 783 | -active (`RST.rst_wmr_protect ) |
| 784 | -clock `RST.ccu_rst_sys_clk |
| 785 | -name wrm_protect_mcu_dram_debug_trigger_enable |
| 786 | -module mcu |
| 787 | -group rst_chkr |
| 788 | */ |
| 789 | |
| 790 | //:DRAM Error Status Register bit 63 0x84_0000_0280 |
| 791 | /* 0in constant |
| 792 | -var `CPU.mcu0.rdpctl.pff_err_sts_bit63.dout |
| 793 | -active (`RST.rst_wmr_protect ) |
| 794 | -clock `RST.ccu_rst_sys_clk |
| 795 | -name wrm_protect_mcu_dram_error_status_bit63 |
| 796 | -module mcu |
| 797 | -group rst_chkr |
| 798 | */ |
| 799 | |
| 800 | //:DRAM Error Status Register bit 62 0x84_0000_0280 |
| 801 | /* 0in constant |
| 802 | -var `CPU.mcu0.rdpctl.pff_err_sts_bit62.dout |
| 803 | -active (`RST.rst_wmr_protect ) |
| 804 | -clock `RST.ccu_rst_sys_clk |
| 805 | -name wrm_protect_mcu_dram_error_status_bit62 |
| 806 | -module mcu |
| 807 | -group rst_chkr |
| 808 | */ |
| 809 | |
| 810 | //:DRAM Error Status Register bit 61 0x84_0000_0280 |
| 811 | /* 0in constant |
| 812 | -var `CPU.mcu0.rdpctl.pff_err_sts_bit61.dout |
| 813 | -active (`RST.rst_wmr_protect ) |
| 814 | -clock `RST.ccu_rst_sys_clk |
| 815 | -name wrm_protect_mcu_dram_error_status_bit61 |
| 816 | -module mcu |
| 817 | -group rst_chkr |
| 818 | */ |
| 819 | |
| 820 | //:DRAM Error Status Register bit 60 0x84_0000_0280 |
| 821 | /* 0in constant |
| 822 | -var `CPU.mcu0.rdpctl.pff_err_sts_bit60.dout |
| 823 | -active (`RST.rst_wmr_protect ) |
| 824 | -clock `RST.ccu_rst_sys_clk |
| 825 | -name wrm_protect_mcu_dram_error_status_bit60 |
| 826 | -module mcu |
| 827 | -group rst_chkr |
| 828 | */ |
| 829 | |
| 830 | //:DRAM Error Status Register bit 59 0x84_0000_0280 |
| 831 | /* 0in constant |
| 832 | -var `CPU.mcu0.rdpctl.pff_err_sts_bit59.dout |
| 833 | -active (`RST.rst_wmr_protect ) |
| 834 | -clock `RST.ccu_rst_sys_clk |
| 835 | -name wrm_protect_mcu_dram_error_status_bit59 |
| 836 | -module mcu |
| 837 | -group rst_chkr |
| 838 | */ |
| 839 | |
| 840 | //:DRAM Error Status Register bit 58 0x84_0000_0280 |
| 841 | /* 0in constant |
| 842 | -var `CPU.mcu0.rdpctl.pff_err_sts_bit58.dout |
| 843 | -active (`RST.rst_wmr_protect ) |
| 844 | -clock `RST.ccu_rst_sys_clk |
| 845 | -name wrm_protect_mcu_dram_error_status_bit58 |
| 846 | -module mcu |
| 847 | -group rst_chkr |
| 848 | */ |
| 849 | |
| 850 | //:DRAM Error Status Register bit 57 0x84_0000_0280 |
| 851 | /* 0in constant |
| 852 | -var `CPU.mcu0.rdpctl.pff_err_sts_bit57.dout |
| 853 | -active (`RST.rst_wmr_protect ) |
| 854 | -clock `RST.ccu_rst_sys_clk |
| 855 | -name wrm_protect_mcu_dram_error_status_bit57 |
| 856 | -module mcu |
| 857 | -group rst_chkr |
| 858 | */ |
| 859 | |
| 860 | //:DRAM Error Status Register bit 56 0x84_0000_0280 |
| 861 | /* 0in constant |
| 862 | -var `CPU.mcu0.rdpctl.pff_err_sts_bit56.dout |
| 863 | -active (`RST.rst_wmr_protect ) |
| 864 | -clock `RST.ccu_rst_sys_clk |
| 865 | -name wrm_protect_mcu_dram_error_status_bit56 |
| 866 | -module mcu |
| 867 | -group rst_chkr |
| 868 | */ |
| 869 | |
| 870 | //:DRAM Error Status Register bit 55 0x84_0000_0280 |
| 871 | /* 0in constant |
| 872 | -var `CPU.mcu0.rdpctl.pff_err_sts_bit55.dout |
| 873 | -active (`RST.rst_wmr_protect ) |
| 874 | -clock `RST.ccu_rst_sys_clk |
| 875 | -name wrm_protect_mcu_dram_error_status_bit55 |
| 876 | -module mcu |
| 877 | -group rst_chkr |
| 878 | */ |
| 879 | |
| 880 | //:DRAM Error Status Register bit 54 0x84_0000_0280 |
| 881 | /* 0in constant |
| 882 | -var `CPU.mcu0.rdpctl.pff_err_sts_bit54.dout |
| 883 | -active (`RST.rst_wmr_protect ) |
| 884 | -clock `RST.ccu_rst_sys_clk |
| 885 | -name wrm_protect_mcu_dram_error_status_bit54 |
| 886 | -module mcu |
| 887 | -group rst_chkr |
| 888 | */ |
| 889 | |
| 890 | //:DRAM Error Status Register bit 15:0 0x84_0000_0280 |
| 891 | /* 0in constant |
| 892 | -var `CPU.mcu0.rdpctl.pff_err_syn.dout |
| 893 | -active (`RST.rst_wmr_protect ) |
| 894 | -clock `RST.ccu_rst_sys_clk |
| 895 | -name wrm_protect_mcu_dram_error_status_bit0to15 |
| 896 | -module mcu |
| 897 | -group rst_chkr |
| 898 | */ |
| 899 | |
| 900 | //:DRAM Error Address Register 0x84_0000_0288 |
| 901 | /* 0in constant |
| 902 | -var `CPU.mcu0.rdpctl.pff_err_addr_reg.dout |
| 903 | -active (`RST.rst_wmr_protect ) |
| 904 | -clock `RST.ccu_rst_sys_clk |
| 905 | -name wrm_protect_mcu_dram_error_addr |
| 906 | -module mcu |
| 907 | -group rst_chkr |
| 908 | */ |
| 909 | |
| 910 | //:DRAM Error Injection enable Register 0x84_0000_0290 |
| 911 | /* 0in constant |
| 912 | -var `CPU.mcu0.drif.pff_err_inj.dout |
| 913 | -active (`RST.rst_wmr_protect ) |
| 914 | -clock `RST.ccu_rst_sys_clk |
| 915 | -name wrm_protect_mcu_dram_error_injection |
| 916 | -module mcu |
| 917 | -group rst_chkr |
| 918 | */ |
| 919 | |
| 920 | //:DRAM Error Injection Register (single shot vs continouos) |
| 921 | /* 0in constant |
| 922 | -var `CPU.mcu0.drif.pff_sshot.dout |
| 923 | -active (`RST.rst_wmr_protect ) |
| 924 | -clock `RST.ccu_rst_sys_clk |
| 925 | -name wrm_protect_mcu_dram_error_injection_sshot |
| 926 | -module mcu |
| 927 | -group rst_chkr |
| 928 | */ |
| 929 | |
| 930 | //:DRAM Error Injection Register (mask to XOR with ECC bits) |
| 931 | /* 0in constant |
| 932 | -var `CPU.mcu0.drif.pff_err_mask.dout |
| 933 | -active (`RST.rst_wmr_protect ) |
| 934 | -clock `RST.ccu_rst_sys_clk |
| 935 | -name wrm_protect_mcu_dram_error_injection_mask |
| 936 | -module mcu |
| 937 | -group rst_chkr |
| 938 | */ |
| 939 | |
| 940 | |
| 941 | |
| 942 | //:DRAM Error Counter Register 0x84_0000_0298 |
| 943 | /* 0in constant |
| 944 | -var `CPU.mcu0.rdpctl.pff_secc_cnt.dout |
| 945 | -active (`RST.rst_wmr_protect ) |
| 946 | -clock `RST.ccu_rst_sys_clk |
| 947 | -name wrm_protect_mcu_dram_error_counter |
| 948 | -module mcu |
| 949 | -group rst_chkr |
| 950 | */ |
| 951 | |
| 952 | //:DRAM Error Location Register 0x84_0000_02a0 |
| 953 | /* 0in constant |
| 954 | -var `CPU.mcu0.rdpctl.pff_err_loc.dout |
| 955 | -active (`RST.rst_wmr_protect ) |
| 956 | -clock `RST.ccu_rst_sys_clk |
| 957 | -name wrm_protect_mcu_dram_err_location |
| 958 | -module mcu |
| 959 | -group rst_chkr |
| 960 | */ |
| 961 | |
| 962 | //:DRAM Error Retry Register18 bits 0x84_0000_02a8 |
| 963 | /* 0in constant |
| 964 | -var `CPU.mcu0.rdpctl.pff_err_retry1.dout |
| 965 | -active (`RST.rst_wmr_protect ) |
| 966 | -clock `RST.ccu_rst_sys_clk |
| 967 | -name wrm_protect_mcu_dram_error_retry1 |
| 968 | -module mcu |
| 969 | -group rst_chkr |
| 970 | */ |
| 971 | |
| 972 | //:DRAM Error Retry Register 18 bits 0x84_0000_02a8 |
| 973 | /* 0in constant |
| 974 | -var `CPU.mcu0.rdpctl.pff_err_retry2.dout |
| 975 | -active (`RST.rst_wmr_protect ) |
| 976 | -clock `RST.ccu_rst_sys_clk |
| 977 | -name wrm_protect_mcu_dram_error_retry2 |
| 978 | -module mcu |
| 979 | -group rst_chkr |
| 980 | */ |
| 981 | |
| 982 | //:DRAM Error Retry Register valid bit 0x84_0000_02a8 |
| 983 | /* 0in constant |
| 984 | -var `CPU.mcu0.rdpctl.pff_retry_reg_valid.dout |
| 985 | -active (`RST.rst_wmr_protect ) |
| 986 | -clock `RST.ccu_rst_sys_clk |
| 987 | -name wrm_protect_mcu_dram_error_retry_valid |
| 988 | -module mcu |
| 989 | -group rst_chkr |
| 990 | */ |
| 991 | |
| 992 | //:FBD Channel State Register 0x84_0000_0800 |
| 993 | /* 0in constant |
| 994 | -var `CPU.mcu0.fbdic.pff_fbd_state.dout |
| 995 | -active (`RST.rst_wmr_protect ) |
| 996 | -clock `RST.ccu_rst_sys_clk |
| 997 | -name wrm_protect_mcu_fbd_channel_state |
| 998 | -module mcu |
| 999 | -group rst_chkr |
| 1000 | */ |
| 1001 | |
| 1002 | //:FBD Fast Reset Flag Register 0x84_0000_0808 |
| 1003 | /* 0in constant |
| 1004 | -var `CPU.mcu0.fbdic.pff_fast_reset.dout |
| 1005 | -active (`RST.rst_wmr_protect ) |
| 1006 | -clock `RST.ccu_rst_sys_clk |
| 1007 | -name wrm_protect_mcu_fbd_fast_reset_flag |
| 1008 | -module mcu |
| 1009 | -group rst_chkr |
| 1010 | */ |
| 1011 | |
| 1012 | //:FBD Channel Reset Register 0x84_0000_0810 |
| 1013 | /* 0in constant |
| 1014 | -var `CPU.mcu0.fbdic.pff_chnl_reset1.dout |
| 1015 | -active (`RST.rst_wmr_protect ) |
| 1016 | -clock `RST.ccu_rst_sys_clk |
| 1017 | -name wrm_protect_mcu_fbd_channel_reset |
| 1018 | -module mcu |
| 1019 | -group rst_chkr |
| 1020 | */ |
| 1021 | |
| 1022 | //:TS1 Southbound to Northbound Mapping Register 0x84_0000_0818 |
| 1023 | /* 0in constant |
| 1024 | -var `CPU.mcu0.fbdic.pff_sb2nb_map.dout |
| 1025 | -active (`RST.rst_wmr_protect ) |
| 1026 | -clock `RST.ccu_rst_sys_clk |
| 1027 | -name wrm_protect_mcu_ts1_sounthbound_northbound_mapping |
| 1028 | -module mcu |
| 1029 | -group rst_chkr |
| 1030 | */ |
| 1031 | |
| 1032 | //:TS1 Test Parameter Register 0x84_0000_0820 |
| 1033 | /* 0in constant |
| 1034 | -var `CPU.mcu0.fbdic.pff_amb_test_param.dout |
| 1035 | -active (`RST.rst_wmr_protect ) |
| 1036 | -clock `RST.ccu_rst_sys_clk |
| 1037 | -name wrm_protect_mcu_ts1_test_parameter |
| 1038 | -module mcu |
| 1039 | -group rst_chkr |
| 1040 | */ |
| 1041 | |
| 1042 | //:TS3 Failover Configuration Register 0x84_0000_0828 |
| 1043 | /* 0in constant |
| 1044 | -var `CPU.mcu0.fbdic.pff_failover_config.dout |
| 1045 | -active (`RST.rst_wmr_protect ) |
| 1046 | -clock `RST.ccu_rst_sys_clk |
| 1047 | -name wrm_protect_mcu_ts3_failover_config |
| 1048 | -module mcu |
| 1049 | -group rst_chkr |
| 1050 | */ |
| 1051 | |
| 1052 | //:Disable State Period Register 0x84_0000_0838 |
| 1053 | /* 0in constant |
| 1054 | -var `CPU.mcu0.fbdic.pff_tdisable_period.dout |
| 1055 | -active (`RST.rst_wmr_protect ) |
| 1056 | -clock `RST.ccu_rst_sys_clk |
| 1057 | -name wrm_protect_mcu_disable_state_period |
| 1058 | -module mcu |
| 1059 | -group rst_chkr |
| 1060 | */ |
| 1061 | |
| 1062 | //:Calibrate State Period Register 0x84_0000_0848 |
| 1063 | /* 0in constant |
| 1064 | -var `CPU.mcu0.fbdic.pff_tcalibrate_period.dout |
| 1065 | -active (`RST.rst_wmr_protect ) |
| 1066 | -clock `RST.ccu_rst_sys_clk |
| 1067 | -name wrm_protect_mcu_calibrate_state_period |
| 1068 | -module mcu |
| 1069 | -group rst_chkr |
| 1070 | */ |
| 1071 | |
| 1072 | //:Training State Minimum Time Register 0x84_0000_0858 |
| 1073 | /* 0in constant |
| 1074 | -var `CPU.mcu0.fbdic.pff_tclktrain_min.dout |
| 1075 | -active (`RST.rst_wmr_protect ) |
| 1076 | -clock `RST.ccu_rst_sys_clk |
| 1077 | -name wrm_protect_mcu_training_state_min_time |
| 1078 | -module mcu |
| 1079 | -group rst_chkr |
| 1080 | */ |
| 1081 | |
| 1082 | //:Training State Timeout Register 0x84_0000_0868 |
| 1083 | /* 0in constant |
| 1084 | -var `CPU.mcu0.fbdic.pff_tclktrain_timeout.dout |
| 1085 | -active (`RST.rst_wmr_protect ) |
| 1086 | -clock `RST.ccu_rst_sys_clk |
| 1087 | -name wrm_protect_mcu_training_state_timeout |
| 1088 | -module mcu |
| 1089 | -group rst_chkr |
| 1090 | */ |
| 1091 | |
| 1092 | //:Testing State Timeout Register 0x84_0000_0878 |
| 1093 | /* 0in constant |
| 1094 | -var `CPU.mcu0.fbdic.pff_testing_timeout.dout |
| 1095 | -active (`RST.rst_wmr_protect ) |
| 1096 | -clock `RST.ccu_rst_sys_clk |
| 1097 | -name wrm_protect_mcu_testing_state_timeout |
| 1098 | -module mcu |
| 1099 | -group rst_chkr |
| 1100 | */ |
| 1101 | |
| 1102 | //:Polling State Timeout Register 0x84_0000_0888 |
| 1103 | /* 0in constant |
| 1104 | -var `CPU.mcu0.fbdic.pff_polling_timeout.dout |
| 1105 | -active (`RST.rst_wmr_protect ) |
| 1106 | -clock `RST.ccu_rst_sys_clk |
| 1107 | -name wrm_protect_mcu_polling_state_timeout |
| 1108 | -module mcu |
| 1109 | -group rst_chkr |
| 1110 | */ |
| 1111 | |
| 1112 | //:Config State Done Register 0x84_0000_0898 |
| 1113 | /* 0in constant |
| 1114 | -var `CPU.mcu0.fbdic.pff_config_timeout.dout |
| 1115 | -active (`RST.rst_wmr_protect ) |
| 1116 | -clock `RST.ccu_rst_sys_clk |
| 1117 | -name wrm_protect_mcu_config_state_timeout |
| 1118 | -module mcu |
| 1119 | -group rst_chkr |
| 1120 | */ |
| 1121 | |
| 1122 | //:DRAM Per-Rank CKE Register 0x84_0000_08a0 |
| 1123 | /* 0in constant |
| 1124 | -var `CPU.mcu0.fbdic.pff_per_rank_cke.dout |
| 1125 | -active (`RST.rst_wmr_protect ) |
| 1126 | -clock `RST.ccu_rst_sys_clk |
| 1127 | -name wrm_protect_mcu_dram_per_rank_cke |
| 1128 | -module mcu |
| 1129 | -group rst_chkr |
| 1130 | */ |
| 1131 | |
| 1132 | //:L0s Duration Register |
| 1133 | /* 0in constant |
| 1134 | -var `CPU.mcu0.fbdic.pff_l0s_time.dout |
| 1135 | -active (`RST.rst_wmr_protect ) |
| 1136 | -clock `RST.ccu_rst_sys_clk |
| 1137 | -name wrm_protect_mcu_l0s_duration |
| 1138 | -module mcu |
| 1139 | -group rst_chkr |
| 1140 | */ |
| 1141 | |
| 1142 | //:Channel Sync Frame Frequency Register 0x84_0000_08b0 |
| 1143 | /* 0in constant |
| 1144 | -var `CPU.mcu0.fbdic.fbdtm.pff_sync_frm_period.dout |
| 1145 | -active (`RST.rst_wmr_protect ) |
| 1146 | -clock `RST.ccu_rst_sys_clk |
| 1147 | -name wrm_protect_mcu_channel_sync_frame_freq |
| 1148 | -module mcu |
| 1149 | -group rst_chkr |
| 1150 | */ |
| 1151 | |
| 1152 | //:SERDES Configuration Bus Register 0x84_0000_08d0 |
| 1153 | /* 0in constant |
| 1154 | -var `CPU.mcu0.fbdic.fbdtm.pff_sds_config.dout |
| 1155 | -active (`RST.rst_wmr_protect ) |
| 1156 | -clock `RST.ccu_rst_sys_clk |
| 1157 | -name wrm_protect_mcu_serdes_config_bus |
| 1158 | -module mcu |
| 1159 | -group rst_chkr |
| 1160 | */ |
| 1161 | |
| 1162 | //:SERDES Transmitter and Receiver Differential Pair Inversion Register 0x84_0000_08d8 |
| 1163 | /* 0in constant |
| 1164 | -var `CPU.mcu0.fbdic.fbdtm.pff_sds_invert.dout |
| 1165 | -active (`RST.rst_wmr_protect ) |
| 1166 | -clock `RST.ccu_rst_sys_clk |
| 1167 | -name wrm_protect_mcu_serdes_transmit_receive_diif_pair_inversion |
| 1168 | -module mcu |
| 1169 | -group rst_chkr |
| 1170 | */ |
| 1171 | |
| 1172 | //:SERDES Test Configuration Bus Register 0x84_0000_08e0 |
| 1173 | /* 0in constant |
| 1174 | -var `CPU.mcu0.fbdic.fbdtm.pff_sds_testcfg.dout |
| 1175 | -active (`RST.rst_wmr_protect ) |
| 1176 | -clock `RST.ccu_rst_sys_clk |
| 1177 | -name wrm_protect_mcu_serdes_test_config_bus |
| 1178 | -module mcu |
| 1179 | -group rst_chkr |
| 1180 | */ |
| 1181 | |
| 1182 | //:DRAM FBD Error Syndrome Register 0x84_0000_0c00 |
| 1183 | /* 0in constant |
| 1184 | -var `CPU.mcu0.fbdic.pff_mcu_syndrome.dout |
| 1185 | -active (`RST.rst_wmr_protect ) |
| 1186 | -clock `RST.ccu_rst_sys_clk |
| 1187 | -name wrm_protect_mcu_dram_fbd_err_syndrome |
| 1188 | -module mcu |
| 1189 | -group rst_chkr |
| 1190 | */ |
| 1191 | |
| 1192 | //:DRAM FBD Injected Error Source Register 0x84_0000_0c08 |
| 1193 | /* 0in constant |
| 1194 | -var `CPU.mcu0.fbdic.pff_inj_err_src.dout |
| 1195 | -active (`RST.rst_wmr_protect ) |
| 1196 | -clock `RST.ccu_rst_sys_clk |
| 1197 | -name wrm_protect_mcu_dram_fbd_injected_err_source |
| 1198 | -module mcu |
| 1199 | -group rst_chkr |
| 1200 | */ |
| 1201 | |
| 1202 | //:DRAM FBR Count Register |
| 1203 | /* 0in constant |
| 1204 | -var `CPU.mcu0.fbdic.pff_fbr_count.dout |
| 1205 | -active (`RST.rst_wmr_protect ) |
| 1206 | -clock `RST.ccu_rst_sys_clk |
| 1207 | -name wrm_protect_mcu_dram_fbr_count |
| 1208 | -module mcu |
| 1209 | -group rst_chkr |
| 1210 | */ |
| 1211 | |
| 1212 | //:IBIST sbfibportctl Register 0x84_0000_0e80 |
| 1213 | /* 0in constant |
| 1214 | -var `CPU.mcu0.fbdic.pff_sbfibportctl.dout |
| 1215 | -active (`RST.rst_wmr_protect ) |
| 1216 | -clock `RST.ccu_rst_sys_clk |
| 1217 | -name wrm_protect_mcu_ibist_sbfibportctl |
| 1218 | -module mcu |
| 1219 | -group rst_chkr |
| 1220 | */ |
| 1221 | |
| 1222 | //:IBIST sbfibpgctl Register 0x84_0000_0e80 |
| 1223 | /* 0in constant |
| 1224 | -var `CPU.mcu0.fbdic.pff_sbfibpgctl.dout |
| 1225 | -active (`RST.rst_wmr_protect ) |
| 1226 | -clock `RST.ccu_rst_sys_clk |
| 1227 | -name wrm_protect_mcu_ibist_sbfibpgctl |
| 1228 | -module mcu |
| 1229 | -group rst_chkr |
| 1230 | */ |
| 1231 | |
| 1232 | //:IBIST sbfibpattbuf1/sbfibtxmsk Register 0x84_0000_0e88 |
| 1233 | /* 0in constant |
| 1234 | -var `CPU.mcu0.fbdic.pff_sbfibpattbuf1.dout |
| 1235 | -active (`RST.rst_wmr_protect ) |
| 1236 | -clock `RST.ccu_rst_sys_clk |
| 1237 | -name wrm_protect_mcu_ibist_sbfibpattbuf1 |
| 1238 | -module mcu |
| 1239 | -group rst_chkr |
| 1240 | */ |
| 1241 | |
| 1242 | //:IBIST sbfibpattbuf1/sbfibtxmsk Register 0x84_0000_0e88 |
| 1243 | /* 0in constant |
| 1244 | -var `CPU.mcu0.fbdic.pff_sbfibtxmsk.dout |
| 1245 | -active (`RST.rst_wmr_protect ) |
| 1246 | -clock `RST.ccu_rst_sys_clk |
| 1247 | -name wrm_protect_mcu_ibist_sbfibtxmsk |
| 1248 | -module mcu |
| 1249 | -group rst_chkr |
| 1250 | */ |
| 1251 | |
| 1252 | //:IBIST sbfibtxshft Register 0x84_0000_0e90 |
| 1253 | /* 0in constant |
| 1254 | -var `CPU.mcu0.fbdic.pff_sbfibtxshft.dout |
| 1255 | -active (`RST.rst_wmr_protect ) |
| 1256 | -clock `RST.ccu_rst_sys_clk |
| 1257 | -name wrm_protect_mcu_ibist_sbfibtxshft |
| 1258 | -module mcu |
| 1259 | -group rst_chkr |
| 1260 | */ |
| 1261 | |
| 1262 | //:IBIST sbfibpattbuf2/sbfibpatt2en Register 0x84_0000_0ea0 |
| 1263 | /* 0in constant |
| 1264 | -var `CPU.mcu0.fbdic.pff_sbfibpattbuf2.dout |
| 1265 | -active (`RST.rst_wmr_protect ) |
| 1266 | -clock `RST.ccu_rst_sys_clk |
| 1267 | -name wrm_protect_mcu_ibist_sbfibpattbuf2 |
| 1268 | -module mcu |
| 1269 | -group rst_chkr |
| 1270 | */ |
| 1271 | |
| 1272 | //:IBIST sbfibpattbuf2/sbfibpatt2en Register 0x84_0000_0ea0 |
| 1273 | /* 0in constant |
| 1274 | -var `CPU.mcu0.fbdic.pff_sbfibpatt2en.dout |
| 1275 | -active (`RST.rst_wmr_protect ) |
| 1276 | -clock `RST.ccu_rst_sys_clk |
| 1277 | -name wrm_protect_mcu_ibist_sbfibpatt2en |
| 1278 | -module mcu |
| 1279 | -group rst_chkr |
| 1280 | */ |
| 1281 | |
| 1282 | //:IBIST sbfibinit/sbibistmisc Register 0x84_0000_0eb0 |
| 1283 | /* 0in constant |
| 1284 | -var `CPU.mcu0.fbdic.pff_sbfibinit.dout |
| 1285 | -active (`RST.rst_wmr_protect ) |
| 1286 | -clock `RST.ccu_rst_sys_clk |
| 1287 | -name wrm_protect_mcu_ibist_sbfibinit |
| 1288 | -module mcu |
| 1289 | -group rst_chkr |
| 1290 | */ |
| 1291 | |
| 1292 | //:IBIST sbfibinit/sbibistmisc Register 0x84_0000_0eb0 |
| 1293 | /* 0in constant |
| 1294 | -var `CPU.mcu0.fbdic.pff_sbibistmisc.dout |
| 1295 | -active (`RST.rst_wmr_protect ) |
| 1296 | -clock `RST.ccu_rst_sys_clk |
| 1297 | -name wrm_protect_mcu_ibist_sbibistmisc |
| 1298 | -module mcu |
| 1299 | -group rst_chkr |
| 1300 | */ |
| 1301 | |
| 1302 | //:IBIST nbfibportctl/nbfibpgctl Register 0x84_0000_0ec0 |
| 1303 | /* 0in constant |
| 1304 | -var `CPU.mcu0.fbdic.pff_nbfibportctl.dout |
| 1305 | -active (`RST.rst_wmr_protect ) |
| 1306 | -clock `RST.ccu_rst_sys_clk |
| 1307 | -name wrm_protect_mcu_ibist_nbfibportctl |
| 1308 | -module mcu |
| 1309 | -group rst_chkr |
| 1310 | */ |
| 1311 | |
| 1312 | //:IBIST nbfibportctl/nbfibpgctl Register 0x84_0000_0ec0 |
| 1313 | /* 0in constant |
| 1314 | -var `CPU.mcu0.fbdic.pff_nbfibpgctl.dout |
| 1315 | -active (`RST.rst_wmr_protect ) |
| 1316 | -clock `RST.ccu_rst_sys_clk |
| 1317 | -name wrm_protect_mcu_ibist_nbfibpgctl |
| 1318 | -module mcu |
| 1319 | -group rst_chkr |
| 1320 | */ |
| 1321 | |
| 1322 | //:IBIST nbfibpattbuf1 Register 0x84_0000_0ec8 |
| 1323 | /* 0in constant |
| 1324 | -var `CPU.mcu0.fbdic.pff_nbfibpattbuf1.dout |
| 1325 | -active (`RST.rst_wmr_protect ) |
| 1326 | -clock `RST.ccu_rst_sys_clk |
| 1327 | -name wrm_protect_mcu_ibist_nbfibpattbuf1 |
| 1328 | -module mcu |
| 1329 | -group rst_chkr |
| 1330 | */ |
| 1331 | |
| 1332 | //:IBIST nbfibrxmsk Register 0x84_0000_0ed0 |
| 1333 | /* 0in constant |
| 1334 | -var `CPU.mcu0.fbdic.pff_nbfibrxmsk.dout |
| 1335 | -active (`RST.rst_wmr_protect ) |
| 1336 | -clock `RST.ccu_rst_sys_clk |
| 1337 | -name wrm_protect_mcu_ibist_nbfibrxmsk |
| 1338 | -module mcu |
| 1339 | -group rst_chkr |
| 1340 | */ |
| 1341 | |
| 1342 | //:IBIST nbfibrxshft Register 0x84_0000_0ed8 |
| 1343 | /* 0in constant |
| 1344 | -var `CPU.mcu0.fbdic.pff_nbfibrxshft.dout |
| 1345 | -active (`RST.rst_wmr_protect ) |
| 1346 | -clock `RST.ccu_rst_sys_clk |
| 1347 | -name wrm_protect_mcu_ibist_nbfibrxshft |
| 1348 | -module mcu |
| 1349 | -group rst_chkr |
| 1350 | */ |
| 1351 | |
| 1352 | //:IBIST nbfibpattbuf2/nbfibpatt2en Register 0x84_0000_0ee0 |
| 1353 | /* 0in constant |
| 1354 | -var `CPU.mcu0.fbdic.pff_nbfibpattbuf2.dout |
| 1355 | -active (`RST.rst_wmr_protect ) |
| 1356 | -clock `RST.ccu_rst_sys_clk |
| 1357 | -name wrm_protect_mcu_ibist_nbfibpattbuf2 |
| 1358 | -module mcu |
| 1359 | -group rst_chkr |
| 1360 | */ |
| 1361 | |
| 1362 | //:IBIST nbfibpattbuf2/nbfibpatt2en Register 0x84_0000_0ee0 |
| 1363 | /* 0in constant |
| 1364 | -var `CPU.mcu0.fbdic.pff_nbfibpatt2en.dout |
| 1365 | -active (`RST.rst_wmr_protect ) |
| 1366 | -clock `RST.ccu_rst_sys_clk |
| 1367 | -name wrm_protect_mcu_ibist_nbfibpatt2en |
| 1368 | -module mcu |
| 1369 | -group rst_chkr |
| 1370 | */ |
| 1371 | |
| 1372 | |
| 1373 | |
| 1374 | // PEU DMU |
| 1375 | |
| 1376 | // TO ENABLE : IMU Error Log Enable Register (0x00631000 / 0x7FFF) |
| 1377 | /* 0in constant |
| 1378 | -var `CPU.dmu.dmc.imu.ics.csr.dmu_imu_ics_default_grp.imu_error_log_en_reg.imu_error_log_en_reg_0.imu_error_log_en_reg_csrbus_read_data |
| 1379 | -active (`RST.rst_wmr_protect ) |
| 1380 | -clock `RST.ccu_rst_sys_clk |
| 1381 | -name wrm_protect_dmu_error_log_enable |
| 1382 | -module dmu |
| 1383 | -group rst_chkr |
| 1384 | */ |
| 1385 | |
| 1386 | // TO ENABLE : IMU Error Status Clear Register (0x00631018 / 0x0) |
| 1387 | /* 0in constant |
| 1388 | -var `CPU.dmu.dmc.imu.ics.csr.dmu_imu_ics_default_grp.imu_logged_error_status_reg.imu_logged_error_status_reg_0.imu_logged_error_status_reg_csrbus_read_data |
| 1389 | -active (`RST.rst_wmr_protect ) |
| 1390 | -clock `RST.ccu_rst_sys_clk |
| 1391 | -name wrm_protect_dmu_error_status_clear |
| 1392 | -module dmu |
| 1393 | -group rst_chkr |
| 1394 | */ |
| 1395 | |
| 1396 | // TO ENABLE : IMU RDS Error Log Register (0x00631028 / 0x0) |
| 1397 | /* 0in constant |
| 1398 | -var `CPU.dmu.dmc.imu.ics.csr.dmu_imu_ics_default_grp.imu_rds_error_log_reg.imu_rds_error_log_reg_0.imu_rds_error_log_reg_csrbus_read_data |
| 1399 | -active (`RST.rst_wmr_protect & ((|`CPU.dmu.dmc.imu.ics.csr.dmu_imu_ics_default_grp.imu_rds_error_log_reg.imu_rds_error_log_reg_0.imu_rds_error_log_reg_csrbus_read_data[7:0]) | (|`CPU.dmu.dmc.imu.ics.csr.dmu_imu_ics_default_grp.imu_rds_error_log_reg.imu_rds_error_log_reg_0.imu_rds_error_log_reg_csrbus_read_data[39:10]))) |
| 1400 | -clock `RST.ccu_rst_sys_clk |
| 1401 | -name wrm_protect_dmu_error_log |
| 1402 | -module dmu |
| 1403 | -group rst_chkr |
| 1404 | */ |
| 1405 | |
| 1406 | // TO ENABLE :IMU SCS Error Log Register (0x00631030 / 0x0) |
| 1407 | /* 0in constant |
| 1408 | -var `CPU.dmu.dmc.imu.ics.csr.dmu_imu_ics_default_grp.imu_scs_error_log_reg.imu_scs_error_log_reg_0.imu_scs_error_log_reg_csrbus_read_data |
| 1409 | -active (`RST.rst_wmr_protect &((|`CPU.dmu.dmc.imu.ics.csr.dmu_imu_ics_default_grp.imu_rds_error_log_reg.imu_rds_error_log_reg_0.imu_rds_error_log_reg_csrbus_read_data[8]) | (|`CPU.dmu.dmc.imu.ics.csr.dmu_imu_ics_default_grp.imu_rds_error_log_reg.imu_rds_error_log_reg_0.imu_rds_error_log_reg_csrbus_read_data[40]))) |
| 1410 | -clock `RST.ccu_rst_sys_clk |
| 1411 | -name wrm_protect_imu_scs_error_log |
| 1412 | -module dmu |
| 1413 | -group rst_chkr |
| 1414 | */ |
| 1415 | |
| 1416 | // TO ENABLE :IMU EQS Error Log Register (0x00631038 / 0x0) |
| 1417 | /* 0in constant |
| 1418 | -var `CPU.dmu.dmc.imu.ics.csr.dmu_imu_ics_default_grp.imu_eqs_error_log_reg.imu_eqs_error_log_reg_0.imu_eqs_error_log_reg_csrbus_read_data[63:0] |
| 1419 | -active (`RST.rst_wmr_protect & ((|`CPU.dmu.dmc.imu.ics.csr.dmu_imu_ics_default_grp.imu_rds_error_log_reg.imu_rds_error_log_reg_0.imu_rds_error_log_reg_csrbus_read_data[9]) | (|`CPU.dmu.dmc.imu.ics.csr.dmu_imu_ics_default_grp.imu_rds_error_log_reg.imu_rds_error_log_reg_0.imu_rds_error_log_reg_csrbus_read_data[41]))) |
| 1420 | -clock `RST.ccu_rst_sys_clk |
| 1421 | -name wrm_protect_imu_eqs_error_log |
| 1422 | -module dmu |
| 1423 | -group rst_chkr |
| 1424 | */ |
| 1425 | |
| 1426 | // TO ENABLE :MMU Error Log Enable Register (0x00641000 / 0x1FFFFF) |
| 1427 | /* 0in constant |
| 1428 | -var `CPU.dmu.dmc.mmu.csr.csr.dmu_mmu_csr_default_grp.log.log_0.log_csrbus_read_data |
| 1429 | -active (`RST.rst_wmr_protect ) |
| 1430 | -clock `RST.ccu_rst_sys_clk |
| 1431 | -name wrm_protect_mmu_error_log_enable |
| 1432 | -module dmu |
| 1433 | -group rst_chkr |
| 1434 | */ |
| 1435 | |
| 1436 | // TO ENABLE :MMU Error Status Clear Register (0x00641018 / 0x0) |
| 1437 | /* 0in constant |
| 1438 | -var `CPU.dmu.dmc.mmu.csr.csr.dmu_mmu_csr_default_grp.err.err_0.err_csrbus_read_data |
| 1439 | -active (`RST.rst_wmr_protect ) |
| 1440 | -clock `RST.ccu_rst_sys_clk |
| 1441 | -name wrm_protect_mmu_error_status_clear |
| 1442 | -module dmu |
| 1443 | -group rst_chkr |
| 1444 | */ |
| 1445 | |
| 1446 | // TO ENABLE :MMU Translation Fault Address Register (0x00641028 / 0x0) |
| 1447 | /* 0in constant |
| 1448 | -var `CPU.dmu.dmc.mmu.csr.csr.dmu_mmu_csr_default_grp.flta.flta_0.flta_csrbus_read_data |
| 1449 | -active (`RST.rst_wmr_protect ) |
| 1450 | -clock `RST.ccu_rst_sys_clk |
| 1451 | -name wrm_protect_mmu_translation_fault_addr |
| 1452 | -module dmu |
| 1453 | -group rst_chkr |
| 1454 | */ |
| 1455 | |
| 1456 | // TO ENABLE :MMU Translation Fault Status Register (0x00641030 / 0x0) |
| 1457 | /* 0in constant |
| 1458 | -var `CPU.dmu.dmc.mmu.csr.csr.dmu_mmu_csr_default_grp.flts.flts_0.flts_csrbus_read_data |
| 1459 | -active (`RST.rst_wmr_protect ) |
| 1460 | -clock `RST.ccu_rst_sys_clk |
| 1461 | -name wrm_protect_mmu_translation_fault_status |
| 1462 | -module dmu |
| 1463 | -group rst_chkr |
| 1464 | */ |
| 1465 | |
| 1466 | // TO ENABLE :ILU Error Log Enable Register (0x00651000 / 0xF0) |
| 1467 | /* 0in constant |
| 1468 | -var `CPU.dmu.ilu.cib.csr.dmu_ilu_cib_default_grp.ilu_log_en.ilu_log_en_0.ilu_log_en_csrbus_read_data |
| 1469 | -active (`RST.rst_wmr_protect ) |
| 1470 | -clock `RST.ccu_rst_sys_clk |
| 1471 | -name wrm_protect_ilu_error_log_enable |
| 1472 | -module dmu |
| 1473 | -group rst_chkr |
| 1474 | */ |
| 1475 | |
| 1476 | // TO ENABLE :ILU Error Status Clear Register (0x00651018 / 0x0) |
| 1477 | /* 0in constant |
| 1478 | -var `CPU.dmu.ilu.cib.csr.dmu_ilu_cib_default_grp.ilu_log_err.ilu_log_err_0.ilu_log_err_csrbus_read_data |
| 1479 | -active (`RST.rst_wmr_protect ) |
| 1480 | -clock `RST.ccu_rst_sys_clk |
| 1481 | -name wrm_protect_ilu_error_status_clear |
| 1482 | -module dmu |
| 1483 | -group rst_chkr |
| 1484 | */ |
| 1485 | |
| 1486 | // TO ENABLE :PEU Control Register (0x00680000 / 0x1) |
| 1487 | /* 0in constant |
| 1488 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ctl.tlu_ctl_0.tlu_ctl_csrbus_read_data |
| 1489 | -active (`RST.rst_wmr_protect ) |
| 1490 | -clock `RST.ccu_rst_sys_clk |
| 1491 | -name wrm_protect_peu_control |
| 1492 | -module peu |
| 1493 | -group rst_chkr |
| 1494 | */ |
| 1495 | |
| 1496 | // TO ENABLE :PEU Ingress Credits Initial Register (0x00680018 / 0x10000200C0) |
| 1497 | /* 0in constant |
| 1498 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tlu_ici.tlu_ici_0.tlu_ici_csrbus_read_data |
| 1499 | -active (`RST.rst_wmr_protect ) |
| 1500 | -clock `RST.ccu_rst_sys_clk |
| 1501 | -name wrm_protect_peu_ingress_credit_initial |
| 1502 | -module peu |
| 1503 | -group rst_chkr |
| 1504 | */ |
| 1505 | |
| 1506 | // TO ENABLE :PEU Other Event Log Enable Register (0x00681000 / 0xFFFFFF) |
| 1507 | /* 0in constant |
| 1508 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_log.oe_log_0.oe_log_csrbus_read_data |
| 1509 | -active (`RST.rst_wmr_protect ) |
| 1510 | -clock `RST.ccu_rst_sys_clk |
| 1511 | -name wrm_protect_peu_other_event_log_enable |
| 1512 | -module peu |
| 1513 | -group rst_chkr |
| 1514 | */ |
| 1515 | |
| 1516 | // TO ENABLE :PEU Other Event Status Clear Register (0x00681018 / 0x0) |
| 1517 | /* 0in constant |
| 1518 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.oe_err_0.oe_err_csrbus_read_data |
| 1519 | -active (`RST.rst_wmr_protect ) |
| 1520 | -clock `RST.ccu_rst_sys_clk |
| 1521 | -name wrm_protect_peu_other_event_status_clear |
| 1522 | -module peu |
| 1523 | -group rst_chkr |
| 1524 | */ |
| 1525 | |
| 1526 | // TO ENABLE :PEU Receive Other Event Header1 Log Register (0x00681028 / 0x0) |
| 1527 | |
| 1528 | /* 0in constant |
| 1529 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.roe_hdr1.roe_hdr1_0.roe_hdr1_csrbus_read_data |
| 1530 | -active (`RST.rst_wmr_protect & (|`CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.oe_err_0.oe_err_csrbus_read_data)) |
| 1531 | -clock `RST.ccu_rst_sys_clk |
| 1532 | -name wrm_protect_peu_receive_other_event_header1_log |
| 1533 | -module peu |
| 1534 | -group rst_chkr |
| 1535 | */ |
| 1536 | |
| 1537 | // TO ENABLE :PEU Receive Other Event Header2 Log Register (0x00681030 / 0x0) |
| 1538 | |
| 1539 | /* 0in constant |
| 1540 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.roe_hdr2.roe_hdr2_0.roe_hdr2_csrbus_read_data |
| 1541 | -active (`RST.rst_wmr_protect & (|`CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.oe_err_0.oe_err_csrbus_read_data)) |
| 1542 | -clock `RST.ccu_rst_sys_clk |
| 1543 | -name wrm_protect_peu_receive_other_event_header2_log |
| 1544 | -module peu |
| 1545 | -group rst_chkr |
| 1546 | */ |
| 1547 | |
| 1548 | // TO ENABLE :PEU Transmit Other Event Header1 Log Register (0x00681038 / 0x0) |
| 1549 | |
| 1550 | /* 0in constant |
| 1551 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.toe_hdr1.toe_hdr1_0.toe_hdr1_csrbus_read_data |
| 1552 | -active (`RST.rst_wmr_protect & (|`CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.oe_err_0.oe_err_csrbus_read_data)) |
| 1553 | -clock `RST.ccu_rst_sys_clk |
| 1554 | -name wrm_protect_peu_transmit_other_event_header1_log |
| 1555 | -module peu |
| 1556 | -group rst_chkr |
| 1557 | */ |
| 1558 | |
| 1559 | // TO ENABLE :PEU Transmit Other Event Header2 Log Register (0x00681040 / 0x0) |
| 1560 | |
| 1561 | /* 0in constant |
| 1562 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.toe_hdr2.toe_hdr2_0.toe_hdr2_csrbus_read_data |
| 1563 | -active (`RST.rst_wmr_protect & (|`CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.oe_err.oe_err_0.oe_err_csrbus_read_data)) |
| 1564 | -clock `RST.ccu_rst_sys_clk |
| 1565 | -name wrm_protect_peu_transmit_other_event_header2_log |
| 1566 | -module peu |
| 1567 | -group rst_chkr |
| 1568 | */ |
| 1569 | |
| 1570 | // TO ENABLE :PEU Uncorrectable Error Log Enable Register (0x00691000 / 0x17F011) |
| 1571 | /* 0in constant |
| 1572 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_log.ue_log_0.ue_log_csrbus_read_data |
| 1573 | -active (`RST.rst_wmr_protect ) |
| 1574 | -clock `RST.ccu_rst_sys_clk |
| 1575 | -name wrm_protect_peu_uncorrectible_error_log_enable |
| 1576 | -module peu |
| 1577 | -group rst_chkr |
| 1578 | */ |
| 1579 | |
| 1580 | // TO ENABLE :PEU Uncorrectable Error Status Clear Register (0x00691018 / 0x0) |
| 1581 | /* 0in constant |
| 1582 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.ue_err_0.ue_err_csrbus_read_data |
| 1583 | -active (`RST.rst_wmr_protect ) |
| 1584 | -clock `RST.ccu_rst_sys_clk |
| 1585 | -name wrm_protect_peu_uncorrectible_error_status_clear |
| 1586 | -module peu |
| 1587 | -group rst_chkr |
| 1588 | */ |
| 1589 | |
| 1590 | // TO ENABLE :PEU Receive Uncorrectable Error Header1 Log Register (0x00691028 |
| 1591 | |
| 1592 | /* 0in constant |
| 1593 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.rue_hdr1.rue_hdr1_0.rue_hdr1_csrbus_read_data |
| 1594 | -active (`RST.rst_wmr_protect & (|`CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.ue_err_0.ue_err_csrbus_read_data)) |
| 1595 | -clock `RST.ccu_rst_sys_clk |
| 1596 | -name wrm_protect_peu_receive_uncorrectible_error_header1_log |
| 1597 | -module peu |
| 1598 | -group rst_chkr |
| 1599 | */ |
| 1600 | |
| 1601 | // TO ENABLE :PEU Receive Uncorrectable Error Header2 Log Register (0x00691030 / |
| 1602 | |
| 1603 | /* 0in constant |
| 1604 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.rue_hdr2.rue_hdr2_0.rue_hdr2_csrbus_read_data |
| 1605 | -active (`RST.rst_wmr_protect & (|`CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.ue_err_0.ue_err_csrbus_read_data)) |
| 1606 | -clock `RST.ccu_rst_sys_clk |
| 1607 | -name wrm_protect_peu_receive_uncorrectible_error_header2_log |
| 1608 | -module peu |
| 1609 | -group rst_chkr |
| 1610 | */ |
| 1611 | |
| 1612 | // TO ENABLE :PEU Transmit Uncorrectable Error Header1 Log Register (0x00691038 |
| 1613 | |
| 1614 | /* 0in constant |
| 1615 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tue_hdr1.tue_hdr1_0.tue_hdr1_csrbus_read_data |
| 1616 | -active (`RST.rst_wmr_protect & (|`CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.ue_err_0.ue_err_csrbus_read_data)) |
| 1617 | -clock `RST.ccu_rst_sys_clk |
| 1618 | -name wrm_protect_peu_transmit_uncorrectible_error_header1_log |
| 1619 | -module peu |
| 1620 | -group rst_chkr |
| 1621 | */ |
| 1622 | |
| 1623 | // TO ENABLE :PEU Transmit Uncorrectable Error Header2 Log Register (0x00691040 / 0x0) |
| 1624 | |
| 1625 | /* 0in constant |
| 1626 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.tue_hdr2.tue_hdr2_0.tue_hdr2_csrbus_read_data |
| 1627 | -active (`RST.rst_wmr_protect & (|`CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ue_err.ue_err_0.ue_err_csrbus_read_data)) |
| 1628 | -clock `RST.ccu_rst_sys_clk |
| 1629 | -name wrm_protect_peu_transmit_uncorrectible_error_header2_log |
| 1630 | -module peu |
| 1631 | -group rst_chkr |
| 1632 | */ |
| 1633 | |
| 1634 | // TO ENABLE :PEU Correctable Error Log Enable Register (0x006A1000 / 0x11C1) |
| 1635 | /* 0in constant |
| 1636 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_log.ce_log_0.ce_log_csrbus_read_data |
| 1637 | -active (`RST.rst_wmr_protect ) |
| 1638 | -clock `RST.ccu_rst_sys_clk |
| 1639 | -name wrm_protect_peu_correctible_error_log_enable |
| 1640 | -module peu |
| 1641 | -group rst_chkr |
| 1642 | */ |
| 1643 | |
| 1644 | // TO ENABLE :PEU Correctable Error Status Clear Register (0x006A1018 / 0x0) |
| 1645 | /* 0in constant |
| 1646 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.ce_err.ce_err_0.ce_err_csrbus_read_data |
| 1647 | -active (`RST.rst_wmr_protect ) |
| 1648 | -clock `RST.ccu_rst_sys_clk |
| 1649 | -name wrm_protect_peu_correctible_error_status_clear |
| 1650 | -module peu |
| 1651 | -group rst_chkr |
| 1652 | */ |
| 1653 | |
| 1654 | // TO ENABLE :PEU DLPL/SERDES Revision Register (0x006E2000 / 0x0) |
| 1655 | /* 0in constant |
| 1656 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.peu_dlpl_serdes_rev.peu_dlpl_serdes_rev_0.peu_dlpl_serdes_rev_csrbus_read_data |
| 1657 | -active (`RST.rst_wmr_protect ) |
| 1658 | -clock `RST.ccu_rst_sys_clk |
| 1659 | -name wrm_protect_peu_DLPL_serdes_revision |
| 1660 | -module peu |
| 1661 | -group rst_chkr |
| 1662 | */ |
| 1663 | |
| 1664 | // TO ENABLE :PEU DLPL Event/Error Log Enable Register (0x006E2108) |
| 1665 | /* 0in constant |
| 1666 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_log_en.event_err_log_en_0.event_err_log_en_csrbus_read_data |
| 1667 | -active (`RST.rst_wmr_protect ) |
| 1668 | -clock `RST.ccu_rst_sys_clk |
| 1669 | -name wrm_protect_peu_DLPL_event_log_enable |
| 1670 | -module peu |
| 1671 | -group rst_chkr |
| 1672 | */ |
| 1673 | |
| 1674 | // TO ENABLE :PEU DLPL Event/Error Status Clear Register (0x006E2120 / 0x0) |
| 1675 | /* 0in constant |
| 1676 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.event_err_sts_clr.event_err_sts_clr_0.event_err_sts_clr_csrbus_read_data |
| 1677 | -active (`RST.rst_wmr_protect ) |
| 1678 | -clock `RST.ccu_rst_sys_clk |
| 1679 | -name wrm_protect_peu_DLPL_event_status_clear |
| 1680 | -module peu |
| 1681 | -group rst_chkr |
| 1682 | */ |
| 1683 | |
| 1684 | // TO ENABLE :PEU SERDES PLL Control/Status Register (0x006E2200 / 0x1) |
| 1685 | /* 0in constant |
| 1686 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_pll.serdes_pll_0.serdes_pll_csrbus_read_data |
| 1687 | -active (`RST.rst_wmr_protect ) |
| 1688 | -clock `RST.ccu_rst_sys_clk |
| 1689 | -name wrm_protect_peu_serdes_pll_control |
| 1690 | -module peu |
| 1691 | -group rst_chkr |
| 1692 | */ |
| 1693 | |
| 1694 | //// TO ENABLE :PEU SERDES Receiver Lane 0 Control Register (0x006E2300 - |
| 1695 | |
| 1696 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_0.serdes_receiver_lane_ctl_csrbus_read_data |
| 1697 | // -active (`RST.rst_wmr_protect ) |
| 1698 | // -clock `RST.ccu_rst_sys_clk |
| 1699 | // -name wrm_protect_peu_serdes_receiver_lane_0 |
| 1700 | // -module peu |
| 1701 | // -group rst_chkr |
| 1702 | //*/ |
| 1703 | // |
| 1704 | //// TO ENABLE :PEU SERDES Receiver Lane 1 Control Register (0x006E2300 - |
| 1705 | |
| 1706 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_1.serdes_receiver_lane_ctl_csrbus_read_data |
| 1707 | // -active (`RST.rst_wmr_protect ) |
| 1708 | // -clock `RST.ccu_rst_sys_clk |
| 1709 | // -name wrm_protect_peu_serdes_receiver_lane_1 |
| 1710 | // -module peu |
| 1711 | // -group rst_chkr |
| 1712 | //*/ |
| 1713 | // |
| 1714 | //// TO ENABLE :PEU SERDES Receiver Lane 2 Control Register (0x006E2300 - |
| 1715 | |
| 1716 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_2.serdes_receiver_lane_ctl_csrbus_read_data |
| 1717 | // -active (`RST.rst_wmr_protect ) |
| 1718 | // -clock `RST.ccu_rst_sys_clk |
| 1719 | // -name wrm_protect_peu_serdes_receiver_lane_2 |
| 1720 | // -module peu |
| 1721 | // -group rst_chkr |
| 1722 | //*/ |
| 1723 | // |
| 1724 | //// TO ENABLE :PEU SERDES Receiver Lane 3 Control Register (0x006E2300 - |
| 1725 | |
| 1726 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_3.serdes_receiver_lane_ctl_csrbus_read_data |
| 1727 | // -active (`RST.rst_wmr_protect ) |
| 1728 | // -clock `RST.ccu_rst_sys_clk |
| 1729 | // -name wrm_protect_peu_serdes_receiver_lane_3 |
| 1730 | // -module peu |
| 1731 | // -group rst_chkr |
| 1732 | //*/ |
| 1733 | // |
| 1734 | //// TO ENABLE :PEU SERDES Receiver Lane 4 Control Register (0x006E2300 - |
| 1735 | |
| 1736 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_4.serdes_receiver_lane_ctl_csrbus_read_data |
| 1737 | // -active (`RST.rst_wmr_protect ) |
| 1738 | // -clock `RST.ccu_rst_sys_clk |
| 1739 | // -name wrm_protect_peu_serdes_receiver_lane_4 |
| 1740 | // -module peu |
| 1741 | // -group rst_chkr |
| 1742 | //*/ |
| 1743 | // |
| 1744 | //// TO ENABLE :PEU SERDES Receiver Lane 5 Control Register (0x006E2300 - |
| 1745 | |
| 1746 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_5.serdes_receiver_lane_ctl_csrbus_read_data |
| 1747 | // -active (`RST.rst_wmr_protect ) |
| 1748 | // -clock `RST.ccu_rst_sys_clk |
| 1749 | // -name wrm_protect_peu_serdes_receiver_lane_5 |
| 1750 | // -module peu |
| 1751 | // -group rst_chkr |
| 1752 | //*/ |
| 1753 | // |
| 1754 | //// TO ENABLE :PEU SERDES Receiver Lane 6 Control Register (0x006E2300 - |
| 1755 | |
| 1756 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_6.serdes_receiver_lane_ctl_csrbus_read_data |
| 1757 | // -active (`RST.rst_wmr_protect ) |
| 1758 | // -clock `RST.ccu_rst_sys_clk |
| 1759 | // -name wrm_protect_peu_serdes_receiver_lane_6 |
| 1760 | // -module peu |
| 1761 | // -group rst_chkr |
| 1762 | //*/ |
| 1763 | // |
| 1764 | //// TO ENABLE :PEU SERDES Receiver Lane 7 Control Register (0x006E2300 - |
| 1765 | |
| 1766 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_ctl.serdes_receiver_lane_ctl_7.serdes_receiver_lane_ctl_csrbus_read_data |
| 1767 | // -active (`RST.rst_wmr_protect ) |
| 1768 | // -clock `RST.ccu_rst_sys_clk |
| 1769 | // -name wrm_protect_peu_serdes_receiver_lane_7 |
| 1770 | // -module peu |
| 1771 | // -group rst_chkr |
| 1772 | //*/ |
| 1773 | // |
| 1774 | //// TO ENABLE :PEU SERDES Receiver Lane 0 Status Register (0x006E2380 - 0x006E23B8 / 0x0) |
| 1775 | |
| 1776 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_0.serdes_receiver_lane_status_csrbus_read_data |
| 1777 | // -active (`RST.rst_wmr_protect ) |
| 1778 | // -clock `RST.ccu_rst_sys_clk |
| 1779 | // -name wrm_protect_peu_serdes_receiver_lane_status_0 |
| 1780 | // -module peu |
| 1781 | // -group rst_chkr |
| 1782 | //*/ |
| 1783 | // |
| 1784 | //// TO ENABLE :PEU SERDES Receiver Lane 1 Status Register (0x006E2380 - 0x006E23B8 / 0x0) |
| 1785 | |
| 1786 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_1.serdes_receiver_lane_status_csrbus_read_data |
| 1787 | // -active (`RST.rst_wmr_protect ) |
| 1788 | // -clock `RST.ccu_rst_sys_clk |
| 1789 | // -name wrm_protect_peu_serdes_receiver_lane_status_1 |
| 1790 | // -module peu |
| 1791 | // -group rst_chkr |
| 1792 | //*/ |
| 1793 | // |
| 1794 | //// TO ENABLE :PEU SERDES Receiver Lane 2 Status Register (0x006E2380 - 0x006E23B8 / 0x0) |
| 1795 | |
| 1796 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_2.serdes_receiver_lane_status_csrbus_read_data |
| 1797 | // -active (`RST.rst_wmr_protect ) |
| 1798 | // -clock `RST.ccu_rst_sys_clk |
| 1799 | // -name wrm_protect_peu_serdes_receiver_lane_status_2 |
| 1800 | // -module peu |
| 1801 | // -group rst_chkr |
| 1802 | //*/ |
| 1803 | // |
| 1804 | //// TO ENABLE :PEU SERDES Receiver Lane 3 Status Register (0x006E2380 - 0x006E23B8 / 0x0) |
| 1805 | |
| 1806 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_3.serdes_receiver_lane_status_csrbus_read_data |
| 1807 | // -active (`RST.rst_wmr_protect ) |
| 1808 | // -clock `RST.ccu_rst_sys_clk |
| 1809 | // -name wrm_protect_peu_serdes_receiver_lane_status_3 |
| 1810 | // -module peu |
| 1811 | // -group rst_chkr |
| 1812 | //*/ |
| 1813 | // |
| 1814 | //// TO ENABLE :PEU SERDES Receiver Lane 4 Status Register (0x006E2380 - 0x006E23B8 / 0x0) |
| 1815 | |
| 1816 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_4.serdes_receiver_lane_status_csrbus_read_data |
| 1817 | // -active (`RST.rst_wmr_protect ) |
| 1818 | // -clock `RST.ccu_rst_sys_clk |
| 1819 | // -name wrm_protect_peu_serdes_receiver_lane_status_4 |
| 1820 | // -module peu |
| 1821 | // -group rst_chkr |
| 1822 | //*/ |
| 1823 | // |
| 1824 | //// TO ENABLE :PEU SERDES Receiver Lane 5 Status Register (0x006E2380 - 0x006E23B8 / 0x0) |
| 1825 | |
| 1826 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_5.serdes_receiver_lane_status_csrbus_read_data |
| 1827 | // -active (`RST.rst_wmr_protect ) |
| 1828 | // -clock `RST.ccu_rst_sys_clk |
| 1829 | // -name wrm_protect_peu_serdes_receiver_lane_status_5 |
| 1830 | // -module peu |
| 1831 | // -group rst_chkr |
| 1832 | //*/ |
| 1833 | // |
| 1834 | //// TO ENABLE :PEU SERDES Receiver Lane 6 Status Register (0x006E2380 - 0x006E23B8 / 0x0) |
| 1835 | |
| 1836 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_6.serdes_receiver_lane_status_csrbus_read_data |
| 1837 | // -active (`RST.rst_wmr_protect ) |
| 1838 | // -clock `RST.ccu_rst_sys_clk |
| 1839 | // -name wrm_protect_peu_serdes_receiver_lane_status_6 |
| 1840 | // -module peu |
| 1841 | // -group rst_chkr |
| 1842 | //*/ |
| 1843 | // |
| 1844 | //// TO ENABLE :PEU SERDES Receiver Lane 7 Status Register (0x006E2380 - 0x006E23B8 / 0x0) |
| 1845 | |
| 1846 | // -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_receiver_lane_status.serdes_receiver_lane_status_7.serdes_receiver_lane_status_csrbus_read_data |
| 1847 | // -active (`RST.rst_wmr_protect ) |
| 1848 | // -clock `RST.ccu_rst_sys_clk |
| 1849 | // -name wrm_protect_peu_serdes_receiver_lane_status_7 |
| 1850 | // -module peu |
| 1851 | // -group rst_chkr |
| 1852 | //*/ |
| 1853 | |
| 1854 | // TO ENABLE :PEU SERDES Transmitter Lane 0 Control Register (0x006E2400 - |
| 1855 | /* 0in constant |
| 1856 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_0.serdes_xmitter_lane_ctl_csrbus_read_data |
| 1857 | -active (`RST.rst_wmr_protect ) |
| 1858 | -clock `RST.ccu_rst_sys_clk |
| 1859 | -name wrm_protect_peu_serdes_transmitter_lane_0 |
| 1860 | -module peu |
| 1861 | -group rst_chkr |
| 1862 | */ |
| 1863 | |
| 1864 | // TO ENABLE :PEU SERDES Transmitter Lane 1 Control Register (0x006E2400 - |
| 1865 | /* 0in constant |
| 1866 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_1.serdes_xmitter_lane_ctl_csrbus_read_data |
| 1867 | -active (`RST.rst_wmr_protect ) |
| 1868 | -clock `RST.ccu_rst_sys_clk |
| 1869 | -name wrm_protect_peu_serdes_transmitter_lane_1 |
| 1870 | -module peu |
| 1871 | -group rst_chkr |
| 1872 | */ |
| 1873 | |
| 1874 | // TO ENABLE :PEU SERDES Transmitter Lane 2 Control Register (0x006E2400 - |
| 1875 | /* 0in constant |
| 1876 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_2.serdes_xmitter_lane_ctl_csrbus_read_data |
| 1877 | -active (`RST.rst_wmr_protect ) |
| 1878 | -clock `RST.ccu_rst_sys_clk |
| 1879 | -name wrm_protect_peu_serdes_transmitter_lane_2 |
| 1880 | -module peu |
| 1881 | -group rst_chkr |
| 1882 | */ |
| 1883 | |
| 1884 | // TO ENABLE :PEU SERDES Transmitter Lane 3 Control Register (0x006E2400 - |
| 1885 | /* 0in constant |
| 1886 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_3.serdes_xmitter_lane_ctl_csrbus_read_data |
| 1887 | -active (`RST.rst_wmr_protect ) |
| 1888 | -clock `RST.ccu_rst_sys_clk |
| 1889 | -name wrm_protect_peu_serdes_transmitter_lane_3 |
| 1890 | -module peu |
| 1891 | -group rst_chkr |
| 1892 | */ |
| 1893 | |
| 1894 | // TO ENABLE :PEU SERDES Transmitter Lane 4 Control Register (0x006E2400 - |
| 1895 | /* 0in constant |
| 1896 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_4.serdes_xmitter_lane_ctl_csrbus_read_data |
| 1897 | -active (`RST.rst_wmr_protect ) |
| 1898 | -clock `RST.ccu_rst_sys_clk |
| 1899 | -name wrm_protect_peu_serdes_transmitter_lane_4 |
| 1900 | -module peu |
| 1901 | -group rst_chkr |
| 1902 | */ |
| 1903 | |
| 1904 | // TO ENABLE :PEU SERDES Transmitter Lane 5 Control Register (0x006E2400 - |
| 1905 | /* 0in constant |
| 1906 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_5.serdes_xmitter_lane_ctl_csrbus_read_data |
| 1907 | -active (`RST.rst_wmr_protect ) |
| 1908 | -clock `RST.ccu_rst_sys_clk |
| 1909 | -name wrm_protect_peu_serdes_transmitter_lane_5 |
| 1910 | -module peu |
| 1911 | -group rst_chkr |
| 1912 | */ |
| 1913 | |
| 1914 | // TO ENABLE :PEU SERDES Transmitter Lane 6 Control Register (0x006E2400 - |
| 1915 | /* 0in constant |
| 1916 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_6.serdes_xmitter_lane_ctl_csrbus_read_data |
| 1917 | -active (`RST.rst_wmr_protect ) |
| 1918 | -clock `RST.ccu_rst_sys_clk |
| 1919 | -name wrm_protect_peu_serdes_transmitter_lane_6 |
| 1920 | -module peu |
| 1921 | -group rst_chkr |
| 1922 | */ |
| 1923 | |
| 1924 | // TO ENABLE :PEU SERDES Transmitter Lane 7 Control Register (0x006E2400 - |
| 1925 | /* 0in constant |
| 1926 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_ctl.serdes_xmitter_lane_ctl_7.serdes_xmitter_lane_ctl_csrbus_read_data |
| 1927 | -active (`RST.rst_wmr_protect ) |
| 1928 | -clock `RST.ccu_rst_sys_clk |
| 1929 | -name wrm_protect_peu_serdes_transmitter_lane_7 |
| 1930 | -module peu |
| 1931 | -group rst_chkr |
| 1932 | */ |
| 1933 | |
| 1934 | // TO ENABLE :PEU SERDES Transmitter Lane 0 Status Register (0x006E2480 - 0x006E24B8 / 0x0) |
| 1935 | /* 0in constant |
| 1936 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_0.serdes_xmitter_lane_status_csrbus_read_data |
| 1937 | -active (`RST.rst_wmr_protect ) |
| 1938 | -clock `RST.ccu_rst_sys_clk |
| 1939 | -name wrm_protect_peu_serdes_transmitter_lane_status_0 |
| 1940 | -module peu |
| 1941 | -group rst_chkr |
| 1942 | */ |
| 1943 | |
| 1944 | // TO ENABLE :PEU SERDES Transmitter Lane 1 Status Register (0x006E2480 - 0x006E24B8 / 0x0) |
| 1945 | /* 0in constant |
| 1946 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_1.serdes_xmitter_lane_status_csrbus_read_data |
| 1947 | -active (`RST.rst_wmr_protect ) |
| 1948 | -clock `RST.ccu_rst_sys_clk |
| 1949 | -name wrm_protect_peu_serdes_transmitter_lane_status_1 |
| 1950 | -module peu |
| 1951 | -group rst_chkr |
| 1952 | */ |
| 1953 | |
| 1954 | // TO ENABLE :PEU SERDES Transmitter Lane 2 Status Register (0x006E2480 - 0x006E24B8 / 0x0) |
| 1955 | /* 0in constant |
| 1956 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_2.serdes_xmitter_lane_status_csrbus_read_data |
| 1957 | -active (`RST.rst_wmr_protect ) |
| 1958 | -clock `RST.ccu_rst_sys_clk |
| 1959 | -name wrm_protect_peu_serdes_transmitter_lane_status_2 |
| 1960 | -module peu |
| 1961 | -group rst_chkr |
| 1962 | */ |
| 1963 | |
| 1964 | // TO ENABLE :PEU SERDES Transmitter Lane 3 Status Register (0x006E2480 - 0x006E24B8 / 0x0) |
| 1965 | /* 0in constant |
| 1966 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_3.serdes_xmitter_lane_status_csrbus_read_data |
| 1967 | -active (`RST.rst_wmr_protect ) |
| 1968 | -clock `RST.ccu_rst_sys_clk |
| 1969 | -name wrm_protect_peu_serdes_transmitter_lane_status_3 |
| 1970 | -module peu |
| 1971 | -group rst_chkr |
| 1972 | */ |
| 1973 | |
| 1974 | // TO ENABLE :PEU SERDES Transmitter Lane 4 Status Register (0x006E2480 - 0x006E24B8 / 0x0) |
| 1975 | /* 0in constant |
| 1976 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_4.serdes_xmitter_lane_status_csrbus_read_data |
| 1977 | -active (`RST.rst_wmr_protect ) |
| 1978 | -clock `RST.ccu_rst_sys_clk |
| 1979 | -name wrm_protect_peu_serdes_transmitter_lane_status_4 |
| 1980 | -module peu |
| 1981 | -group rst_chkr |
| 1982 | */ |
| 1983 | |
| 1984 | // TO ENABLE :PEU SERDES Transmitter Lane 5 Status Register (0x006E2480 - 0x006E24B8 / 0x0) |
| 1985 | /* 0in constant |
| 1986 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_5.serdes_xmitter_lane_status_csrbus_read_data |
| 1987 | -active (`RST.rst_wmr_protect ) |
| 1988 | -clock `RST.ccu_rst_sys_clk |
| 1989 | -name wrm_protect_peu_serdes_transmitter_lane_status_5 |
| 1990 | -module peu |
| 1991 | -group rst_chkr |
| 1992 | */ |
| 1993 | |
| 1994 | // TO ENABLE :PEU SERDES Transmitter Lane 6 Status Register (0x006E2480 - 0x006E24B8 / 0x0) |
| 1995 | /* 0in constant |
| 1996 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_6.serdes_xmitter_lane_status_csrbus_read_data |
| 1997 | -active (`RST.rst_wmr_protect ) |
| 1998 | -clock `RST.ccu_rst_sys_clk |
| 1999 | -name wrm_protect_peu_serdes_transmitter_lane_status_6 |
| 2000 | -module peu |
| 2001 | -group rst_chkr |
| 2002 | */ |
| 2003 | |
| 2004 | // TO ENABLE :PEU SERDES Transmitter Lane 7 Status Register (0x006E2480 - 0x006E24B8 / 0x0) |
| 2005 | /* 0in constant |
| 2006 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_xmitter_lane_status.serdes_xmitter_lane_status_7.serdes_xmitter_lane_status_csrbus_read_data |
| 2007 | -active (`RST.rst_wmr_protect ) |
| 2008 | -clock `RST.ccu_rst_sys_clk |
| 2009 | -name wrm_protect_peu_serdes_transmitter_lane_status_7 |
| 2010 | -module peu |
| 2011 | -group rst_chkr |
| 2012 | */ |
| 2013 | |
| 2014 | // TO ENABLE :PEU SERDES MACRO 0 Test Configuration Register (0x006E2500 - 0x006E2508 / 0x03) |
| 2015 | /* 0in constant |
| 2016 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_macro_test_cfg.serdes_macro_test_cfg_0.serdes_macro_test_cfg_csrbus_read_data |
| 2017 | -active (`RST.rst_wmr_protect ) |
| 2018 | -clock `RST.ccu_rst_sys_clk |
| 2019 | -name wrm_protect_peu_serdes_macro_test_conf_0 |
| 2020 | -module peu |
| 2021 | -group rst_chkr |
| 2022 | */ |
| 2023 | |
| 2024 | // TO ENABLE :PEU SERDES MACRO 1 Test Configuration Register (0x006E2500 - 0x006E2508 / 0x03) |
| 2025 | /* 0in constant |
| 2026 | -var `CPU.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_default_grp.serdes_macro_test_cfg.serdes_macro_test_cfg_1.serdes_macro_test_cfg_csrbus_read_data |
| 2027 | -active (`RST.rst_wmr_protect ) |
| 2028 | -clock `RST.ccu_rst_sys_clk |
| 2029 | -name wrm_protect_peu_serdes_macro_test_conf_1 |
| 2030 | -module peu |
| 2031 | -group rst_chkr |
| 2032 | */ |
| 2033 | |
| 2034 | |
| 2035 | // L2 |
| 2036 | //L2 Error Enable register 0xAA-0000-0000 or 0xBA-0000-0000 |
| 2037 | /* 0in constant |
| 2038 | -var `CPU.l2t0.csr.ff_csr_l2_erren_d1.dout |
| 2039 | -active (`RST.rst_wmr_protect ) |
| 2040 | -clock `RST.ccu_rst_sys_clk |
| 2041 | -name wrm_protect_l2_error_enable |
| 2042 | -module l2t |
| 2043 | -group rst_chkr |
| 2044 | */ |
| 2045 | |
| 2046 | //L2 Error Status Reg 0xAB-0000-0000 or 0xBB-0000-0000 |
| 2047 | /* 0in constant |
| 2048 | -var `CPU.l2t0.csr.csr_l2_errstate_reg |
| 2049 | -active (`RST.rst_wmr_protect ) |
| 2050 | -clock `RST.ccu_rst_sys_clk |
| 2051 | -name wrm_protect_l2_error_status |
| 2052 | -module l2t |
| 2053 | -group rst_chkr |
| 2054 | */ |
| 2055 | //L2 Error Address Unknown 0xAC-0000-0000 or 0xBC-0000-0000 |
| 2056 | /* 0in constant |
| 2057 | -var `CPU.l2t0.csr.ff_csr_l2_erraddr_d1.dout |
| 2058 | -active (`RST.rst_wmr_protect ) |
| 2059 | -clock `RST.ccu_rst_sys_clk |
| 2060 | -name wrm_protect_l2_error_address |
| 2061 | -module l2t |
| 2062 | -group rst_chkr |
| 2063 | */ |
| 2064 | //L2 Notdata Error Register 0xAE-0000-0000 or 0xBE-0000-0000 |
| 2065 | /* 0in constant |
| 2066 | -var `CPU.l2t0.csr.csr_l2_notdata_reg |
| 2067 | -active (`RST.rst_wmr_protect ) |
| 2068 | -clock `RST.ccu_rst_sys_clk |
| 2069 | -name wrm_protect_l2_notdata_error |
| 2070 | -module l2t |
| 2071 | -group rst_chkr |
| 2072 | */ |
| 2073 | //L2 Error Inject 0 0xAD-0000- 0000 or 0xBD-0000-0000 |
| 2074 | /* 0in constant |
| 2075 | -var `CPU.l2t0.csr.ff_csr_l2_errinj_d1.dout |
| 2076 | -active (`RST.rst_wmr_protect ) |
| 2077 | -clock `RST.ccu_rst_sys_clk |
| 2078 | -name wrm_protect_l2_error_inject |
| 2079 | -module l2t |
| 2080 | -group rst_chkr |
| 2081 | */ |
| 2082 | //L2 Mask Reg 0 0xAF-0000-0000 |
| 2083 | /* 0in constant |
| 2084 | -var `CPU.l2t0.csr.ff_l2_mask_register.dout |
| 2085 | -active (`RST.rst_wmr_protect ) |
| 2086 | -clock `RST.ccu_rst_sys_clk |
| 2087 | -name wrm_protect_l2_mask |
| 2088 | -module l2t |
| 2089 | -group rst_chkr |
| 2090 | */ |
| 2091 | //L2 Address Compare Reg 0 0xBF-0000-0000 |
| 2092 | /* 0in constant |
| 2093 | -var `CPU.l2t0.csr.ff_l2_compare_register.dout |
| 2094 | -active (`RST.rst_wmr_protect ) |
| 2095 | -clock `RST.ccu_rst_sys_clk |
| 2096 | -name wrm_protect_l2_address_compare |
| 2097 | -module l2t |
| 2098 | -group rst_chkr |
| 2099 | */ |
| 2100 | |
| 2101 | //l2t1 |
| 2102 | //L2 Error Enable register 0xAA-0000-0000 or 0xBA-0000-0000 |
| 2103 | /* 0in constant |
| 2104 | -var `CPU.l2t1.csr.ff_csr_l2_erren_d1.dout |
| 2105 | -active (`RST.rst_wmr_protect ) |
| 2106 | -clock `RST.ccu_rst_sys_clk |
| 2107 | -name wrm_protect_l2_error_enable |
| 2108 | -module l2t |
| 2109 | -group rst_chkr |
| 2110 | */ |
| 2111 | |
| 2112 | //L2 Error Status Reg 0xAB-0000-0000 or 0xBB-0000-0000 |
| 2113 | /* 0in constant |
| 2114 | -var `CPU.l2t1.csr.csr_l2_errstate_reg |
| 2115 | -active (`RST.rst_wmr_protect ) |
| 2116 | -clock `RST.ccu_rst_sys_clk |
| 2117 | -name wrm_protect_l2_error_status |
| 2118 | -module l2t |
| 2119 | -group rst_chkr |
| 2120 | */ |
| 2121 | //L2 Error Address Unknown 0xAC-0000-0000 or 0xBC-0000-0000 |
| 2122 | /* 0in constant |
| 2123 | -var `CPU.l2t1.csr.ff_csr_l2_erraddr_d1.dout |
| 2124 | -active (`RST.rst_wmr_protect ) |
| 2125 | -clock `RST.ccu_rst_sys_clk |
| 2126 | -name wrm_protect_l2_error_address |
| 2127 | -module l2t |
| 2128 | -group rst_chkr |
| 2129 | */ |
| 2130 | //L2 Notdata Error Register 0xAE-0000-0000 or 0xBE-0000-0000 |
| 2131 | /* 0in constant |
| 2132 | -var `CPU.l2t1.csr.csr_l2_notdata_reg |
| 2133 | -active (`RST.rst_wmr_protect ) |
| 2134 | -clock `RST.ccu_rst_sys_clk |
| 2135 | -name wrm_protect_l2_notdata_error |
| 2136 | -module l2t |
| 2137 | -group rst_chkr |
| 2138 | */ |
| 2139 | //L2 Error Inject 0 0xAD-0000- 0000 or 0xBD-0000-0000 |
| 2140 | /* 0in constant |
| 2141 | -var `CPU.l2t1.csr.ff_csr_l2_errinj_d1.dout |
| 2142 | -active (`RST.rst_wmr_protect ) |
| 2143 | -clock `RST.ccu_rst_sys_clk |
| 2144 | -name wrm_protect_l2_error_inject |
| 2145 | -module l2t |
| 2146 | -group rst_chkr |
| 2147 | */ |
| 2148 | //L2 Mask Reg 0 0xAF-0000-0000 |
| 2149 | /* 0in constant |
| 2150 | -var `CPU.l2t1.csr.ff_l2_mask_register.dout |
| 2151 | -active (`RST.rst_wmr_protect ) |
| 2152 | -clock `RST.ccu_rst_sys_clk |
| 2153 | -name wrm_protect_l2_mask |
| 2154 | -module l2t |
| 2155 | -group rst_chkr |
| 2156 | */ |
| 2157 | //L2 Address Compare Reg 0 0xBF-0000-0000 |
| 2158 | /* 0in constant |
| 2159 | -var `CPU.l2t1.csr.ff_l2_compare_register.dout |
| 2160 | -active (`RST.rst_wmr_protect ) |
| 2161 | -clock `RST.ccu_rst_sys_clk |
| 2162 | -name wrm_protect_l2_address_compare |
| 2163 | -module l2t |
| 2164 | -group rst_chkr |
| 2165 | */ |
| 2166 | //l2t2 |
| 2167 | //L2 Error Enable register 0xAA-0000-0000 or 0xBA-0000-0000 |
| 2168 | /* 0in constant |
| 2169 | -var `CPU.l2t2.csr.ff_csr_l2_erren_d1.dout |
| 2170 | -active (`RST.rst_wmr_protect ) |
| 2171 | -clock `RST.ccu_rst_sys_clk |
| 2172 | -name wrm_protect_l2_error_enable |
| 2173 | -module l2t |
| 2174 | -group rst_chkr |
| 2175 | */ |
| 2176 | |
| 2177 | //L2 Error Status Reg 0xAB-0000-0000 or 0xBB-0000-0000 |
| 2178 | /* 0in constant |
| 2179 | -var `CPU.l2t2.csr.csr_l2_errstate_reg |
| 2180 | -active (`RST.rst_wmr_protect ) |
| 2181 | -clock `RST.ccu_rst_sys_clk |
| 2182 | -name wrm_protect_l2_error_status |
| 2183 | -module l2t |
| 2184 | -group rst_chkr |
| 2185 | */ |
| 2186 | //L2 Error Address Unknown 0xAC-0000-0000 or 0xBC-0000-0000 |
| 2187 | /* 0in constant |
| 2188 | -var `CPU.l2t2.csr.ff_csr_l2_erraddr_d1.dout |
| 2189 | -active (`RST.rst_wmr_protect ) |
| 2190 | -clock `RST.ccu_rst_sys_clk |
| 2191 | -name wrm_protect_l2_error_address |
| 2192 | -module l2t |
| 2193 | -group rst_chkr |
| 2194 | */ |
| 2195 | //L2 Notdata Error Register 0xAE-0000-0000 or 0xBE-0000-0000 |
| 2196 | /* 0in constant |
| 2197 | -var `CPU.l2t2.csr.csr_l2_notdata_reg |
| 2198 | -active (`RST.rst_wmr_protect ) |
| 2199 | -clock `RST.ccu_rst_sys_clk |
| 2200 | -name wrm_protect_l2_notdata_error |
| 2201 | -module l2t |
| 2202 | -group rst_chkr |
| 2203 | */ |
| 2204 | //L2 Error Inject 0 0xAD-0000- 0000 or 0xBD-0000-0000 |
| 2205 | /* 0in constant |
| 2206 | -var `CPU.l2t2.csr.ff_csr_l2_errinj_d1.dout |
| 2207 | -active (`RST.rst_wmr_protect ) |
| 2208 | -clock `RST.ccu_rst_sys_clk |
| 2209 | -name wrm_protect_l2_error_inject |
| 2210 | -module l2t |
| 2211 | -group rst_chkr |
| 2212 | */ |
| 2213 | //L2 Mask Reg 0 0xAF-0000-0000 |
| 2214 | /* 0in constant |
| 2215 | -var `CPU.l2t2.csr.ff_l2_mask_register.dout |
| 2216 | -active (`RST.rst_wmr_protect ) |
| 2217 | -clock `RST.ccu_rst_sys_clk |
| 2218 | -name wrm_protect_l2_mask |
| 2219 | -module l2t |
| 2220 | -group rst_chkr |
| 2221 | */ |
| 2222 | //L2 Address Compare Reg 0 0xBF-0000-0000 |
| 2223 | /* 0in constant |
| 2224 | -var `CPU.l2t2.csr.ff_l2_compare_register.dout |
| 2225 | -active (`RST.rst_wmr_protect ) |
| 2226 | -clock `RST.ccu_rst_sys_clk |
| 2227 | -name wrm_protect_l2_address_compare |
| 2228 | -module l2t |
| 2229 | -group rst_chkr |
| 2230 | */ |
| 2231 | |
| 2232 | //L2 Error Enable register 0xAA-0000-0000 or 0xBA-0000-0000 |
| 2233 | /* 0in constant |
| 2234 | -var `CPU.l2t3.csr.ff_csr_l2_erren_d1.dout |
| 2235 | -active (`RST.rst_wmr_protect ) |
| 2236 | -clock `RST.ccu_rst_sys_clk |
| 2237 | -name wrm_protect_l2_error_enable |
| 2238 | -module l2t |
| 2239 | -group rst_chkr |
| 2240 | */ |
| 2241 | |
| 2242 | //L2 Error Status Reg 0xAB-0000-0000 or 0xBB-0000-0000 |
| 2243 | /* 0in constant |
| 2244 | -var `CPU.l2t3.csr.csr_l2_errstate_reg |
| 2245 | -active (`RST.rst_wmr_protect ) |
| 2246 | -clock `RST.ccu_rst_sys_clk |
| 2247 | -name wrm_protect_l2_error_status |
| 2248 | -module l2t |
| 2249 | -group rst_chkr |
| 2250 | */ |
| 2251 | //L2 Error Address Unknown 0xAC-0000-0000 or 0xBC-0000-0000 |
| 2252 | /* 0in constant |
| 2253 | -var `CPU.l2t3.csr.ff_csr_l2_erraddr_d1.dout |
| 2254 | -active (`RST.rst_wmr_protect ) |
| 2255 | -clock `RST.ccu_rst_sys_clk |
| 2256 | -name wrm_protect_l2_error_address |
| 2257 | -module l2t |
| 2258 | -group rst_chkr |
| 2259 | */ |
| 2260 | //L2 Notdata Error Register 0xAE-0000-0000 or 0xBE-0000-0000 |
| 2261 | /* 0in constant |
| 2262 | -var `CPU.l2t3.csr.csr_l2_notdata_reg |
| 2263 | -active (`RST.rst_wmr_protect ) |
| 2264 | -clock `RST.ccu_rst_sys_clk |
| 2265 | -name wrm_protect_l2_notdata_error |
| 2266 | -module l2t |
| 2267 | -group rst_chkr |
| 2268 | */ |
| 2269 | //L2 Error Inject 0 0xAD-0000- 0000 or 0xBD-0000-0000 |
| 2270 | /* 0in constant |
| 2271 | -var `CPU.l2t3.csr.ff_csr_l2_errinj_d1.dout |
| 2272 | -active (`RST.rst_wmr_protect ) |
| 2273 | -clock `RST.ccu_rst_sys_clk |
| 2274 | -name wrm_protect_l2_error_inject |
| 2275 | -module l2t |
| 2276 | -group rst_chkr |
| 2277 | */ |
| 2278 | //L2 Mask Reg 0 0xAF-0000-0000 |
| 2279 | /* 0in constant |
| 2280 | -var `CPU.l2t3.csr.ff_l2_mask_register.dout |
| 2281 | -active (`RST.rst_wmr_protect ) |
| 2282 | -clock `RST.ccu_rst_sys_clk |
| 2283 | -name wrm_protect_l2_mask |
| 2284 | -module l2t |
| 2285 | -group rst_chkr |
| 2286 | */ |
| 2287 | //L2 Address Compare Reg 0 0xBF-0000-0000 |
| 2288 | /* 0in constant |
| 2289 | -var `CPU.l2t3.csr.ff_l2_compare_register.dout |
| 2290 | -active (`RST.rst_wmr_protect ) |
| 2291 | -clock `RST.ccu_rst_sys_clk |
| 2292 | -name wrm_protect_l2_address_compare |
| 2293 | -module l2t |
| 2294 | -group rst_chkr |
| 2295 | */ |
| 2296 | |
| 2297 | //l2t4 |
| 2298 | //L2 Error Enable register 0xAA-0000-0000 or 0xBA-0000-0000 |
| 2299 | /* 0in constant |
| 2300 | -var `CPU.l2t4.csr.ff_csr_l2_erren_d1.dout |
| 2301 | -active (`RST.rst_wmr_protect ) |
| 2302 | -clock `RST.ccu_rst_sys_clk |
| 2303 | -name wrm_protect_l2_error_enable |
| 2304 | -module l2t |
| 2305 | -group rst_chkr |
| 2306 | */ |
| 2307 | |
| 2308 | //L2 Error Status Reg 0xAB-0000-0000 or 0xBB-0000-0000 |
| 2309 | /* 0in constant |
| 2310 | -var `CPU.l2t4.csr.csr_l2_errstate_reg |
| 2311 | -active (`RST.rst_wmr_protect ) |
| 2312 | -clock `RST.ccu_rst_sys_clk |
| 2313 | -name wrm_protect_l2_error_status |
| 2314 | -module l2t |
| 2315 | -group rst_chkr |
| 2316 | */ |
| 2317 | //L2 Error Address Unknown 0xAC-0000-0000 or 0xBC-0000-0000 |
| 2318 | /* 0in constant |
| 2319 | -var `CPU.l2t4.csr.ff_csr_l2_erraddr_d1.dout |
| 2320 | -active (`RST.rst_wmr_protect ) |
| 2321 | -clock `RST.ccu_rst_sys_clk |
| 2322 | -name wrm_protect_l2_error_address |
| 2323 | -module l2t |
| 2324 | -group rst_chkr |
| 2325 | */ |
| 2326 | //L2 Notdata Error Register 0xAE-0000-0000 or 0xBE-0000-0000 |
| 2327 | /* 0in constant |
| 2328 | -var `CPU.l2t4.csr.csr_l2_notdata_reg |
| 2329 | -active (`RST.rst_wmr_protect ) |
| 2330 | -clock `RST.ccu_rst_sys_clk |
| 2331 | -name wrm_protect_l2_notdata_error |
| 2332 | -module l2t |
| 2333 | -group rst_chkr |
| 2334 | */ |
| 2335 | //L2 Error Inject 0 0xAD-0000- 0000 or 0xBD-0000-0000 |
| 2336 | /* 0in constant |
| 2337 | -var `CPU.l2t4.csr.ff_csr_l2_errinj_d1.dout |
| 2338 | -active (`RST.rst_wmr_protect ) |
| 2339 | -clock `RST.ccu_rst_sys_clk |
| 2340 | -name wrm_protect_l2_error_inject |
| 2341 | -module l2t |
| 2342 | -group rst_chkr |
| 2343 | */ |
| 2344 | //L2 Mask Reg 0 0xAF-0000-0000 |
| 2345 | /* 0in constant |
| 2346 | -var `CPU.l2t4.csr.ff_l2_mask_register.dout |
| 2347 | -active (`RST.rst_wmr_protect ) |
| 2348 | -clock `RST.ccu_rst_sys_clk |
| 2349 | -name wrm_protect_l2_mask |
| 2350 | -module l2t |
| 2351 | -group rst_chkr |
| 2352 | */ |
| 2353 | //L2 Address Compare Reg 0 0xBF-0000-0000 |
| 2354 | /* 0in constant |
| 2355 | -var `CPU.l2t4.csr.ff_l2_compare_register.dout |
| 2356 | -active (`RST.rst_wmr_protect ) |
| 2357 | -clock `RST.ccu_rst_sys_clk |
| 2358 | -name wrm_protect_l2_address_compare |
| 2359 | -module l2t |
| 2360 | -group rst_chkr |
| 2361 | */ |
| 2362 | |
| 2363 | //l2t5 |
| 2364 | //L2 Error Enable register 0xAA-0000-0000 or 0xBA-0000-0000 |
| 2365 | /* 0in constant |
| 2366 | -var `CPU.l2t5.csr.ff_csr_l2_erren_d1.dout |
| 2367 | -active (`RST.rst_wmr_protect ) |
| 2368 | -clock `RST.ccu_rst_sys_clk |
| 2369 | -name wrm_protect_l2_error_enable |
| 2370 | -module l2t |
| 2371 | -group rst_chkr |
| 2372 | */ |
| 2373 | |
| 2374 | //L2 Error Status Reg 0xAB-0000-0000 or 0xBB-0000-0000 |
| 2375 | /* 0in constant |
| 2376 | -var `CPU.l2t5.csr.csr_l2_errstate_reg |
| 2377 | -active (`RST.rst_wmr_protect ) |
| 2378 | -clock `RST.ccu_rst_sys_clk |
| 2379 | -name wrm_protect_l2_error_status |
| 2380 | -module l2t |
| 2381 | -group rst_chkr |
| 2382 | */ |
| 2383 | //L2 Error Address Unknown 0xAC-0000-0000 or 0xBC-0000-0000 |
| 2384 | /* 0in constant |
| 2385 | -var `CPU.l2t5.csr.ff_csr_l2_erraddr_d1.dout |
| 2386 | -active (`RST.rst_wmr_protect ) |
| 2387 | -clock `RST.ccu_rst_sys_clk |
| 2388 | -name wrm_protect_l2_error_address |
| 2389 | -module l2t |
| 2390 | -group rst_chkr |
| 2391 | */ |
| 2392 | //L2 Notdata Error Register 0xAE-0000-0000 or 0xBE-0000-0000 |
| 2393 | /* 0in constant |
| 2394 | -var `CPU.l2t5.csr.csr_l2_notdata_reg |
| 2395 | -active (`RST.rst_wmr_protect ) |
| 2396 | -clock `RST.ccu_rst_sys_clk |
| 2397 | -name wrm_protect_l2_notdata_error |
| 2398 | -module l2t |
| 2399 | -group rst_chkr |
| 2400 | */ |
| 2401 | //L2 Error Inject 0 0xAD-0000- 0000 or 0xBD-0000-0000 |
| 2402 | /* 0in constant |
| 2403 | -var `CPU.l2t5.csr.ff_csr_l2_errinj_d1.dout |
| 2404 | -active (`RST.rst_wmr_protect ) |
| 2405 | -clock `RST.ccu_rst_sys_clk |
| 2406 | -name wrm_protect_l2_error_inject |
| 2407 | -module l2t |
| 2408 | -group rst_chkr |
| 2409 | */ |
| 2410 | //L2 Mask Reg 0 0xAF-0000-0000 |
| 2411 | /* 0in constant |
| 2412 | -var `CPU.l2t5.csr.ff_l2_mask_register.dout |
| 2413 | -active (`RST.rst_wmr_protect ) |
| 2414 | -clock `RST.ccu_rst_sys_clk |
| 2415 | -name wrm_protect_l2_mask |
| 2416 | -module l2t |
| 2417 | -group rst_chkr |
| 2418 | */ |
| 2419 | //L2 Address Compare Reg 0 0xBF-0000-0000 |
| 2420 | /* 0in constant |
| 2421 | -var `CPU.l2t5.csr.ff_l2_compare_register.dout |
| 2422 | -active (`RST.rst_wmr_protect ) |
| 2423 | -clock `RST.ccu_rst_sys_clk |
| 2424 | -name wrm_protect_l2_address_compare |
| 2425 | -module l2t |
| 2426 | -group rst_chkr |
| 2427 | */ |
| 2428 | |
| 2429 | //l2t6 |
| 2430 | //L2 Error Enable register 0xAA-0000-0000 or 0xBA-0000-0000 |
| 2431 | /* 0in constant |
| 2432 | -var `CPU.l2t6.csr.ff_csr_l2_erren_d1.dout |
| 2433 | -active (`RST.rst_wmr_protect ) |
| 2434 | -clock `RST.ccu_rst_sys_clk |
| 2435 | -name wrm_protect_l2_error_enable |
| 2436 | -module l2t |
| 2437 | -group rst_chkr |
| 2438 | */ |
| 2439 | |
| 2440 | //L2 Error Status Reg 0xAB-0000-0000 or 0xBB-0000-0000 |
| 2441 | /* 0in constant |
| 2442 | -var `CPU.l2t6.csr.csr_l2_errstate_reg |
| 2443 | -active (`RST.rst_wmr_protect ) |
| 2444 | -clock `RST.ccu_rst_sys_clk |
| 2445 | -name wrm_protect_l2_error_status |
| 2446 | -module l2t |
| 2447 | -group rst_chkr |
| 2448 | */ |
| 2449 | //L2 Error Address Unknown 0xAC-0000-0000 or 0xBC-0000-0000 |
| 2450 | /* 0in constant |
| 2451 | -var `CPU.l2t6.csr.ff_csr_l2_erraddr_d1.dout |
| 2452 | -active (`RST.rst_wmr_protect ) |
| 2453 | -clock `RST.ccu_rst_sys_clk |
| 2454 | -name wrm_protect_l2_error_address |
| 2455 | -module l2t |
| 2456 | -group rst_chkr |
| 2457 | */ |
| 2458 | //L2 Notdata Error Register 0xAE-0000-0000 or 0xBE-0000-0000 |
| 2459 | /* 0in constant |
| 2460 | -var `CPU.l2t6.csr.csr_l2_notdata_reg |
| 2461 | -active (`RST.rst_wmr_protect ) |
| 2462 | -clock `RST.ccu_rst_sys_clk |
| 2463 | -name wrm_protect_l2_notdata_error |
| 2464 | -module l2t |
| 2465 | -group rst_chkr |
| 2466 | */ |
| 2467 | //L2 Error Inject 0 0xAD-0000- 0000 or 0xBD-0000-0000 |
| 2468 | /* 0in constant |
| 2469 | -var `CPU.l2t6.csr.ff_csr_l2_errinj_d1.dout |
| 2470 | -active (`RST.rst_wmr_protect ) |
| 2471 | -clock `RST.ccu_rst_sys_clk |
| 2472 | -name wrm_protect_l2_error_inject |
| 2473 | -module l2t |
| 2474 | -group rst_chkr |
| 2475 | */ |
| 2476 | //L2 Mask Reg 0 0xAF-0000-0000 |
| 2477 | /* 0in constant |
| 2478 | -var `CPU.l2t6.csr.ff_l2_mask_register.dout |
| 2479 | -active (`RST.rst_wmr_protect ) |
| 2480 | -clock `RST.ccu_rst_sys_clk |
| 2481 | -name wrm_protect_l2_mask |
| 2482 | -module l2t |
| 2483 | -group rst_chkr |
| 2484 | */ |
| 2485 | //L2 Address Compare Reg 0 0xBF-0000-0000 |
| 2486 | /* 0in constant |
| 2487 | -var `CPU.l2t6.csr.ff_l2_compare_register.dout |
| 2488 | -active (`RST.rst_wmr_protect ) |
| 2489 | -clock `RST.ccu_rst_sys_clk |
| 2490 | -name wrm_protect_l2_address_compare |
| 2491 | -module l2t |
| 2492 | -group rst_chkr |
| 2493 | */ |
| 2494 | |
| 2495 | //l2t7 |
| 2496 | //L2 Error Enable register 0xAA-0000-0000 or 0xBA-0000-0000 |
| 2497 | /* 0in constant |
| 2498 | -var `CPU.l2t7.csr.ff_csr_l2_erren_d1.dout |
| 2499 | -active (`RST.rst_wmr_protect ) |
| 2500 | -clock `RST.ccu_rst_sys_clk |
| 2501 | -name wrm_protect_l2_error_enable |
| 2502 | -module l2t |
| 2503 | -group rst_chkr |
| 2504 | */ |
| 2505 | |
| 2506 | //L2 Error Status Reg 0xAB-0000-0000 or 0xBB-0000-0000 |
| 2507 | /* 0in constant |
| 2508 | -var `CPU.l2t7.csr.csr_l2_errstate_reg |
| 2509 | -active (`RST.rst_wmr_protect ) |
| 2510 | -clock `RST.ccu_rst_sys_clk |
| 2511 | -name wrm_protect_l2_error_status |
| 2512 | -module l2t |
| 2513 | -group rst_chkr |
| 2514 | */ |
| 2515 | //L2 Error Address Unknown 0xAC-0000-0000 or 0xBC-0000-0000 |
| 2516 | /* 0in constant |
| 2517 | -var `CPU.l2t7.csr.ff_csr_l2_erraddr_d1.dout |
| 2518 | -active (`RST.rst_wmr_protect ) |
| 2519 | -clock `RST.ccu_rst_sys_clk |
| 2520 | -name wrm_protect_l2_error_address |
| 2521 | -module l2t |
| 2522 | -group rst_chkr |
| 2523 | */ |
| 2524 | //L2 Notdata Error Register 0xAE-0000-0000 or 0xBE-0000-0000 |
| 2525 | /* 0in constant |
| 2526 | -var `CPU.l2t7.csr.csr_l2_notdata_reg |
| 2527 | -active (`RST.rst_wmr_protect ) |
| 2528 | -clock `RST.ccu_rst_sys_clk |
| 2529 | -name wrm_protect_l2_notdata_error |
| 2530 | -module l2t |
| 2531 | -group rst_chkr |
| 2532 | */ |
| 2533 | //L2 Error Inject 0 0xAD-0000- 0000 or 0xBD-0000-0000 |
| 2534 | /* 0in constant |
| 2535 | -var `CPU.l2t7.csr.ff_csr_l2_errinj_d1.dout |
| 2536 | -active (`RST.rst_wmr_protect ) |
| 2537 | -clock `RST.ccu_rst_sys_clk |
| 2538 | -name wrm_protect_l2_error_inject |
| 2539 | -module l2t |
| 2540 | -group rst_chkr |
| 2541 | */ |
| 2542 | //L2 Mask Reg 0 0xAF-0000-0000 |
| 2543 | /* 0in constant |
| 2544 | -var `CPU.l2t7.csr.ff_l2_mask_register.dout |
| 2545 | -active (`RST.rst_wmr_protect ) |
| 2546 | -clock `RST.ccu_rst_sys_clk |
| 2547 | -name wrm_protect_l2_mask |
| 2548 | -module l2t |
| 2549 | -group rst_chkr |
| 2550 | */ |
| 2551 | //L2 Address Compare Reg 0 0xBF-0000-0000 |
| 2552 | /* 0in constant |
| 2553 | -var `CPU.l2t7.csr.ff_l2_compare_register.dout |
| 2554 | -active (`RST.rst_wmr_protect ) |
| 2555 | -clock `RST.ccu_rst_sys_clk |
| 2556 | -name wrm_protect_l2_address_compare |
| 2557 | -module l2t |
| 2558 | -group rst_chkr |
| 2559 | */ |
| 2560 | |
| 2561 | `endif |
| 2562 | |
| 2563 | |
| 2564 | endmodule // warm_protect_checker |
| 2565 | |