| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fc_top.vr |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #define PROG_FILE |
| 36 | |
| 37 | #include <vera_defines.vrh> // standard header file from Vera |
| 38 | #include <VeraListProgram.vrh> // standard header file from Vera |
| 39 | #include <ListMacros.vrh> // standard header file from Vera |
| 40 | |
| 41 | #include "cpu.h" // constant definitions for CPU rtl at :/design/cpu/rtl/ |
| 42 | |
| 43 | // added this #ifndef for excluding code for NIU in Opensparc T2 |
| 44 | #ifndef FC_NO_NIU_T2 |
| 45 | #include "mbox_class.vrh" |
| 46 | #include "get_mbox_id.vrh" |
| 47 | #include "niu_verilog_tasks.vri" |
| 48 | |
| 49 | //IP PacketGen related |
| 50 | |
| 51 | #include "pcg_defines.vri" |
| 52 | #include "pcg_types.vri" |
| 53 | #include "pack_db.vrh" |
| 54 | #include "flow_db.vrh" |
| 55 | #include "flow_db_tasks.vrh" |
| 56 | #include "pg_top_pp.vrh" |
| 57 | #include "pc_top_pp.vrh" |
| 58 | #include "mac_pio_class.vrh" |
| 59 | #include "pio_driver.vrh" |
| 60 | #include "bmac_util.vrh" |
| 61 | #include "pcs_util.vrh" |
| 62 | #include "xpcs_util.vrh" |
| 63 | #include "fflp_util.vrh" |
| 64 | #include "txc_util.vrh" |
| 65 | #include "niu_gen_pio.vrh" |
| 66 | |
| 67 | // New code for pktconfig and RDMC MOdel |
| 68 | #include "pktConfig.vrh" |
| 69 | #include "niu_rxdmc.vrh" |
| 70 | |
| 71 | #include "rand_packet.vrh" |
| 72 | |
| 73 | |
| 74 | #ifndef GATESIM |
| 75 | #ifndef NIU_SYSTEMC_T2 |
| 76 | #include "niu_rx_coverage.vrh" |
| 77 | #endif |
| 78 | #endif |
| 79 | |
| 80 | #ifndef RXC_SAT |
| 81 | #ifndef MAC_SAT |
| 82 | #include "niu_rxdma_wr_chk.vrh" |
| 83 | #endif |
| 84 | #endif |
| 85 | |
| 86 | #ifndef MAC_SAT |
| 87 | #ifndef NIU_SYSTEMC_T2 |
| 88 | #include "control_fifo_mon.vrh" |
| 89 | #include "control_fifo_chkr.vrh" |
| 90 | #include "rdmc_mon.vrh" |
| 91 | #endif |
| 92 | #include "mac_mon.vrh" |
| 93 | #endif |
| 94 | |
| 95 | #include "hostRdCbMgr.vrh" |
| 96 | #endif // #ifndef FC_NO_NIU_T2 |
| 97 | |
| 98 | |
| 99 | // interfaces & binds |
| 100 | #include <fc_top.if.vrh> |
| 101 | #include <ccxDevices.if.vrh> |
| 102 | #include <ccxDevices.binds.vrh> |
| 103 | |
| 104 | #include "asmEventsToVera.if.vrh" |
| 105 | #include "errorCountTasks.if.vrh" |
| 106 | #include "sparcBenchUtils_if.vrh" |
| 107 | #ifndef GATESIM |
| 108 | #include "fc_jtpor.if.vrh" |
| 109 | #endif |
| 110 | |
| 111 | // defines |
| 112 | #include "defines.vri" |
| 113 | #include <ccxDevicesDefines.vri> |
| 114 | #include "plusArgMacros.vri" |
| 115 | #include "std_display_defines.vri" |
| 116 | |
| 117 | // classes refered to in this file |
| 118 | #include "std_display_class.vrh" |
| 119 | #include "baseUtilsClass.vrh" |
| 120 | #include "sparcBenchUtils.vrh" |
| 121 | #include "utilsClass.vrh" |
| 122 | #include "ssi.if.vrh" |
| 123 | #include "ssi.vrh" |
| 124 | #include "baseParamsClass.vrh" |
| 125 | #include "sparcParams.vrh" |
| 126 | |
| 127 | #include "asmEvent.vrh" |
| 128 | #include "baseAsmToVeraIntf.vrh" |
| 129 | #include "asmEventsToVera.vrh" |
| 130 | |
| 131 | #ifndef FC_NO_NIU_T2 |
| 132 | #include "asmToVeraIntf.vrh" |
| 133 | #include "niu_tx_descp.vrh" |
| 134 | #include "niu_tx_port.vrh" |
| 135 | #endif |
| 136 | |
| 137 | #include "generic_ev_packet.vrh" // packet for generic user event |
| 138 | |
| 139 | /***************************** |
| 140 | * TCU Driver classes * |
| 141 | *****************************/ |
| 142 | #include "tcu_tasks.vrh" |
| 143 | #include "sys_reset.vrh" |
| 144 | #ifndef GATESIM |
| 145 | #include "fcShadowScanClass.vrh" |
| 146 | #endif |
| 147 | |
| 148 | #ifndef FC_NO_NIU_T2 |
| 149 | #ifndef RXC_SAT |
| 150 | #include "rxc_class.vrh" |
| 151 | #include "ip_ingress_classes.vrh" |
| 152 | #include "ip_ingress_db.vrh" |
| 153 | #include "ip_util.vrh" |
| 154 | #endif |
| 155 | |
| 156 | // Interrupt |
| 157 | #include "niu_int_qmgr.vrh" |
| 158 | #include "niu_int_mgr.vrh" |
| 159 | #include "niu_dma_bind.vrh" |
| 160 | #ifndef NIU_SYSTEMC_T2 |
| 161 | #include "niu_intr_mon.vrh" |
| 162 | #endif |
| 163 | #endif //#ifndef FC_NO_NIU_T2 |
| 164 | |
| 165 | #ifdef USE_JTAG_DRIVER |
| 166 | #ifdef FC_JTAG_DEBUG_COVERAGE |
| 167 | #include "ncu_coverage.vrh" |
| 168 | #include "ncu_rtl_cov.vrh" |
| 169 | #endif |
| 170 | //------- Run TCU along with SPARC diag ------------ |
| 171 | extern function integer tcu_diag(StandardDisplay gDbg); |
| 172 | #endif |
| 173 | |
| 174 | // verilog tasks/functions that vera is going to call |
| 175 | #include <verilog_tasks_misc.vri> |
| 176 | #include "seedingVerilogTasks.vri" |
| 177 | |
| 178 | // PEU Integration |
| 179 | #ifndef FC_NO_PEU_VERA |
| 180 | #include "report_verilog_tasks.vrh" |
| 181 | #include "cReport.vrh" |
| 182 | #include "Testbench.vrh" |
| 183 | #include "peu_verilog_tasks.vri" |
| 184 | #include "FNXPCIEXactorExports.vri" |
| 185 | |
| 186 | // dma checker |
| 187 | #ifndef GATESIM |
| 188 | hdl_task mem_check ( bit [39:0] pa, |
| 189 | bit [(64*8)-1:0] data |
| 190 | ) "tb_top.ldst_sync.ldst_l2.mem_check"; |
| 191 | #endif |
| 192 | |
| 193 | #include "top_defines.vrh" |
| 194 | #include "ios_l2_stub.vrh" |
| 195 | #include "fc_l2_sio_stub.vrh" |
| 196 | |
| 197 | #include "niu_sig.if.vrh" |
| 198 | #include "niu_checker.vrh" |
| 199 | |
| 200 | #else |
| 201 | #ifdef USE_BOBO |
| 202 | hdl_task bobo_write_64bit (bit [39:0] pa, |
| 203 | bit [63:0] data64 |
| 204 | ) "tb_top.bobo_write_64bit"; |
| 205 | #else |
| 206 | #ifndef FC_NO_PEU_T2 |
| 207 | hdl_task pep_write_32bit (bit [39:0] pa, |
| 208 | bit [31:0] data32 |
| 209 | ) "tb_top.ept.pci_dma.dma.pio.pep_write_32bit"; |
| 210 | #endif // FC_NO_PEU_T2 |
| 211 | #endif // USE_BOBO |
| 212 | #endif // FC_NO_PEU_VERA |
| 213 | |
| 214 | // Mcu Mon for Rx checker added here |
| 215 | #include "FcMcuMon.vrh" |
| 216 | #include "FcMcuMonPort.if.vrh" |
| 217 | |
| 218 | // ras |
| 219 | #ifndef GATESIM |
| 220 | #include <verilog_tasks_RandErr.vri> |
| 221 | #endif |
| 222 | |
| 223 | #include "ios_injerr.vrh" |
| 224 | #include "../../ios/vera/include/ios_verilog_tasks.vri" |
| 225 | |
| 226 | #ifndef FC_NO_NIU_T2 |
| 227 | #include "sioniu_err_mon.vrh" |
| 228 | #endif |
| 229 | #include "siodmu_err_mon.vrh" |
| 230 | |
| 231 | #ifndef GATESIM |
| 232 | #include "ios_err_interrupt.vrh" |
| 233 | #endif |
| 234 | |
| 235 | // extern FcMcuMon fcmcumon[4] |
| 236 | |
| 237 | #ifndef FC_NO_PEU_VERA |
| 238 | //// extern class PEUTestBase {} |
| 239 | extern class N2fcCtx {} |
| 240 | #endif |
| 241 | |
| 242 | |
| 243 | // events. Note: these are macro, so no ';' at the end |
| 244 | MakeVeraList(string) |
| 245 | MakeVeraList(EventClass) |
| 246 | |
| 247 | // FOR TXC |
| 248 | hdl_task write_sys_mem ( |
| 249 | bit [63:0] addr, |
| 250 | bit [63:0] data, |
| 251 | bit [7:0] be |
| 252 | ) "tb_top.write_sys_mem"; |
| 253 | |
| 254 | hdl_task read_sys_mem ( |
| 255 | bit [63:0] addr, |
| 256 | var bit [63:0] rd_data |
| 257 | ) "tb_top.read_sys_mem" ; |
| 258 | |
| 259 | #ifndef FC_NO_NIU_T2 |
| 260 | hdl_task force_tcam_entry (bit [7:0] tcam_index, bit [199:0] tcam_key) "tb_top.force_tcam_entry" ; |
| 261 | hdl_task backdoor_init_tcam () "tb_top.backdoor_init_tcam" ; |
| 262 | #endif |
| 263 | hdl_task force_pkg_pin_TRIGIN(bit is_forcing, bit value) "tb_top.force_pkg_pin_TRIGIN"; |
| 264 | hdl_task force_tcu_clk_stop_at_tcu(bit is_forcing, bit value) "tb_top.force_tcu_clk_stop_at_tcu"; |
| 265 | hdl_task force_tcu_siu_L2_write(bit [39:0] addr, bit [63:0] wr_data) "tb_top.force_tcu_siu_L2_write"; |
| 266 | hdl_task force_tcu_siu_L2_read(bit [39:0] addr, var bit [63:0] rd_data) "tb_top.force_tcu_siu_L2_read"; |
| 267 | |
| 268 | // for tlr glitch enable |
| 269 | hdl_task force_tlrState() "`TOP.force_tlrState"; |
| 270 | hdl_task release_tlrState() "`TOP.release_tlrState"; |
| 271 | // |
| 272 | // include interface coverages |
| 273 | #ifdef FC_COVERAGE |
| 274 | #include "ncu_coverage.vrh" |
| 275 | #include "ncu_rtl_cov.vrh" |
| 276 | #include "l2sat_coverage.vrh" |
| 277 | #include "l2sat_misc_cov.vrh" |
| 278 | #include "mcusat_coverage.vri" |
| 279 | #include "dmu_coverage.vri" |
| 280 | |
| 281 | #ifndef FC_NO_PEU_VERA |
| 282 | #include "ilu_peu_coverage.vrh" |
| 283 | #endif |
| 284 | #ifndef GATESIM |
| 285 | #include "siu_coverage.vrh" |
| 286 | #endif |
| 287 | #include "fc_coverage.vrh" |
| 288 | #endif |
| 289 | // |
| 290 | #ifdef FC_JTAG_DEBUG_COVERAGE |
| 291 | #include "ncu_coverage.vrh" |
| 292 | #include "ncu_rtl_cov.vrh" |
| 293 | #endif |
| 294 | |
| 295 | //SIU monitors/checkers |
| 296 | #ifndef FC_NO_NIU_T2 |
| 297 | #include "siu_niu_mon.vrh" |
| 298 | #endif |
| 299 | #include "siu_dmu_mon.vrh" |
| 300 | #include "siu_l2_mon.vrh" |
| 301 | #include "siu_order_checker.vrh" |
| 302 | #include "siu_err_mask.vrh" |
| 303 | //L2 monitors/checkers |
| 304 | #ifndef GATESIM |
| 305 | #include <l2jbi.if.vrh> |
| 306 | #include <l2jbi_ports_binds.vrh> |
| 307 | #endif |
| 308 | #include <cpxorder.if.vrh> |
| 309 | #include <cpxorder_ports_binds.vrh> |
| 310 | |
| 311 | #include "siu_ncu_mondo.if.vrh" |
| 312 | #include "siu_ncu_mondo_ports_binds.vrh" |
| 313 | #include "siu_ncu_mondo_checker.vrh" |
| 314 | |
| 315 | extern task MonitorCPX(); |
| 316 | #ifndef GATESIM |
| 317 | extern task CheckJbiInvBeforeAck(); |
| 318 | #endif |
| 319 | |
| 320 | #include "fc_top_defines.vri" // common definitions for fc bench at /verif/env/common/vera/include/ |
| 321 | #include "ucb_top.vri" // constants/port/if/bind definitions for UCB at :/verif/env/tcu/vera/include/ |
| 322 | #include "ucb___packet.vrh" // UCB pkt definition at :/verif/env/tcu/vera/packets/ |
| 323 | #include "ucb_monitor.vrh" // UCB protocol monitor at :/verif/env/tcu/vera/classes/ |
| 324 | |
| 325 | #ifndef GATESIM |
| 326 | #include "ccu_top.vri" // constants/port/if/bind definitions for CCU at :/verif/env/tcu/vera/include/ |
| 327 | #include "cluster_hdr_top.vri" // constants/port/if/bind definitions for cluster hdrs at :/verif/env/tcu/vera/include/ |
| 328 | #include "ccu_clk_packet.vrh" // ccu/clk pkt definition at :/verif/env/tcu/vera/packets/ |
| 329 | #include "ccu_clks_states.vrh" // ccu/clk state at :/verif/env/tcu/vera/classes/ |
| 330 | #include "ccu_checker.vrh" // ccu checker at :/verif/env/tcu/vera/classes/ |
| 331 | #include "cluster_hdr_chkr.vrh" // cluster header checkers at :/verif/env/tcu/vera/classes/ |
| 332 | #include "ccu_clk_chkr_4fc.vrh" // ccu and cluster header checkers at :/verif/env/tcu/vera/classes/ |
| 333 | #endif // #ifndef GATESIM |
| 334 | |
| 335 | //===================================================================== |
| 336 | //================ main vera program ================================= |
| 337 | //===================================================================== |
| 338 | |
| 339 | program fc_test |
| 340 | { |
| 341 | |
| 342 | |
| 343 | // This is where the global 'extern declerations' are. Typedefs too. |
| 344 | // Other files needing globals include this. |
| 345 | #define STORAGE_CLASS |
| 346 | #include "globals.vri" |
| 347 | #ifndef FC_NO_NIU_T2 |
| 348 | #include "global_variable.vri" |
| 349 | #endif |
| 350 | |
| 351 | string dispmonScope = "vera_top"; // display scope for dispmon (ie. gDbg and dbg) |
| 352 | integer verbose = (get_plus_arg(CHECK, "fc_vera_top_verbose"))? 1 : 0; // non-zero: print out info for debugging fc_top.vr |
| 353 | |
| 354 | integer generic_ev_mbox; // mailbox for generic user event |
| 355 | SSI bootrom; |
| 356 | |
| 357 | reg asmDiagRun; |
| 358 | reg asmDiagDone; |
| 359 | integer ipp_config0[4]; |
| 360 | integer ipp_config1[4]; |
| 361 | integer opp_config0[4]; |
| 362 | integer opp_config1[4]; |
| 363 | integer mac_config0[4]; |
| 364 | integer mac_config1[4]; |
| 365 | integer ntx_config[2]; |
| 366 | integer bif_config[2]; |
| 367 | integer RX_TEST_REACHED_END = 0; |
| 368 | |
| 369 | |
| 370 | //Block detection |
| 371 | integer port_type_flag[9]; // Port Types |
| 372 | bit [8:0] active_port=0; // Active ports on fedx |
| 373 | |
| 374 | #ifndef FC_NO_NIU_T2 |
| 375 | bit [3:0] rtl_mac; // For each rtl level mac the bit is set to 1 |
| 376 | bit [3:0] gate_mac=0; // For each gate level mac the bit is set to 1 |
| 377 | bit [3:0] active_mac=0; // For each active mac the bit is set to 1 |
| 378 | bit [3:0] fake_mac=0; // For each fake level mac the bit is set to 1 |
| 379 | #endif |
| 380 | |
| 381 | //Block detection IPP |
| 382 | bit [3:0] rtl_ipp=0; // For each rtl level ipp the bit is set to 1 |
| 383 | bit [3:0] gate_ipp=0; // For each gate level ipp the bit is set to 1 |
| 384 | bit [3:0] active_ipp=0; // For each active ipp the bit is set to 1 |
| 385 | bit [3:0] fake_ipp=0; // For each fake level ipp the bit is set to 1 |
| 386 | |
| 387 | //Block detection OPP |
| 388 | bit [3:0] rtl_opp=0; // For each rtl level opp the bit is set to 1 |
| 389 | bit [3:0] gate_opp=0; // For each gate level opp the bit is set to 1 |
| 390 | bit [3:0] active_opp=0; // For each active opp the bit is set to 1 |
| 391 | bit [3:0] fake_opp=0; // For each fake level opp the bit is set to 1 |
| 392 | |
| 393 | //Block detection BIF |
| 394 | bit rtl_mif=0; // For rtl level bif the bit is set to 1 |
| 395 | bit gate_mif=0; // For gate level bif the bit is set to 1 |
| 396 | bit active_mif=0; // For active bif the bit is set to 1 |
| 397 | bit fake_mif=0; // For fake level bif the bit is set to 1 |
| 398 | |
| 399 | #ifndef FC_NO_NIU_T2 |
| 400 | //Setting Multiple Mac Port |
| 401 | bit[31:0] get_mac_port; |
| 402 | integer mac_speed0,mac_speed1,mac_speed2,mac_speed3; |
| 403 | bit [2047:0] bit_str; |
| 404 | string init_mac_ports,temp_port; |
| 405 | integer port_no[]; |
| 406 | #endif |
| 407 | integer i; |
| 408 | string str; |
| 409 | bit [39:0] address; // MAQ_Tx |
| 410 | bit [511:0] wri_data; // MAQ_Tx |
| 411 | FcMcuMon fcmcumon[4]; |
| 412 | bit [63:0] FCMemoryAddress_A[4]; |
| 413 | bit [63:0] FCMemoryAddress_B[4]; |
| 414 | bit [63:0] FCMemoryAddress_C[4]; |
| 415 | event FCMemorySync_A[4]; |
| 416 | event FCMemorySync_B[4]; |
| 417 | event FCMemorySync_C[4]; |
| 418 | |
| 419 | #ifndef GATESIM |
| 420 | ios_err_interrupt_mon ras_interrupt; |
| 421 | #endif // #ifndef GATESIM |
| 422 | ios_ras_inj ras_injector; |
| 423 | #ifndef FC_NO_NIU_T2 |
| 424 | sioniu_err_mon sioniu_errmon; |
| 425 | #endif |
| 426 | siodmu_err_mon siodmu_errmon; |
| 427 | |
| 428 | //SIU monitors |
| 429 | #ifndef FC_NO_NIU_T2 |
| 430 | siu_niu_monitor siuniu_mon; |
| 431 | #endif |
| 432 | siu_dmu_monitor siudmu_mon; |
| 433 | |
| 434 | siu_l2_monitor siul2_mon[]; |
| 435 | siu_order_checker order_chk; |
| 436 | #ifndef FC_NO_NIU_T2 |
| 437 | integer niu_snd_mbox, niu_rec_mbox; |
| 438 | #endif |
| 439 | integer dmu_snd_mbox, dmu_rec_mbox, ncu_rec_mbox; |
| 440 | integer l2_snd_mbox[], l2_rec_mbox[]; |
| 441 | |
| 442 | siu_ncu_mondo_checker siu_ncu_mondo_chk; |
| 443 | |
| 444 | // ************************************************** |
| 445 | // ***Variables for Checker tasks |
| 446 | // ************************************************** |
| 447 | |
| 448 | bit VERIF_RESET=0; // reset for the verification environment. |
| 449 | bit token_debug=1; // for comments concerning the token flow. |
| 450 | |
| 451 | bit TCU_DONE=1; // indicate when the TCU is done default is 1 |
| 452 | // when TCU is run will be set to 0 & 1 |
| 453 | bit TCU_Test_En=0; |
| 454 | bit jtag_reset_done = 0; // when USE_JTAG_DRIVER, set it to 1 after reseting jtag completed |
| 455 | |
| 456 | integer numberOfCores = 0; // Keep track of how many cores available |
| 457 | reg [63:0] bootedThreads; // to store which threads booted |
| 458 | |
| 459 | #ifndef FC_NO_NIU_T2 |
| 460 | //Checker Interface enable |
| 461 | bit mac_ipp_interface_ena =1; |
| 462 | bit mac_opp_interface_ena =1; |
| 463 | |
| 464 | //Checker Protocol Check Enable |
| 465 | bit mac_ipp_proto_ena =1; |
| 466 | bit mac_opp_proto_ena =1; |
| 467 | |
| 468 | //Checker Data Check Enable |
| 469 | bit mac_ipp_data_ena =1; |
| 470 | bit mac_opp_data_ena =1; |
| 471 | #endif |
| 472 | |
| 473 | // interface coverages. |
| 474 | |
| 475 | StandardDisplay dbg; |
| 476 | bit coverage_on; |
| 477 | event dmu_diag_done; |
| 478 | |
| 479 | #ifdef FC_JTAG_DEBUG_COVERAGE |
| 480 | ncu_intf_cov ncu_intf_cov_obj; |
| 481 | ncu_rtl_cov ncu_rtl_cov_obj; |
| 482 | #endif |
| 483 | |
| 484 | #ifdef FC_COVERAGE |
| 485 | ncu_intf_cov ncu_intf_cov_obj; |
| 486 | ncu_rtl_cov ncu_rtl_cov_obj; |
| 487 | l2sat_intf_coverage_class Interface_coverage; |
| 488 | dram_coverage dram_coverage_obj; |
| 489 | dmu_coverage dmu_coverage_obj; |
| 490 | |
| 491 | #ifndef FC_NO_PEU_VERA |
| 492 | ilu_peu_intf_coverage ilu_peu_intf_coverage_obj; |
| 493 | #endif |
| 494 | siu_intf_coverage siu_intf_coverage_obj; |
| 495 | siu_intf_schmoo_coverage siu_schmoo_coverage_obj; |
| 496 | siu_ipcs_coverage siu_ipcs_coverage_obj; |
| 497 | siu_opcs_coverage siu_opcs_coverage_obj; |
| 498 | fc_cov fc_cov_obj; |
| 499 | fc_modes_cov fc_modes_cov_obj; //Modes coverage object |
| 500 | fc_ncu_internal_coverage fc_ncu_internal_coverage_obj; |
| 501 | fc_siu_internal_coverage fc_siu_internal_coverage_obj; |
| 502 | fc_l2_internal_coverage fc_l2_internal_coverage_obj; |
| 503 | fc_siu_ras_coverage fc_siu_ras_coverage_obj; |
| 504 | #ifndef FC_NO_NIU_T2 |
| 505 | fc_niu_coverage fc_niu_coverage_obj; |
| 506 | #endif |
| 507 | fc_mcu_ras_coverage fc_mcu_ras_coverage_obj; |
| 508 | #endif |
| 509 | |
| 510 | #ifndef FC_NO_NIU_T2 |
| 511 | mbox_class mbox_id; |
| 512 | Mesg be_msg; |
| 513 | #endif |
| 514 | |
| 515 | integer pack_db_lock; |
| 516 | integer flow_db_lock; |
| 517 | integer pack_db_index = 0; |
| 518 | integer flow_num = 0; |
| 519 | integer quiet_on = 0; |
| 520 | integer n; |
| 521 | integer tcuerrorcount = 0; |
| 522 | integer flow_mb; |
| 523 | integer config_mb; |
| 524 | integer config0_mb; |
| 525 | integer config1_mb; |
| 526 | |
| 527 | #ifndef FC_NO_NIU_T2 |
| 528 | CSparseMem SparseMem; |
| 529 | CHostErrInjTab HostErrInj; |
| 530 | CHostRdCbMgr hostRdCbMgr; |
| 531 | |
| 532 | pg pack_gen[16]; // Allocate pointers for 4 packet generators |
| 533 | pg ptr_to_first_pg; |
| 534 | pc pack_check[4]; |
| 535 | pack_db_entry pack_db[]; |
| 536 | flow_db_entry flow_db[]; |
| 537 | |
| 538 | node_db node[32]; |
| 539 | tup_descr tud[32]; |
| 540 | fr_cl fr[8]; |
| 541 | DMAChannel dma[32]; |
| 542 | |
| 543 | #ifndef MAC_SAT |
| 544 | #ifndef NIU_SYSTEMC_T2 |
| 545 | control_fifo_mon control_fifo_monitor; |
| 546 | control_fifo_chkr control_fifo_checker; |
| 547 | RdmcMonitor rdmc_mon; |
| 548 | #endif |
| 549 | MacMonitor mac_mon_rx; // 02/16/06 |
| 550 | MacMonitor mac_mon_tx; |
| 551 | #endif |
| 552 | |
| 553 | pio_drv pio_driver_class; |
| 554 | mac_pio_cl mac_pio_class; |
| 555 | mac_util_class mac_util; |
| 556 | bmac_util_class bmac_util; |
| 557 | pcs_util_class pcs_util; |
| 558 | xpcs_util_class xpcs_util; |
| 559 | fflp_util_class fflp_util; |
| 560 | CNiuDMABind NiuDMABind; |
| 561 | niu_gen_pio gen_pio_drv; |
| 562 | |
| 563 | event RX_chk_done; |
| 564 | event mac_init_done; |
| 565 | event TX_rvcd_allpkts[4]; |
| 566 | txc_util_class txc_util; |
| 567 | |
| 568 | CpktConfig pktConfig; |
| 569 | CRDMC rdmc; |
| 570 | rand_packet rx_rand_packet; |
| 571 | |
| 572 | #ifndef GATESIM |
| 573 | #ifndef NIU_SYSTEMC_T2 |
| 574 | niu_intf_coverage niu_rx_intf_coverage; |
| 575 | #endif |
| 576 | #endif |
| 577 | |
| 578 | #ifndef RXC_SAT |
| 579 | #ifndef MAC_SAT |
| 580 | Cniu_rxdma_wr_chkr niu_rxdma_wrchk; |
| 581 | #endif |
| 582 | #endif |
| 583 | |
| 584 | #ifndef MAC_SAT |
| 585 | RxDMAChannel rx_dma[32]; |
| 586 | #ifndef RXC_SAT |
| 587 | Crxc rxc_cl; |
| 588 | #endif |
| 589 | #endif |
| 590 | |
| 591 | /* Interrupt Related variables*/ |
| 592 | CNiuIntrQMgr NiuIntrQ; |
| 593 | CNiuIntrMgr NiuIntrMgr; |
| 594 | #ifndef GATESIM |
| 595 | #ifndef NIU_SYSTEMC_T2 |
| 596 | CNiuIntMonitor NiuIntMon; |
| 597 | #endif |
| 598 | #endif |
| 599 | |
| 600 | #ifndef FC_NO_PEU_VERA |
| 601 | ReportClass MyReport; |
| 602 | N2fcCtx peutest; |
| 603 | |
| 604 | integer non_posted_read_cmpl_outstanding; |
| 605 | integer non_posted_write_cmpl_outstanding; |
| 606 | |
| 607 | bit PEU_Test_En = 0; |
| 608 | event e_StartPEUTest; |
| 609 | integer asm2peu_mbox; |
| 610 | N2fcPiuShadowRegs PiuCsrs; |
| 611 | bit [63:0] IOSMemoryAddress[8]; |
| 612 | event IOSMemorySync[8]; |
| 613 | integer fc_peu_dma_ptr=0; |
| 614 | fc_l2_sio_stub l2sio_stub; |
| 615 | |
| 616 | ios_l2_stub l2_stub[]; |
| 617 | |
| 618 | VeraList_l2_packet l2_list0; |
| 619 | VeraList_l2_packet l2_list1; |
| 620 | VeraList_l2_packet l2_list2; |
| 621 | VeraList_l2_packet l2_list3; |
| 622 | VeraList_l2_packet l2_list4; |
| 623 | VeraList_l2_packet l2_list5; |
| 624 | VeraList_l2_packet l2_list6; |
| 625 | VeraList_l2_packet l2_list7; |
| 626 | |
| 627 | niu_checker niuchk; |
| 628 | |
| 629 | #endif // #ifndef FC_NO_PEU_VERA |
| 630 | #endif // #ifndef FC_NO_NIU_T2 |
| 631 | |
| 632 | |
| 633 | bit vera_top_debug = 0; |
| 634 | bit reset_complete = 0; |
| 635 | |
| 636 | #ifndef GATESIM |
| 637 | //CCU_clk_chkr_4fc ccu_clk_chkr_4fc; // ccu and clock checkers |
| 638 | #endif |
| 639 | |
| 640 | /***************************************************************** |
| 641 | * TCU Driver * |
| 642 | *****************************************************************/ |
| 643 | SystemTap dft; |
| 644 | SystemReset reset; |
| 645 | tcu_siu_packet tcu_siu_pkt; // for L2 access |
| 646 | reg [39:0] jtagDoneMemAddr; // indicate JTAG done to ASM |
| 647 | #ifndef GATESIM |
| 648 | fcShadowScanClass shScanCapture; // capture the shadow scan bits |
| 649 | #endif |
| 650 | |
| 651 | event e_StartJtag; |
| 652 | |
| 653 | // review |
| 654 | // VeraListIterator_EventClass event_it; |
| 655 | // VeraList_EventClass vera_tasks[]; |
| 656 | // VeraList_string str_list = new; |
| 657 | |
| 658 | |
| 659 | // vera tasks that verilog calls, if any |
| 660 | //#include "vera_tasks.vrh" |
| 661 | |
| 662 | //======================================================= |
| 663 | //====== end of variable declarations =================== |
| 664 | //======================================================= |
| 665 | |
| 666 | //----------------------------------------------------------------------------- |
| 667 | // You must seed the RNG from *top* *BEFORE* class instantiations and forks. |
| 668 | // YES, this matters in vera > V5, see vera docs. If you don't seed before |
| 669 | // instantiating a class, that class ALWAYS repeats random numbers which is |
| 670 | // NOT what you want. |
| 671 | //----------------------------------------------------------------------------- |
| 672 | #define HDNLNAME gSeedFileHndl |
| 673 | #define SEEDNAME gSeed |
| 674 | #include "seeding.vri" |
| 675 | |
| 676 | gDbg = new(); |
| 677 | dbg = gDbg; // gDbg and dbg are the same |
| 678 | |
| 679 | #ifndef GATESIM |
| 680 | //ccu_clk_chkr_4fc = new(dbg); // ccu and cluster header checkers. By default, they're disable |
| 681 | #endif |
| 682 | |
| 683 | generic_ev_mbox = alloc(MAILBOX, 0, 1); |
| 684 | |
| 685 | #ifndef FC_NO_NIU_T2 |
| 686 | flow_db_init(); |
| 687 | mbox_id = new; |
| 688 | ptr_to_first_pg = null; |
| 689 | |
| 690 | be_msg = new(e_mesg_debug2); |
| 691 | SparseMem = new(); |
| 692 | HostErrInj = new(); |
| 693 | hostRdCbMgr = new(0); |
| 694 | |
| 695 | flow_mb = alloc(MAILBOX, 0, 1); |
| 696 | config_mb = alloc(MAILBOX, 0, 1); |
| 697 | config0_mb = alloc(MAILBOX, 0, 1); |
| 698 | config1_mb = alloc(MAILBOX, 0, 1); |
| 699 | |
| 700 | NiuIntrQ = new(); |
| 701 | NiuIntrMgr = new(); |
| 702 | NiuDMABind = new(); |
| 703 | #ifndef GATESIM |
| 704 | #ifndef NIU_SYSTEMC_T2 |
| 705 | NiuIntMon = new(); |
| 706 | #endif |
| 707 | #endif |
| 708 | |
| 709 | mac_pio_class = new( ); |
| 710 | mac_util = new(); |
| 711 | bmac_util = new(); |
| 712 | pcs_util = new(); |
| 713 | xpcs_util = new(); |
| 714 | fflp_util = new; |
| 715 | gen_pio_drv = new(); |
| 716 | pktConfig = new(); |
| 717 | rdmc = new(); |
| 718 | txc_util = new(); |
| 719 | |
| 720 | // For Rx checker |
| 721 | fcmcumon[0] = new(DramWriteMCU0, 2'b00); |
| 722 | fcmcumon[1] = new(DramWriteMCU1, 2'b01); |
| 723 | fcmcumon[2] = new(DramWriteMCU2, 2'b10); |
| 724 | fcmcumon[3] = new(DramWriteMCU3, 2'b11); |
| 725 | trigger(OFF,FCMemorySync_A[0]); |
| 726 | trigger(OFF,FCMemorySync_A[1]); |
| 727 | trigger(OFF,FCMemorySync_A[2]); |
| 728 | trigger(OFF,FCMemorySync_A[3]); |
| 729 | |
| 730 | trigger(OFF,FCMemorySync_B[0]); |
| 731 | trigger(OFF,FCMemorySync_B[1]); |
| 732 | trigger(OFF,FCMemorySync_B[2]); |
| 733 | trigger(OFF,FCMemorySync_B[3]); |
| 734 | |
| 735 | trigger(OFF,FCMemorySync_C[0]); |
| 736 | trigger(OFF,FCMemorySync_C[1]); |
| 737 | trigger(OFF,FCMemorySync_C[2]); |
| 738 | trigger(OFF,FCMemorySync_C[3]); |
| 739 | |
| 740 | trigger(OFF,RX_chk_done); |
| 741 | |
| 742 | if (get_plus_arg(CHECK, "ENABLE_RANDOM_LAYER")) |
| 743 | { |
| 744 | rx_rand_packet = new(); |
| 745 | } |
| 746 | else |
| 747 | { |
| 748 | printf("\n Random Layer disabled \n"); |
| 749 | } |
| 750 | |
| 751 | if (get_plus_arg(CHECK, "ENABLE_COV_OBJECT")) |
| 752 | { |
| 753 | #ifndef GATESIM |
| 754 | #ifndef NIU_SYSTEMC_T2 |
| 755 | niu_rx_intf_coverage = new(); |
| 756 | #endif |
| 757 | #endif |
| 758 | } |
| 759 | else |
| 760 | { |
| 761 | printf("\n coverage objects disabled \n"); |
| 762 | } |
| 763 | #endif // FC_NO_NIU_T2 |
| 764 | |
| 765 | |
| 766 | #ifndef FC_NO_PEU_VERA |
| 767 | if ( get_plus_arg(CHECK, "PEU_TEST") ) { |
| 768 | l2_list0 = new(); |
| 769 | l2_list1 = new(); |
| 770 | l2_list2 = new(); |
| 771 | l2_list3 = new(); |
| 772 | l2_list4 = new(); |
| 773 | l2_list5 = new(); |
| 774 | l2_list6 = new(); |
| 775 | l2_list7 = new(); |
| 776 | printf("Time before L2 %0d\n", get_time(LO)); |
| 777 | l2sio_stub = new(dbg); |
| 778 | l2_stub[0] = new(l2_stub_bind0, 0, dbg, l2_list0); |
| 779 | l2_stub[1] = new(l2_stub_bind1, 1, dbg, l2_list1); |
| 780 | l2_stub[2] = new(l2_stub_bind2, 2, dbg, l2_list2); |
| 781 | l2_stub[3] = new(l2_stub_bind3, 3, dbg, l2_list3); |
| 782 | l2_stub[4] = new(l2_stub_bind4, 4, dbg, l2_list4); |
| 783 | l2_stub[5] = new(l2_stub_bind5, 5, dbg, l2_list5); |
| 784 | l2_stub[6] = new(l2_stub_bind6, 6, dbg, l2_list6); |
| 785 | l2_stub[7] = new(l2_stub_bind7, 7, dbg, l2_list7); |
| 786 | trigger(OFF,IOSMemorySync[0]); |
| 787 | trigger(OFF,IOSMemorySync[1]); |
| 788 | trigger(OFF,IOSMemorySync[2]); |
| 789 | trigger(OFF,IOSMemorySync[3]); |
| 790 | trigger(OFF,IOSMemorySync[4]); |
| 791 | trigger(OFF,IOSMemorySync[5]); |
| 792 | trigger(OFF,IOSMemorySync[6]); |
| 793 | trigger(OFF,IOSMemorySync[7]); |
| 794 | niuchk = new(dbg); |
| 795 | |
| 796 | PEU_Test_En = 1; |
| 797 | //printf(" DENALI= %s \n", get_env("DENALI")); // now this is printed by sims |
| 798 | printf(" PATH= %s \n", get_env("PATH")); |
| 799 | //printf(" LM_LICENSE_FILE= %s \n", get_env("LM_LICENSE_FILE")); // now this is printed by sims |
| 800 | MyReport = new; |
| 801 | asm2peu_mbox = alloc(MAILBOX, 0, 1); |
| 802 | } |
| 803 | #endif // FC_NO_PEU_VERA |
| 804 | |
| 805 | #ifndef FC_NO_NIU_T2 |
| 806 | mac_config0[0] = 1; // config1 config0 |
| 807 | mac_config0[1] = 1; // 0 1 RTL |
| 808 | mac_config0[2] = 1; // 1 1 DUmmy |
| 809 | mac_config0[3] = 1; |
| 810 | |
| 811 | mac_config1[0] =1 ; |
| 812 | mac_config1[1] =1 ; |
| 813 | mac_config1[2] =1 ; |
| 814 | mac_config1[3] =1 ; |
| 815 | |
| 816 | if( get_plus_arg( CHECK, "GET_MAC_PORTS=")) |
| 817 | get_mac_port = get_plus_arg( STR, "GET_MAC_PORTS="); |
| 818 | printf("The val of get_mac_port is %h\n",get_mac_port); |
| 819 | init_mac_ports.bittostr(get_mac_port); |
| 820 | for (i=0; i<init_mac_ports.len();i++) |
| 821 | { |
| 822 | temp_port =init_mac_ports.substr(i,i); |
| 823 | printf("\nTemp = %d",temp_port.atoi()); |
| 824 | port_no[i]=temp_port.atoi(); |
| 825 | } |
| 826 | |
| 827 | #ifndef MAC_SAT |
| 828 | #ifndef NIU_SYSTEMC_T2 |
| 829 | // Control Fifo Monitors per port |
| 830 | if (get_plus_arg(CHECK, "DIS_CTRL_MON")) |
| 831 | { |
| 832 | printf("\n Control FIFO Monitor Disabled \n"); |
| 833 | } |
| 834 | else |
| 835 | { |
| 836 | control_fifo_monitor = new(get_mac_port[1:0]); |
| 837 | } |
| 838 | |
| 839 | // Control Fifo Checkers per port |
| 840 | if (get_plus_arg(CHECK, "ENABLE_CTRL_FIFO_CHKR")) |
| 841 | { |
| 842 | control_fifo_checker = new(get_mac_port[1:0]); |
| 843 | } |
| 844 | else |
| 845 | { |
| 846 | printf("\n Control FIFO Checkers Disabled \n"); |
| 847 | } |
| 848 | |
| 849 | if (get_plus_arg(CHECK, "RDMC_MON_ENABLE")) { |
| 850 | fork |
| 851 | rdmc_mon = new(vera_top_debug); |
| 852 | join none |
| 853 | } |
| 854 | #endif |
| 855 | |
| 856 | if (get_plus_arg(CHECK, "MAC_MON_ENABLE")) { |
| 857 | fork |
| 858 | mac_mon_tx = new(vera_top_debug, "Tx"); |
| 859 | mac_mon_rx = new(vera_top_debug, "Rx"); |
| 860 | join none |
| 861 | } |
| 862 | #endif |
| 863 | |
| 864 | if ( get_plus_arg(CHECK, "MAC_SPEED0=") ) |
| 865 | { |
| 866 | mac_speed0 = get_plus_arg(NUM, "MAC_SPEED0") ; |
| 867 | printf("INFO:MAC0 port is set %0d Speed\n" ,mac_speed0); |
| 868 | } |
| 869 | if ( get_plus_arg(CHECK, "MAC_SPEED1=") ) |
| 870 | { |
| 871 | mac_speed1 = get_plus_arg(NUM, "MAC_SPEED1") ; |
| 872 | printf("INFO:MAC1 port is set %0d Speed\n" ,mac_speed1); |
| 873 | } |
| 874 | if ( get_plus_arg(CHECK, "MAC_SPEED2=") ) |
| 875 | { |
| 876 | mac_speed2 = get_plus_arg(NUM, "MAC_SPEED2") ; |
| 877 | printf("INFO:MAC2 port is set %0d Speed\n" ,mac_speed2); |
| 878 | } |
| 879 | if ( get_plus_arg(CHECK, "MAC_SPEED3=") ) |
| 880 | { |
| 881 | mac_speed3 = get_plus_arg(NUM, "MAC_SPEED3") ; |
| 882 | printf("INFO:MAC3 port is set %0d Speed\n" ,mac_speed3); |
| 883 | } |
| 884 | |
| 885 | if ( get_plus_arg(CHECK, "TX_TEST") ) { |
| 886 | } |
| 887 | else { |
| 888 | // dmc_util.dmc_init(); |
| 889 | } |
| 890 | |
| 891 | for (i=0; i<init_mac_ports.len();i++) |
| 892 | { |
| 893 | case(port_no[i]) |
| 894 | { |
| 895 | 0: { |
| 896 | mac_config1[0]=0; |
| 897 | } |
| 898 | 1: { |
| 899 | mac_config1[1]=0; |
| 900 | } |
| 901 | 2: { |
| 902 | mac_config1[2]=0; |
| 903 | } |
| 904 | 3: { |
| 905 | mac_config1[3]=0; |
| 906 | } |
| 907 | } |
| 908 | } |
| 909 | |
| 910 | |
| 911 | ntx_config[0] = 1; |
| 912 | ntx_config[1] = 1; |
| 913 | |
| 914 | for(n=0;n<4;n++) { |
| 915 | rtl_mac[n] = (!mac_config1[n] & mac_config0[n]); |
| 916 | } |
| 917 | |
| 918 | for(n=0;n<4;n++) { |
| 919 | if (rtl_mac[n] ) { |
| 920 | pack_gen[n] = new(n,0); // Attach a pg to port #n |
| 921 | pack_gen[n+8] = new(n+8,0); // Attach a pg to port #n+8 for tx side |
| 922 | } |
| 923 | } |
| 924 | |
| 925 | // 02/02/06 |
| 926 | if ( get_plus_arg(CHECK, "REG_TEST") ) { |
| 927 | printf("do not init TXC\n"); |
| 928 | } |
| 929 | else |
| 930 | { |
| 931 | #ifndef MAC_SAT |
| 932 | txc_util.txc_init(); |
| 933 | #endif |
| 934 | } |
| 935 | #endif // FC_NO_NIU_T2 |
| 936 | |
| 937 | |
| 938 | //----------------------------------------------------------------------------- |
| 939 | // Classes and forks (POST SEEDING!!!) |
| 940 | //----------------------------------------------------------------------------- |
| 941 | gOutOfBoot = 0; |
| 942 | |
| 943 | gClkPeriod = period_if.core_period async; |
| 944 | |
| 945 | // clock period can be dynamic so track it. |
| 946 | fork { |
| 947 | while (1) { |
| 948 | @(posedge period_if.core_period_change); |
| 949 | gClkPeriod = period_if.core_period async; |
| 950 | gUtil.updateClockPeriod(gClkPeriod); |
| 951 | } |
| 952 | } join none |
| 953 | |
| 954 | // Check Plusargs, knob/parameter files, config files, etc |
| 955 | gParam = new(gDbg); |
| 956 | |
| 957 | if (gParam.asmDiagName !== null) { |
| 958 | asmDiagRun = 1; // indicate that an assembly diag will be run |
| 959 | asmDiagDone = 0; // set to 1 when assembly diag completes |
| 960 | } else { |
| 961 | asmDiagRun = 0; |
| 962 | asmDiagDone = 1; |
| 963 | } |
| 964 | |
| 965 | // utils, base utils |
| 966 | gUtil = new(gDbg, gClkPeriod); |
| 967 | |
| 968 | // $EVENTs |
| 969 | gAsmEventsToVera = new(gDbg,gParam.coreEnableReg,0,0); // main/common $EVENTs code |
| 970 | gAsmEventsToVera.readEventFile("diag.ev"); |
| 971 | |
| 972 | // check coverage option |
| 973 | if( mChkPlusarg(coverage_on) ) coverage_on = 1; |
| 974 | else coverage_on = 0; // off by default |
| 975 | |
| 976 | #ifdef FC_JTAG_DEBUG_COVERAGE |
| 977 | if ((coverage_on) && |
| 978 | ! mChkPlusarg(coverage_off)) { |
| 979 | fork { |
| 980 | printf("Instantiating vera coverage objects\n"); |
| 981 | ncu_intf_cov_obj = new("ncu_intf_cov_obj", gDbg ); |
| 982 | ncu_rtl_cov_obj = new("ncu_rtl_cov_obj", gDbg ); |
| 983 | }join none |
| 984 | } |
| 985 | #endif |
| 986 | |
| 987 | |
| 988 | #ifdef FC_COVERAGE |
| 989 | if (( mChkPlusarg(fc_coverage) || coverage_on) && |
| 990 | ! mChkPlusarg(coverage_off)) { |
| 991 | fork { |
| 992 | printf("Instantiating vera coverage objects\n"); |
| 993 | ncu_intf_cov_obj = new("ncu_intf_cov_obj", gDbg ); |
| 994 | ncu_rtl_cov_obj = new("ncu_rtl_cov_obj", gDbg ); |
| 995 | }join none |
| 996 | } |
| 997 | #endif |
| 998 | |
| 999 | |
| 1000 | /***************************************************************** |
| 1001 | * TCU Driver * |
| 1002 | *****************************************************************/ |
| 1003 | #ifdef USE_JTAG_DRIVER // added this to not drive Tap pins in functional Mode. |
| 1004 | dft = new(gDbg); // warning: new() resets JTAG TAP, so advances sim time |
| 1005 | reset = new(dbg, dft); |
| 1006 | fork { |
| 1007 | dft.fc_bench_jtag_POR_reset(); // reset JTAG TAP (see tcu_task.vr for details) |
| 1008 | jtag_reset_done = 1; |
| 1009 | } join none |
| 1010 | #endif |
| 1011 | // for L2 access from TCU |
| 1012 | tcu_siu_pkt = new (JTAG_RD, 0, 0); |
| 1013 | |
| 1014 | #ifndef AXIS_DDR2_MODEL |
| 1015 | bootrom = new (gDbg,ncu,ssi); |
| 1016 | #endif |
| 1017 | |
| 1018 | // Initialize bench, virtual ports, $EVENTs, etc. |
| 1019 | gUtil.initTB(0,0,0,1); // initTB(reg useMCUbfms = 0, reg useL1Tags = 0); |
| 1020 | |
| 1021 | // this waits for reset to be done. |
| 1022 | // skip it when vera diag wants to run very early on (reset diag). |
| 1023 | //if (! mChkPlusarg(vera_driven_reset)) |
| 1024 | fork |
| 1025 | { |
| 1026 | gUtil.initDut(); |
| 1027 | reset_complete = 1'b1; // inidicate the fulsh reset complete |
| 1028 | } |
| 1029 | join none |
| 1030 | |
| 1031 | for (i=0; i<8; i++) { |
| 1032 | if(gParam.coreAvilable[i]) { |
| 1033 | numberOfCores++; |
| 1034 | } |
| 1035 | } |
| 1036 | if(!numberOfCores) { |
| 1037 | numberOfCores = 1; // default |
| 1038 | } |
| 1039 | |
| 1040 | //============================= |
| 1041 | // - ported from IOS sat |
| 1042 | // ------- start coverage objects after reset has been de-asserted --------- |
| 1043 | |
| 1044 | |
| 1045 | #ifdef FC_COVERAGE |
| 1046 | if (( mChkPlusarg(fc_coverage) || coverage_on) && !mChkPlusarg(coverage_off)) { |
| 1047 | printf("probe_if.flush_reset_complete = %d \n", probe_if.flush_reset_complete); |
| 1048 | fork { |
| 1049 | // @(posedge probe_if.flush_reset_complete); |
| 1050 | printf("Instantiating vera coverage objects\n"); |
| 1051 | printf("probe_if.flush_reset_complete = %d \n", probe_if.flush_reset_complete); |
| 1052 | //ncu_intf_cov_obj = new("ncu_intf_cov_obj", gDbg ); |
| 1053 | //ncu_rtl_cov_obj = new("ncu_rtl_cov_obj", gDbg ); |
| 1054 | Interface_coverage = new(gDbg); |
| 1055 | InitMiscCov(Interface_coverage); |
| 1056 | dram_coverage_obj = new(); |
| 1057 | dmu_coverage_obj = new(dbg); |
| 1058 | |
| 1059 | #ifndef FC_NO_PEU_VERA |
| 1060 | ilu_peu_intf_coverage_obj = new(); |
| 1061 | #endif |
| 1062 | siu_intf_coverage_obj = new(dbg); |
| 1063 | siu_schmoo_coverage_obj = new(dbg); |
| 1064 | siu_ipcs_coverage_obj = new(dbg); |
| 1065 | siu_opcs_coverage_obj = new(dbg); |
| 1066 | fc_cov_obj = new("fc_cov_obj", gDbg ); |
| 1067 | fc_modes_cov_obj = new(); //New modes coverage object |
| 1068 | fc_ncu_internal_coverage_obj = new(dbg); |
| 1069 | fc_siu_internal_coverage_obj = new(dbg); |
| 1070 | fc_l2_internal_coverage_obj = new(dbg); |
| 1071 | fc_siu_ras_coverage_obj = new(dbg); |
| 1072 | #ifndef FC_NO_NIU_T2 |
| 1073 | fc_niu_coverage_obj = new(dbg); |
| 1074 | #endif |
| 1075 | fc_mcu_ras_coverage_obj = new(); |
| 1076 | } join none |
| 1077 | } |
| 1078 | #endif // FC_COVERAGE |
| 1079 | |
| 1080 | // set name of coverage database file |
| 1081 | // Note: this file contains results for _all_ coverage objects |
| 1082 | coverage_set_database_file_name("raw_coverage/coverage.db"); |
| 1083 | // by default, no data saved (until diag passes) |
| 1084 | // unless +force_save_cov is set as vcs plusarg |
| 1085 | if ( mChkPlusarg(force_save_cov) ) { |
| 1086 | coverage_save_database(1); |
| 1087 | } else { |
| 1088 | coverage_save_database(0); |
| 1089 | } |
| 1090 | |
| 1091 | fork { |
| 1092 | #ifndef FC_NO_NIU_T2 |
| 1093 | niu_snd_mbox = alloc(MAILBOX, 0, 1); |
| 1094 | niu_rec_mbox = alloc(MAILBOX, 0, 1); |
| 1095 | siuniu_mon = new(niumon_bind, niu_snd_mbox, niu_rec_mbox, dbg); |
| 1096 | #endif |
| 1097 | dmu_snd_mbox = alloc(MAILBOX, 0, 1); |
| 1098 | dmu_rec_mbox = alloc(MAILBOX, 0, 1); |
| 1099 | siudmu_mon = new(dmumon_bind, dmu_snd_mbox, dmu_rec_mbox, dbg); |
| 1100 | ncu_rec_mbox = alloc(MAILBOX, 0, 1); |
| 1101 | |
| 1102 | // mailbox |
| 1103 | for (i=0; i<8; i++) |
| 1104 | { |
| 1105 | l2_snd_mbox[i] = alloc(MAILBOX, 0, 1); |
| 1106 | l2_rec_mbox[i] = alloc(MAILBOX, 0, 1); |
| 1107 | } |
| 1108 | |
| 1109 | siul2_mon[0] = new(l2_mon_bind0, l2_snd_mbox[0], l2_rec_mbox[0], 0, dbg); |
| 1110 | siul2_mon[1] = new(l2_mon_bind1, l2_snd_mbox[1], l2_rec_mbox[1], 1, dbg); |
| 1111 | siul2_mon[2] = new(l2_mon_bind2, l2_snd_mbox[2], l2_rec_mbox[2], 2, dbg); |
| 1112 | siul2_mon[3] = new(l2_mon_bind3, l2_snd_mbox[3], l2_rec_mbox[3], 3, dbg); |
| 1113 | siul2_mon[4] = new(l2_mon_bind4, l2_snd_mbox[4], l2_rec_mbox[4], 4, dbg); |
| 1114 | siul2_mon[5] = new(l2_mon_bind5, l2_snd_mbox[5], l2_rec_mbox[5], 5, dbg); |
| 1115 | siul2_mon[6] = new(l2_mon_bind6, l2_snd_mbox[6], l2_rec_mbox[6], 6, dbg); |
| 1116 | siul2_mon[7] = new(l2_mon_bind7, l2_snd_mbox[7], l2_rec_mbox[7], 7, dbg); |
| 1117 | |
| 1118 | order_chk = new( |
| 1119 | #ifndef FC_NO_NIU_T2 |
| 1120 | niu_snd_mbox, niu_rec_mbox, |
| 1121 | #endif |
| 1122 | dmu_snd_mbox, dmu_rec_mbox, ncu_rec_mbox, |
| 1123 | l2_snd_mbox[0], l2_rec_mbox[0], |
| 1124 | l2_snd_mbox[1], l2_rec_mbox[1], |
| 1125 | l2_snd_mbox[2], l2_rec_mbox[2], |
| 1126 | l2_snd_mbox[3], l2_rec_mbox[3], |
| 1127 | l2_snd_mbox[4], l2_rec_mbox[4], |
| 1128 | l2_snd_mbox[5], l2_rec_mbox[5], |
| 1129 | l2_snd_mbox[6], l2_rec_mbox[6], |
| 1130 | l2_snd_mbox[7], l2_rec_mbox[7], |
| 1131 | dbg); |
| 1132 | |
| 1133 | } join |
| 1134 | |
| 1135 | //L2 monitors |
| 1136 | fork |
| 1137 | { |
| 1138 | if (!get_plus_arg(CHECK, "cpxorder_disable")) |
| 1139 | MonitorCPX(); |
| 1140 | } |
| 1141 | { |
| 1142 | #ifndef GATESIM |
| 1143 | if (!get_plus_arg(CHECK, "l2jbi_disable")) |
| 1144 | CheckJbiInvBeforeAck(); |
| 1145 | #endif |
| 1146 | } |
| 1147 | join none |
| 1148 | |
| 1149 | if (get_plus_arg(CHECK, "siu_ncu_mondo_chk_on")) |
| 1150 | { |
| 1151 | siu_ncu_mondo_chk = new(mondo_ncu_bind); |
| 1152 | } |
| 1153 | |
| 1154 | #ifndef RXC_SAT |
| 1155 | #ifndef MAC_SAT |
| 1156 | |
| 1157 | #ifndef FC_NO_NIU_T2 |
| 1158 | if ( get_plus_arg(CHECK, "RX_TEST") ) { |
| 1159 | niu_rxdma_wrchk = new; |
| 1160 | } |
| 1161 | #endif |
| 1162 | |
| 1163 | #endif |
| 1164 | #endif |
| 1165 | |
| 1166 | #ifndef FC_NO_NIU_T2 |
| 1167 | if ( get_plus_arg(CHECK, "NIU_NO_PACKET_CHECKER") ) { |
| 1168 | } |
| 1169 | else { |
| 1170 | if (mac_speed0 == 10000) { |
| 1171 | pack_check[0] = new(0,8); // Attach a pc to port 0 |
| 1172 | } else if (mac_speed0 == 1000) { |
| 1173 | pack_check[0] = new(0,1); // Attach a pc to port 0 |
| 1174 | } |
| 1175 | else { |
| 1176 | pack_check[0] = new(0,0); // Attach a pc to port 0 |
| 1177 | } |
| 1178 | |
| 1179 | if (mac_speed1 == 10000) { |
| 1180 | pack_check[1] = new(1,8); // Attach a pc to port 1 |
| 1181 | } else |
| 1182 | if (mac_speed1 == 1000) { |
| 1183 | pack_check[1] = new(1,1); // Attach a pc to port 1 |
| 1184 | } |
| 1185 | else { |
| 1186 | pack_check[1] = new(1,0); // Attach a pc to port 1 |
| 1187 | } |
| 1188 | } |
| 1189 | #endif |
| 1190 | |
| 1191 | fork |
| 1192 | ras_injector = new( |
| 1193 | #ifndef FC_NO_NIU_T2 |
| 1194 | niu_sii_inj_bind, |
| 1195 | #endif |
| 1196 | dmu_sii_inj_bind, |
| 1197 | #ifndef FC_NO_NIU_T2 |
| 1198 | sio_niu_inj_bind, |
| 1199 | #endif |
| 1200 | sio_dmu_inj_bind, l2_0_sio_inj_bind, l2_1_sio_inj_bind, |
| 1201 | l2_2_sio_inj_bind, l2_3_sio_inj_bind, l2_4_sio_inj_bind, |
| 1202 | l2_5_sio_inj_bind, l2_6_sio_inj_bind, l2_7_sio_inj_bind, |
| 1203 | sii_ncu_inj_bind, dbg); |
| 1204 | join none |
| 1205 | |
| 1206 | #ifndef GATESIM |
| 1207 | ras_interrupt = new (1000); // interrupt itme out = 1000 |
| 1208 | #endif |
| 1209 | #ifndef FC_NO_NIU_T2 |
| 1210 | sioniu_errmon = new(sioniu_errmon_bind, dbg); |
| 1211 | #endif |
| 1212 | siodmu_errmon = new(siodmu_errmon_bind, dbg); |
| 1213 | |
| 1214 | //// OK, all setup is done. Do the testing //// |
| 1215 | |
| 1216 | gUtil.wait4termination(gParam.maxCycle); // this task running in background |
| 1217 | |
| 1218 | |
| 1219 | //============= start of big testcases(s) fork/join ================== |
| 1220 | // THIS FORK IS FOR FORKING TESTCASES, DO NOT ADD ANYTHING ELSE HERE. |
| 1221 | // YOUR BENCH CODE GOES ABOVE, BEFORE TESTCASES START. |
| 1222 | //==================================================================== |
| 1223 | |
| 1224 | fork |
| 1225 | { //---- this thread runs PEU diag -------- |
| 1226 | #ifndef FC_NO_PEU_VERA |
| 1227 | //----------------------------------------------------------------------------------- |
| 1228 | // PEU section |
| 1229 | // Executing the PEU diag here |
| 1230 | //----------------------------------------------------------------------------------- |
| 1231 | // |
| 1232 | if (PEU_Test_En == 1) { |
| 1233 | // call this to stop verilog from doing $finish once the asm finishes |
| 1234 | //verilog_set_no_verilog_finish(); // only Vera can finish the simulation |
| 1235 | // Since peutest.execute() never seems to return right now, doing the above |
| 1236 | // will cause the sim to run forever. |
| 1237 | PR_NORMAL(dispmonScope, MON_NORMAL,"PEU Diag Starting Now ; Later it will be initialization of PEU"); |
| 1238 | repeat (40) @(posedge probe_if.clk); |
| 1239 | PiuCsrs = new(); |
| 1240 | peutest = new(); |
| 1241 | |
| 1242 | PR_NORMAL(dispmonScope, MON_NORMAL,"PEU B4 Test.Execute. Waiting for assembly to enable peutest"); |
| 1243 | sync (ALL, e_StartPEUTest); |
| 1244 | PR_NORMAL(dispmonScope, MON_NORMAL,"PEU B4 Test.Execute. Done Waiting for assembly to enable peutest"); |
| 1245 | peutest.execute(); // THIS BETTER BLOCK UNTIL DONE!!! |
| 1246 | } |
| 1247 | #endif |
| 1248 | } |
| 1249 | |
| 1250 | |
| 1251 | |
| 1252 | { //---- this thread invokes vera diag when use JTAG driver ----- |
| 1253 | #ifdef USE_JTAG_DRIVER |
| 1254 | // if (!jtag_reset_done) |
| 1255 | // wait_var(jtag_reset_done); // wait for JTAG TAP is reseted. |
| 1256 | |
| 1257 | // skip this stuff when vera diag wants to run very early on (reset diag). |
| 1258 | //if (! mChkPlusarg(vera_driven_reset)) { |
| 1259 | // call this to stop verilog from doing $finish once the asm finishes |
| 1260 | verilog_set_no_verilog_finish(); // only Vera can finish the simulation |
| 1261 | #ifndef GATESIM |
| 1262 | shScanCapture = new(gDbg); // shadow scan capture whenever tcu_shscan_scan_en = '1' |
| 1263 | #endif |
| 1264 | |
| 1265 | TCU_Test_En = 1; |
| 1266 | TCU_DONE = 0; |
| 1267 | PR_NORMAL(dispmonScope, MON_NORMAL, psprintf("Number of Cores Available: %d", numberOfCores)); |
| 1268 | |
| 1269 | PR_NORMAL(dispmonScope, MON_NORMAL, psprintf("Number of Cores Available: %d", numberOfCores)); |
| 1270 | bootedThreads = gUtil.getThreadEnables(); // get 64-bit finish_mask |
| 1271 | PR_NORMAL(dispmonScope, MON_NORMAL, psprintf("Number of threads enabled: %d", bootedThreads)); |
| 1272 | |
| 1273 | tcuerrorcount = tcu_diag(gDbg); // run vera diag |
| 1274 | TCU_DONE = 1; |
| 1275 | PR_NORMAL(dispmonScope, MON_NORMAL,"DEBUG : TCU Vera Diag completed"); |
| 1276 | |
| 1277 | #endif |
| 1278 | } |
| 1279 | |
| 1280 | { //--- use this thread to run non tcu/peu vera diag -------------------- |
| 1281 | if (gParam.veraDiagName !== null) { |
| 1282 | // call this to stop verilog from doing $finish once the asm finishes |
| 1283 | //verilog_set_no_verilog_finish(); // only Vera can finish the simulation |
| 1284 | // Run the testcase |
| 1285 | // TestCase testCase = new(); // NEEDS to be blocking |
| 1286 | // or block here |
| 1287 | // printf("DEBUG : Other Vera Diag Has Completed \n"); |
| 1288 | } |
| 1289 | } |
| 1290 | |
| 1291 | { //----- thread to wait for assembly diag to complete------ |
| 1292 | if (!get_plus_arg(CHECK, "nowait_asmdiag_done") && gParam.asmDiagName !== null) { |
| 1293 | // if you don't want to wait for asm code to finish, |
| 1294 | // put a condition here other than "1". |
| 1295 | // MUST be off of time zero or sim_status will X -> 0! |
| 1296 | repeat (2) @(posedge probe_if.clk); |
| 1297 | if (asmDiagRun) @(probe_if.sim_status); // verilog half is done |
| 1298 | asmDiagDone = 1; // indicate Assembly diag done |
| 1299 | PR_NORMAL(dispmonScope, MON_NORMAL,"DEBUG : Assembly Diag Has Completed"); |
| 1300 | #ifndef FC_NO_PEU_VERA |
| 1301 | // check whether the peu transations have completed |
| 1302 | if (PEU_Test_En == 1) peutest.CheckIfDone(); |
| 1303 | #endif |
| 1304 | } |
| 1305 | } |
| 1306 | join all // JOIN ALL this may require assembly code to run and finish! |
| 1307 | |
| 1308 | //========================================================================== |
| 1309 | //============= end of big testcase fork/join ============================== |
| 1310 | //========================================================================== |
| 1311 | |
| 1312 | #ifndef FC_NO_NIU_T2 |
| 1313 | // All final wrapup messages etc. here. Assumes an assembly diag |
| 1314 | // ran and passed. If an assembly diag ran and failed this is a don't care. |
| 1315 | if (probe_if.sim_status[ASM_PASS]) { |
| 1316 | // wait for all packets in flight to be checked |
| 1317 | if ( get_plus_arg(CHECK, "RX_TEST") ) { |
| 1318 | sync (ALL, RX_chk_done); |
| 1319 | PR_NORMAL(dispmonScope, MON_NORMAL,"Synced on Event RX_chk_done"); |
| 1320 | } |
| 1321 | } |
| 1322 | #endif |
| 1323 | if (TCU_Test_En == 1) { |
| 1324 | gDbg.errors += tcuerrorcount; // error count from running tcu diag |
| 1325 | } |
| 1326 | |
| 1327 | #ifndef FC_NO_PEU_VERA |
| 1328 | if (PEU_Test_En == 1) { |
| 1329 | gDbg.errors += be_msg.get_error_count(); |
| 1330 | gDbg.warnings += be_msg.get_warning_count(); |
| 1331 | MyReport.report_test_complete(); |
| 1332 | PR_NORMAL(dispmonScope, MON_NORMAL,"DEBUG : A PEU diag ran.\n"); |
| 1333 | } |
| 1334 | #endif |
| 1335 | |
| 1336 | |
| 1337 | // let vera check for errors, print pass/fail only if |
| 1338 | // verilog did not see an error!!! |
| 1339 | if (probe_if.sim_status[ASM_ERR]) |
| 1340 | // have verilog error so tell exitBench |
| 1341 | gUtil.exitBench(*,*,1,1); // (scope, message, noPrint, externalFail) |
| 1342 | else |
| 1343 | // will check gDbg.errors & gDbg.warnings |
| 1344 | gUtil.exitBench(); |
| 1345 | |
| 1346 | |
| 1347 | } // end of main vera program (ie. program fc_test) |