| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ilupeuPioCfgIORdStr.vr |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | class PioCfgIORdPEUStr extends PioBasePEUStr { |
| 36 | |
| 37 | |
| 38 | // ****************************************************************** |
| 39 | // The Test Environment objects need to execute the strategy. |
| 40 | // ****************************************************************** |
| 41 | protected PEUTestEnv _env; |
| 42 | protected integer _errQueue; |
| 43 | |
| 44 | |
| 45 | // ****************************************************************** |
| 46 | // TLP Fields - These fields will be randomized using the parameters |
| 47 | // in the following section, and obeying the constraints defined |
| 48 | // within this class. |
| 49 | // ****************************************************************** |
| 50 | protected bit [1:0] _format_req; |
| 51 | protected bit [1:0] _format_cpl; |
| 52 | protected bit [4:0] _type_req; |
| 53 | protected bit [4:0] _type_cpl; |
| 54 | |
| 55 | protected bit [2:0] _tc; |
| 56 | |
| 57 | protected bit _td_req; |
| 58 | protected bit _td_cpl; |
| 59 | protected bit _ep_req; |
| 60 | protected bit _ep_cpl; |
| 61 | |
| 62 | protected bit [1:0] _attr; |
| 63 | protected bit [9:0] _len_req; |
| 64 | protected bit [9:0] _len_cpl; |
| 65 | protected bit [15:0] _req_id; |
| 66 | protected bit [7:0] _tag; |
| 67 | protected rand bit [31:0] _addr_lsb; |
| 68 | |
| 69 | protected bit [3:0] _last_dwbe; |
| 70 | protected bit [3:0] _first_dwbe; |
| 71 | |
| 72 | protected bit [15:0] _cpl_id; |
| 73 | protected bit [2:0] _cpl_status; |
| 74 | protected bit _bcm; |
| 75 | protected bit [11:0] _byte_count; |
| 76 | protected bit [6:0] _lower_addr; |
| 77 | protected integer _data; |
| 78 | |
| 79 | protected bit [PEC_PCI__HDR] reqHdr; |
| 80 | protected bit [PEC_PCI__HDR] cplHdr; |
| 81 | protected bit [PEC_PCI__HDR] urHdr; |
| 82 | |
| 83 | |
| 84 | |
| 85 | // ****************************************************************** |
| 86 | // The following constraint is used to generate the correct values |
| 87 | // for the TLP. |
| 88 | // ****************************************************************** |
| 89 | constraint generate_tlp { |
| 90 | |
| 91 | this._addr_lsb in {this._addr_lsb_min : this._addr_lsb_max}; |
| 92 | |
| 93 | if (this._type_req == PEC_PCI__TYPE_CFG0) |
| 94 | this._addr_lsb[15:12] == 4'b_0000; |
| 95 | |
| 96 | if (this._type_req == PEC_PCI__TYPE_CFG1) |
| 97 | this._addr_lsb[15:12] == 4'b_0000; |
| 98 | } |
| 99 | |
| 100 | |
| 101 | // ****************************************************************** |
| 102 | // Constructor |
| 103 | // ****************************************************************** |
| 104 | public task new(PEUTestEnv a_env, (integer a_errQueue = 'bx)); |
| 105 | |
| 106 | // ****************************************************************** |
| 107 | // Break this out as common class fullchip and ios can use |
| 108 | // ****************************************************************** |
| 109 | public task SetPacketParams(); |
| 110 | |
| 111 | // ****************************************************************** |
| 112 | // Execute the strategy. Drive a TLP into the ILU, and expect it out |
| 113 | // of the PEU. |
| 114 | // ****************************************************************** |
| 115 | public task Execute(); |
| 116 | } |
| 117 | |
| 118 | |
| 119 | |
| 120 | //------------------------------------------------------------------- |
| 121 | // Method Name: |
| 122 | // Description: |
| 123 | //------------------------------------------------------------------- |
| 124 | task PioCfgIORdPEUStr::new(PEUTestEnv a_env, (integer a_errQueue = 'bx)) { |
| 125 | |
| 126 | |
| 127 | super.new(a_env); |
| 128 | this._env = a_env; |
| 129 | this._errQueue = a_errQueue; |
| 130 | } |
| 131 | |
| 132 | |
| 133 | |
| 134 | //------------------------------------------------------------------- |
| 135 | // Method Name: |
| 136 | // Description: |
| 137 | //------------------------------------------------------------------- |
| 138 | task PioCfgIORdPEUStr::SetPacketParams() { |
| 139 | |
| 140 | integer pass_constrain = 0; |
| 141 | this._env.allocRdTag(this._tag); |
| 142 | |
| 143 | |
| 144 | this._format_req = PEC_PCI__FMT_NO_DATA_3DW; |
| 145 | this._type_cpl = PEC_PCI__TYPE_CPL; |
| 146 | this._tc = 3'b_000; |
| 147 | this._td_req = 1'b_0; |
| 148 | this._ep_req = 1'b_0; |
| 149 | this._attr = 2'b_00; |
| 150 | this._len_req = 10'h_001; |
| 151 | this._req_id = 16'h_0000; |
| 152 | this._last_dwbe = 4'b_0000; |
| 153 | this._byte_count = 12'd_4; |
| 154 | this._lower_addr = 7'b_000_0000; |
| 155 | |
| 156 | |
| 157 | this._first_dwbe = urandom_range(this._first_dwbe_max, this._first_dwbe_min); |
| 158 | this._cpl_id = urandom_range(this._cpl_id_max, this._cpl_id_min); |
| 159 | this._data = urandom_range(this._data_max, this._data_min); |
| 160 | |
| 161 | |
| 162 | randcase { |
| 163 | this._type_req_prob_cfg0 : this._type_req = PEC_PCI__TYPE_CFG0; |
| 164 | this._type_req_prob_cfg1 : this._type_req = PEC_PCI__TYPE_CFG1; |
| 165 | this._type_req_prob_io : this._type_req = PEC_PCI__TYPE_IO; |
| 166 | } |
| 167 | |
| 168 | randcase { |
| 169 | this._td_cpl_prob_false : this._td_cpl = 1'b_0; |
| 170 | this._td_cpl_prob_true : this._td_cpl = 1'b_1; |
| 171 | } |
| 172 | |
| 173 | randcase { |
| 174 | this._ep_cpl_prob_false : this._ep_cpl = 1'b_0; |
| 175 | this._ep_cpl_prob_true : this._ep_cpl = 1'b_1; |
| 176 | } |
| 177 | |
| 178 | randcase { |
| 179 | this._cpl_status_prob_sc : this._cpl_status = PEC_PCI__CPL_STATUS_SC; |
| 180 | this._cpl_status_prob_ur : this._cpl_status = PEC_PCI__CPL_STATUS_UR; |
| 181 | this._cpl_status_prob_crs : this._cpl_status = PEC_PCI__CPL_STATUS_CRS; |
| 182 | this._cpl_status_prob_ca : this._cpl_status = PEC_PCI__CPL_STATUS_CA; |
| 183 | this._cpl_status_prob_rsvd1 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD1; |
| 184 | this._cpl_status_prob_rsvd2 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD2; |
| 185 | this._cpl_status_prob_rsvd3 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD3; |
| 186 | this._cpl_status_prob_rsvd4 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD4; |
| 187 | } |
| 188 | |
| 189 | randcase { |
| 190 | this._bcm_prob_false : this._bcm = 1'b_0; |
| 191 | this._bcm_prob_true : this._bcm = 1'b_1; |
| 192 | } |
| 193 | |
| 194 | |
| 195 | this._format_cpl = (this._cpl_status === PEC_PCI__CPL_STATUS_SC) ? |
| 196 | PEC_PCI__FMT_DATA_3DW : PEC_PCI__FMT_NO_DATA_3DW; |
| 197 | |
| 198 | this._len_cpl = (this._cpl_status === PEC_PCI__CPL_STATUS_SC) ? |
| 199 | 10'h_001 : 10'h_000; |
| 200 | |
| 201 | // Fu: 8/23/06 |
| 202 | #ifdef N2_FC |
| 203 | while (!pass_constrain) |
| 204 | { |
| 205 | this._addr_lsb = urandom_range(this._addr_lsb_max, this._addr_lsb_min); |
| 206 | pass_constrain = 1; |
| 207 | if (this._type_req == PEC_PCI__TYPE_CFG0) |
| 208 | if (this._addr_lsb[15:12] != 4'b_0000) pass_constrain = 0; |
| 209 | |
| 210 | if (this._type_req == PEC_PCI__TYPE_CFG1) |
| 211 | if (this._addr_lsb[15:12] != 4'b_0000) pass_constrain = 0; |
| 212 | } |
| 213 | /// |
| 214 | #else |
| 215 | |
| 216 | if( this.randomize() != OK ) { |
| 217 | _env.Report.report(RTYP_TEST_ERROR,"PioCfgIORdPEUStr::SetPacketParams - randomize failure \n" ); |
| 218 | } |
| 219 | #endif |
| 220 | |
| 221 | reqHdr [PEC_PCI__HDR] = {128{1'b_0}}; |
| 222 | reqHdr [PEC_PCI__FMT] = this._format_req; |
| 223 | reqHdr [PEC_PCI__TYPE] = this._type_req; |
| 224 | reqHdr [PEC_PCI__TC] = this._tc; |
| 225 | reqHdr [PEC_PCI__TD] = this._td_req; |
| 226 | reqHdr [PEC_PCI__EP] = this._ep_req; |
| 227 | reqHdr [PEC_PCI__ATTR] = this._attr; |
| 228 | reqHdr [PEC_PCI__LEN] = this._len_req; |
| 229 | reqHdr [PEC_PCI__REQ_ID] = this._req_id; |
| 230 | reqHdr [PEC_PCI__TLP_TAG] = this._tag; |
| 231 | reqHdr [PEC_PCI__LAST_DWBE] = this._last_dwbe; |
| 232 | reqHdr [PEC_PCI__FIRST_DWBE] = this._first_dwbe; |
| 233 | reqHdr [PEC_PCI__ADDR32] = { this._addr_lsb[31:2], 2'b_00 }; |
| 234 | |
| 235 | cplHdr [PEC_PCI__HDR] = {128{1'b_0}}; |
| 236 | cplHdr [PEC_PCI__FMT] = this._format_cpl; |
| 237 | cplHdr [PEC_PCI__TYPE] = this._type_cpl; |
| 238 | cplHdr [PEC_PCI__TC] = this._tc; |
| 239 | cplHdr [PEC_PCI__TD] = this._td_cpl; |
| 240 | cplHdr [PEC_PCI__EP] = this._ep_cpl; |
| 241 | cplHdr [PEC_PCI__ATTR] = this._attr; |
| 242 | cplHdr [PEC_PCI__LEN] = this._len_cpl; |
| 243 | cplHdr [PEC_PCI__CPL_ID] = this._cpl_id; |
| 244 | cplHdr [PEC_PCI__CPL_STATUS] = this._cpl_status; |
| 245 | cplHdr [PEC_PCI__BCM] = this._bcm; |
| 246 | cplHdr [PEC_PCI__BYTECOUNT] = this._byte_count; |
| 247 | cplHdr [PEC_PCI__CPL_REQ_ID] = this._req_id; |
| 248 | cplHdr [PEC_PCI__CPL_TAG] = this._tag; |
| 249 | cplHdr [PEC_PCI__LOWADDR] = this._lower_addr; |
| 250 | |
| 251 | urHdr [PEC_PCI__HDR] = {128{1'b_0}}; |
| 252 | urHdr [PEC_PCI__FMT] = this._format_cpl; |
| 253 | urHdr [PEC_PCI__TYPE] = this._type_cpl; |
| 254 | urHdr [PEC_PCI__TC] = this._tc; |
| 255 | urHdr [PEC_PCI__TD] = this._td_cpl; |
| 256 | urHdr [PEC_PCI__EP] = this._ep_cpl; |
| 257 | urHdr [PEC_PCI__ATTR] = this._attr; |
| 258 | urHdr [PEC_PCI__LEN] = this._len_cpl; |
| 259 | urHdr [PEC_PCI__CPL_ID] = this._cpl_id; |
| 260 | urHdr [PEC_PCI__CPL_STATUS] = PEC_PCI__CPL_STATUS_UR; |
| 261 | urHdr [PEC_PCI__BCM] = this._bcm; |
| 262 | urHdr [PEC_PCI__BYTECOUNT] = this._byte_count; |
| 263 | urHdr [PEC_PCI__CPL_REQ_ID] = this._req_id; |
| 264 | urHdr [PEC_PCI__CPL_TAG] = this._tag; |
| 265 | urHdr [PEC_PCI__LOWADDR] = this._lower_addr; |
| 266 | |
| 267 | } |
| 268 | |
| 269 | task PioCfgIORdPEUStr::Execute() { |
| 270 | |
| 271 | bit CfgRdCpl=0; //If set the env will flip the completion byte order |
| 272 | // since Denali does it automatically so DMUXtr doesn't |
| 273 | // need to store an array for the payload |
| 274 | |
| 275 | SetPacketParams(); |
| 276 | |
| 277 | this._env.driveILU(reqHdr, 0, 0); |
| 278 | |
| 279 | |
| 280 | this._env.expectPCIE(reqHdr, 0); |
| 281 | |
| 282 | |
| 283 | //Added CfgRdCpl since Denali flips the bytes for Cfg Reads |
| 284 | // this will flip the bytes back so the DMUXtr doesn't need to be changed |
| 285 | //IOS extends this class and has its own execute so it won't affect IOS |
| 286 | //FullChip needs to do the same |
| 287 | CfgRdCpl = (this._type_req !== PEC_PCI__TYPE_IO); |
| 288 | |
| 289 | if ( (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) || |
| 290 | (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) || |
| 291 | (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) || |
| 292 | (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) { |
| 293 | this._env.Pod.FNXPCIEEnableTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplSt ); //Malformed Completion TLP - Reserved completion status (%u). |
| 294 | } |
| 295 | |
| 296 | // |
| 297 | repeat( urandom_range( _env.Scenario.ilupeuPioCfgIORdCplDelayMax, _env.Scenario.ilupeuPioCfgIORdCplDelayMin)) @(posedge CLOCK); |
| 298 | |
| 299 | if ( this._ep_cpl && super.f_abortErrTlp ) |
| 300 | this._env.drivePCIE(cplHdr, this._data, *, *, *, 1,CfgRdCpl); |
| 301 | else |
| 302 | this._env.drivePCIE(cplHdr, this._data,*,*,*,*,CfgRdCpl ); |
| 303 | |
| 304 | |
| 305 | if ((this._cpl_status === PEC_PCI__CPL_STATUS_CA) || |
| 306 | (this._cpl_status === PEC_PCI__CPL_STATUS_UR) || |
| 307 | (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) || |
| 308 | (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) || |
| 309 | (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) || |
| 310 | (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) { |
| 311 | this._env.expectILU(urHdr, this._data); |
| 312 | mailbox_put(this._errQueue, e_ERR_oe_ruc); |
| 313 | mailbox_put(this._errQueue, cplHdr ); |
| 314 | if ( (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) || |
| 315 | (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) || |
| 316 | (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) || |
| 317 | (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) { |
| 318 | this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplSt ); //Malformed Completion TLP - Reserved completion status (%u). |
| 319 | } |
| 320 | } |
| 321 | |
| 322 | else if (this._cpl_status === PEC_PCI__CPL_STATUS_CRS) { |
| 323 | |
| 324 | this._env.expectTimeoutCpl(reqHdr); |
| 325 | mailbox_put(this._errQueue, e_ERR_oe_crs); |
| 326 | mailbox_put(this._errQueue, cplHdr ); |
| 327 | } |
| 328 | |
| 329 | else if (this._ep_cpl === 1'b_1) { |
| 330 | |
| 331 | @(posedge CLOCK); |
| 332 | cplHdr [PEC_PCI__EP] = 0; |
| 333 | CfgRdCpl = 0; //Since a completion has already been sent for this req |
| 334 | // Denali won't flip the read bits |
| 335 | this._env.drivePCIE(cplHdr, this._data,*,*,*,*,CfgRdCpl ); |
| 336 | this._env.expectILU(cplHdr, this._data); |
| 337 | if ( this._errQueue != 0 ) |
| 338 | { |
| 339 | cplHdr [PEC_PCI__EP] = 1; |
| 340 | //N2 - Add checking of request header |
| 341 | |
| 342 | // mailbox_put( this._errQueue, e_ERR_none ); |
| 343 | // mailbox_put( this._errQueue, -1 ); |
| 344 | // mailbox_put( this._errQueue, reqHdr ); |
| 345 | mailbox_put(this._errQueue, e_ERR_ue_pp); |
| 346 | mailbox_put(this._errQueue, cplHdr); |
| 347 | } |
| 348 | } |
| 349 | |
| 350 | else { |
| 351 | |
| 352 | this._env.expectILU(cplHdr, this._data); |
| 353 | } |
| 354 | |
| 355 | |
| 356 | this._env.freePioTag(this._tag); |
| 357 | } |