| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: xmac_util.vr |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #include <vera_defines.vrh> |
| 36 | #include "mac_defines.vri" |
| 37 | #include "xmac_memory_map.vri" |
| 38 | #include "pio_driver.vrh" |
| 39 | #include "mac_pio_class.vrh" |
| 40 | #include "mif_memory_map.vri" |
| 41 | #include "esr_ctl_memory_map.vri" |
| 42 | |
| 43 | extern mac_pio_cl mac_pio_class; |
| 44 | |
| 45 | class mac_util_class { |
| 46 | task new(); |
| 47 | function bit check_cmd(bit [63:0]cmd, bit [63:0] opt); |
| 48 | task get_mac_debug_level(var integer mac_debug, var integer mac_quick,var integer mac_verbose ); |
| 49 | task xmii_init ( integer iport, bit[63:0] cmd); |
| 50 | task mac_loopback_init(); |
| 51 | task mac_init(integer iport, bit [63:0] cmd); |
| 52 | task mac_init_sub(integer iport, bit [63:0] cmd); |
| 53 | task tx_mac_reset(integer iport, bit [39:0] base_addr, integer MAC_INIT_DEBUG); |
| 54 | task rx_mac_reset(integer iport, bit [39:0] base_addr, integer MAC_INIT_DEBUG); |
| 55 | task init_all_reg(integer iport ); |
| 56 | task setup_reg(integer iport, bit[63:0] cmd, bit [39:0] addr, bit [31:0] data,bit [31:0] verify_mask); |
| 57 | task mac_pci_rd(bit [39:0] addr, var bit [31:0] exp_value); |
| 58 | task mac_pci_rd_cmp(bit [39:0] addr, bit [31:0] exp__value, bit [31:0] data_mask); |
| 59 | function bit[39:0] get_mac_reg_base(integer iport); |
| 60 | function bit[(16*20)-1:0] get_xmac_reg_name(integer id); |
| 61 | function bit[32:0] get_xmac_reg_adr(integer id); |
| 62 | function bit[32:0] xmac_reg_addr (integer sel); |
| 63 | function bit[31:0] xmac_reg_mask (integer sel); |
| 64 | function bit[31:0] xmac_reg_default (integer sel); |
| 65 | task wr_ipp_xmac_reg(integer mac_id,bit[39:0] addr, bit[31:0]wr_data); |
| 66 | task rd_ipp_xmac_reg(integer mac_id,bit[39:0] addr, var bit[31:0]rd_data, bit compare ); |
| 67 | task ipp_shadow_rd (bit[39:0] addr, var bit[31:0] rd_data, var bit[31:0] data_mask, var bit data_valid); |
| 68 | task poll_serdes_rdy(); |
| 69 | } |
| 70 | |
| 71 | task mac_util_class :: new(){ } |
| 72 | |
| 73 | // task to poll serdes_rdy signals |
| 74 | task mac_util_class :: poll_serdes_rdy() { |
| 75 | integer count = 0; |
| 76 | integer rdy_detected = 0; |
| 77 | bit [31:0] r_data; |
| 78 | |
| 79 | while(!rdy_detected) { |
| 80 | if(count != 0) |
| 81 | repeat (1000) @(posedge CLOCK); |
| 82 | mac_pio_class.xmac_pio_rd(ESER_INTERNAL_SIGNALS,r_data,1'b0); |
| 83 | if(r_data[29] || r_data[27]) { |
| 84 | count = 0; |
| 85 | rdy_detected = 1; |
| 86 | printf("INFO : serdes_rdy high\n"); |
| 87 | } else { |
| 88 | count++; |
| 89 | if(count > 20) { |
| 90 | printf("ERROR : serdes_rdy didn't go high after 20000 clocks\n"); |
| 91 | rdy_detected = 1; |
| 92 | } else rdy_detected = 0; |
| 93 | } |
| 94 | } |
| 95 | |
| 96 | } |
| 97 | |
| 98 | function bit mac_util_class :: check_cmd(bit [63:0]cmd, bit [63:0] opt){ |
| 99 | if((cmd & opt) > 0) check_cmd=1; |
| 100 | else check_cmd=0; |
| 101 | } |
| 102 | |
| 103 | task mac_util_class::get_mac_debug_level(var integer mac_debug, var integer mac_quick, var integer mac_verbose) { |
| 104 | mac_debug = 0; |
| 105 | if( get_plus_arg( CHECK, "MAC_TEST_DEBUG") ) { |
| 106 | mac_debug = get_plus_arg(NUM, "MAC_TEST_DEBUG" ); |
| 107 | } |
| 108 | mac_quick = get_plus_arg( CHECK, "MAC_QUICK_TEST"); |
| 109 | mac_verbose = get_plus_arg( CHECK, "MAC_VERBOSE_TEST"); |
| 110 | } |
| 111 | |
| 112 | |
| 113 | task mac_util_class::xmii_init(integer iport, bit[63:0] cmd) { |
| 114 | integer mac_debug,mac_quick,mac_verbose; |
| 115 | integer MAC_INIT_DEBUG; |
| 116 | bit [39:0] base_addr; |
| 117 | bit [31:0] data; |
| 118 | |
| 119 | get_mac_debug_level(mac_debug,mac_quick,mac_verbose); |
| 120 | mac_verbose = get_plus_arg( CHECK, "MAC_VERBOSE_TEST"); |
| 121 | printf("xmac_init: xmii_init MAC%0d time=%0d\n", iport, get_time(LO)); |
| 122 | |
| 123 | base_addr = get_mac_reg_base(iport); |
| 124 | if (get_plus_arg(CHECK, "ATCA_MODE")) { |
| 125 | mac_pio_class.xmac_pio_wr(MIF_CONFIG, 32'h0001_0000); //atca mode = 1 |
| 126 | mac_pio_class.xmac_pio_wr(ESER_SERDES_RESET, 32'h0000_0003); //reset the serdes |
| 127 | mac_pio_class.xmac_pio_wr(ESER_SER0_PLL_CONFIG, 32'h0000_0079); //configure to 1G |
| 128 | mac_pio_class.xmac_pio_wr(ESER_SER1_PLL_CONFIG, 32'h0000_0079); //configure to 1G |
| 129 | mac_pio_class.xmac_pio_wr(ESER_SERDES_RESET, 32'h0000_0000); //release the serdes |
| 130 | } |
| 131 | |
| 132 | //mac_pio_class.xmac_pio_wr(base_addr + XTxMAC_SW_RST, 32'h03); //reset |
| 133 | //repeat(10) @(CLOCK); |
| 134 | //mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_SW_RST, 32'h03); //reset |
| 135 | //repeat(10) @(CLOCK); |
| 136 | //tx_mac_reset(iport, base_addr, MAC_INIT_DEBUG); //reset |
| 137 | //rx_mac_reset(iport, base_addr, MAC_INIT_DEBUG); //reset |
| 138 | |
| 139 | if(check_cmd(cmd, MAC_CONF_10000)) data = 32'h0100_0604; |
| 140 | if(check_cmd(cmd, MAC_CONF_1000)) { |
| 141 | if(get_plus_arg(CHECK, "PCS_SERDES")) data = 32'h0d00_0603; |
| 142 | else data = 32'h6D00_0603; |
| 143 | } |
| 144 | if(check_cmd(cmd, MAC_CONF_100)) data = 32'hd500_0703; //D180_0703 |
| 145 | if(check_cmd(cmd, MAC_CONF_10)) data = 32'h5500_0703; //5080_0703 |
| 146 | |
| 147 | data[11] = get_plus_arg(CHECK, "MAC_ER_CK_DIS") ? 0 : 1; |
| 148 | data[18] = get_plus_arg(CHECK, "RX_DROP_PKT_CHECK"); // mac2ipp_pkt_cnt_en |
| 149 | |
| 150 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_CONFIG, data); //first wr to config |
| 151 | |
| 152 | tx_mac_reset(iport, base_addr, MAC_INIT_DEBUG); //reset |
| 153 | rx_mac_reset(iport, base_addr, MAC_INIT_DEBUG); //reset |
| 154 | repeat(2) @(CLOCK); |
| 155 | mac_pio_class.xmac_pio_rd(base_addr + XMAC_CONFIG, data, 1'b0); |
| 156 | //data[0]=1; |
| 157 | //data[8]=1; |
| 158 | printf("xmac_init:MAC%0d Writing XMAC_CONFIG Reg=0x%0h time=%0d\n", iport, data, get_time(LO)); |
| 159 | //mac_pio_class.xmac_pio_wr(base_addr + XMAC_CONFIG, data); //sec wr to config |
| 160 | //tx_mac_reset(iport, base_addr, MAC_INIT_DEBUG); //reset |
| 161 | //rx_mac_reset(iport, base_addr, MAC_INIT_DEBUG); //reset |
| 162 | |
| 163 | if(get_plus_arg(CHECK,"JUMBO_FRAME_EN")) |
| 164 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_MAX, 32'h0000_3FFF); |
| 165 | printf("xmac_init: Setting up MAC to support JUMBO_FRAMES, XMAC_MAX=0x3FFF\n"); |
| 166 | |
| 167 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT1, 32'h0); |
| 168 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT2, 32'h0); |
| 169 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT3, 32'h0); |
| 170 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT4, 32'h0); |
| 171 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT5, 32'h0); |
| 172 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT6, 32'h0); |
| 173 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT7, 32'h0); |
| 174 | data[0] = 1'b1; |
| 175 | data[8] = 1'b1; |
| 176 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_CONFIG, data); //3rd wr to confignn |
| 177 | |
| 178 | // initialize these counters to 0 for proper exit check |
| 179 | if (get_plus_arg(CHECK, "ENABLE_RX_EXIT_ROUTINE")) { |
| 180 | mac_pio_class.xmac_pio_wr(base_addr + MAC_CRC_ER_CNT, 32'h0); |
| 181 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_MPSZER_CNT, 32'h0); |
| 182 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_FRAG_CNT, 32'h0); |
| 183 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_BC_FRM_CNT, 32'h0); |
| 184 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_MC_FRM_CNT, 32'h0); |
| 185 | mac_pio_class.xmac_pio_wr(base_addr + MAC_CD_VIO_CNT, 32'h0); |
| 186 | } |
| 187 | |
| 188 | } |
| 189 | |
| 190 | |
| 191 | //This task program the MAC to enter into loopback mode at xmac levle -- Babu |
| 192 | task mac_util_class :: mac_loopback_init() { |
| 193 | bit [3:0] MAC_LOOP_BACK_MODE; |
| 194 | string init_loopback,temp_port; |
| 195 | bit [31:0] loopback; |
| 196 | bit[39:0] base_addr; |
| 197 | bit [31:0] rd_data, wr_data; |
| 198 | integer j; |
| 199 | |
| 200 | MAC_LOOP_BACK_MODE = 0; |
| 201 | |
| 202 | if( get_plus_arg( CHECK, "MAC_LOOP_BACK=")) { |
| 203 | loopback = get_plus_arg( STR, "MAC_LOOP_BACK="); |
| 204 | init_loopback.bittostr(loopback); |
| 205 | for (j=0; j<init_loopback.len();j++) |
| 206 | { |
| 207 | temp_port =init_loopback.substr(j,j); |
| 208 | MAC_LOOP_BACK_MODE = MAC_LOOP_BACK_MODE | ( 1<<temp_port.atoi()); |
| 209 | } |
| 210 | } |
| 211 | else MAC_LOOP_BACK_MODE = 0; |
| 212 | |
| 213 | |
| 214 | if(MAC_LOOP_BACK_MODE[0]) { |
| 215 | base_addr = get_mac_reg_base(0); |
| 216 | mac_pio_class.xmac_pio_rd(base_addr + XMAC_CONFIG, rd_data,1'b0); |
| 217 | wr_data = rd_data | 32'h0200_0000; |
| 218 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_CONFIG, wr_data); |
| 219 | printf("xmac_init:mac_loopback_init port 0 addr = %x wr_data = %x \n", base_addr + XMAC_CONFIG, wr_data); |
| 220 | } |
| 221 | |
| 222 | if(MAC_LOOP_BACK_MODE[1]) { |
| 223 | base_addr = get_mac_reg_base(1); |
| 224 | mac_pio_class.xmac_pio_rd(base_addr + XMAC_CONFIG, rd_data,1'b0); |
| 225 | wr_data = rd_data | 32'h0200_0000; |
| 226 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_CONFIG, wr_data); |
| 227 | printf("xmac_init:mac_loopback_init port 1 addr = %x wr_data = %x \n", base_addr + XMAC_CONFIG, wr_data); |
| 228 | } |
| 229 | |
| 230 | if(MAC_LOOP_BACK_MODE[2]) { |
| 231 | base_addr = get_mac_reg_base(2); |
| 232 | mac_pio_class.xmac_pio_rd(base_addr + MAC_XIF_CONFIG , rd_data,1'b0); |
| 233 | wr_data = rd_data | 32'h0000_001B; |
| 234 | mac_pio_class.xmac_pio_wr(base_addr + MAC_XIF_CONFIG, wr_data); |
| 235 | printf("xmac_init:mac_loopback_init port 2 addr = %x wr_data = %x \n", base_addr + MAC_XIF_CONFIG, wr_data); |
| 236 | } |
| 237 | |
| 238 | if(MAC_LOOP_BACK_MODE[3]) { |
| 239 | base_addr = get_mac_reg_base(3); |
| 240 | mac_pio_class.xmac_pio_rd(base_addr + MAC_XIF_CONFIG, rd_data,1'b0); |
| 241 | wr_data = rd_data | 32'h0000_001B; |
| 242 | mac_pio_class.xmac_pio_wr(base_addr + MAC_XIF_CONFIG, wr_data); |
| 243 | printf("xmac_init:mac_loopback_init port 3 addr = %x wr_data = %x \n", base_addr + MAC_XIF_CONFIG, wr_data); |
| 244 | } |
| 245 | } |
| 246 | |
| 247 | task mac_util_class::mac_init(integer iport, bit [63:0] cmd) { |
| 248 | bit [31:0] data; |
| 249 | bit [39:0] base_addr; |
| 250 | |
| 251 | printf("xmac_init: Setting up registers for MAC%0d time=%0d\n", iport, get_time(LO)); |
| 252 | cmd[0] = 0; // RX_MAC_RESET |
| 253 | cmd[1] = 0; // TX_MAC_RESET |
| 254 | |
| 255 | if( check_cmd(cmd,MAC_CONF_10000) ) xmii_init(iport,MAC_CONF_10000); |
| 256 | else { |
| 257 | base_addr = get_mac_reg_base(iport); |
| 258 | mac_init_sub(iport,RX_MAC_RESET | TX_MAC_RESET | cmd); |
| 259 | mac_init_sub(iport,RX_MAC_RESET | TX_MAC_RESET | cmd); |
| 260 | mac_init_sub(iport,RX_MAC_RESET | TX_MAC_RESET | cmd); |
| 261 | printf("xmac_init: DONE time=%0d\n", iport, get_time(LO)); |
| 262 | } |
| 263 | } |
| 264 | |
| 265 | |
| 266 | task mac_util_class :: mac_init_sub(integer iport, bit [63:0] cmd) { |
| 267 | bit [39:0] base_addr; |
| 268 | bit [31:0] data, data2, rx_data, tx_data; |
| 269 | integer MAC_INIT_DEBUG; |
| 270 | integer mac_debug,mac_quick,mac_verbose; |
| 271 | |
| 272 | get_mac_debug_level(mac_debug,mac_quick,mac_verbose); |
| 273 | base_addr = get_mac_reg_base(iport); |
| 274 | MAC_INIT_DEBUG = check_cmd(cmd,MI_DEBUG) | mac_debug; |
| 275 | |
| 276 | fork |
| 277 | if(check_cmd(cmd,TX_MAC_RESET)) tx_mac_reset(iport,base_addr,MAC_INIT_DEBUG); |
| 278 | if(check_cmd(cmd,RX_MAC_RESET)) rx_mac_reset(iport,base_addr,MAC_INIT_DEBUG); |
| 279 | join all |
| 280 | |
| 281 | if( check_cmd(cmd,MAC_INIT_ALL_REG) ) init_all_reg(iport ); |
| 282 | |
| 283 | // MAC CONFIG CODE |
| 284 | if( check_cmd(cmd,MAC_CONF_10) | check_cmd(cmd,MAC_CONF_100) | check_cmd(cmd,MAC_CONF_1000) ) { |
| 285 | bit [47:0] tmp48; |
| 286 | |
| 287 | // Disable both rx and tx mac |
| 288 | data = 0; |
| 289 | |
| 290 | // Config register is cleared to all zero's. Both (rx & tx) macs are disabled. |
| 291 | // The only bit that must be set correctly is bit 27. Otherwise the mac might |
| 292 | // not be able to recover. |
| 293 | |
| 294 | data[28] = check_cmd(cmd, MAC_NOT_MUXED) ? 0 : 1; |
| 295 | if( iport>14 | check_cmd(cmd, MAC_CONF_1000) ) { // After bit[28] default modification |
| 296 | data[28] = 0; |
| 297 | data[27] = 1; |
| 298 | } |
| 299 | else data[27] = 0; |
| 300 | data = 32'h0000_0007; |
| 301 | |
| 302 | setup_reg(iport, cmd, base_addr + TxMAC_CONFIG,data, 32'hffff_fff8); |
| 303 | |
| 304 | printf("xmac_init:Waiting for MAC[%0d] Disable to complete ...\n",iport); |
| 305 | mac_pio_class.xmac_pio_rd(base_addr + TxMAC_CONFIG, data,1'b1); |
| 306 | while(data[0] == 1 ) { |
| 307 | repeat(10) @(CLOCK); |
| 308 | mac_pio_class.xmac_pio_rd(base_addr + TxMAC_CONFIG, data,1'b1); |
| 309 | } |
| 310 | |
| 311 | data = 32'h0000_0009; |
| 312 | |
| 313 | if(get_plus_arg( CHECK, "RX_DROP_PKT_CHECK")) |
| 314 | data[18] = 1'b1; // mac2ipp_pkt_cnt_en design/niu/mac/xmac/rtl/xmac_slv.v line:1966 |
| 315 | |
| 316 | setup_reg(iport, cmd, base_addr + RxMAC_CONFIG, data,32'hffff_fff6); |
| 317 | |
| 318 | |
| 319 | mac_pio_class.xmac_pio_rd(base_addr + RxMAC_CONFIG, data,1'b1); |
| 320 | while(data[0] == 1 ) { |
| 321 | repeat(10) @(CLOCK); |
| 322 | mac_pio_class.xmac_pio_rd(base_addr + RxMAC_CONFIG, data,1'b1); |
| 323 | } |
| 324 | |
| 325 | //data = 32'h0000_0019; |
| 326 | //setup_reg(iport, cmd, base_addr + XIF_CONFIG, data,32'hffff_ffe6); |
| 327 | printf("xmac_init:MAC[%0d] Disable completed.\n",iport); |
| 328 | |
| 329 | // Wait for both macs to finish enable |
| 330 | printf("xmac_init:Waiting for MAC[%0d] Enable to complete ...\n",iport); |
| 331 | mac_pio_class.xmac_pio_rd(base_addr + XMAC_CONFIG, data,1'b1); |
| 332 | //while(data[0] == 0 | data[8] == 0) { |
| 333 | // repeat(10) @(CLOCK); |
| 334 | // mac_pci_rd(base_addr + MAC_CONFIG, data); |
| 335 | // } |
| 336 | printf("xmac_init:MAC[%0d] Enable completed.\n",iport); |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | //////////////////////////////////////////////////////////////////////////////// |
| 341 | // mac reset Tasks |
| 342 | //////////////////////////////////////////////////////////////////////////////// |
| 343 | |
| 344 | task mac_util_class::tx_mac_reset(integer iport, bit[39:0] base_addr, integer MAC_INIT_DEBUG) { |
| 345 | bit [31:0] tx_data; |
| 346 | integer count = 0; |
| 347 | |
| 348 | // Assert Reset on TX |
| 349 | mac_pio_class.xmac_pio_wr(base_addr + XTxMAC_SW_RST, 32'h01); |
| 350 | printf("xmac_init:MAC%0d Writing XTxMAC_SW_RST=1 (%h).\n", iport, base_addr+XTxMAC_SW_RST); |
| 351 | |
| 352 | repeat(10) @(CLOCK); |
| 353 | printf("xmac_init:Waiting for TX MAC%0d to reset ...\n",iport); |
| 354 | |
| 355 | // Wait for Reset on TX Mac to complete |
| 356 | mac_pio_class.mac_pio_rd(base_addr + XTxMAC_SW_RST, tx_data); |
| 357 | while(tx_data != 0) { |
| 358 | repeat(5) @(CLOCK); |
| 359 | mac_pio_class.mac_pio_rd(base_addr + XTxMAC_SW_RST, tx_data); |
| 360 | count ++; |
| 361 | if(count > 100) { |
| 362 | tx_data = 32'h0; |
| 363 | printf("ERROR : MACTX_SWRST FAILED\n"); |
| 364 | } |
| 365 | } |
| 366 | |
| 367 | printf("xmac_init:TX MAC%0d reset complete ...\n",iport); |
| 368 | repeat(10) @(CLOCK); |
| 369 | } |
| 370 | |
| 371 | |
| 372 | task mac_util_class :: rx_mac_reset(integer iport, bit [39:0] base_addr, integer MAC_INIT_DEBUG) { |
| 373 | bit [31:0] rx_data; |
| 374 | integer count = 0; |
| 375 | |
| 376 | // Assert Reset on RX Mac |
| 377 | mac_pio_class.xmac_pio_wr(base_addr + XRxMAC_SW_RST, 32'h01); |
| 378 | printf("xmac_init:MAC%0d Writing XRxMAC_SW_RST=1 (%h).\n", iport, base_addr+XRxMAC_SW_RST); |
| 379 | |
| 380 | repeat(10) @(CLOCK); |
| 381 | printf("xmac_init: Waiting for RX MAC%0d to reset ...\n",iport); |
| 382 | |
| 383 | // Wait for Reset on RX Mac to complete |
| 384 | mac_pio_class.mac_pio_rd(base_addr + XRxMAC_SW_RST, rx_data); |
| 385 | while(rx_data != 0) { |
| 386 | repeat(5) @(CLOCK); |
| 387 | mac_pio_class.mac_pio_rd(base_addr + XRxMAC_SW_RST, rx_data); |
| 388 | count ++; |
| 389 | if(count > 100) { |
| 390 | rx_data = 32'h0; |
| 391 | printf("ERROR : MACRX_SWRST FAILED\n"); |
| 392 | } |
| 393 | } |
| 394 | |
| 395 | printf("xmac_init: RX MAC%0d reset complete ...\n",iport); |
| 396 | repeat(10) @(CLOCK); |
| 397 | } |
| 398 | |
| 399 | |
| 400 | |
| 401 | //////////////////////////////////////////////////////////////////////////////// |
| 402 | // |
| 403 | // init_all_reg Task |
| 404 | // |
| 405 | //////////////////////////////////////////////////////////////////////////////// |
| 406 | |
| 407 | task mac_util_class :: init_all_reg(integer iport ) { |
| 408 | bit [47:0] tmp48; |
| 409 | |
| 410 | bit [39:0] base_addr; |
| 411 | bit [31:0] data; |
| 412 | bit [31:0] rd_data; |
| 413 | base_addr = get_mac_reg_base(iport); |
| 414 | |
| 415 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_BT_CNT, 32'h0000_0000); |
| 416 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_BT_CNT, 32'h0000_0000); |
| 417 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_BC_FRM_CNT, 32'h0000_0000); |
| 418 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_MC_FRM_CNT, 32'h0000_0000); |
| 419 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_FRAG_CNT, 32'h0000_0000); |
| 420 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT1, 32'h0000_0000); |
| 421 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT2, 32'h0000_0000); |
| 422 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT3, 32'h0000_0000); |
| 423 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT4, 32'h0000_0000); |
| 424 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT5, 32'h0000_0000); |
| 425 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT6, 32'h0000_0000); |
| 426 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT7, 32'h0000_0000); |
| 427 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_MPSZER_CNT, 32'h0000_0000); |
| 428 | mac_pio_class.xmac_pio_wr(base_addr + MAC_CRC_ER_CNT, 32'h0000_0000); |
| 429 | mac_pio_class.xmac_pio_wr(base_addr + MAC_CD_VIO_CNT, 32'h0000_0000); |
| 430 | mac_pio_class.xmac_pio_wr(base_addr + MAC_AL_ER_CNT, 32'h0000_0000); |
| 431 | |
| 432 | mac_pio_class.xmac_pio_wr(base_addr + TxMAC_FRM_CNT, 32'h0000_0000); |
| 433 | mac_pio_class.xmac_pio_wr(base_addr + TxMAC_BYTE_CNT, 32'h0000_0000); |
| 434 | |
| 435 | |
| 436 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR0, 32'h0000_0000); |
| 437 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR1, 32'h0000_0000); |
| 438 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR2, 32'h0000_0000); |
| 439 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR3, 32'h0000_0000); |
| 440 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR4, 32'h0000_0000); |
| 441 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR5, 32'h0000_0000); |
| 442 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR6, 32'h0000_0000); |
| 443 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR7, 32'h0000_0000); |
| 444 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR8, 32'h0000_0000); |
| 445 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR9, 32'h0000_0000); |
| 446 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR10, 32'h0000_0000); |
| 447 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR11, 32'h0000_0000); |
| 448 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR12, 32'h0000_0000); |
| 449 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR13, 32'h0000_0000); |
| 450 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR14, 32'h0000_0000); |
| 451 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR15, 32'h0000_0000); |
| 452 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR16, 32'h0000_0000); |
| 453 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR17, 32'h0000_0000); |
| 454 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR18, 32'h0000_0000); |
| 455 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR19, 32'h0000_0000); |
| 456 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR20, 32'h0000_0000); |
| 457 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR21, 32'h0000_0000); |
| 458 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR22, 32'h0000_0000); |
| 459 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR23, 32'h0000_0000); |
| 460 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR24, 32'h0000_0000); |
| 461 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR25, 32'h0000_0000); |
| 462 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR26, 32'h0000_0000); |
| 463 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR27, 32'h0000_0000); |
| 464 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR28, 32'h0000_0000); |
| 465 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR29, 32'h0000_0000); |
| 466 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR30, 32'h0000_0000); |
| 467 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR31, 32'h0000_0000); |
| 468 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR32, 32'h0000_0000); |
| 469 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR33, 32'h0000_0000); |
| 470 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR34, 32'h0000_0000); |
| 471 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR35, 32'h0000_0000); |
| 472 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR36, 32'h0000_0000); |
| 473 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR37, 32'h0000_0000); |
| 474 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR38, 32'h0000_0000); |
| 475 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR39, 32'h0000_0000); |
| 476 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR40, 32'h0000_0000); |
| 477 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR41, 32'h0000_0000); |
| 478 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR42, 32'h0000_0000); |
| 479 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR43, 32'h0000_0000); |
| 480 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR44, 32'h0000_0000); |
| 481 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR45, 32'h0000_0000); |
| 482 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR46, 32'h0000_0000); |
| 483 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR47, 32'h0000_0000); |
| 484 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR48, 32'h0000_0000); |
| 485 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR49, 32'h0000_0000); |
| 486 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR50, 32'h0000_0000); |
| 487 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR51, 32'h0000_0000); |
| 488 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR52, 32'h0000_0000); |
| 489 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR53, 32'h0000_0000); |
| 490 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR54, 32'h0000_0000); |
| 491 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR55, 32'h0000_0000); |
| 492 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR56, 32'h0000_0000); |
| 493 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR57, 32'h0000_0000); |
| 494 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR58, 32'h0000_0000); |
| 495 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR59, 32'h0000_0000); |
| 496 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR60, 32'h0000_0000); |
| 497 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR61, 32'h0000_0000); |
| 498 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR62, 32'h0000_0000); |
| 499 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR63, 32'h0000_0000); |
| 500 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR64, 32'h0000_0000); |
| 501 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR65, 32'h0000_0000); |
| 502 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR66, 32'h0000_0000); |
| 503 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR67, 32'h0000_0000); |
| 504 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR68, 32'h0000_0000); |
| 505 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR69, 32'h0000_0000); |
| 506 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR70, 32'h0000_0000); |
| 507 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR71, 32'h0000_0000); |
| 508 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR72, 32'h0000_0000); |
| 509 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR73, 32'h0000_0000); |
| 510 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR74, 32'h0000_0000); |
| 511 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR75, 32'h0000_0000); |
| 512 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR76, 32'h0000_0000); |
| 513 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR77, 32'h0000_0000); |
| 514 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR78, 32'h0000_0000); |
| 515 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR79, 32'h0000_0000); |
| 516 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR80, 32'h0000_0000); |
| 517 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR81, 32'h0000_0000); |
| 518 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR82, 32'h0000_0000); |
| 519 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR83, 32'h0000_0000); |
| 520 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR84, 32'h0000_0000); |
| 521 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR85, 32'h0000_0000); |
| 522 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR86, 32'h0000_0000); |
| 523 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR87, 32'h0000_0000); |
| 524 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR88, 32'h0000_0000); |
| 525 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR89, 32'h0000_0000); |
| 526 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR90, 32'h0000_0000); |
| 527 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR91, 32'h0000_0000); |
| 528 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR92, 32'h0000_0000); |
| 529 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR93, 32'h0000_0000); |
| 530 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR94, 32'h0000_0000); |
| 531 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR95, 32'h0000_0000); |
| 532 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR96, 32'h0000_0000); |
| 533 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR97, 32'h0000_0000); |
| 534 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR98, 32'h0000_0000); |
| 535 | |
| 536 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADD_FILT0, 32'h0000_0000); |
| 537 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADD_FILT1, 32'h0000_0000); |
| 538 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADD_FILT2, 32'h0000_0000); |
| 539 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADD_FILT12_MASK,32'h0000_0000); |
| 540 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADD_FILT00_MASK,32'h0000_0000); |
| 541 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADD_FILT00_MASK,32'h0000_0000); |
| 542 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR_CMPEN_LSB,32'h0000_0000); |
| 543 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_ADDR_CMPEN_MSB,32'h0000_0000); |
| 544 | |
| 545 | |
| 546 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO0, 32'h0000_0000); |
| 547 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO1, 32'h0000_0000); |
| 548 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO2, 32'h0000_0000); |
| 549 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO3, 32'h0000_0000); |
| 550 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO4, 32'h0000_0000); |
| 551 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO5, 32'h0000_0000); |
| 552 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO6, 32'h0000_0000); |
| 553 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO7, 32'h0000_0000); |
| 554 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO8, 32'h0000_0000); |
| 555 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO9, 32'h0000_0000); |
| 556 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO10, 32'h0000_0000); |
| 557 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO11, 32'h0000_0000); |
| 558 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO12, 32'h0000_0000); |
| 559 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO13, 32'h0000_0000); |
| 560 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO14, 32'h0000_0000); |
| 561 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO15, 32'h0000_0000); |
| 562 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO16, 32'h0000_0000); |
| 563 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO17, 32'h0000_0000); |
| 564 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO18, 32'h0000_0000); |
| 565 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO19, 32'h0000_0000); |
| 566 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO20, 32'h0000_0000); |
| 567 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO21, 32'h0000_0000); |
| 568 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO22, 32'h0000_0000); |
| 569 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO23, 32'h0000_0000); |
| 570 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO24, 32'h0000_0000); |
| 571 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO25, 32'h0000_0000); |
| 572 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO26, 32'h0000_0000); |
| 573 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO27, 32'h0000_0000); |
| 574 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO28, 32'h0000_0000); |
| 575 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO29, 32'h0000_0000); |
| 576 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO30, 32'h0000_0000); |
| 577 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_HOST_INFO31, 32'h0000_0000); |
| 578 | |
| 579 | |
| 580 | } |
| 581 | |
| 582 | //////////////////////////////////////////////////////////////////////////////// |
| 583 | // |
| 584 | // setup_res Task |
| 585 | // |
| 586 | //////////////////////////////////////////////////////////////////////////////// |
| 587 | |
| 588 | task mac_util_class :: setup_reg(integer iport, bit[63:0] cmd, bit [39:0] addr, bit [31:0] data, bit [31:0] verify_mask) { |
| 589 | bit [31:0] data2; |
| 590 | |
| 591 | if(check_cmd(cmd,MI_DEBUG)) |
| 592 | printf("xmac_init:MAC%0d Writing %s Reg=0x%0h (%h).\n", iport, get_xmac_reg_name(addr[7:0]), data, addr); |
| 593 | |
| 594 | mac_pio_class.xmac_pio_wr(addr, data); |
| 595 | |
| 596 | if(check_cmd(cmd,MAC_REG_VERIFY)) { // This is just for basic SANITY testing |
| 597 | mac_pio_class.mac_pio_rd(addr, data2); |
| 598 | if((data & verify_mask) != (data2 & verify_mask)) |
| 599 | printf("Error: xmac_init: Register Write Verify: Register %s (%h), Wrote: %h Read: %h Mask: %h\n", |
| 600 | get_xmac_reg_name(addr[7:0]),addr,data,data2,verify_mask); |
| 601 | } |
| 602 | } |
| 603 | |
| 604 | task mac_util_class :: wr_ipp_xmac_reg(integer mac_id, bit[39:0] addr, bit[31:0] wr_data) { |
| 605 | bit [32:0] base_addr; |
| 606 | base_addr = get_mac_reg_base(mac_id); |
| 607 | |
| 608 | mac_pio_class.xmac_pio_wr(base_addr + addr, wr_data); |
| 609 | } |
| 610 | |
| 611 | task mac_util_class :: rd_ipp_xmac_reg(integer mac_id,bit[39:0] addr, \ |
| 612 | var bit[31:0]rd_data, bit compare) { |
| 613 | bit [32:0] base_addr; |
| 614 | base_addr = get_mac_reg_base(mac_id); |
| 615 | |
| 616 | mac_pio_class.xmac_pio_rd(base_addr + addr, rd_data,compare); |
| 617 | } |
| 618 | |
| 619 | task mac_util_class :: ipp_shadow_rd (bit[39:0] addr, var bit[31:0] rd_data,\ |
| 620 | var bit[31:0] data_mask, var bit data_valid) { |
| 621 | integer port_id; |
| 622 | case(addr[19:12]) |
| 623 | { |
| 624 | 8'h80:port_id = 0; |
| 625 | 8'h82:port_id = 0; |
| 626 | 8'h86:port_id = 1; |
| 627 | 8'h88:port_id = 1; |
| 628 | 8'h8c:port_id = 2; |
| 629 | 8'h90:port_id = 3; |
| 630 | } |
| 631 | mac_pio_class.xmac_shadow_class[port_id].get_data(addr,rd_data,data_mask,data_valid); |
| 632 | } |
| 633 | |
| 634 | //////////////////////////////////////////////////////////////////////////////// |
| 635 | // |
| 636 | // mac_pci_rd Task |
| 637 | // |
| 638 | //////////////////////////////////////////////////////////////////////////////// |
| 639 | |
| 640 | task mac_util_class :: mac_pci_rd(bit [39:0] addr, var bit [31:0] exp_value) { |
| 641 | semaphore_get(WAIT, mac_pio_class.pio_drv_mac.pio_access, 1); |
| 642 | mac_pio_class.pio_drv_mac.address = addr; |
| 643 | mac_pio_class.pio_drv_mac.rd_wr = 1'b1; |
| 644 | mac_pio_class.pio_drv_mac.cfg_access = 1'b0; |
| 645 | //pio_driver.exp_data = exp_value; |
| 646 | //pio_driver.data_mask = 0; |
| 647 | //pio_driver.data_mask = 32'hffff_ffff; |
| 648 | //pio_driver.exp_data_valid = 1'b1; |
| 649 | trigger(ONE_SHOT, mac_pio_class.pio_drv_mac.pio_start); |
| 650 | sync(ALL, mac_pio_class.pio_drv_mac.pio_complete); |
| 651 | exp_value = mac_pio_class.pio_drv_mac.rd_data; |
| 652 | semaphore_put(mac_pio_class.pio_drv_mac.pio_access, 1); |
| 653 | } |
| 654 | |
| 655 | |
| 656 | |
| 657 | task mac_util_class :: mac_pci_rd_cmp(bit [39:0] addr, bit [31:0] exp_value, bit [31:0] data_mask) { |
| 658 | semaphore_get(WAIT, mac_pio_class.pio_drv_mac.pio_access, 1); |
| 659 | mac_pio_class.pio_drv_mac.address = addr; |
| 660 | mac_pio_class.pio_drv_mac.rd_wr = 1'b1; |
| 661 | mac_pio_class.pio_drv_mac.cfg_access = 1'b0; |
| 662 | //pio_driver.exp_data = exp_value; |
| 663 | //pio_driver.data_mask = data_mask; |
| 664 | //pio_driver.exp_data_valid = 1'b1; |
| 665 | trigger(ONE_SHOT, mac_pio_class.pio_drv_mac.pio_start); |
| 666 | sync(ALL, mac_pio_class.pio_drv_mac.pio_complete); |
| 667 | |
| 668 | /***** |
| 669 | if ((pio_driver.rd_data & pio_driver.data_mask) !== (pio_driver.exp_data & pio_driver.data_mask)) { |
| 670 | printf("Error: Register %s (%h) data mismatch: \n",get_xmac_reg_name(addr[7:0]),addr); |
| 671 | printf(" Expected: %h Got: %h Mask: %h\n",pio_driver.exp_data, |
| 672 | pio_driver.rd_data, pio_driver.data_mask); |
| 673 | printf("\n"); |
| 674 | } |
| 675 | ****/ |
| 676 | |
| 677 | semaphore_put(mac_pio_class.pio_drv_mac.pio_access, 1); |
| 678 | } |
| 679 | |
| 680 | |
| 681 | function bit[39:0] mac_util_class :: get_mac_reg_base(integer iport) { |
| 682 | |
| 683 | case(iport) { |
| 684 | 0: get_mac_reg_base = MAC0_BASE; |
| 685 | 1: get_mac_reg_base = MAC1_BASE; |
| 686 | 2: get_mac_reg_base = MAC2_BASE; |
| 687 | 3: get_mac_reg_base = MAC3_BASE; |
| 688 | default: error("Error: Invalid PORT (%0d) for get_mac_reg_base task.\n",iport); |
| 689 | } |
| 690 | |
| 691 | } |
| 692 | |
| 693 | |
| 694 | |
| 695 | function bit[(16*20)-1:0] mac_util_class :: get_xmac_reg_name(integer id) { |
| 696 | case(id) { |
| 697 | |
| 698 | XTxMAC_SW_RST: get_xmac_reg_name = "XTxMAC_SW_RST"; |
| 699 | XRxMAC_SW_RST: get_xmac_reg_name = "XRxMAC_SW_RST"; |
| 700 | XTxMAC_STATUS: get_xmac_reg_name = "XTxMAC_STATUS"; |
| 701 | XRxMAC_STATUS: get_xmac_reg_name = "XRxMAC_STATUS"; |
| 702 | XMAC_CTRL_STAT: get_xmac_reg_name = "XMAC_CTRL_STAT"; |
| 703 | XTxMAC_STAT_MSK: get_xmac_reg_name = "XTxMAC_STAT_MSK"; |
| 704 | XRxMAC_STAT_MSK: get_xmac_reg_name = "XRxMAC_STAT_MSK"; |
| 705 | XMAC_C_S_MSK: get_xmac_reg_name = "XMAC_C_S_MSK"; |
| 706 | XMAC_CONFIG: get_xmac_reg_name = "XMAC_CONFIG"; |
| 707 | XMAC_IPG: get_xmac_reg_name = "XMAC_IPG"; |
| 708 | XMAC_MIN: get_xmac_reg_name = "XMAC_MIN"; |
| 709 | XMAC_MAX: get_xmac_reg_name = "XMAC_MAX"; |
| 710 | RxMAC_BT_CNT: get_xmac_reg_name = "RxMAC_BT_CNT"; |
| 711 | RxMAC_BC_FRM_CNT: get_xmac_reg_name = "RxMAC_BC_FRM_CNT"; |
| 712 | RxMAC_MC_FRM_CNT: get_xmac_reg_name = "RxMAC_MC_FRM_CNT"; |
| 713 | RxMAC_FRAG_CNT: get_xmac_reg_name = "RxMAC_FRAG_CNT"; |
| 714 | RxMAC_HIST_CNT1: get_xmac_reg_name = "RxMAC_HIST_CNT1"; |
| 715 | RxMAC_HIST_CNT2: get_xmac_reg_name = "RxMAC_HIST_CNT2"; |
| 716 | RxMAC_HIST_CNT3: get_xmac_reg_name = "RxMAC_HIST_CNT3"; |
| 717 | RxMAC_HIST_CNT4: get_xmac_reg_name = "RxMAC_HIST_CNT4"; |
| 718 | RxMAC_HIST_CNT5: get_xmac_reg_name = "RxMAC_HIST_CNT5"; |
| 719 | RxMAC_HIST_CNT6: get_xmac_reg_name = "RxMAC_HIST_CNT6"; |
| 720 | RxMAC_MPSZER_CNT: get_xmac_reg_name = "RxMAC_MPSZER_CNT"; |
| 721 | MAC_CRC_ER_CNT: get_xmac_reg_name = "MAC_CRC_ER_CNT"; |
| 722 | MAC_CD_VIO_CNT: get_xmac_reg_name = "MAC_CD_VIO_CNT"; |
| 723 | MAC_AL_ER_CNT: get_xmac_reg_name = "MAC_AL_ER_CNT"; |
| 724 | TxMAC_FRM_CNT: get_xmac_reg_name = "TxMAC_FRM_CNT"; |
| 725 | TxMAC_BYTE_CNT: get_xmac_reg_name = "TxMAC_BYTE_CNT"; |
| 726 | XMAC_SM_REG: get_xmac_reg_name = "XMAC_SM_REG"; |
| 727 | XMAC_ADDR_CMPEN_LSB: get_xmac_reg_name = "XMAC_ADDR_CMPEN_LSB"; |
| 728 | XMAC_ADDR_CMPEN_MSB: get_xmac_reg_name = "XMAC_ADDR_CMPEN_MSB"; |
| 729 | XMAC_ADDR0: get_xmac_reg_name = "XMAC_ADDR0"; |
| 730 | XMAC_ADDR1: get_xmac_reg_name = "XMAC_ADDR1"; |
| 731 | XMAC_ADDR2: get_xmac_reg_name = "XMAC_ADDR2"; |
| 732 | XMAC_ADDR3: get_xmac_reg_name = "XMAC_ADDR3"; |
| 733 | XMAC_ADDR4: get_xmac_reg_name = "XMAC_ADDR4"; |
| 734 | XMAC_ADDR5: get_xmac_reg_name = "XMAC_ADDR5"; |
| 735 | XMAC_ADDR6: get_xmac_reg_name = "XMAC_ADDR6"; |
| 736 | XMAC_ADDR7: get_xmac_reg_name = "XMAC_ADDR7"; |
| 737 | XMAC_ADDR8: get_xmac_reg_name = "XMAC_ADDR8"; |
| 738 | XMAC_ADDR9: get_xmac_reg_name = "XMAC_ADDR9"; |
| 739 | XMAC_ADDR10: get_xmac_reg_name = "XMAC_ADDR10"; |
| 740 | XMAC_ADDR11: get_xmac_reg_name = "XMAC_ADDR11"; |
| 741 | XMAC_ADDR12: get_xmac_reg_name = "XMAC_ADDR12"; |
| 742 | XMAC_ADDR13: get_xmac_reg_name = "XMAC_ADDR13"; |
| 743 | XMAC_ADDR14: get_xmac_reg_name = "XMAC_ADDR14"; |
| 744 | XMAC_ADDR15: get_xmac_reg_name = "XMAC_ADDR15"; |
| 745 | XMAC_ADDR16: get_xmac_reg_name = "XMAC_ADDR16"; |
| 746 | XMAC_ADDR17: get_xmac_reg_name = "XMAC_ADDR17"; |
| 747 | XMAC_ADDR18: get_xmac_reg_name = "XMAC_ADDR18"; |
| 748 | XMAC_ADDR19: get_xmac_reg_name = "XMAC_ADDR19"; |
| 749 | XMAC_ADDR20: get_xmac_reg_name = "XMAC_ADDR20"; |
| 750 | XMAC_ADDR21: get_xmac_reg_name = "XMAC_ADDR21"; |
| 751 | XMAC_ADDR22: get_xmac_reg_name = "XMAC_ADDR22"; |
| 752 | XMAC_ADDR23: get_xmac_reg_name = "XMAC_ADDR23"; |
| 753 | XMAC_ADDR24: get_xmac_reg_name = "XMAC_ADDR24"; |
| 754 | XMAC_ADDR25: get_xmac_reg_name = "XMAC_ADDR25"; |
| 755 | XMAC_ADDR26: get_xmac_reg_name = "XMAC_ADDR26"; |
| 756 | XMAC_ADDR27: get_xmac_reg_name = "XMAC_ADDR27"; |
| 757 | XMAC_ADDR28: get_xmac_reg_name = "XMAC_ADDR28"; |
| 758 | XMAC_ADDR29: get_xmac_reg_name = "XMAC_ADDR29"; |
| 759 | XMAC_ADDR30: get_xmac_reg_name = "XMAC_ADDR30"; |
| 760 | XMAC_ADDR31: get_xmac_reg_name = "XMAC_ADDR31"; |
| 761 | XMAC_ADDR32: get_xmac_reg_name = "XMAC_ADDR32"; |
| 762 | XMAC_ADDR33: get_xmac_reg_name = "XMAC_ADDR33"; |
| 763 | XMAC_ADDR34: get_xmac_reg_name = "XMAC_ADDR34"; |
| 764 | XMAC_ADDR35: get_xmac_reg_name = "XMAC_ADDR35"; |
| 765 | XMAC_ADDR36: get_xmac_reg_name = "XMAC_ADDR36"; |
| 766 | XMAC_ADDR37: get_xmac_reg_name = "XMAC_ADDR37"; |
| 767 | XMAC_ADDR38: get_xmac_reg_name = "XMAC_ADDR38"; |
| 768 | XMAC_ADDR39: get_xmac_reg_name = "XMAC_ADDR39"; |
| 769 | XMAC_ADDR40: get_xmac_reg_name = "XMAC_ADDR40"; |
| 770 | XMAC_ADDR41: get_xmac_reg_name = "XMAC_ADDR41"; |
| 771 | XMAC_ADDR42: get_xmac_reg_name = "XMAC_ADDR42"; |
| 772 | XMAC_ADDR43: get_xmac_reg_name = "XMAC_ADDR43"; |
| 773 | XMAC_ADDR44: get_xmac_reg_name = "XMAC_ADDR44"; |
| 774 | XMAC_ADDR45: get_xmac_reg_name = "XMAC_ADDR45"; |
| 775 | XMAC_ADDR46: get_xmac_reg_name = "XMAC_ADDR46"; |
| 776 | XMAC_ADDR47: get_xmac_reg_name = "XMAC_ADDR47"; |
| 777 | XMAC_ADDR48: get_xmac_reg_name = "XMAC_ADDR48"; |
| 778 | XMAC_ADDR49: get_xmac_reg_name = "XMAC_ADDR49"; |
| 779 | XMAC_ADDR50: get_xmac_reg_name = "XMAC_ADDR50"; |
| 780 | |
| 781 | XMAC_ADDR51: get_xmac_reg_name = "XMAC_ADDR51"; |
| 782 | XMAC_ADDR52: get_xmac_reg_name = "XMAC_ADDR52"; |
| 783 | XMAC_ADDR53: get_xmac_reg_name = "XMAC_ADDR53"; |
| 784 | XMAC_ADDR54: get_xmac_reg_name = "XMAC_ADDR54"; |
| 785 | XMAC_ADDR55: get_xmac_reg_name = "XMAC_ADDR55"; |
| 786 | XMAC_ADDR56: get_xmac_reg_name = "XMAC_ADDR56"; |
| 787 | XMAC_ADDR57: get_xmac_reg_name = "XMAC_ADDR57"; |
| 788 | XMAC_ADDR58: get_xmac_reg_name = "XMAC_ADDR58"; |
| 789 | XMAC_ADDR59: get_xmac_reg_name = "XMAC_ADDR59"; |
| 790 | XMAC_ADDR60: get_xmac_reg_name = "XMAC_ADDR60"; |
| 791 | XMAC_ADDR61: get_xmac_reg_name = "XMAC_ADDR61"; |
| 792 | XMAC_ADDR62: get_xmac_reg_name = "XMAC_ADDR62"; |
| 793 | XMAC_ADDR63: get_xmac_reg_name = "XMAC_ADDR63"; |
| 794 | XMAC_ADDR64: get_xmac_reg_name = "XMAC_ADDR64"; |
| 795 | XMAC_ADDR65: get_xmac_reg_name = "XMAC_ADDR65"; |
| 796 | XMAC_ADDR66: get_xmac_reg_name = "XMAC_ADDR66"; |
| 797 | XMAC_ADDR67: get_xmac_reg_name = "XMAC_ADDR67"; |
| 798 | XMAC_ADDR68: get_xmac_reg_name = "XMAC_ADDR68"; |
| 799 | XMAC_ADDR69: get_xmac_reg_name = "XMAC_ADDR69"; |
| 800 | XMAC_ADDR70: get_xmac_reg_name = "XMAC_ADDR70"; |
| 801 | XMAC_ADDR71: get_xmac_reg_name = "XMAC_ADDR71"; |
| 802 | XMAC_ADDR72: get_xmac_reg_name = "XMAC_ADDR72"; |
| 803 | XMAC_ADDR73: get_xmac_reg_name = "XMAC_ADDR73"; |
| 804 | XMAC_ADDR74: get_xmac_reg_name = "XMAC_ADDR74"; |
| 805 | XMAC_ADDR75: get_xmac_reg_name = "XMAC_ADDR75"; |
| 806 | XMAC_ADDR76: get_xmac_reg_name = "XMAC_ADDR76"; |
| 807 | XMAC_ADDR77: get_xmac_reg_name = "XMAC_ADDR77"; |
| 808 | XMAC_ADDR78: get_xmac_reg_name = "XMAC_ADDR78"; |
| 809 | XMAC_ADDR79: get_xmac_reg_name = "XMAC_ADDR79"; |
| 810 | XMAC_ADDR80: get_xmac_reg_name = "XMAC_ADDR80"; |
| 811 | XMAC_ADDR81: get_xmac_reg_name = "XMAC_ADDR81"; |
| 812 | XMAC_ADDR82: get_xmac_reg_name = "XMAC_ADDR82"; |
| 813 | XMAC_ADDR83: get_xmac_reg_name = "XMAC_ADDR83"; |
| 814 | XMAC_ADDR84: get_xmac_reg_name = "XMAC_ADDR84"; |
| 815 | XMAC_ADDR85: get_xmac_reg_name = "XMAC_ADDR85"; |
| 816 | XMAC_ADDR86: get_xmac_reg_name = "XMAC_ADDR86"; |
| 817 | XMAC_ADDR87: get_xmac_reg_name = "XMAC_ADDR87"; |
| 818 | XMAC_ADDR88: get_xmac_reg_name = "XMAC_ADDR88"; |
| 819 | XMAC_ADDR89: get_xmac_reg_name = "XMAC_ADDR89"; |
| 820 | XMAC_ADDR90: get_xmac_reg_name = "XMAC_ADDR90"; |
| 821 | XMAC_ADDR91: get_xmac_reg_name = "XMAC_ADDR91"; |
| 822 | XMAC_ADDR92: get_xmac_reg_name = "XMAC_ADDR92"; |
| 823 | XMAC_ADDR93: get_xmac_reg_name = "XMAC_ADDR93"; |
| 824 | XMAC_ADDR94: get_xmac_reg_name = "XMAC_ADDR94"; |
| 825 | XMAC_ADDR95: get_xmac_reg_name = "XMAC_ADDR95"; |
| 826 | XMAC_ADDR96: get_xmac_reg_name = "XMAC_ADDR96"; |
| 827 | XMAC_ADDR97: get_xmac_reg_name = "XMAC_ADDR97"; |
| 828 | XMAC_ADDR98: get_xmac_reg_name = "XMAC_ADDR98"; |
| 829 | |
| 830 | |
| 831 | |
| 832 | XMAC_FC_ADDR0: get_xmac_reg_name = "XMAC_FC_ADDR0"; |
| 833 | XMAC_FC_ADDR1: get_xmac_reg_name = "XMAC_FC_ADDR1"; |
| 834 | XMAC_FC_ADDR2: get_xmac_reg_name = "XMAC_FC_ADDR2"; |
| 835 | |
| 836 | XMAC_ADD_FILT0: get_xmac_reg_name = "XMAC_ADD_FILT0"; |
| 837 | XMAC_ADD_FILT1: get_xmac_reg_name = "XMAC_ADD_FILT1"; |
| 838 | XMAC_ADD_FILT2: get_xmac_reg_name = "XMAC_ADD_FILT2"; |
| 839 | XMAC_ADD_FILT12_MASK: get_xmac_reg_name = "XMAC_ADD_FILT12_MASK"; |
| 840 | XMAC_ADD_FILT00_MASK: get_xmac_reg_name = "XMAC_ADD_FILT00_MASK"; |
| 841 | |
| 842 | XMAC_HASH_TBL0: get_xmac_reg_name = "XMAC_HASH_TBL0"; |
| 843 | XMAC_HASH_TBL1: get_xmac_reg_name = "XMAC_HASH_TBL1"; |
| 844 | XMAC_HASH_TBL2: get_xmac_reg_name = "XMAC_HASH_TBL2"; |
| 845 | XMAC_HASH_TBL3: get_xmac_reg_name = "XMAC_HASH_TBL3"; |
| 846 | XMAC_HASH_TBL4: get_xmac_reg_name = "XMAC_HASH_TBL4"; |
| 847 | XMAC_HASH_TBL5: get_xmac_reg_name = "XMAC_HASH_TBL5"; |
| 848 | XMAC_HASH_TBL6: get_xmac_reg_name = "XMAC_HASH_TBL6"; |
| 849 | XMAC_HASH_TBL7: get_xmac_reg_name = "XMAC_HASH_TBL7"; |
| 850 | XMAC_HASH_TBL8: get_xmac_reg_name = "XMAC_HASH_TBL8"; |
| 851 | XMAC_HASH_TBL9: get_xmac_reg_name = "XMAC_HASH_TBL9"; |
| 852 | XMAC_HASH_TBL10: get_xmac_reg_name = "XMAC_HASH_TBL10"; |
| 853 | XMAC_HASH_TBL11: get_xmac_reg_name = "XMAC_HASH_TBL11"; |
| 854 | XMAC_HASH_TBL12: get_xmac_reg_name = "XMAC_HASH_TBL12"; |
| 855 | XMAC_HASH_TBL13: get_xmac_reg_name = "XMAC_HASH_TBL13"; |
| 856 | XMAC_HASH_TBL14: get_xmac_reg_name = "XMAC_HASH_TBL14"; |
| 857 | XMAC_HASH_TBL15: get_xmac_reg_name = "XMAC_HASH_TBL15"; |
| 858 | |
| 859 | |
| 860 | XMAC_HOST_INFO0: get_xmac_reg_name = "XMAC_HOST_INFO0"; |
| 861 | XMAC_HOST_INFO1: get_xmac_reg_name = "XMAC_HOST_INFO1"; |
| 862 | XMAC_HOST_INFO2: get_xmac_reg_name = "XMAC_HOST_INFO2"; |
| 863 | XMAC_HOST_INFO3: get_xmac_reg_name = "XMAC_HOST_INFO3"; |
| 864 | XMAC_HOST_INFO4: get_xmac_reg_name = "XMAC_HOST_INFO4"; |
| 865 | XMAC_HOST_INFO5: get_xmac_reg_name = "XMAC_HOST_INFO5"; |
| 866 | XMAC_HOST_INFO6: get_xmac_reg_name = "XMAC_HOST_INFO6"; |
| 867 | XMAC_HOST_INFO7: get_xmac_reg_name = "XMAC_HOST_INFO7"; |
| 868 | XMAC_HOST_INFO8: get_xmac_reg_name = "XMAC_HOST_INFO8"; |
| 869 | XMAC_HOST_INFO9: get_xmac_reg_name = "XMAC_HOST_INFO9"; |
| 870 | XMAC_HOST_INFO10: get_xmac_reg_name = "XMAC_HOST_INFO10"; |
| 871 | XMAC_HOST_INFO11: get_xmac_reg_name = "XMAC_HOST_INFO11"; |
| 872 | XMAC_HOST_INFO12: get_xmac_reg_name = "XMAC_HOST_INFO12"; |
| 873 | XMAC_HOST_INFO13: get_xmac_reg_name = "XMAC_HOST_INFO13"; |
| 874 | XMAC_HOST_INFO14: get_xmac_reg_name = "XMAC_HOST_INFO14"; |
| 875 | XMAC_HOST_INFO15: get_xmac_reg_name = "XMAC_HOST_INFO15"; |
| 876 | XMAC_HOST_INFO16: get_xmac_reg_name = "XMAC_HOST_INFO16"; |
| 877 | XMAC_HOST_INFO17: get_xmac_reg_name = "XMAC_HOST_INFO17"; |
| 878 | XMAC_HOST_INFO18: get_xmac_reg_name = "XMAC_HOST_INFO18"; |
| 879 | XMAC_HOST_INFO19: get_xmac_reg_name = "XMAC_HOST_INFO19"; |
| 880 | XMAC_HOST_INFO20: get_xmac_reg_name = "XMAC_HOST_INFO20"; |
| 881 | XMAC_HOST_INFO21: get_xmac_reg_name = "XMAC_HOST_INFO21"; |
| 882 | XMAC_HOST_INFO22: get_xmac_reg_name = "XMAC_HOST_INFO22"; |
| 883 | XMAC_HOST_INFO23: get_xmac_reg_name = "XMAC_HOST_INFO23"; |
| 884 | XMAC_HOST_INFO24: get_xmac_reg_name = "XMAC_HOST_INFO24"; |
| 885 | XMAC_HOST_INFO25: get_xmac_reg_name = "XMAC_HOST_INFO25"; |
| 886 | XMAC_HOST_INFO26: get_xmac_reg_name = "XMAC_HOST_INFO26"; |
| 887 | XMAC_HOST_INFO27: get_xmac_reg_name = "XMAC_HOST_INFO27"; |
| 888 | XMAC_HOST_INFO28: get_xmac_reg_name = "XMAC_HOST_INFO28"; |
| 889 | XMAC_HOST_INFO29: get_xmac_reg_name = "XMAC_HOST_INFO29"; |
| 890 | XMAC_HOST_INFO30: get_xmac_reg_name = "XMAC_HOST_INFO30"; |
| 891 | XMAC_HOST_INFO31: get_xmac_reg_name = "XMAC_HOST_INFO31"; |
| 892 | |
| 893 | |
| 894 | |
| 895 | } |
| 896 | } |
| 897 | |
| 898 | function bit[32:0] mac_util_class :: get_xmac_reg_adr(integer id) { |
| 899 | case(id) { |
| 900 | 0: get_xmac_reg_adr = XTxMAC_SW_RST; |
| 901 | 1: get_xmac_reg_adr = XRxMAC_SW_RST; |
| 902 | 2: get_xmac_reg_adr = XTxMAC_STATUS; |
| 903 | 3: get_xmac_reg_adr = XRxMAC_STATUS; |
| 904 | 4: get_xmac_reg_adr = XMAC_CTRL_STAT; |
| 905 | 5: get_xmac_reg_adr = XTxMAC_STAT_MSK; |
| 906 | 6: get_xmac_reg_adr = XRxMAC_STAT_MSK; |
| 907 | 7: get_xmac_reg_adr = XMAC_C_S_MSK; |
| 908 | 8: get_xmac_reg_adr = XMAC_CONFIG; |
| 909 | 9: get_xmac_reg_adr = XMAC_IPG; |
| 910 | 10: get_xmac_reg_adr = XMAC_MIN; |
| 911 | 11: get_xmac_reg_adr = XMAC_MAX; |
| 912 | 12: get_xmac_reg_adr = RxMAC_BT_CNT; |
| 913 | 13: get_xmac_reg_adr = RxMAC_BC_FRM_CNT; |
| 914 | 14: get_xmac_reg_adr = RxMAC_MC_FRM_CNT; |
| 915 | 15: get_xmac_reg_adr = RxMAC_FRAG_CNT; |
| 916 | 16: get_xmac_reg_adr = RxMAC_HIST_CNT1; |
| 917 | 17: get_xmac_reg_adr = RxMAC_HIST_CNT2; |
| 918 | 18: get_xmac_reg_adr = RxMAC_HIST_CNT3; |
| 919 | 19: get_xmac_reg_adr = RxMAC_HIST_CNT4; |
| 920 | 20: get_xmac_reg_adr = RxMAC_HIST_CNT5; |
| 921 | 21: get_xmac_reg_adr = RxMAC_HIST_CNT6; |
| 922 | 22: get_xmac_reg_adr = RxMAC_MPSZER_CNT; |
| 923 | 23: get_xmac_reg_adr = MAC_CRC_ER_CNT; |
| 924 | 24: get_xmac_reg_adr = MAC_CD_VIO_CNT; |
| 925 | 25: get_xmac_reg_adr = MAC_AL_ER_CNT; |
| 926 | 26: get_xmac_reg_adr = TxMAC_FRM_CNT; |
| 927 | 27: get_xmac_reg_adr = TxMAC_BYTE_CNT; |
| 928 | 28: get_xmac_reg_adr = XMAC_SM_REG; |
| 929 | 29: get_xmac_reg_adr = XMAC_ADDR0; |
| 930 | 30: get_xmac_reg_adr = XMAC_ADDR1; |
| 931 | 31: get_xmac_reg_adr = XMAC_ADDR2; |
| 932 | 32: get_xmac_reg_adr = XMAC_ADDR_CMPEN_LSB; |
| 933 | 33: get_xmac_reg_adr = XMAC_ADDR_CMPEN_MSB; |
| 934 | 34: get_xmac_reg_adr = XMAC_ADDR3; |
| 935 | 35: get_xmac_reg_adr = XMAC_ADDR4; |
| 936 | 36: get_xmac_reg_adr = XMAC_ADDR5; |
| 937 | 37: get_xmac_reg_adr = XMAC_ADDR6; |
| 938 | 38: get_xmac_reg_adr = XMAC_ADDR7; |
| 939 | 39: get_xmac_reg_adr = XMAC_ADDR8; |
| 940 | 40: get_xmac_reg_adr = XMAC_ADDR9; |
| 941 | 41: get_xmac_reg_adr = XMAC_ADDR10; |
| 942 | 42: get_xmac_reg_adr = XMAC_ADDR11; |
| 943 | 43: get_xmac_reg_adr = XMAC_ADDR12; |
| 944 | 44: get_xmac_reg_adr = XMAC_ADDR13; |
| 945 | 45: get_xmac_reg_adr = XMAC_ADDR14; |
| 946 | 46: get_xmac_reg_adr = XMAC_ADDR15; |
| 947 | 47: get_xmac_reg_adr = XMAC_ADDR16; |
| 948 | 48: get_xmac_reg_adr = XMAC_ADDR17; |
| 949 | 49: get_xmac_reg_adr = XMAC_ADDR18; |
| 950 | 50: get_xmac_reg_adr = XMAC_ADDR19; |
| 951 | 51: get_xmac_reg_adr = XMAC_ADDR20; |
| 952 | 52: get_xmac_reg_adr = XMAC_ADDR21; |
| 953 | 53: get_xmac_reg_adr = XMAC_ADDR22; |
| 954 | 54: get_xmac_reg_adr = XMAC_ADDR23; |
| 955 | 55: get_xmac_reg_adr = XMAC_ADDR24; |
| 956 | 56: get_xmac_reg_adr = XMAC_ADDR25; |
| 957 | 57: get_xmac_reg_adr = XMAC_ADDR26; |
| 958 | 58: get_xmac_reg_adr = XMAC_ADDR27; |
| 959 | 59: get_xmac_reg_adr = XMAC_ADDR28; |
| 960 | 60: get_xmac_reg_adr = XMAC_ADDR29; |
| 961 | 61: get_xmac_reg_adr = XMAC_ADDR30; |
| 962 | 62: get_xmac_reg_adr = XMAC_ADDR31; |
| 963 | 63: get_xmac_reg_adr = XMAC_ADDR32; |
| 964 | 64: get_xmac_reg_adr = XMAC_ADDR33; |
| 965 | 65: get_xmac_reg_adr = XMAC_ADDR34; |
| 966 | 66: get_xmac_reg_adr = XMAC_ADDR35; |
| 967 | 67: get_xmac_reg_adr = XMAC_ADDR36; |
| 968 | 68: get_xmac_reg_adr = XMAC_ADDR37; |
| 969 | 69: get_xmac_reg_adr = XMAC_ADDR38; |
| 970 | 70: get_xmac_reg_adr = XMAC_ADDR39; |
| 971 | 71: get_xmac_reg_adr = XMAC_ADDR40; |
| 972 | 72: get_xmac_reg_adr = XMAC_ADDR41; |
| 973 | 73: get_xmac_reg_adr = XMAC_ADDR42; |
| 974 | 74: get_xmac_reg_adr = XMAC_ADDR43; |
| 975 | 75: get_xmac_reg_adr = XMAC_ADDR44; |
| 976 | 76: get_xmac_reg_adr = XMAC_ADDR45; |
| 977 | 77: get_xmac_reg_adr = XMAC_ADDR46; |
| 978 | 78: get_xmac_reg_adr = XMAC_ADDR47; |
| 979 | 79: get_xmac_reg_adr = XMAC_ADDR48; |
| 980 | 80: get_xmac_reg_adr = XMAC_ADDR49; |
| 981 | 81: get_xmac_reg_adr = XMAC_ADDR50; |
| 982 | 82: get_xmac_reg_adr = XMAC_ADDR51; |
| 983 | 83: get_xmac_reg_adr = XMAC_ADDR52; |
| 984 | 84: get_xmac_reg_adr = XMAC_ADDR53; |
| 985 | 85: get_xmac_reg_adr = XMAC_ADDR54; |
| 986 | 86: get_xmac_reg_adr = XMAC_ADDR55; |
| 987 | 87: get_xmac_reg_adr = XMAC_ADDR56; |
| 988 | 88: get_xmac_reg_adr = XMAC_ADDR57; |
| 989 | 89: get_xmac_reg_adr = XMAC_ADDR58; |
| 990 | 90: get_xmac_reg_adr = XMAC_ADDR59; |
| 991 | 91: get_xmac_reg_adr = XMAC_ADDR60; |
| 992 | 92: get_xmac_reg_adr = XMAC_ADDR61; |
| 993 | 93: get_xmac_reg_adr = XMAC_ADDR62; |
| 994 | 94: get_xmac_reg_adr = XMAC_ADDR63; |
| 995 | 95: get_xmac_reg_adr = XMAC_ADDR64; |
| 996 | 96: get_xmac_reg_adr = XMAC_ADDR65; |
| 997 | 97: get_xmac_reg_adr = XMAC_ADDR66; |
| 998 | 98: get_xmac_reg_adr = XMAC_ADDR67; |
| 999 | 99: get_xmac_reg_adr = XMAC_ADDR68; |
| 1000 | 100: get_xmac_reg_adr = XMAC_ADDR69; |
| 1001 | 101: get_xmac_reg_adr = XMAC_ADDR70; |
| 1002 | 102: get_xmac_reg_adr = XMAC_ADDR71; |
| 1003 | 103: get_xmac_reg_adr = XMAC_ADDR72; |
| 1004 | 104: get_xmac_reg_adr = XMAC_ADDR73; |
| 1005 | 105: get_xmac_reg_adr = XMAC_ADDR74; |
| 1006 | 106: get_xmac_reg_adr = XMAC_ADDR75; |
| 1007 | 107: get_xmac_reg_adr = XMAC_ADDR76; |
| 1008 | 108: get_xmac_reg_adr = XMAC_ADDR77; |
| 1009 | 109: get_xmac_reg_adr = XMAC_ADDR78; |
| 1010 | 110: get_xmac_reg_adr = XMAC_ADDR79; |
| 1011 | 111: get_xmac_reg_adr = XMAC_ADDR80; |
| 1012 | 112: get_xmac_reg_adr = XMAC_ADDR81; |
| 1013 | 113: get_xmac_reg_adr = XMAC_ADDR82; |
| 1014 | 114: get_xmac_reg_adr = XMAC_ADDR83; |
| 1015 | 115: get_xmac_reg_adr = XMAC_ADDR84; |
| 1016 | 116: get_xmac_reg_adr = XMAC_ADDR85; |
| 1017 | 117: get_xmac_reg_adr = XMAC_ADDR86; |
| 1018 | 118: get_xmac_reg_adr = XMAC_ADDR87; |
| 1019 | 119: get_xmac_reg_adr = XMAC_ADDR88; |
| 1020 | 120: get_xmac_reg_adr = XMAC_ADDR89; |
| 1021 | 121: get_xmac_reg_adr = XMAC_ADDR90; |
| 1022 | 122: get_xmac_reg_adr = XMAC_ADDR91; |
| 1023 | 123: get_xmac_reg_adr = XMAC_ADDR92; |
| 1024 | 124: get_xmac_reg_adr = XMAC_ADDR93; |
| 1025 | 125: get_xmac_reg_adr = XMAC_ADDR94; |
| 1026 | 126: get_xmac_reg_adr = XMAC_ADDR95; |
| 1027 | 127: get_xmac_reg_adr = XMAC_ADDR96; |
| 1028 | 128: get_xmac_reg_adr = XMAC_ADDR97; |
| 1029 | 129: get_xmac_reg_adr = XMAC_ADDR98; |
| 1030 | 223: get_xmac_reg_adr = XMAC_FC_ADDR0; |
| 1031 | 224: get_xmac_reg_adr = XMAC_FC_ADDR1; |
| 1032 | 225: get_xmac_reg_adr = XMAC_FC_ADDR2; |
| 1033 | 226: get_xmac_reg_adr = XMAC_ADD_FILT0; |
| 1034 | 227: get_xmac_reg_adr = XMAC_ADD_FILT1; |
| 1035 | 228: get_xmac_reg_adr = XMAC_ADD_FILT2; |
| 1036 | 229: get_xmac_reg_adr = XMAC_ADD_FILT12_MASK; |
| 1037 | 230: get_xmac_reg_adr = XMAC_ADD_FILT00_MASK; |
| 1038 | 231: get_xmac_reg_adr = XMAC_HASH_TBL0; |
| 1039 | 232: get_xmac_reg_adr = XMAC_HASH_TBL1; |
| 1040 | 233: get_xmac_reg_adr = XMAC_HASH_TBL2; |
| 1041 | 234: get_xmac_reg_adr = XMAC_HASH_TBL3; |
| 1042 | 235: get_xmac_reg_adr = XMAC_HASH_TBL4; |
| 1043 | 236: get_xmac_reg_adr = XMAC_HASH_TBL5; |
| 1044 | 237: get_xmac_reg_adr = XMAC_HASH_TBL6; |
| 1045 | 238: get_xmac_reg_adr = XMAC_HASH_TBL7; |
| 1046 | 239: get_xmac_reg_adr = XMAC_HASH_TBL8; |
| 1047 | 240: get_xmac_reg_adr = XMAC_HASH_TBL9; |
| 1048 | 241: get_xmac_reg_adr = XMAC_HASH_TBL10; |
| 1049 | 242: get_xmac_reg_adr = XMAC_HASH_TBL11; |
| 1050 | 243: get_xmac_reg_adr = XMAC_HASH_TBL12; |
| 1051 | 244: get_xmac_reg_adr = XMAC_HASH_TBL13; |
| 1052 | 245: get_xmac_reg_adr = XMAC_HASH_TBL14; |
| 1053 | 246: get_xmac_reg_adr = XMAC_HASH_TBL15; |
| 1054 | 247: get_xmac_reg_adr = XMAC_HOST_INFO0; |
| 1055 | 248: get_xmac_reg_adr = XMAC_HOST_INFO1; |
| 1056 | 249: get_xmac_reg_adr = XMAC_HOST_INFO2; |
| 1057 | 250: get_xmac_reg_adr = XMAC_HOST_INFO3; |
| 1058 | 251: get_xmac_reg_adr = XMAC_HOST_INFO4; |
| 1059 | 252: get_xmac_reg_adr = XMAC_HOST_INFO5; |
| 1060 | 253: get_xmac_reg_adr = XMAC_HOST_INFO6; |
| 1061 | 254: get_xmac_reg_adr = XMAC_HOST_INFO7; |
| 1062 | 255: get_xmac_reg_adr = XMAC_HOST_INFO8; |
| 1063 | 256: get_xmac_reg_adr = XMAC_HOST_INFO9; |
| 1064 | 257: get_xmac_reg_adr = XMAC_HOST_INFO10; |
| 1065 | 258: get_xmac_reg_adr = XMAC_HOST_INFO11; |
| 1066 | 259: get_xmac_reg_adr = XMAC_HOST_INFO12; |
| 1067 | 260: get_xmac_reg_adr = XMAC_HOST_INFO13; |
| 1068 | 261: get_xmac_reg_adr = XMAC_HOST_INFO14; |
| 1069 | 262: get_xmac_reg_adr = XMAC_HOST_INFO15; |
| 1070 | 263: get_xmac_reg_adr = XMAC_HOST_INFO16; |
| 1071 | 264: get_xmac_reg_adr = XMAC_HOST_INFO17; |
| 1072 | 265: get_xmac_reg_adr = XMAC_HOST_INFO18; |
| 1073 | 266: get_xmac_reg_adr = XMAC_HOST_INFO19; |
| 1074 | 267: get_xmac_reg_adr = XMAC_HOST_INFO20; |
| 1075 | 268: get_xmac_reg_adr = XMAC_HOST_INFO21; |
| 1076 | 269: get_xmac_reg_adr = XMAC_HOST_INFO22; |
| 1077 | 270: get_xmac_reg_adr = XMAC_HOST_INFO23; |
| 1078 | 271: get_xmac_reg_adr = XMAC_HOST_INFO24; |
| 1079 | 272: get_xmac_reg_adr = XMAC_HOST_INFO25; |
| 1080 | 273: get_xmac_reg_adr = XMAC_HOST_INFO26; |
| 1081 | 274: get_xmac_reg_adr = XMAC_HOST_INFO27; |
| 1082 | 275: get_xmac_reg_adr = XMAC_HOST_INFO28; |
| 1083 | 276: get_xmac_reg_adr = XMAC_HOST_INFO29; |
| 1084 | 277: get_xmac_reg_adr = XMAC_HOST_INFO30; |
| 1085 | 278: get_xmac_reg_adr = XMAC_HOST_INFO31; |
| 1086 | 279: get_xmac_reg_adr = RxMAC_HIST_CNT7; |
| 1087 | default: error("Error: Invalid register ID (%0d) for get_bmac_reg_adr.\n",id); |
| 1088 | } |
| 1089 | } |
| 1090 | |
| 1091 | |
| 1092 | |
| 1093 | |
| 1094 | |
| 1095 | |
| 1096 | function bit[32:0] mac_util_class :: xmac_reg_addr (integer sel) { |
| 1097 | integer n,m; |
| 1098 | bit [32:0] base_addr; |
| 1099 | |
| 1100 | n = sel%XMAC_TOTAL_REGS; |
| 1101 | m = (sel-n) / XMAC_TOTAL_REGS; |
| 1102 | |
| 1103 | base_addr = get_mac_reg_base(m); |
| 1104 | xmac_reg_addr = base_addr + get_xmac_reg_adr(n); |
| 1105 | } |
| 1106 | |
| 1107 | |
| 1108 | |
| 1109 | |
| 1110 | function bit[31:0] mac_util_class :: xmac_reg_mask (integer sel) { |
| 1111 | integer n; |
| 1112 | |
| 1113 | n = sel%XMAC_TOTAL_REGS; |
| 1114 | |
| 1115 | case(n) { |
| 1116 | |
| 1117 | 0: xmac_reg_mask = XTxMAC_SW_RST_MASK; |
| 1118 | 1: xmac_reg_mask = XRxMAC_SW_RST_MASK; |
| 1119 | 2: xmac_reg_mask = XTxMAC_STATUS_MASK; |
| 1120 | 3: xmac_reg_mask = XRxMAC_STATUS_MASK; |
| 1121 | 4: xmac_reg_mask = XMAC_CTRL_STAT_MASK; |
| 1122 | 5: xmac_reg_mask = XTxMAC_STAT_MSK_MASK; |
| 1123 | 6: xmac_reg_mask = XRxMAC_STAT_MSK_MASK; |
| 1124 | 7: xmac_reg_mask = XMAC_C_S_MSK_MASK; |
| 1125 | 8: xmac_reg_mask = XMAC_CONFIG_MASK; |
| 1126 | 9: xmac_reg_mask = XMAC_IPG_MASK; |
| 1127 | 10: xmac_reg_mask = XMAC_MIN_MASK; |
| 1128 | 11: xmac_reg_mask = XMAC_MAX_MASK; |
| 1129 | 12: xmac_reg_mask = RxMAC_BT_CNT_MASK; |
| 1130 | 13: xmac_reg_mask = RxMAC_BC_FRM_CNT_MASK; |
| 1131 | 14: xmac_reg_mask = RxMAC_MC_FRM_CNT_MASK; |
| 1132 | 15: xmac_reg_mask = RxMAC_FRAG_CNT_MASK; |
| 1133 | 16: xmac_reg_mask = RxMAC_HIST_CNT1_MASK; |
| 1134 | 17: xmac_reg_mask = RxMAC_HIST_CNT2_MASK; |
| 1135 | 18: xmac_reg_mask = RxMAC_HIST_CNT3_MASK; |
| 1136 | 19: xmac_reg_mask = RxMAC_HIST_CNT4_MASK; |
| 1137 | 20: xmac_reg_mask = RxMAC_HIST_CNT5_MASK; |
| 1138 | 21: xmac_reg_mask = RxMAC_HIST_CNT6_MASK; |
| 1139 | 22: xmac_reg_mask = RxMAC_MPSZER_CNT_MASK; |
| 1140 | 23: xmac_reg_mask = MAC_CRC_ER_CNT_MASK; |
| 1141 | 24: xmac_reg_mask = MAC_CD_VIO_CNT_MASK; |
| 1142 | 25: xmac_reg_mask = MAC_AL_ER_CNT_MASK; |
| 1143 | 26: xmac_reg_mask = TxMAC_FRM_CNT_MASK; |
| 1144 | 27: xmac_reg_mask = TxMAC_BYTE_CNT_MASK; |
| 1145 | 28: xmac_reg_mask = XMAC_SM_REG_MASK; |
| 1146 | 29: xmac_reg_mask = XMAC_ADDR0_MASK; |
| 1147 | 30: xmac_reg_mask = XMAC_ADDR1_MASK; |
| 1148 | 31: xmac_reg_mask = XMAC_ADDR2_MASK; |
| 1149 | 32: xmac_reg_mask = XMAC_ADDR_CMPEN_LSB_MASK; |
| 1150 | 33: xmac_reg_mask = XMAC_ADDR_CMPEN_MSB_MASK; |
| 1151 | 34: xmac_reg_mask = XMAC_ADDR3_MASK; |
| 1152 | 35: xmac_reg_mask = XMAC_ADDR4_MASK; |
| 1153 | 36: xmac_reg_mask = XMAC_ADDR5_MASK; |
| 1154 | 37: xmac_reg_mask = XMAC_ADDR6_MASK; |
| 1155 | 38: xmac_reg_mask = XMAC_ADDR7_MASK; |
| 1156 | 39: xmac_reg_mask = XMAC_ADDR8_MASK; |
| 1157 | 40: xmac_reg_mask = XMAC_ADDR9_MASK; |
| 1158 | 41: xmac_reg_mask = XMAC_ADDR10_MASK; |
| 1159 | 42: xmac_reg_mask = XMAC_ADDR11_MASK; |
| 1160 | 43: xmac_reg_mask = XMAC_ADDR12_MASK; |
| 1161 | 44: xmac_reg_mask = XMAC_ADDR13_MASK; |
| 1162 | 45: xmac_reg_mask = XMAC_ADDR14_MASK; |
| 1163 | 46: xmac_reg_mask = XMAC_ADDR15_MASK; |
| 1164 | 47: xmac_reg_mask = XMAC_ADDR16_MASK; |
| 1165 | 48: xmac_reg_mask = XMAC_ADDR17_MASK; |
| 1166 | 49: xmac_reg_mask = XMAC_ADDR18_MASK; |
| 1167 | 50: xmac_reg_mask = XMAC_ADDR19_MASK; |
| 1168 | 51: xmac_reg_mask = XMAC_ADDR20_MASK; |
| 1169 | 52: xmac_reg_mask = XMAC_ADDR21_MASK; |
| 1170 | 53: xmac_reg_mask = XMAC_ADDR22_MASK; |
| 1171 | 54: xmac_reg_mask = XMAC_ADDR23_MASK; |
| 1172 | 55: xmac_reg_mask = XMAC_ADDR24_MASK; |
| 1173 | 56: xmac_reg_mask = XMAC_ADDR25_MASK; |
| 1174 | 57: xmac_reg_mask = XMAC_ADDR26_MASK; |
| 1175 | 58: xmac_reg_mask = XMAC_ADDR27_MASK; |
| 1176 | 59: xmac_reg_mask = XMAC_ADDR28_MASK; |
| 1177 | 60: xmac_reg_mask = XMAC_ADDR29_MASK; |
| 1178 | 61: xmac_reg_mask = XMAC_ADDR30_MASK; |
| 1179 | 62: xmac_reg_mask = XMAC_ADDR31_MASK; |
| 1180 | 63: xmac_reg_mask = XMAC_ADDR32_MASK; |
| 1181 | 64: xmac_reg_mask = XMAC_ADDR33_MASK; |
| 1182 | 65: xmac_reg_mask = XMAC_ADDR34_MASK; |
| 1183 | 66: xmac_reg_mask = XMAC_ADDR35_MASK; |
| 1184 | 67: xmac_reg_mask = XMAC_ADDR36_MASK; |
| 1185 | 68: xmac_reg_mask = XMAC_ADDR37_MASK; |
| 1186 | 69: xmac_reg_mask = XMAC_ADDR38_MASK; |
| 1187 | 70: xmac_reg_mask = XMAC_ADDR39_MASK; |
| 1188 | 71: xmac_reg_mask = XMAC_ADDR40_MASK; |
| 1189 | 72: xmac_reg_mask = XMAC_ADDR41_MASK; |
| 1190 | 73: xmac_reg_mask = XMAC_ADDR42_MASK; |
| 1191 | 74: xmac_reg_mask = XMAC_ADDR43_MASK; |
| 1192 | 75: xmac_reg_mask = XMAC_ADDR44_MASK; |
| 1193 | 76: xmac_reg_mask = XMAC_ADDR45_MASK; |
| 1194 | 77: xmac_reg_mask = XMAC_ADDR46_MASK; |
| 1195 | 78: xmac_reg_mask = XMAC_ADDR47_MASK; |
| 1196 | 79: xmac_reg_mask = XMAC_ADDR48_MASK; |
| 1197 | 80: xmac_reg_mask = XMAC_ADDR49_MASK; |
| 1198 | 81: xmac_reg_mask = XMAC_ADDR50_MASK; |
| 1199 | 82: xmac_reg_mask = XMAC_ADDR51_MASK; |
| 1200 | 83: xmac_reg_mask = XMAC_ADDR52_MASK; |
| 1201 | 84: xmac_reg_mask = XMAC_ADDR53_MASK; |
| 1202 | 85: xmac_reg_mask = XMAC_ADDR54_MASK; |
| 1203 | 86: xmac_reg_mask = XMAC_ADDR55_MASK; |
| 1204 | 87: xmac_reg_mask = XMAC_ADDR56_MASK; |
| 1205 | 88: xmac_reg_mask = XMAC_ADDR57_MASK; |
| 1206 | 89: xmac_reg_mask = XMAC_ADDR58_MASK; |
| 1207 | 90: xmac_reg_mask = XMAC_ADDR59_MASK; |
| 1208 | 91: xmac_reg_mask = XMAC_ADDR60_MASK; |
| 1209 | 92: xmac_reg_mask = XMAC_ADDR61_MASK; |
| 1210 | 93: xmac_reg_mask = XMAC_ADDR62_MASK; |
| 1211 | 94: xmac_reg_mask = XMAC_ADDR63_MASK; |
| 1212 | 95: xmac_reg_mask = XMAC_ADDR64_MASK; |
| 1213 | 96: xmac_reg_mask = XMAC_ADDR65_MASK; |
| 1214 | 97: xmac_reg_mask = XMAC_ADDR66_MASK; |
| 1215 | 98: xmac_reg_mask = XMAC_ADDR67_MASK; |
| 1216 | 99: xmac_reg_mask = XMAC_ADDR68_MASK; |
| 1217 | 100: xmac_reg_mask = XMAC_ADDR69_MASK; |
| 1218 | 101: xmac_reg_mask = XMAC_ADDR70_MASK; |
| 1219 | 102: xmac_reg_mask = XMAC_ADDR71_MASK; |
| 1220 | 103: xmac_reg_mask = XMAC_ADDR72_MASK; |
| 1221 | 104: xmac_reg_mask = XMAC_ADDR73_MASK; |
| 1222 | 105: xmac_reg_mask = XMAC_ADDR74_MASK; |
| 1223 | 106: xmac_reg_mask = XMAC_ADDR75_MASK; |
| 1224 | 107: xmac_reg_mask = XMAC_ADDR76_MASK; |
| 1225 | 108: xmac_reg_mask = XMAC_ADDR77_MASK; |
| 1226 | 109: xmac_reg_mask = XMAC_ADDR78_MASK; |
| 1227 | 110: xmac_reg_mask = XMAC_ADDR79_MASK; |
| 1228 | 111: xmac_reg_mask = XMAC_ADDR80_MASK; |
| 1229 | 112: xmac_reg_mask = XMAC_ADDR81_MASK; |
| 1230 | 113: xmac_reg_mask = XMAC_ADDR82_MASK; |
| 1231 | 114: xmac_reg_mask = XMAC_ADDR83_MASK; |
| 1232 | 115: xmac_reg_mask = XMAC_ADDR84_MASK; |
| 1233 | 116: xmac_reg_mask = XMAC_ADDR85_MASK; |
| 1234 | 117: xmac_reg_mask = XMAC_ADDR86_MASK; |
| 1235 | 118: xmac_reg_mask = XMAC_ADDR87_MASK; |
| 1236 | 119: xmac_reg_mask = XMAC_ADDR88_MASK; |
| 1237 | 120: xmac_reg_mask = XMAC_ADDR89_MASK; |
| 1238 | 121: xmac_reg_mask = XMAC_ADDR90_MASK; |
| 1239 | 122: xmac_reg_mask = XMAC_ADDR91_MASK; |
| 1240 | 123: xmac_reg_mask = XMAC_ADDR92_MASK; |
| 1241 | 124: xmac_reg_mask = XMAC_ADDR93_MASK; |
| 1242 | 125: xmac_reg_mask = XMAC_ADDR94_MASK; |
| 1243 | 126: xmac_reg_mask = XMAC_ADDR95_MASK; |
| 1244 | 127: xmac_reg_mask = XMAC_ADDR96_MASK; |
| 1245 | 128: xmac_reg_mask = XMAC_ADDR97_MASK; |
| 1246 | 129: xmac_reg_mask = XMAC_ADDR98_MASK; |
| 1247 | 223: xmac_reg_mask = XMAC_FC_ADDR0_MASK; |
| 1248 | 224: xmac_reg_mask = XMAC_FC_ADDR1_MASK; |
| 1249 | 225: xmac_reg_mask = XMAC_FC_ADDR2_MASK; |
| 1250 | 226: xmac_reg_mask = XMAC_ADD_FILT0_MASK; |
| 1251 | 227: xmac_reg_mask = XMAC_ADD_FILT1_MASK; |
| 1252 | 228: xmac_reg_mask = XMAC_ADD_FILT2_MASK; |
| 1253 | 229: xmac_reg_mask = XMAC_ADD_FILT12_MASK_MASK; |
| 1254 | 230: xmac_reg_mask = XMAC_ADD_FILT00_MASK_MASK; |
| 1255 | 231: xmac_reg_mask = XMAC_HASH_TBL0_MASK; |
| 1256 | 232: xmac_reg_mask = XMAC_HASH_TBL1_MASK; |
| 1257 | 233: xmac_reg_mask = XMAC_HASH_TBL2_MASK; |
| 1258 | 234: xmac_reg_mask = XMAC_HASH_TBL3_MASK; |
| 1259 | 235: xmac_reg_mask = XMAC_HASH_TBL4_MASK; |
| 1260 | 236: xmac_reg_mask = XMAC_HASH_TBL5_MASK; |
| 1261 | 237: xmac_reg_mask = XMAC_HASH_TBL6_MASK; |
| 1262 | 238: xmac_reg_mask = XMAC_HASH_TBL7_MASK; |
| 1263 | 239: xmac_reg_mask = XMAC_HASH_TBL8_MASK; |
| 1264 | 240: xmac_reg_mask = XMAC_HASH_TBL9_MASK; |
| 1265 | 241: xmac_reg_mask = XMAC_HASH_TBL10_MASK; |
| 1266 | 242: xmac_reg_mask = XMAC_HASH_TBL11_MASK; |
| 1267 | 243: xmac_reg_mask = XMAC_HASH_TBL12_MASK; |
| 1268 | 244: xmac_reg_mask = XMAC_HASH_TBL13_MASK; |
| 1269 | 245: xmac_reg_mask = XMAC_HASH_TBL14_MASK; |
| 1270 | 246: xmac_reg_mask = XMAC_HASH_TBL15_MASK; |
| 1271 | 247: xmac_reg_mask = XMAC_HOST_INFO0_MASK; |
| 1272 | 248: xmac_reg_mask = XMAC_HOST_INFO1_MASK; |
| 1273 | 249: xmac_reg_mask = XMAC_HOST_INFO2_MASK; |
| 1274 | 250: xmac_reg_mask = XMAC_HOST_INFO3_MASK; |
| 1275 | 251: xmac_reg_mask = XMAC_HOST_INFO4_MASK; |
| 1276 | 252: xmac_reg_mask = XMAC_HOST_INFO5_MASK; |
| 1277 | 253: xmac_reg_mask = XMAC_HOST_INFO6_MASK; |
| 1278 | 254: xmac_reg_mask = XMAC_HOST_INFO7_MASK; |
| 1279 | 255: xmac_reg_mask = XMAC_HOST_INFO8_MASK; |
| 1280 | 256: xmac_reg_mask = XMAC_HOST_INFO9_MASK; |
| 1281 | 257: xmac_reg_mask = XMAC_HOST_INFO10_MASK; |
| 1282 | 258: xmac_reg_mask = XMAC_HOST_INFO11_MASK; |
| 1283 | 259: xmac_reg_mask = XMAC_HOST_INFO12_MASK; |
| 1284 | 260: xmac_reg_mask = XMAC_HOST_INFO13_MASK; |
| 1285 | 261: xmac_reg_mask = XMAC_HOST_INFO14_MASK; |
| 1286 | 262: xmac_reg_mask = XMAC_HOST_INFO15_MASK; |
| 1287 | 263: xmac_reg_mask = XMAC_HOST_INFO16_MASK; |
| 1288 | 264: xmac_reg_mask = XMAC_HOST_INFO17_MASK; |
| 1289 | 265: xmac_reg_mask = XMAC_HOST_INFO18_MASK; |
| 1290 | 266: xmac_reg_mask = XMAC_HOST_INFO19_MASK; |
| 1291 | 267: xmac_reg_mask = XMAC_HOST_INFO20_MASK; |
| 1292 | 268: xmac_reg_mask = XMAC_HOST_INFO21_MASK; |
| 1293 | 269: xmac_reg_mask = XMAC_HOST_INFO22_MASK; |
| 1294 | 270: xmac_reg_mask = XMAC_HOST_INFO23_MASK; |
| 1295 | 271: xmac_reg_mask = XMAC_HOST_INFO24_MASK; |
| 1296 | 272: xmac_reg_mask = XMAC_HOST_INFO25_MASK; |
| 1297 | 273: xmac_reg_mask = XMAC_HOST_INFO26_MASK; |
| 1298 | 274: xmac_reg_mask = XMAC_HOST_INFO27_MASK; |
| 1299 | 275: xmac_reg_mask = XMAC_HOST_INFO28_MASK; |
| 1300 | 276: xmac_reg_mask = XMAC_HOST_INFO29_MASK; |
| 1301 | 277: xmac_reg_mask = XMAC_HOST_INFO30_MASK; |
| 1302 | 278: xmac_reg_mask = XMAC_HOST_INFO31_MASK; |
| 1303 | |
| 1304 | |
| 1305 | } |
| 1306 | } |
| 1307 | |
| 1308 | function bit[31:0] mac_util_class :: xmac_reg_default (integer sel) { |
| 1309 | integer n; |
| 1310 | |
| 1311 | n = sel%XMAC_TOTAL_REGS; |
| 1312 | |
| 1313 | case(n) { |
| 1314 | |
| 1315 | 0: xmac_reg_default = XTxMAC_SW_RST_DEFAULT; |
| 1316 | 1: xmac_reg_default = XRxMAC_SW_RST_DEFAULT; |
| 1317 | 2: xmac_reg_default = XTxMAC_STATUS_DEFAULT; |
| 1318 | 3: xmac_reg_default = XRxMAC_STATUS_DEFAULT; |
| 1319 | 4: xmac_reg_default = XMAC_CTRL_STAT_DEFAULT; |
| 1320 | 5: xmac_reg_default = XTxMAC_STAT_MSK_DEFAULT; |
| 1321 | 6: xmac_reg_default = XRxMAC_STAT_MSK_DEFAULT; |
| 1322 | 7: xmac_reg_default = XMAC_C_S_MSK_DEFAULT; |
| 1323 | 8: xmac_reg_default = XMAC_CONFIG_DEFAULT; |
| 1324 | 9: xmac_reg_default = XMAC_IPG_DEFAULT; |
| 1325 | 10: xmac_reg_default = XMAC_MIN_DEFAULT; |
| 1326 | 11: xmac_reg_default = XMAC_MAX_DEFAULT; |
| 1327 | 12: xmac_reg_default = RxMAC_BT_CNT_DEFAULT; |
| 1328 | 13: xmac_reg_default = RxMAC_BC_FRM_CNT_DEFAULT; |
| 1329 | 14: xmac_reg_default = RxMAC_MC_FRM_CNT_DEFAULT; |
| 1330 | 15: xmac_reg_default = RxMAC_FRAG_CNT_DEFAULT; |
| 1331 | 16: xmac_reg_default = RxMAC_HIST_CNT1_DEFAULT; |
| 1332 | 17: xmac_reg_default = RxMAC_HIST_CNT2_DEFAULT; |
| 1333 | 18: xmac_reg_default = RxMAC_HIST_CNT3_DEFAULT; |
| 1334 | 19: xmac_reg_default = RxMAC_HIST_CNT4_DEFAULT; |
| 1335 | 20: xmac_reg_default = RxMAC_HIST_CNT5_DEFAULT; |
| 1336 | 21: xmac_reg_default = RxMAC_HIST_CNT6_DEFAULT; |
| 1337 | 22: xmac_reg_default = RxMAC_MPSZER_CNT_DEFAULT; |
| 1338 | 23: xmac_reg_default = MAC_CRC_ER_CNT_DEFAULT; |
| 1339 | 24: xmac_reg_default = MAC_CD_VIO_CNT_DEFAULT; |
| 1340 | 25: xmac_reg_default = MAC_AL_ER_CNT_DEFAULT; |
| 1341 | 26: xmac_reg_default = TxMAC_FRM_CNT_DEFAULT; |
| 1342 | 27: xmac_reg_default = TxMAC_BYTE_CNT_DEFAULT; |
| 1343 | 28: xmac_reg_default = XMAC_SM_REG_DEFAULT; |
| 1344 | 29: xmac_reg_default = XMAC_ADDR0_DEFAULT; |
| 1345 | 30: xmac_reg_default = XMAC_ADDR1_DEFAULT; |
| 1346 | 31: xmac_reg_default = XMAC_ADDR2_DEFAULT; |
| 1347 | 32: xmac_reg_default = XMAC_ADDR_CMPEN_LSB_DEFAULT; |
| 1348 | 33: xmac_reg_default = XMAC_ADDR_CMPEN_MSB_DEFAULT; |
| 1349 | 34: xmac_reg_default = XMAC_ADDR3_DEFAULT; |
| 1350 | 35: xmac_reg_default = XMAC_ADDR4_DEFAULT; |
| 1351 | 36: xmac_reg_default = XMAC_ADDR5_DEFAULT; |
| 1352 | 37: xmac_reg_default = XMAC_ADDR6_DEFAULT; |
| 1353 | 38: xmac_reg_default = XMAC_ADDR7_DEFAULT; |
| 1354 | 39: xmac_reg_default = XMAC_ADDR8_DEFAULT; |
| 1355 | 40: xmac_reg_default = XMAC_ADDR9_DEFAULT; |
| 1356 | 41: xmac_reg_default = XMAC_ADDR10_DEFAULT; |
| 1357 | 42: xmac_reg_default = XMAC_ADDR11_DEFAULT; |
| 1358 | 43: xmac_reg_default = XMAC_ADDR12_DEFAULT; |
| 1359 | 44: xmac_reg_default = XMAC_ADDR13_DEFAULT; |
| 1360 | 45: xmac_reg_default = XMAC_ADDR14_DEFAULT; |
| 1361 | 46: xmac_reg_default = XMAC_ADDR15_DEFAULT; |
| 1362 | 47: xmac_reg_default = XMAC_ADDR16_DEFAULT; |
| 1363 | 48: xmac_reg_default = XMAC_ADDR17_DEFAULT; |
| 1364 | 49: xmac_reg_default = XMAC_ADDR18_DEFAULT; |
| 1365 | 50: xmac_reg_default = XMAC_ADDR19_DEFAULT; |
| 1366 | 51: xmac_reg_default = XMAC_ADDR20_DEFAULT; |
| 1367 | 52: xmac_reg_default = XMAC_ADDR21_DEFAULT; |
| 1368 | 53: xmac_reg_default = XMAC_ADDR22_DEFAULT; |
| 1369 | 54: xmac_reg_default = XMAC_ADDR23_DEFAULT; |
| 1370 | 55: xmac_reg_default = XMAC_ADDR24_DEFAULT; |
| 1371 | 56: xmac_reg_default = XMAC_ADDR25_DEFAULT; |
| 1372 | 57: xmac_reg_default = XMAC_ADDR26_DEFAULT; |
| 1373 | 58: xmac_reg_default = XMAC_ADDR27_DEFAULT; |
| 1374 | 59: xmac_reg_default = XMAC_ADDR28_DEFAULT; |
| 1375 | 60: xmac_reg_default = XMAC_ADDR29_DEFAULT; |
| 1376 | 61: xmac_reg_default = XMAC_ADDR30_DEFAULT; |
| 1377 | 62: xmac_reg_default = XMAC_ADDR31_DEFAULT; |
| 1378 | 63: xmac_reg_default = XMAC_ADDR32_DEFAULT; |
| 1379 | 64: xmac_reg_default = XMAC_ADDR33_DEFAULT; |
| 1380 | 65: xmac_reg_default = XMAC_ADDR34_DEFAULT; |
| 1381 | 66: xmac_reg_default = XMAC_ADDR35_DEFAULT; |
| 1382 | 67: xmac_reg_default = XMAC_ADDR36_DEFAULT; |
| 1383 | 68: xmac_reg_default = XMAC_ADDR37_DEFAULT; |
| 1384 | 69: xmac_reg_default = XMAC_ADDR38_DEFAULT; |
| 1385 | 70: xmac_reg_default = XMAC_ADDR39_DEFAULT; |
| 1386 | 71: xmac_reg_default = XMAC_ADDR40_DEFAULT; |
| 1387 | 72: xmac_reg_default = XMAC_ADDR41_DEFAULT; |
| 1388 | 73: xmac_reg_default = XMAC_ADDR42_DEFAULT; |
| 1389 | 74: xmac_reg_default = XMAC_ADDR43_DEFAULT; |
| 1390 | 75: xmac_reg_default = XMAC_ADDR44_DEFAULT; |
| 1391 | 76: xmac_reg_default = XMAC_ADDR45_DEFAULT; |
| 1392 | 77: xmac_reg_default = XMAC_ADDR46_DEFAULT; |
| 1393 | 78: xmac_reg_default = XMAC_ADDR47_DEFAULT; |
| 1394 | 79: xmac_reg_default = XMAC_ADDR48_DEFAULT; |
| 1395 | 80: xmac_reg_default = XMAC_ADDR49_DEFAULT; |
| 1396 | 81: xmac_reg_default = XMAC_ADDR50_DEFAULT; |
| 1397 | 82: xmac_reg_default = XMAC_ADDR51_DEFAULT; |
| 1398 | 83: xmac_reg_default = XMAC_ADDR52_DEFAULT; |
| 1399 | 84: xmac_reg_default = XMAC_ADDR53_DEFAULT; |
| 1400 | 85: xmac_reg_default = XMAC_ADDR54_DEFAULT; |
| 1401 | 86: xmac_reg_default = XMAC_ADDR55_DEFAULT; |
| 1402 | 87: xmac_reg_default = XMAC_ADDR56_DEFAULT; |
| 1403 | 88: xmac_reg_default = XMAC_ADDR57_DEFAULT; |
| 1404 | 89: xmac_reg_default = XMAC_ADDR58_DEFAULT; |
| 1405 | 90: xmac_reg_default = XMAC_ADDR59_DEFAULT; |
| 1406 | 91: xmac_reg_default = XMAC_ADDR60_DEFAULT; |
| 1407 | 92: xmac_reg_default = XMAC_ADDR61_DEFAULT; |
| 1408 | 93: xmac_reg_default = XMAC_ADDR62_DEFAULT; |
| 1409 | 94: xmac_reg_default = XMAC_ADDR63_DEFAULT; |
| 1410 | 95: xmac_reg_default = XMAC_ADDR64_DEFAULT; |
| 1411 | 96: xmac_reg_default = XMAC_ADDR65_DEFAULT; |
| 1412 | 97: xmac_reg_default = XMAC_ADDR66_DEFAULT; |
| 1413 | 98: xmac_reg_default = XMAC_ADDR67_DEFAULT; |
| 1414 | 99: xmac_reg_default = XMAC_ADDR68_DEFAULT; |
| 1415 | 100: xmac_reg_default = XMAC_ADDR69_DEFAULT; |
| 1416 | 101: xmac_reg_default = XMAC_ADDR70_DEFAULT; |
| 1417 | 102: xmac_reg_default = XMAC_ADDR71_DEFAULT; |
| 1418 | 103: xmac_reg_default = XMAC_ADDR72_DEFAULT; |
| 1419 | 104: xmac_reg_default = XMAC_ADDR73_DEFAULT; |
| 1420 | 105: xmac_reg_default = XMAC_ADDR74_DEFAULT; |
| 1421 | 106: xmac_reg_default = XMAC_ADDR75_DEFAULT; |
| 1422 | 107: xmac_reg_default = XMAC_ADDR76_DEFAULT; |
| 1423 | 108: xmac_reg_default = XMAC_ADDR77_DEFAULT; |
| 1424 | 109: xmac_reg_default = XMAC_ADDR78_DEFAULT; |
| 1425 | 110: xmac_reg_default = XMAC_ADDR79_DEFAULT; |
| 1426 | 111: xmac_reg_default = XMAC_ADDR80_DEFAULT; |
| 1427 | 112: xmac_reg_default = XMAC_ADDR81_DEFAULT; |
| 1428 | 113: xmac_reg_default = XMAC_ADDR82_DEFAULT; |
| 1429 | 114: xmac_reg_default = XMAC_ADDR83_DEFAULT; |
| 1430 | 115: xmac_reg_default = XMAC_ADDR84_DEFAULT; |
| 1431 | 116: xmac_reg_default = XMAC_ADDR85_DEFAULT; |
| 1432 | 117: xmac_reg_default = XMAC_ADDR86_DEFAULT; |
| 1433 | 118: xmac_reg_default = XMAC_ADDR87_DEFAULT; |
| 1434 | 119: xmac_reg_default = XMAC_ADDR88_DEFAULT; |
| 1435 | 120: xmac_reg_default = XMAC_ADDR89_DEFAULT; |
| 1436 | 121: xmac_reg_default = XMAC_ADDR90_DEFAULT; |
| 1437 | 122: xmac_reg_default = XMAC_ADDR91_DEFAULT; |
| 1438 | 123: xmac_reg_default = XMAC_ADDR92_DEFAULT; |
| 1439 | 124: xmac_reg_default = XMAC_ADDR93_DEFAULT; |
| 1440 | 125: xmac_reg_default = XMAC_ADDR94_DEFAULT; |
| 1441 | 126: xmac_reg_default = XMAC_ADDR95_DEFAULT; |
| 1442 | 127: xmac_reg_default = XMAC_ADDR96_DEFAULT; |
| 1443 | 128: xmac_reg_default = XMAC_ADDR97_DEFAULT; |
| 1444 | 129: xmac_reg_default = XMAC_ADDR98_DEFAULT; |
| 1445 | 223: xmac_reg_default = XMAC_FC_ADDR0_DEFAULT; |
| 1446 | 224: xmac_reg_default = XMAC_FC_ADDR1_DEFAULT; |
| 1447 | 225: xmac_reg_default = XMAC_FC_ADDR2_DEFAULT; |
| 1448 | 226: xmac_reg_default = XMAC_ADD_FILT0_DEFAULT; |
| 1449 | 227: xmac_reg_default = XMAC_ADD_FILT1_DEFAULT; |
| 1450 | 228: xmac_reg_default = XMAC_ADD_FILT2_DEFAULT; |
| 1451 | 229: xmac_reg_default = XMAC_ADD_FILT12_MASK_DEFAULT; |
| 1452 | 230: xmac_reg_default = XMAC_ADD_FILT00_MASK_DEFAULT; |
| 1453 | 231: xmac_reg_default = XMAC_HASH_TBL0_DEFAULT; |
| 1454 | 232: xmac_reg_default = XMAC_HASH_TBL1_DEFAULT; |
| 1455 | 233: xmac_reg_default = XMAC_HASH_TBL2_DEFAULT; |
| 1456 | 234: xmac_reg_default = XMAC_HASH_TBL3_DEFAULT; |
| 1457 | 235: xmac_reg_default = XMAC_HASH_TBL4_DEFAULT; |
| 1458 | 236: xmac_reg_default = XMAC_HASH_TBL5_DEFAULT; |
| 1459 | 237: xmac_reg_default = XMAC_HASH_TBL6_DEFAULT; |
| 1460 | 238: xmac_reg_default = XMAC_HASH_TBL7_DEFAULT; |
| 1461 | 239: xmac_reg_default = XMAC_HASH_TBL8_DEFAULT; |
| 1462 | 240: xmac_reg_default = XMAC_HASH_TBL9_DEFAULT; |
| 1463 | 241: xmac_reg_default = XMAC_HASH_TBL10_DEFAULT; |
| 1464 | 242: xmac_reg_default = XMAC_HASH_TBL11_DEFAULT; |
| 1465 | 243: xmac_reg_default = XMAC_HASH_TBL12_DEFAULT; |
| 1466 | 244: xmac_reg_default = XMAC_HASH_TBL13_DEFAULT; |
| 1467 | 245: xmac_reg_default = XMAC_HASH_TBL14_DEFAULT; |
| 1468 | 246: xmac_reg_default = XMAC_HASH_TBL15_DEFAULT; |
| 1469 | 247: xmac_reg_default = XMAC_HOST_INFO0_DEFAULT; |
| 1470 | 248: xmac_reg_default = XMAC_HOST_INFO1_DEFAULT; |
| 1471 | 249: xmac_reg_default = XMAC_HOST_INFO2_DEFAULT; |
| 1472 | 250: xmac_reg_default = XMAC_HOST_INFO3_DEFAULT; |
| 1473 | 251: xmac_reg_default = XMAC_HOST_INFO4_DEFAULT; |
| 1474 | 252: xmac_reg_default = XMAC_HOST_INFO5_DEFAULT; |
| 1475 | 253: xmac_reg_default = XMAC_HOST_INFO6_DEFAULT; |
| 1476 | 254: xmac_reg_default = XMAC_HOST_INFO7_DEFAULT; |
| 1477 | 255: xmac_reg_default = XMAC_HOST_INFO8_DEFAULT; |
| 1478 | 256: xmac_reg_default = XMAC_HOST_INFO9_DEFAULT; |
| 1479 | 257: xmac_reg_default = XMAC_HOST_INFO10_DEFAULT; |
| 1480 | 258: xmac_reg_default = XMAC_HOST_INFO11_DEFAULT; |
| 1481 | 259: xmac_reg_default = XMAC_HOST_INFO12_DEFAULT; |
| 1482 | 260: xmac_reg_default = XMAC_HOST_INFO13_DEFAULT; |
| 1483 | 261: xmac_reg_default = XMAC_HOST_INFO14_DEFAULT; |
| 1484 | 262: xmac_reg_default = XMAC_HOST_INFO15_DEFAULT; |
| 1485 | 263: xmac_reg_default = XMAC_HOST_INFO16_DEFAULT; |
| 1486 | 264: xmac_reg_default = XMAC_HOST_INFO17_DEFAULT; |
| 1487 | 265: xmac_reg_default = XMAC_HOST_INFO18_DEFAULT; |
| 1488 | 266: xmac_reg_default = XMAC_HOST_INFO19_DEFAULT; |
| 1489 | 267: xmac_reg_default = XMAC_HOST_INFO20_DEFAULT; |
| 1490 | 268: xmac_reg_default = XMAC_HOST_INFO21_DEFAULT; |
| 1491 | 269: xmac_reg_default = XMAC_HOST_INFO22_DEFAULT; |
| 1492 | 270: xmac_reg_default = XMAC_HOST_INFO23_DEFAULT; |
| 1493 | 271: xmac_reg_default = XMAC_HOST_INFO24_DEFAULT; |
| 1494 | 272: xmac_reg_default = XMAC_HOST_INFO25_DEFAULT; |
| 1495 | 273: xmac_reg_default = XMAC_HOST_INFO26_DEFAULT; |
| 1496 | 274: xmac_reg_default = XMAC_HOST_INFO27_DEFAULT; |
| 1497 | 275: xmac_reg_default = XMAC_HOST_INFO28_DEFAULT; |
| 1498 | 276: xmac_reg_default = XMAC_HOST_INFO29_DEFAULT; |
| 1499 | 277: xmac_reg_default = XMAC_HOST_INFO30_DEFAULT; |
| 1500 | 278: xmac_reg_default = XMAC_HOST_INFO31_DEFAULT; |
| 1501 | |
| 1502 | |
| 1503 | } |
| 1504 | } |
| 1505 | |
| 1506 | |
| 1507 | |