| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_intr_monitor.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `ifdef NIU_GATE |
| 36 | // Do nothing |
| 37 | `else |
| 38 | |
| 39 | `include "neptune_defines.h" |
| 40 | |
| 41 | module niu_intr_monitor; |
| 42 | `ifdef NIU_SYSTEMC_T2 |
| 43 | `else |
| 44 | |
| 45 | wire clk = `RDP.niu_pio.niu_clk; |
| 46 | wire activate_ig_sm = `RDP.niu_pio.niu_pio_ic.niu_pio_ig_sm.activate_ig_sm; |
| 47 | wire activate_ig_sm_rel = `RDP.niu_pio.niu_pio_ic.niu_pio_ig_sm.activate_ig_sm_rel; |
| 48 | wire ibusy = `RDP.niu_pio.ibusy; |
| 49 | wire [63:0] intr_req_group = `RDP.niu_pio.niu_pio_ic.intr_req_group; |
| 50 | wire [63:0] intr_rel_group = `RDP.niu_pio.niu_pio_ic.intr_rel_group; |
| 51 | |
| 52 | reg activate_ig_sm_2a; |
| 53 | reg activate_ig_sm_3a; |
| 54 | reg activate_ig_sm_4a; |
| 55 | reg activate_ig_sm_5a; |
| 56 | reg activate_ig_sm_6a; |
| 57 | reg activate_ig_sm_7a; |
| 58 | reg activate_ig_sm_8a; |
| 59 | reg activate_ig_sm_9a; |
| 60 | reg activate_ig_sm_10a; |
| 61 | |
| 62 | |
| 63 | reg count_req_clk_en_2a; |
| 64 | reg count_req_clk_en_3a; |
| 65 | reg count_req_clk_en_4a; |
| 66 | reg count_req_clk_en_5a; |
| 67 | reg count_req_clk_en_6a; |
| 68 | |
| 69 | |
| 70 | reg case_detected = 0; |
| 71 | reg req_rel_hit_skew0 = 0; |
| 72 | reg req_rel_hit_skew1 = 0; |
| 73 | reg req_rel_hit_skew2 = 0; |
| 74 | reg req_rel_hit_skew3 = 0; |
| 75 | reg req_rel_hit_skew4 = 0; |
| 76 | reg req_rel_hit_skew5 = 0; |
| 77 | |
| 78 | integer count_req_clk = 0; |
| 79 | reg count_req_clk_en = 0; |
| 80 | reg end_of_req_signal = 0; |
| 81 | |
| 82 | integer count_rel_clk = 0; |
| 83 | reg count_rel_clk_en = 0; |
| 84 | reg end_of_rel_signal = 0; |
| 85 | |
| 86 | |
| 87 | |
| 88 | |
| 89 | reg reverse_case_detected = 0; |
| 90 | |
| 91 | reg count_rel_clk_en_2a; |
| 92 | reg count_rel_clk_en_3a; |
| 93 | reg count_rel_clk_en_4a; |
| 94 | reg count_rel_clk_en_5a; |
| 95 | reg count_rel_clk_en_6a; |
| 96 | |
| 97 | reg activate_ig_sm_rel_2a; |
| 98 | reg activate_ig_sm_rel_3a; |
| 99 | reg activate_ig_sm_rel_4a; |
| 100 | reg activate_ig_sm_rel_5a; |
| 101 | reg activate_ig_sm_rel_6a; |
| 102 | |
| 103 | reg rel_req_hit_skew1 = 0; |
| 104 | reg rel_req_hit_skew2 = 0; |
| 105 | reg rel_req_hit_skew3 = 0; |
| 106 | reg rel_req_hit_skew4 = 0; |
| 107 | reg rel_req_hit_skew5 = 0; |
| 108 | |
| 109 | |
| 110 | reg [63:0] intr_req_group_2a; |
| 111 | reg [63:0] intr_req_group_3a; |
| 112 | reg [63:0] intr_req_group_4a; |
| 113 | reg [63:0] intr_req_group_5a; |
| 114 | reg [63:0] intr_req_group_6a; |
| 115 | |
| 116 | reg [63:0] intr_rel_group_2a; |
| 117 | reg [63:0] intr_rel_group_3a; |
| 118 | reg [63:0] intr_rel_group_4a; |
| 119 | reg [63:0] intr_rel_group_5a; |
| 120 | reg [63:0] intr_rel_group_6a; |
| 121 | |
| 122 | |
| 123 | reg req_rel_cov_en; |
| 124 | reg rel_req_cov_en; |
| 125 | |
| 126 | |
| 127 | wire req_rel_hit_skew0_noibusy; |
| 128 | wire req_rel_hit_skew1_noibusy; |
| 129 | wire req_rel_hit_skew2_noibusy; |
| 130 | wire req_rel_hit_skew3_noibusy; |
| 131 | wire req_rel_hit_skew4_noibusy; |
| 132 | wire req_rel_hit_skew5_noibusy; |
| 133 | |
| 134 | wire req_rel_hit_skew0_ibusy; |
| 135 | wire req_rel_hit_skew1_ibusy; |
| 136 | wire req_rel_hit_skew2_ibusy; |
| 137 | wire req_rel_hit_skew3_ibusy; |
| 138 | wire req_rel_hit_skew4_ibusy; |
| 139 | wire req_rel_hit_skew5_ibusy; |
| 140 | |
| 141 | wire rel_req_hit_skew1_noibusy; |
| 142 | wire rel_req_hit_skew2_noibusy; |
| 143 | wire rel_req_hit_skew3_noibusy; |
| 144 | wire rel_req_hit_skew4_noibusy; |
| 145 | wire rel_req_hit_skew5_noibusy; |
| 146 | |
| 147 | wire rel_req_hit_skew1_ibusy; |
| 148 | wire rel_req_hit_skew2_ibusy; |
| 149 | wire rel_req_hit_skew3_ibusy; |
| 150 | wire rel_req_hit_skew4_ibusy; |
| 151 | wire rel_req_hit_skew5_ibusy; |
| 152 | |
| 153 | |
| 154 | |
| 155 | //Create enable signal for coverage: req followed by release... |
| 156 | always @(posedge activate_ig_sm) |
| 157 | req_rel_cov_en <= 1; |
| 158 | |
| 159 | always @(posedge clk) |
| 160 | if(end_of_req_signal && end_of_rel_signal && case_detected) |
| 161 | req_rel_cov_en <= 0; |
| 162 | |
| 163 | |
| 164 | |
| 165 | |
| 166 | //Create enable signal for coverage release followed by req (reverse_case)... |
| 167 | always @(posedge activate_ig_sm_rel) |
| 168 | rel_req_cov_en <=1; |
| 169 | |
| 170 | always @(posedge clk) |
| 171 | if(end_of_req_signal && end_of_rel_signal && reverse_case_detected) |
| 172 | rel_req_cov_en <=0; |
| 173 | |
| 174 | |
| 175 | |
| 176 | //Stage group ID signals |
| 177 | always @(posedge clk) |
| 178 | begin |
| 179 | intr_req_group_2a <= intr_req_group; |
| 180 | intr_req_group_3a <= intr_req_group_2a; |
| 181 | intr_req_group_4a <= intr_req_group_3a; |
| 182 | intr_req_group_5a <= intr_req_group_4a; |
| 183 | intr_req_group_6a <= intr_req_group_5a; |
| 184 | |
| 185 | intr_rel_group_2a <= intr_rel_group; |
| 186 | intr_rel_group_3a <= intr_rel_group_2a; |
| 187 | intr_rel_group_4a <= intr_rel_group_3a; |
| 188 | intr_rel_group_5a <= intr_rel_group_4a; |
| 189 | intr_rel_group_6a <= intr_rel_group_5a; |
| 190 | end // always @ (posedge clk) |
| 191 | |
| 192 | |
| 193 | |
| 194 | //Stage request signal (activate_ig_sm) |
| 195 | always @(posedge clk) |
| 196 | begin |
| 197 | activate_ig_sm_2a <= activate_ig_sm; |
| 198 | activate_ig_sm_3a <= activate_ig_sm_2a; |
| 199 | activate_ig_sm_4a <= activate_ig_sm_3a; |
| 200 | activate_ig_sm_5a <= activate_ig_sm_4a; |
| 201 | activate_ig_sm_6a <= activate_ig_sm_5a; |
| 202 | activate_ig_sm_7a <= activate_ig_sm_6a; |
| 203 | activate_ig_sm_8a <= activate_ig_sm_7a; |
| 204 | activate_ig_sm_9a <= activate_ig_sm_8a; |
| 205 | activate_ig_sm_10a <= activate_ig_sm_9a; |
| 206 | |
| 207 | end // always @ (posedge clk) |
| 208 | |
| 209 | |
| 210 | //Stage count_req_clk_en signal... |
| 211 | always @(posedge clk) |
| 212 | begin |
| 213 | count_req_clk_en_2a <= count_req_clk_en; |
| 214 | count_req_clk_en_3a <= count_req_clk_en_2a; |
| 215 | count_req_clk_en_4a <= count_req_clk_en_3a; |
| 216 | count_req_clk_en_5a <= count_req_clk_en_4a; |
| 217 | count_req_clk_en_6a <= count_req_clk_en_5a; |
| 218 | end // always @ (posedge clk) |
| 219 | |
| 220 | |
| 221 | |
| 222 | |
| 223 | |
| 224 | // detect overlap of req followed by rel and sweep with in 6 cycles... |
| 225 | |
| 226 | always @(posedge clk) |
| 227 | if (activate_ig_sm && !count_req_clk_en && activate_ig_sm_rel && !count_rel_clk_en && (intr_req_group !== intr_rel_group) ) |
| 228 | begin |
| 229 | req_rel_hit_skew0 <= 1; |
| 230 | case_detected <= 1; |
| 231 | |
| 232 | end |
| 233 | else if (activate_ig_sm_2a && !count_req_clk_en_2a && activate_ig_sm_rel && !count_rel_clk_en && (intr_req_group_2a !== intr_rel_group) ) |
| 234 | begin |
| 235 | req_rel_hit_skew1 <= 1; |
| 236 | case_detected <= 1; |
| 237 | end |
| 238 | else if (activate_ig_sm_3a && !count_req_clk_en_3a && activate_ig_sm_rel && !count_rel_clk_en && (intr_req_group_3a !== intr_rel_group) ) |
| 239 | begin |
| 240 | req_rel_hit_skew2 = 1; |
| 241 | case_detected <= 1; |
| 242 | end |
| 243 | else if (activate_ig_sm_4a && !count_req_clk_en_4a && activate_ig_sm_rel && !count_rel_clk_en && (intr_req_group_4a !== intr_rel_group) ) |
| 244 | begin |
| 245 | req_rel_hit_skew3 = 1; |
| 246 | case_detected = 1; |
| 247 | end |
| 248 | else if (activate_ig_sm_5a && !count_req_clk_en_5a && activate_ig_sm_rel && !count_rel_clk_en && (intr_req_group_5a !== intr_rel_group) ) |
| 249 | begin |
| 250 | req_rel_hit_skew4 = 1; |
| 251 | case_detected = 1; |
| 252 | end |
| 253 | else if (activate_ig_sm_6a && !count_req_clk_en_6a && activate_ig_sm_rel && !count_rel_clk_en && (intr_req_group_6a !== intr_rel_group) ) |
| 254 | begin |
| 255 | req_rel_hit_skew5 = 1; |
| 256 | case_detected = 1; |
| 257 | end |
| 258 | |
| 259 | // Now detect our cases!!! |
| 260 | // qualify our hits with ibusy... |
| 261 | assign req_rel_hit_skew0_noibusy = req_rel_hit_skew0 && !ibusy; |
| 262 | assign req_rel_hit_skew1_noibusy = req_rel_hit_skew1 && !ibusy; |
| 263 | assign req_rel_hit_skew2_noibusy = req_rel_hit_skew2 && !ibusy; |
| 264 | assign req_rel_hit_skew3_noibusy = req_rel_hit_skew3 && !ibusy; |
| 265 | assign req_rel_hit_skew4_noibusy = req_rel_hit_skew4 && !ibusy; |
| 266 | assign req_rel_hit_skew5_noibusy = req_rel_hit_skew5 && !ibusy; |
| 267 | |
| 268 | assign req_rel_hit_skew0_ibusy = req_rel_hit_skew0 && ibusy; |
| 269 | assign req_rel_hit_skew1_ibusy = req_rel_hit_skew1 && ibusy; |
| 270 | assign req_rel_hit_skew2_ibusy = req_rel_hit_skew2 && ibusy; |
| 271 | assign req_rel_hit_skew3_ibusy = req_rel_hit_skew3 && ibusy; |
| 272 | assign req_rel_hit_skew4_ibusy = req_rel_hit_skew4 && ibusy; |
| 273 | assign req_rel_hit_skew5_ibusy = req_rel_hit_skew5 && ibusy; |
| 274 | |
| 275 | |
| 276 | |
| 277 | |
| 278 | |
| 279 | // Calculate length in clocks for the request signal |
| 280 | always @(posedge clk) |
| 281 | if (activate_ig_sm && !count_req_clk_en ) |
| 282 | begin |
| 283 | count_req_clk <= 1; |
| 284 | count_req_clk_en <= 1; |
| 285 | end |
| 286 | |
| 287 | // clear signal denoting end_of_req |
| 288 | always @(posedge activate_ig_sm) |
| 289 | end_of_req_signal <= 0; |
| 290 | |
| 291 | always @(posedge clk) |
| 292 | begin |
| 293 | if (count_req_clk_en) |
| 294 | begin |
| 295 | if (activate_ig_sm) |
| 296 | begin |
| 297 | count_req_clk = count_req_clk + 1; |
| 298 | end |
| 299 | end |
| 300 | end |
| 301 | |
| 302 | always @(negedge clk) |
| 303 | if (count_req_clk_en) |
| 304 | begin |
| 305 | if (!activate_ig_sm) |
| 306 | begin |
| 307 | count_req_clk_en <= 0; |
| 308 | end_of_req_signal <= 1; |
| 309 | end |
| 310 | end |
| 311 | |
| 312 | |
| 313 | |
| 314 | |
| 315 | |
| 316 | // Calculate length in clocks for the rel signal |
| 317 | always @(posedge clk) |
| 318 | if (activate_ig_sm_rel && !count_rel_clk_en ) |
| 319 | begin |
| 320 | count_rel_clk <= 1; |
| 321 | count_rel_clk_en <= 1; |
| 322 | end |
| 323 | |
| 324 | // clear signal denoting end_of_rel |
| 325 | always @(posedge activate_ig_sm_rel) |
| 326 | end_of_rel_signal <= 0; |
| 327 | |
| 328 | always @(posedge clk) |
| 329 | begin |
| 330 | if (count_rel_clk_en) |
| 331 | begin |
| 332 | if (activate_ig_sm_rel) |
| 333 | begin |
| 334 | count_rel_clk = count_rel_clk + 1; |
| 335 | end |
| 336 | end |
| 337 | end |
| 338 | |
| 339 | |
| 340 | always @(negedge clk) |
| 341 | if (count_rel_clk_en) |
| 342 | begin |
| 343 | if (!activate_ig_sm_rel) |
| 344 | begin |
| 345 | count_rel_clk_en <= 0; |
| 346 | end_of_rel_signal <= 1; |
| 347 | end |
| 348 | end |
| 349 | |
| 350 | |
| 351 | always @(posedge clk) |
| 352 | if(end_of_req_signal && end_of_rel_signal && case_detected) |
| 353 | begin |
| 354 | |
| 355 | // reset signals... |
| 356 | case_detected <= 0; |
| 357 | |
| 358 | req_rel_hit_skew0 <= 0; |
| 359 | req_rel_hit_skew1 <= 0; |
| 360 | req_rel_hit_skew2 <= 0; |
| 361 | req_rel_hit_skew3 <= 0; |
| 362 | req_rel_hit_skew4 <= 0; |
| 363 | req_rel_hit_skew5 <= 0; |
| 364 | |
| 365 | |
| 366 | |
| 367 | |
| 368 | end // if (end_of_req_signal && end_of_rel_signal && case_detected) |
| 369 | |
| 370 | |
| 371 | |
| 372 | /// Now detect overlap of release followed by req and sweep with in 6 cycles... |
| 373 | |
| 374 | |
| 375 | // Stage count_rel_clk_en signal... |
| 376 | always @(posedge clk) |
| 377 | begin |
| 378 | count_rel_clk_en_2a <= count_rel_clk_en; |
| 379 | count_rel_clk_en_3a <= count_rel_clk_en_2a; |
| 380 | count_rel_clk_en_4a <= count_rel_clk_en_3a; |
| 381 | count_rel_clk_en_5a <= count_rel_clk_en_4a; |
| 382 | count_rel_clk_en_6a <= count_rel_clk_en_5a; |
| 383 | end // always @ (posedge clk) |
| 384 | |
| 385 | |
| 386 | // Stage release signal (activate_ig_sm_rel) |
| 387 | always @(posedge clk) |
| 388 | begin |
| 389 | activate_ig_sm_rel_2a <= activate_ig_sm_rel; |
| 390 | activate_ig_sm_rel_3a <= activate_ig_sm_rel_2a; |
| 391 | activate_ig_sm_rel_4a <= activate_ig_sm_rel_3a; |
| 392 | activate_ig_sm_rel_5a <= activate_ig_sm_rel_4a; |
| 393 | activate_ig_sm_rel_6a <= activate_ig_sm_rel_5a; |
| 394 | |
| 395 | end // always @ (posedge clk) |
| 396 | |
| 397 | |
| 398 | // Now detect overlap... |
| 399 | always @(posedge clk) |
| 400 | if (activate_ig_sm && !count_req_clk_en && activate_ig_sm_rel_2a && !count_rel_clk_en_2a && (intr_req_group !== intr_rel_group_2a) ) |
| 401 | begin |
| 402 | rel_req_hit_skew1 <= 1; |
| 403 | reverse_case_detected <= 1; |
| 404 | end |
| 405 | else if (activate_ig_sm && !count_req_clk_en && activate_ig_sm_rel_3a && !count_rel_clk_en_3a && (intr_req_group !== intr_rel_group_3a) ) |
| 406 | begin |
| 407 | rel_req_hit_skew2 <= 1; |
| 408 | reverse_case_detected <= 1; |
| 409 | end |
| 410 | else if (activate_ig_sm && !count_req_clk_en && activate_ig_sm_rel_4a && !count_rel_clk_en_4a && (intr_req_group !== intr_rel_group_4a) ) |
| 411 | begin |
| 412 | rel_req_hit_skew3 <= 1; |
| 413 | reverse_case_detected <= 1; |
| 414 | end |
| 415 | else if (activate_ig_sm && !count_req_clk_en && activate_ig_sm_rel_5a && !count_rel_clk_en_5a && (intr_req_group !== intr_rel_group_5a) ) |
| 416 | begin |
| 417 | rel_req_hit_skew4 <= 1; |
| 418 | reverse_case_detected <= 1; |
| 419 | end |
| 420 | else if (activate_ig_sm && !count_req_clk_en && activate_ig_sm_rel_6a && !count_rel_clk_en_6a && (intr_req_group !== intr_rel_group_6a) ) |
| 421 | begin |
| 422 | rel_req_hit_skew5 <= 1; |
| 423 | reverse_case_detected <= 1; |
| 424 | end |
| 425 | |
| 426 | // Now detect our reverse cases!!! |
| 427 | // qualify our hits with ibusy... |
| 428 | assign rel_req_hit_skew1_noibusy = rel_req_hit_skew1 && !ibusy; |
| 429 | assign rel_req_hit_skew2_noibusy = rel_req_hit_skew2 && !ibusy; |
| 430 | assign rel_req_hit_skew3_noibusy = rel_req_hit_skew3 && !ibusy; |
| 431 | assign rel_req_hit_skew4_noibusy = rel_req_hit_skew4 && !ibusy; |
| 432 | assign rel_req_hit_skew5_noibusy = rel_req_hit_skew5 && !ibusy; |
| 433 | |
| 434 | |
| 435 | assign rel_req_hit_skew1_ibusy = rel_req_hit_skew1 && ibusy; |
| 436 | assign rel_req_hit_skew2_ibusy = rel_req_hit_skew2 && ibusy; |
| 437 | assign rel_req_hit_skew3_ibusy = rel_req_hit_skew3 && ibusy; |
| 438 | assign rel_req_hit_skew4_ibusy = rel_req_hit_skew4 && ibusy; |
| 439 | assign rel_req_hit_skew5_ibusy = rel_req_hit_skew5 && ibusy; |
| 440 | |
| 441 | |
| 442 | |
| 443 | always @(posedge clk) |
| 444 | if(end_of_req_signal && end_of_rel_signal && reverse_case_detected) |
| 445 | begin |
| 446 | // reset signals... |
| 447 | reverse_case_detected <= 0; |
| 448 | |
| 449 | rel_req_hit_skew1 = 0; |
| 450 | rel_req_hit_skew2 = 0; |
| 451 | rel_req_hit_skew3 = 0; |
| 452 | rel_req_hit_skew4 = 0; |
| 453 | rel_req_hit_skew5 = 0; |
| 454 | |
| 455 | |
| 456 | |
| 457 | end // if (end_of_req_signal && end_of_rel_signal && reverse_case_detected) |
| 458 | |
| 459 | |
| 460 | always @(posedge clk) |
| 461 | if(!reverse_case_detected) |
| 462 | begin |
| 463 | // reset detect signals here... |
| 464 | // rel_len1_ovrlp_req_len1_skew0 <= 0; |
| 465 | // rel_len1_ovrlp_req_len1_skew1 <= 0; |
| 466 | // rel_len1_ovrlp_req_len1_skew2 <= 0; |
| 467 | end |
| 468 | |
| 469 | |
| 470 | |
| 471 | |
| 472 | |
| 473 | |
| 474 | |
| 475 | |
| 476 | |
| 477 | |
| 478 | |
| 479 | |
| 480 | |
| 481 | `endif // NIU_SYSTEMC_MODEL |
| 482 | endmodule // niu_intr_monitor |
| 483 | |
| 484 | `endif // if NIU_GATE... else...endif |
| 485 | |
| 486 | |