| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: rgmii_mux.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module rgmii_mux(txclk, |
| 36 | tx_config, |
| 37 | txd0_d4, |
| 38 | txd1_d5, |
| 39 | txd2_d6, |
| 40 | txd3_d7, |
| 41 | txen_er, |
| 42 | rxclk, |
| 43 | rx_config, |
| 44 | rxd0_d4, |
| 45 | rxd1_d5, |
| 46 | rxd2_d6, |
| 47 | rxd3_d7, |
| 48 | rxer_dv, |
| 49 | txd, |
| 50 | txen, |
| 51 | txer, |
| 52 | rxd, |
| 53 | rxdv, |
| 54 | rxer); |
| 55 | |
| 56 | input txclk; |
| 57 | input [3:0] tx_config; |
| 58 | input txd0_d4, txd1_d5, txd2_d6, txd3_d7; |
| 59 | input txen_er; |
| 60 | output [7:0] txd; |
| 61 | output txen, txer; |
| 62 | |
| 63 | input rxclk; |
| 64 | input [3:0] rx_config; |
| 65 | output rxd0_d4, rxd1_d5, rxd2_d6,rxd3_d7; |
| 66 | output rxer_dv; |
| 67 | input [7:0] rxd; |
| 68 | input rxdv, rxer; |
| 69 | |
| 70 | |
| 71 | reg [3:0] txd_r; |
| 72 | reg [3:0] txd_f; |
| 73 | reg txen_r; |
| 74 | reg txen, txer; |
| 75 | |
| 76 | |
| 77 | reg rxd0_d4, rxd1_d5, rxd2_d6,rxd3_d7; |
| 78 | reg rxer_dv; |
| 79 | |
| 80 | //wire rxer_dv; |
| 81 | |
| 82 | |
| 83 | // ----- TX negedge register ----- |
| 84 | |
| 85 | |
| 86 | always @(negedge txclk) |
| 87 | begin |
| 88 | //if (tx_config[3:0] == 4'b0011) |
| 89 | // begin |
| 90 | txd_f[3] <= #0.5 txd3_d7; |
| 91 | txd_f[2] <= #0.5 txd2_d6; |
| 92 | txd_f[1] <= #0.5 txd1_d5; |
| 93 | txd_f[0] <= #0.5 txd0_d4; |
| 94 | txen_r <= #0.5 txen_er; |
| 95 | //end |
| 96 | end |
| 97 | |
| 98 | always @(posedge txclk) |
| 99 | begin |
| 100 | txd_r[3:0] <= #0.5 {txd3_d7, txd2_d6, txd1_d5,txd0_d4}; |
| 101 | txen <= #0.5 txen_er; |
| 102 | txer <= #0.5 txen_r; |
| 103 | end |
| 104 | |
| 105 | assign txd[7:0] = {txd_f[3:0],txd_r[3:0]}; |
| 106 | |
| 107 | |
| 108 | always @(negedge rxclk) |
| 109 | //always @(posedge rxclk) |
| 110 | begin |
| 111 | rxd0_d4 <= #0.5 rxd[0]; |
| 112 | rxd1_d5 <= #0.5 rxd[1]; |
| 113 | rxd2_d6 <= #0.5 rxd[2]; |
| 114 | rxd3_d7 <= #0.5 rxd[3]; |
| 115 | rxer_dv <= #0.5 rxdv; |
| 116 | |
| 117 | end |
| 118 | |
| 119 | //always @(negedge rxclk) |
| 120 | always @(posedge rxclk) |
| 121 | begin |
| 122 | rxd0_d4 <= #0.5 rxd[4]; |
| 123 | rxd1_d5 <= #0.5 rxd[5]; |
| 124 | rxd2_d6 <= #0.5 rxd[6]; |
| 125 | rxd3_d7 <= #0.5 rxd[7]; |
| 126 | rxer_dv <= #0.5 rxer; |
| 127 | |
| 128 | end |
| 129 | |
| 130 | // ----- RX Mux ----- |
| 131 | /** |
| 132 | assign #0.5 {rxd0_d4, rxd1_d5, rxd2_d6, rxd3_d7, rxer_dv} = (rxclk==1) ? |
| 133 | {rxd[4],rxd[5], rxd[6],rxd[7], rxer} : |
| 134 | {rxd[0], rxd[1],rxd[2],rxd[3], rxdv}; |
| 135 | |
| 136 | assign #0.0 {rxd0_d4, rxd1_d5, rxd2_d6, rxd3_d7, rxer_dv} = (rxclk==1) ? |
| 137 | {rxd[4],rxd[5], rxd[6],rxd[7], rxer} : |
| 138 | {rxd[0], rxd[1],rxd[2],rxd[3], rxdv}; |
| 139 | |
| 140 | ***************************/ |
| 141 | endmodule |
| 142 | |