| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ccu_ucbflow_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module ccu_ucbflow_ctl ( |
| 36 | rst_n, |
| 37 | iol2clk, |
| 38 | scan_in, |
| 39 | scan_out, |
| 40 | tcu_pce_ov, |
| 41 | tcu_clk_stop, |
| 42 | tcu_aclk, |
| 43 | tcu_bclk, |
| 44 | tcu_scan_en, |
| 45 | ncu_ccu_vld, |
| 46 | ncu_ccu_data, |
| 47 | ccu_ncu_stall, |
| 48 | ccu_ncu_vld, |
| 49 | ccu_ncu_data, |
| 50 | ncu_ccu_stall, |
| 51 | rd_req_vld, |
| 52 | wr_req_vld, |
| 53 | thr_id_in, |
| 54 | buf_id_in, |
| 55 | addr_in, |
| 56 | data_in, |
| 57 | req_acpted, |
| 58 | rd_ack_vld, |
| 59 | rd_nack_vld, |
| 60 | thr_id_out, |
| 61 | buf_id_out, |
| 62 | data_out, |
| 63 | ack_busy) ; |
| 64 | wire indata_buf_vld; |
| 65 | wire [127:0] indata_buf; |
| 66 | wire ccu_ucbbusin4_ctl_scanin; |
| 67 | wire ccu_ucbbusin4_ctl_scanout; |
| 68 | wire ccu_ncu_stall_a1; |
| 69 | wire read_pending; |
| 70 | wire write_pending; |
| 71 | wire buf_full; |
| 72 | wire rd_buf; |
| 73 | wire [1:0] buf_head_next; |
| 74 | wire [1:0] buf_head; |
| 75 | wire buf_head_next0_; |
| 76 | wire buf_head0_; |
| 77 | wire buf_head_ff0_scanin; |
| 78 | wire buf_head_ff0_scanout; |
| 79 | wire l1clk; |
| 80 | wire buf_head_ff1_scanin; |
| 81 | wire buf_head_ff1_scanout; |
| 82 | wire wr_buf; |
| 83 | wire [1:0] buf_tail_next; |
| 84 | wire [1:0] buf_tail; |
| 85 | wire buf_tail_next0_; |
| 86 | wire buf_tail0_; |
| 87 | wire buf_tail_ff0_scanin; |
| 88 | wire buf_tail_ff0_scanout; |
| 89 | wire buf_tail_ff1_scanin; |
| 90 | wire buf_tail_ff1_scanout; |
| 91 | wire buf_full_next; |
| 92 | wire buf_full_ff_scanin; |
| 93 | wire buf_full_ff_scanout; |
| 94 | wire buf_empty_next; |
| 95 | wire buf_empty_next_; |
| 96 | wire buf_empty; |
| 97 | wire buf_empty_; |
| 98 | wire buf_empty_ff_scanin; |
| 99 | wire buf_empty_ff_scanout; |
| 100 | wire [116:0] req_in; |
| 101 | wire [8:0] unconnected_rsvd; |
| 102 | wire buf0_en; |
| 103 | wire buf0_ff_scanin; |
| 104 | wire buf0_ff_scanout; |
| 105 | wire [116:0] buf0; |
| 106 | wire buf1_en; |
| 107 | wire buf1_ff_scanin; |
| 108 | wire buf1_ff_scanout; |
| 109 | wire [116:0] buf1; |
| 110 | wire [116:0] req_out; |
| 111 | wire [2:0] unconnected_size_in; |
| 112 | wire wr_req_vld_nq; |
| 113 | wire rd_req_vld_nq; |
| 114 | wire ack_buf_wr; |
| 115 | wire ack_buf_vld_next; |
| 116 | wire ack_buf_rd; |
| 117 | wire ack_buf_vld; |
| 118 | wire ack_buf_vld_ff_scanin; |
| 119 | wire ack_buf_vld_ff_scanout; |
| 120 | wire ack_buf_is_nack_ff_scanin; |
| 121 | wire ack_buf_is_nack_ff_scanout; |
| 122 | wire ack_buf_is_nack; |
| 123 | wire [3:0] ack_typ_out; |
| 124 | wire [75:0] ack_buf_in; |
| 125 | wire ack_buf_ff_scanin; |
| 126 | wire ack_buf_ff_scanout; |
| 127 | wire [75:0] ack_buf; |
| 128 | wire [31:0] ack_buf_vec; |
| 129 | wire outdata_buf_busy; |
| 130 | wire outdata_buf_wr; |
| 131 | wire [127:0] outdata_buf_in; |
| 132 | wire [31:0] outdata_vec_in; |
| 133 | wire ccu_ucbbusout4_ctl_scanin; |
| 134 | wire ccu_ucbbusout4_ctl_scanout; |
| 135 | wire se; |
| 136 | wire siclk; |
| 137 | wire soclk; |
| 138 | wire pce_ov; |
| 139 | wire stop; |
| 140 | |
| 141 | |
| 142 | |
| 143 | // Globals |
| 144 | input rst_n; |
| 145 | input iol2clk; |
| 146 | input scan_in; |
| 147 | output scan_out; |
| 148 | input tcu_pce_ov; |
| 149 | input tcu_clk_stop; |
| 150 | input tcu_aclk ; |
| 151 | input tcu_bclk ; |
| 152 | input tcu_scan_en ; |
| 153 | |
| 154 | // Downstream from NCU |
| 155 | input ncu_ccu_vld; |
| 156 | input [3:0] ncu_ccu_data; |
| 157 | output ccu_ncu_stall; |
| 158 | |
| 159 | // Upstream to NCU |
| 160 | output ccu_ncu_vld; |
| 161 | output [3:0] ccu_ncu_data; |
| 162 | input ncu_ccu_stall; |
| 163 | |
| 164 | // CMDs to local unit |
| 165 | output rd_req_vld; |
| 166 | output wr_req_vld; |
| 167 | output [5:0] thr_id_in; |
| 168 | output [1:0] buf_id_in; |
| 169 | output [39:0] addr_in; |
| 170 | output [63:0] data_in; |
| 171 | input req_acpted; |
| 172 | |
| 173 | // Ack/Nack from local unit |
| 174 | input rd_ack_vld; |
| 175 | input rd_nack_vld; |
| 176 | input [5:0] thr_id_out; |
| 177 | input [1:0] buf_id_out; |
| 178 | input [63:0] data_out; |
| 179 | output ack_busy; |
| 180 | |
| 181 | |
| 182 | |
| 183 | |
| 184 | // Local signals |
| 185 | |
| 186 | |
| 187 | |
| 188 | |
| 189 | //wire int_buf_rd; |
| 190 | //wire int_buf_wr; |
| 191 | //wire int_buf_vld; |
| 192 | //wire int_buf_vld_next; |
| 193 | //wire [6:0] int_buf_in; |
| 194 | //wire [6:0] int_buf; |
| 195 | //wire [3:0] int_buf_vec; |
| 196 | |
| 197 | //wire int_last_rd; |
| 198 | |
| 199 | |
| 200 | //////////////////////////////////////////////////////////////////////// |
| 201 | // Code starts here |
| 202 | //////////////////////////////////////////////////////////////////////// |
| 203 | /************************************************************ |
| 204 | * Inbound Data |
| 205 | ************************************************************/ |
| 206 | /*ccu_ucbbusin4_ctl auto_template ( .scan_in(ccu_ucbbusin4_ctl_scanin), |
| 207 | .vld(ncu_ccu_vld), |
| 208 | .data(ncu_ccu_data[3:0]), |
| 209 | .stall(ccu_ncu_stall), |
| 210 | .stall_a1(ccu_ncu_stall_a1) ); |
| 211 | */ |
| 212 | ccu_ucbbusin4_ctl ccu_ucbbusin4_ctl (/*autoinst*/ |
| 213 | // Outputs |
| 214 | .stall(ccu_ncu_stall), // Templated |
| 215 | .indata_buf_vld(indata_buf_vld), |
| 216 | .indata_buf(indata_buf[127:0]), |
| 217 | // Inputs |
| 218 | .rst_n(rst_n), |
| 219 | .scan_in(ccu_ucbbusin4_ctl_scanin), |
| 220 | .scan_out(ccu_ucbbusin4_ctl_scanout), |
| 221 | .iol2clk(iol2clk), |
| 222 | .tcu_pce_ov(tcu_pce_ov), |
| 223 | .tcu_clk_stop(tcu_clk_stop), |
| 224 | .tcu_aclk (tcu_aclk ), |
| 225 | .tcu_bclk (tcu_bclk ), |
| 226 | .tcu_scan_en (tcu_scan_en ), |
| 227 | .vld(ncu_ccu_vld), // Templated |
| 228 | .data(ncu_ccu_data[3:0]), // Templated |
| 229 | .stall_a1(ccu_ncu_stall_a1)); // Templated |
| 230 | |
| 231 | /************************************************************ |
| 232 | * Decode inbound packet type |
| 233 | ************************************************************/ |
| 234 | assign read_pending = (indata_buf[3:0] == 4'b0100) & indata_buf_vld; |
| 235 | |
| 236 | assign write_pending = (indata_buf[3:0] == 4'b0101) & indata_buf_vld; |
| 237 | |
| 238 | assign ccu_ncu_stall_a1 = (read_pending | write_pending) & buf_full; |
| 239 | |
| 240 | /************************************************************ |
| 241 | * Inbound buffer |
| 242 | ************************************************************/ |
| 243 | // Head pointer |
| 244 | assign rd_buf = req_acpted; |
| 245 | assign buf_head_next[1:0] = rd_buf ? {buf_head[0],buf_head[1]} : buf_head[1:0]; |
| 246 | |
| 247 | assign buf_head_next0_ = ~buf_head_next[0] ; |
| 248 | assign buf_head[0] = ~buf_head0_ ; |
| 249 | msff_width_1 buf_head_ff0 |
| 250 | ( |
| 251 | .scan_in(buf_head_ff0_scanin), |
| 252 | .scan_out(buf_head_ff0_scanout), |
| 253 | .dout (buf_head0_), |
| 254 | .l1clk (l1clk), |
| 255 | .din (buf_head_next0_), |
| 256 | .reset(rst_n), |
| 257 | .siclk(siclk), |
| 258 | .soclk(soclk) |
| 259 | ); |
| 260 | |
| 261 | msff_width_1 buf_head_ff1 |
| 262 | ( |
| 263 | .scan_in(buf_head_ff1_scanin), |
| 264 | .scan_out(buf_head_ff1_scanout), |
| 265 | .dout (buf_head[1]), |
| 266 | .l1clk (l1clk), |
| 267 | .din (buf_head_next[1]), |
| 268 | .reset(rst_n), |
| 269 | .siclk(siclk), |
| 270 | .soclk(soclk) |
| 271 | ); |
| 272 | |
| 273 | // Tail pointer |
| 274 | assign wr_buf = (read_pending | write_pending) & ~buf_full; |
| 275 | |
| 276 | assign buf_tail_next[1:0] = wr_buf ? {buf_tail[0], buf_tail[1]} : buf_tail[1:0]; |
| 277 | |
| 278 | assign buf_tail_next0_ = ~buf_tail_next[0]; |
| 279 | assign buf_tail[0] = ~buf_tail0_ ; |
| 280 | msff_width_1 buf_tail_ff0 |
| 281 | ( |
| 282 | .scan_in(buf_tail_ff0_scanin), |
| 283 | .scan_out(buf_tail_ff0_scanout), |
| 284 | .dout (buf_tail0_), |
| 285 | .l1clk (l1clk), |
| 286 | .din (buf_tail_next0_), |
| 287 | .reset(rst_n), |
| 288 | .siclk(siclk), |
| 289 | .soclk(soclk) |
| 290 | ); |
| 291 | |
| 292 | msff_width_1 buf_tail_ff1 |
| 293 | ( |
| 294 | .scan_in(buf_tail_ff1_scanin), |
| 295 | .scan_out(buf_tail_ff1_scanout), |
| 296 | .dout (buf_tail[1]), |
| 297 | .l1clk (l1clk), |
| 298 | .din (buf_tail_next[1]), |
| 299 | .reset(rst_n), |
| 300 | .siclk(siclk), |
| 301 | .soclk(soclk) |
| 302 | ); |
| 303 | |
| 304 | // Buffer full |
| 305 | assign buf_full_next = (buf_head_next[1:0] == buf_tail_next[1:0]) & wr_buf; |
| 306 | msff_en_width_1 buf_full_ff |
| 307 | ( |
| 308 | .scan_in(buf_full_ff_scanin), |
| 309 | .scan_out(buf_full_ff_scanout), |
| 310 | .dout (buf_full), |
| 311 | .l1clk (l1clk), |
| 312 | .en (rd_buf|wr_buf), |
| 313 | .din (buf_full_next), |
| 314 | .reset(rst_n), |
| 315 | .siclk(siclk), |
| 316 | .soclk(soclk) |
| 317 | ); |
| 318 | |
| 319 | // Buffer empty |
| 320 | assign buf_empty_next = ((buf_head_next[1:0] == buf_tail_next[1:0]) & rd_buf) ; |
| 321 | assign buf_empty_next_ = ~buf_empty_next ; |
| 322 | assign buf_empty = ~buf_empty_ ; |
| 323 | msff_en_width_1 buf_empty_ff |
| 324 | ( |
| 325 | .scan_in(buf_empty_ff_scanin), |
| 326 | .scan_out(buf_empty_ff_scanout), |
| 327 | .dout (buf_empty_), |
| 328 | .l1clk (l1clk), |
| 329 | .en (rd_buf|wr_buf), |
| 330 | .din (buf_empty_next_), |
| 331 | .reset(rst_n), |
| 332 | .siclk(siclk), |
| 333 | .soclk(soclk) |
| 334 | ); |
| 335 | |
| 336 | assign { req_in[116:53], |
| 337 | unconnected_rsvd[8:0], |
| 338 | req_in[52:0] } = { indata_buf[127:64], |
| 339 | indata_buf[63:55], |
| 340 | indata_buf[54:15], |
| 341 | indata_buf[14:12], |
| 342 | indata_buf[11:10], |
| 343 | indata_buf[9:4], |
| 344 | write_pending, |
| 345 | read_pending }; |
| 346 | |
| 347 | // Buffer 0 |
| 348 | assign buf0_en = buf_tail[0] & wr_buf; |
| 349 | msff_en_width_117 buf0_ff |
| 350 | ( |
| 351 | .scan_in(buf0_ff_scanin), |
| 352 | .scan_out(buf0_ff_scanout), |
| 353 | .dout (buf0[116:0]), |
| 354 | .l1clk (l1clk), |
| 355 | .en (buf0_en), |
| 356 | .din (req_in[116:0]), |
| 357 | .reset(rst_n), |
| 358 | .siclk(siclk), |
| 359 | .soclk(soclk) |
| 360 | ); |
| 361 | // Buffer 1 |
| 362 | assign buf1_en = buf_tail[1] & wr_buf; |
| 363 | msff_en_width_117 buf1_ff |
| 364 | ( |
| 365 | .scan_in(buf1_ff_scanin), |
| 366 | .scan_out(buf1_ff_scanout), |
| 367 | .dout (buf1[116:0]), |
| 368 | .l1clk (l1clk), |
| 369 | .en (buf1_en), |
| 370 | .din (req_in[116:0]), |
| 371 | .reset(rst_n), |
| 372 | .siclk(siclk), |
| 373 | .soclk(soclk) |
| 374 | ); |
| 375 | |
| 376 | assign req_out[116:0] = buf_head[0] ? buf0[116:0] : |
| 377 | buf_head[1] ? buf1[116:0] : 117'b0; |
| 378 | |
| 379 | |
| 380 | /************************************************************ |
| 381 | * Inbound interface to local unit |
| 382 | ************************************************************/ |
| 383 | assign {data_in[63:0], |
| 384 | addr_in[39:0], |
| 385 | unconnected_size_in[2:0], |
| 386 | buf_id_in[1:0], |
| 387 | thr_id_in[5:0], |
| 388 | wr_req_vld_nq, |
| 389 | rd_req_vld_nq} = req_out[116:0]; |
| 390 | |
| 391 | assign rd_req_vld = rd_req_vld_nq & ~buf_empty; |
| 392 | assign wr_req_vld = wr_req_vld_nq & ~buf_empty; |
| 393 | |
| 394 | |
| 395 | /************************************************************ |
| 396 | * Outbound Ack/Nack |
| 397 | ************************************************************/ |
| 398 | assign ack_buf_wr = rd_ack_vld | rd_nack_vld; |
| 399 | |
| 400 | assign ack_buf_vld_next = ack_buf_wr ? 1'b1 : |
| 401 | ack_buf_rd ? 1'b0 : ack_buf_vld; |
| 402 | |
| 403 | msff_width_1 ack_buf_vld_ff |
| 404 | ( |
| 405 | .scan_in(ack_buf_vld_ff_scanin), |
| 406 | .scan_out(ack_buf_vld_ff_scanout), |
| 407 | .dout (ack_buf_vld), |
| 408 | .l1clk (l1clk), |
| 409 | .din (ack_buf_vld_next), |
| 410 | .reset(rst_n), |
| 411 | .siclk(siclk), |
| 412 | .soclk(soclk) |
| 413 | ); |
| 414 | |
| 415 | msff_en_width_1 ack_buf_is_nack_ff |
| 416 | ( |
| 417 | .scan_in(ack_buf_is_nack_ff_scanin), |
| 418 | .scan_out(ack_buf_is_nack_ff_scanout), |
| 419 | .dout (ack_buf_is_nack), |
| 420 | .l1clk (l1clk), |
| 421 | .en (ack_buf_wr), |
| 422 | .din (rd_nack_vld), |
| 423 | .reset(rst_n), |
| 424 | .siclk(siclk), |
| 425 | .soclk(soclk) |
| 426 | ); |
| 427 | |
| 428 | assign ack_typ_out[3:0] = rd_ack_vld ? 4'b0001: //UCB_READ_ACK |
| 429 | 4'b0000; //UCB_READ_NACK |
| 430 | |
| 431 | assign ack_buf_in[75:0] = { data_out[63:0], |
| 432 | buf_id_out[1:0], |
| 433 | thr_id_out[5:0], |
| 434 | ack_typ_out[3:0] }; |
| 435 | |
| 436 | msff_en_width_76 ack_buf_ff |
| 437 | ( |
| 438 | .scan_in(ack_buf_ff_scanin), |
| 439 | .scan_out(ack_buf_ff_scanout), |
| 440 | .dout (ack_buf[75:0]), |
| 441 | .l1clk (l1clk), |
| 442 | .en (ack_buf_wr), |
| 443 | .din (ack_buf_in[75:0]), |
| 444 | .reset(rst_n), |
| 445 | .siclk(siclk), |
| 446 | .soclk(soclk) |
| 447 | ); |
| 448 | |
| 449 | assign ack_buf_vec[31:0] = ack_buf_is_nack ? {16'h0000,16'hffff} : {32'hffff_ffff} ; |
| 450 | |
| 451 | assign ack_busy = ack_buf_vld; |
| 452 | |
| 453 | assign ack_buf_rd = ~outdata_buf_busy & ack_buf_vld ; |
| 454 | |
| 455 | assign outdata_buf_wr = ack_buf_rd ; |
| 456 | |
| 457 | assign outdata_buf_in[127:0] = {ack_buf[75:12], //payload 64bit |
| 458 | 9'b0, //reserved [63:55] |
| 459 | 40'h00_0000_0000, //40bit addr [54:15] |
| 460 | 3'b000, //size [14:12] |
| 461 | ack_buf[11:10], //buf_id 2bit |
| 462 | ack_buf[9:4], //thr_id 6bit |
| 463 | ack_buf[3:0]}; //type 4bit |
| 464 | |
| 465 | assign outdata_vec_in[31:0] = ack_buf_vec[31:0] ; |
| 466 | |
| 467 | |
| 468 | /*ccu_ucbbusout4_ctl auto_template ( |
| 469 | .vld(ccu_ncu_vld), |
| 470 | .data(ccu_ncu_data[3:0]), |
| 471 | .stall(ncu_ccu_stall), |
| 472 | .outdata_vec_in(outdata_vec_in[31:0]) ); |
| 473 | */ |
| 474 | ccu_ucbbusout4_ctl ccu_ucbbusout4_ctl (/*autoinst*/ |
| 475 | // Outputs |
| 476 | .vld(ccu_ncu_vld), // Templated |
| 477 | .data(ccu_ncu_data[3:0]), // Templated |
| 478 | .outdata_buf_busy(outdata_buf_busy), |
| 479 | // Inputs |
| 480 | .rst_n (rst_n), |
| 481 | .scan_in(ccu_ucbbusout4_ctl_scanin), |
| 482 | .scan_out(ccu_ucbbusout4_ctl_scanout), |
| 483 | .iol2clk(iol2clk), |
| 484 | .tcu_pce_ov(tcu_pce_ov), |
| 485 | .tcu_clk_stop(tcu_clk_stop), |
| 486 | .tcu_aclk (tcu_aclk ), |
| 487 | .tcu_bclk (tcu_bclk ), |
| 488 | .tcu_scan_en (tcu_scan_en ), |
| 489 | .stall(ncu_ccu_stall), // Templated |
| 490 | .outdata_buf_in(outdata_buf_in[127:0]), |
| 491 | .outdata_vec_in(outdata_vec_in[31:0]), // Templated |
| 492 | .outdata_buf_wr(outdata_buf_wr)); |
| 493 | |
| 494 | // scan renames |
| 495 | assign se = tcu_scan_en; |
| 496 | // end scan |
| 497 | |
| 498 | /**** adding clock header ****/ |
| 499 | l1clkhdr_wrapper clkgen ( |
| 500 | .l2clk (iol2clk), |
| 501 | .l1en (1'b1), |
| 502 | // .pce_ov (1'b0 ), |
| 503 | .stop (1'b0 ), |
| 504 | // .se (1'b0 ), |
| 505 | .l1clk (l1clk), |
| 506 | .pce_ov(pce_ov), |
| 507 | .se(se) |
| 508 | ); |
| 509 | |
| 510 | /*** building tcu port ***/ |
| 511 | assign siclk = tcu_aclk ; |
| 512 | assign soclk = tcu_bclk ; |
| 513 | assign pce_ov = tcu_pce_ov; |
| 514 | assign stop = tcu_clk_stop; |
| 515 | |
| 516 | // fixscan start: |
| 517 | assign ccu_ucbbusin4_ctl_scanin = scan_in ; |
| 518 | assign buf_head_ff0_scanin = ccu_ucbbusin4_ctl_scanout; |
| 519 | assign buf_head_ff1_scanin = buf_head_ff0_scanout ; |
| 520 | assign buf_tail_ff0_scanin = buf_head_ff1_scanout ; |
| 521 | assign buf_tail_ff1_scanin = buf_tail_ff0_scanout ; |
| 522 | assign buf_full_ff_scanin = buf_tail_ff1_scanout ; |
| 523 | assign buf_empty_ff_scanin = buf_full_ff_scanout ; |
| 524 | assign buf0_ff_scanin = buf_empty_ff_scanout ; |
| 525 | assign buf1_ff_scanin = buf0_ff_scanout ; |
| 526 | assign ack_buf_vld_ff_scanin = buf1_ff_scanout ; |
| 527 | assign ack_buf_is_nack_ff_scanin = ack_buf_vld_ff_scanout ; |
| 528 | assign ack_buf_ff_scanin = ack_buf_is_nack_ff_scanout; |
| 529 | assign ccu_ucbbusout4_ctl_scanin = ack_buf_ff_scanout ; |
| 530 | assign scan_out = ccu_ucbbusout4_ctl_scanout; |
| 531 | // fixscan end: |
| 532 | endmodule // ucb_flow_ccu |
| 533 | |
| 534 | // verilog-library-directories:(".") |
| 535 | |
| 536 | |
| 537 | // Verilog define statements for ccu_ucbbusin4_ctl.sv and ccu_ucbbusout4_ctl.sv: |
| 538 | |
| 539 | `define UCB_BUS_WIDTH 4 |
| 540 | `define UCB_BUS_WIDTH_M1 3 |
| 541 | `define CYC_NUM 32 |
| 542 | `define CYC_NUM_M1 31 |
| 543 | |
| 544 | |
| 545 | // `define UCB_BUS_WIDTH 4 |
| 546 | // `define UCB_BUS_WIDTH_M1 3 |
| 547 | // `define CYC_NUM 32 |
| 548 | // `define CYC_NUM_M1 31 |
| 549 | |
| 550 | module ccu_ucbbusin4_ctl ( |
| 551 | rst_n, |
| 552 | iol2clk, |
| 553 | scan_in, |
| 554 | scan_out, |
| 555 | tcu_pce_ov, |
| 556 | tcu_clk_stop, |
| 557 | tcu_aclk, |
| 558 | tcu_bclk, |
| 559 | tcu_scan_en, |
| 560 | vld, |
| 561 | data, |
| 562 | stall, |
| 563 | indata_buf_vld, |
| 564 | indata_buf, |
| 565 | stall_a1) ; |
| 566 | wire stall_d1_; |
| 567 | wire stall_d1; |
| 568 | wire vld_d1_ff_scanin; |
| 569 | wire vld_d1_ff_scanout; |
| 570 | wire vld_d1; |
| 571 | wire l1clk; |
| 572 | wire data_d1_ff_scanin; |
| 573 | wire data_d1_ff_scanout; |
| 574 | wire [3:0] data_d1; |
| 575 | wire stall_ff_scanin; |
| 576 | wire stall_ff_scanout; |
| 577 | wire stall_d1_ff_scanin; |
| 578 | wire stall_d1_ff_scanout; |
| 579 | wire skid_buf0_en; |
| 580 | wire vld_buf0_ff_scanin; |
| 581 | wire vld_buf0_ff_scanout; |
| 582 | wire vld_buf0; |
| 583 | wire data_buf0_ff_scanin; |
| 584 | wire data_buf0_ff_scanout; |
| 585 | wire [3:0] data_buf0; |
| 586 | wire skid_buf1_en_ff_scanin; |
| 587 | wire skid_buf1_en_ff_scanout; |
| 588 | wire skid_buf1_en; |
| 589 | wire vld_buf1_ff_scanin; |
| 590 | wire vld_buf1_ff_scanout; |
| 591 | wire vld_buf1; |
| 592 | wire data_buf1_ff_scanin; |
| 593 | wire data_buf1_ff_scanout; |
| 594 | wire [3:0] data_buf1; |
| 595 | wire skid_buf0_sel; |
| 596 | wire skid_buf1_sel_ff_scanin; |
| 597 | wire skid_buf1_sel_ff_scanout; |
| 598 | wire skid_buf1_sel; |
| 599 | wire vld_mux; |
| 600 | wire [3:0] data_mux; |
| 601 | wire [31:0] indata_vec_next; |
| 602 | wire [31:0] indata_vec; |
| 603 | wire stall_a1_; |
| 604 | wire indata_vec_ff_scanin; |
| 605 | wire indata_vec_ff_scanout; |
| 606 | wire [127:0] indata_buf_next; |
| 607 | wire indata_buf_ff_scanin; |
| 608 | wire indata_buf_ff_scanout; |
| 609 | wire indata_vec0_d1_ff_scanin; |
| 610 | wire indata_vec0_d1_ff_scanout; |
| 611 | wire indata_vec0_d1; |
| 612 | wire siclk; |
| 613 | wire soclk; |
| 614 | wire pce_ov; |
| 615 | wire stop; |
| 616 | wire se; |
| 617 | |
| 618 | |
| 619 | //////////////////////////////////////////////////////////////////////// |
| 620 | // Signal declarations |
| 621 | //////////////////////////////////////////////////////////////////////// |
| 622 | // Global interface |
| 623 | input rst_n; |
| 624 | input iol2clk; |
| 625 | input scan_in; |
| 626 | output scan_out; |
| 627 | input tcu_pce_ov; |
| 628 | input tcu_clk_stop; |
| 629 | input tcu_aclk ; |
| 630 | input tcu_bclk ; |
| 631 | input tcu_scan_en ; |
| 632 | |
| 633 | // UCB bus interface |
| 634 | input vld; |
| 635 | input [`UCB_BUS_WIDTH_M1 :0] data; |
| 636 | output stall; |
| 637 | |
| 638 | |
| 639 | // Local interface |
| 640 | output indata_buf_vld; |
| 641 | output [127:0] indata_buf; |
| 642 | input stall_a1; |
| 643 | |
| 644 | |
| 645 | // Internal signals |
| 646 | |
| 647 | //////////////////////////////////////////////////////////////////////// |
| 648 | // Code starts here |
| 649 | //////////////////////////////////////////////////////////////////////// |
| 650 | /************************************************************ |
| 651 | * UCB bus interface flops |
| 652 | * This is to make signals going between IOB and UCB flop-to-flop |
| 653 | * to improve timing. |
| 654 | ************************************************************/ |
| 655 | assign stall_d1_ = ~stall_d1; |
| 656 | msff_en_width_1 vld_d1_ff |
| 657 | ( |
| 658 | .scan_in(vld_d1_ff_scanin), |
| 659 | .scan_out(vld_d1_ff_scanout), |
| 660 | .dout (vld_d1), |
| 661 | .l1clk (l1clk), |
| 662 | .en (stall_d1_), |
| 663 | .din (vld), |
| 664 | .reset(rst_n), |
| 665 | .siclk(siclk), |
| 666 | .soclk(soclk) |
| 667 | ); |
| 668 | |
| 669 | msff_en_width_4 data_d1_ff |
| 670 | ( |
| 671 | .scan_in(data_d1_ff_scanin), |
| 672 | .scan_out(data_d1_ff_scanout), |
| 673 | .dout (data_d1[`UCB_BUS_WIDTH_M1:0]), |
| 674 | .l1clk (l1clk), |
| 675 | .en (stall_d1_), |
| 676 | .din (data[`UCB_BUS_WIDTH_M1:0]), |
| 677 | .reset(rst_n), |
| 678 | .siclk(siclk), |
| 679 | .soclk(soclk) |
| 680 | ); |
| 681 | |
| 682 | msff_width_1 stall_ff |
| 683 | ( |
| 684 | .scan_in(stall_ff_scanin), |
| 685 | .scan_out(stall_ff_scanout), |
| 686 | .dout (stall), |
| 687 | .l1clk (l1clk), |
| 688 | .din (stall_a1), |
| 689 | .reset(rst_n), |
| 690 | .siclk(siclk), |
| 691 | .soclk(soclk) |
| 692 | ); |
| 693 | |
| 694 | msff_width_1 stall_d1_ff |
| 695 | ( |
| 696 | .scan_in(stall_d1_ff_scanin), |
| 697 | .scan_out(stall_d1_ff_scanout), |
| 698 | .dout (stall_d1), |
| 699 | .l1clk (l1clk), |
| 700 | .din (stall), |
| 701 | .reset(rst_n), |
| 702 | .siclk(siclk), |
| 703 | .soclk(soclk) |
| 704 | ); |
| 705 | |
| 706 | |
| 707 | /************************************************************ |
| 708 | * Skid buffer |
| 709 | * We need a two deep skid buffer to handle stalling. |
| 710 | ************************************************************/ |
| 711 | // Assertion: stall has to be deasserted for more than 1 cycle |
| 712 | // ie time between two separate stalls has to be |
| 713 | // at least two cycles. Otherwise, contents from |
| 714 | // skid buffer will be lost. |
| 715 | |
| 716 | // Buffer 0 |
| 717 | assign skid_buf0_en = stall_a1 & ~stall; |
| 718 | |
| 719 | msff_en_width_1 vld_buf0_ff |
| 720 | ( |
| 721 | .scan_in(vld_buf0_ff_scanin), |
| 722 | .scan_out(vld_buf0_ff_scanout), |
| 723 | .dout (vld_buf0), |
| 724 | .l1clk (l1clk), |
| 725 | .en (skid_buf0_en), |
| 726 | .din (vld_d1), |
| 727 | .reset(rst_n), |
| 728 | .siclk(siclk), |
| 729 | .soclk(soclk) |
| 730 | ); |
| 731 | |
| 732 | msff_en_width_4 data_buf0_ff |
| 733 | ( |
| 734 | .scan_in(data_buf0_ff_scanin), |
| 735 | .scan_out(data_buf0_ff_scanout), |
| 736 | .dout (data_buf0[`UCB_BUS_WIDTH_M1 :0]), |
| 737 | .l1clk (l1clk), |
| 738 | .en (skid_buf0_en), |
| 739 | .din (data_d1[`UCB_BUS_WIDTH_M1 :0]), |
| 740 | .reset(rst_n), |
| 741 | .siclk(siclk), |
| 742 | .soclk(soclk) |
| 743 | ); |
| 744 | |
| 745 | // Buffer 1 |
| 746 | msff_width_1 skid_buf1_en_ff |
| 747 | ( |
| 748 | .scan_in(skid_buf1_en_ff_scanin), |
| 749 | .scan_out(skid_buf1_en_ff_scanout), |
| 750 | .dout (skid_buf1_en), |
| 751 | .l1clk (l1clk), |
| 752 | .din (skid_buf0_en), |
| 753 | .reset(rst_n), |
| 754 | .siclk(siclk), |
| 755 | .soclk(soclk) |
| 756 | ); |
| 757 | |
| 758 | msff_en_width_1 vld_buf1_ff |
| 759 | ( |
| 760 | .scan_in(vld_buf1_ff_scanin), |
| 761 | .scan_out(vld_buf1_ff_scanout), |
| 762 | .dout (vld_buf1), |
| 763 | .l1clk (l1clk), |
| 764 | .en (skid_buf1_en), |
| 765 | .din (vld_d1), |
| 766 | .reset(rst_n), |
| 767 | .siclk(siclk), |
| 768 | .soclk(soclk) |
| 769 | ); |
| 770 | |
| 771 | msff_en_width_4 data_buf1_ff |
| 772 | ( |
| 773 | .scan_in(data_buf1_ff_scanin), |
| 774 | .scan_out(data_buf1_ff_scanout), |
| 775 | .dout (data_buf1[`UCB_BUS_WIDTH_M1 :0]), |
| 776 | .l1clk (l1clk), |
| 777 | .en (skid_buf1_en), |
| 778 | .din (data_d1[`UCB_BUS_WIDTH_M1 :0]), |
| 779 | .reset(rst_n), |
| 780 | .siclk(siclk), |
| 781 | .soclk(soclk) |
| 782 | ); |
| 783 | |
| 784 | |
| 785 | /************************************************************ |
| 786 | * Mux between skid buffer and interface flop |
| 787 | ************************************************************/ |
| 788 | // Assertion: stall has to be deasserted for more than 1 cycle |
| 789 | // ie time between two separate stalls has to be |
| 790 | // at least two cycles. Otherwise, contents from |
| 791 | // skid buffer will be lost. |
| 792 | |
| 793 | assign skid_buf0_sel = ~stall_a1 & stall; |
| 794 | |
| 795 | msff_width_1 skid_buf1_sel_ff |
| 796 | ( |
| 797 | .scan_in(skid_buf1_sel_ff_scanin), |
| 798 | .scan_out(skid_buf1_sel_ff_scanout), |
| 799 | .dout (skid_buf1_sel), |
| 800 | .l1clk (l1clk), |
| 801 | .din (skid_buf0_sel), |
| 802 | .reset(rst_n), |
| 803 | .siclk(siclk), |
| 804 | .soclk(soclk) |
| 805 | ); |
| 806 | |
| 807 | assign vld_mux = skid_buf0_sel ? vld_buf0 : |
| 808 | skid_buf1_sel ? vld_buf1 : |
| 809 | vld_d1; |
| 810 | |
| 811 | assign data_mux[`UCB_BUS_WIDTH_M1 :0] = skid_buf0_sel ? data_buf0[`UCB_BUS_WIDTH_M1 :0] : |
| 812 | skid_buf1_sel ? data_buf1[`UCB_BUS_WIDTH_M1 :0] : |
| 813 | data_d1[`UCB_BUS_WIDTH_M1 :0]; |
| 814 | |
| 815 | |
| 816 | /************************************************************ |
| 817 | * Assemble inbound data |
| 818 | ************************************************************/ |
| 819 | // valid vector |
| 820 | assign indata_vec_next[`CYC_NUM_M1:0] = {vld_mux, indata_vec[`CYC_NUM_M1 :1]}; |
| 821 | |
| 822 | assign stall_a1_ = ~stall_a1; |
| 823 | msff_en_width_32 indata_vec_ff |
| 824 | ( |
| 825 | .scan_in(indata_vec_ff_scanin), |
| 826 | .scan_out(indata_vec_ff_scanout), |
| 827 | .dout (indata_vec[`CYC_NUM_M1 :0]), |
| 828 | .l1clk (l1clk), |
| 829 | .en (stall_a1_), |
| 830 | .din (indata_vec_next[`CYC_NUM_M1 :0]), |
| 831 | .reset(rst_n), |
| 832 | .siclk(siclk), |
| 833 | .soclk(soclk) |
| 834 | ); |
| 835 | |
| 836 | // data buffer |
| 837 | assign indata_buf_next[127:0] = {data_mux[`UCB_BUS_WIDTH_M1 :0], indata_buf[127:`UCB_BUS_WIDTH ]}; |
| 838 | msff_en_width_128 indata_buf_ff |
| 839 | ( |
| 840 | .scan_in(indata_buf_ff_scanin), |
| 841 | .scan_out(indata_buf_ff_scanout), |
| 842 | .dout (indata_buf[127:0]), |
| 843 | .l1clk (l1clk), |
| 844 | .en (stall_a1_), |
| 845 | .din (indata_buf_next[127:0]), |
| 846 | .reset(rst_n), |
| 847 | .siclk(siclk), |
| 848 | .soclk(soclk) |
| 849 | ); |
| 850 | |
| 851 | // detect a new packet |
| 852 | msff_en_width_1 indata_vec0_d1_ff |
| 853 | ( |
| 854 | .scan_in(indata_vec0_d1_ff_scanin), |
| 855 | .scan_out(indata_vec0_d1_ff_scanout), |
| 856 | .dout (indata_vec0_d1), |
| 857 | .l1clk (l1clk), |
| 858 | .en (stall_a1_), |
| 859 | .din (indata_vec[0]), |
| 860 | .reset(rst_n), |
| 861 | .siclk(siclk), |
| 862 | .soclk(soclk) |
| 863 | ); |
| 864 | |
| 865 | assign indata_buf_vld = indata_vec[0] & ~indata_vec0_d1; |
| 866 | |
| 867 | |
| 868 | |
| 869 | /**** adding clock header ****/ |
| 870 | l1clkhdr_wrapper clkgen ( |
| 871 | .l2clk (iol2clk), |
| 872 | .l1en (1'b1), |
| 873 | // .pce_ov (1'b0 ), |
| 874 | .stop (1'b0 ), |
| 875 | // .se (1'b0 ), |
| 876 | .l1clk (l1clk), |
| 877 | .pce_ov(pce_ov), |
| 878 | .se(se) |
| 879 | ); |
| 880 | |
| 881 | /*** building tcu port ***/ |
| 882 | assign siclk = tcu_aclk ; |
| 883 | assign soclk = tcu_bclk ; |
| 884 | assign pce_ov = tcu_pce_ov ; |
| 885 | assign stop = tcu_clk_stop; |
| 886 | // scan renames |
| 887 | assign se = tcu_scan_en ; |
| 888 | // end scan |
| 889 | |
| 890 | // fixscan start: |
| 891 | assign vld_d1_ff_scanin = scan_in ; |
| 892 | assign data_d1_ff_scanin = vld_d1_ff_scanout ; |
| 893 | assign stall_ff_scanin = data_d1_ff_scanout ; |
| 894 | assign stall_d1_ff_scanin = stall_ff_scanout ; |
| 895 | assign vld_buf0_ff_scanin = stall_d1_ff_scanout ; |
| 896 | assign data_buf0_ff_scanin = vld_buf0_ff_scanout ; |
| 897 | assign skid_buf1_en_ff_scanin = data_buf0_ff_scanout ; |
| 898 | assign vld_buf1_ff_scanin = skid_buf1_en_ff_scanout ; |
| 899 | assign data_buf1_ff_scanin = vld_buf1_ff_scanout ; |
| 900 | assign skid_buf1_sel_ff_scanin = data_buf1_ff_scanout ; |
| 901 | assign indata_vec_ff_scanin = skid_buf1_sel_ff_scanout ; |
| 902 | assign indata_buf_ff_scanin = indata_vec_ff_scanout ; |
| 903 | assign indata_vec0_d1_ff_scanin = indata_buf_ff_scanout ; |
| 904 | assign scan_out = indata_vec0_d1_ff_scanout; |
| 905 | // fixscan end: |
| 906 | endmodule // ucb_bus_in |
| 907 | |
| 908 | |
| 909 | |
| 910 | |
| 911 | // *********************************************** |
| 912 | // any PARAMS parms go into naming of macro |
| 913 | // *********************************************** |
| 914 | |
| 915 | module msff_en_width_1 ( |
| 916 | reset, |
| 917 | din, |
| 918 | en, |
| 919 | l1clk, |
| 920 | scan_in, |
| 921 | siclk, |
| 922 | soclk, |
| 923 | dout, |
| 924 | scan_out); |
| 925 | wire [0:0] fdin; |
| 926 | |
| 927 | input reset; |
| 928 | input [0:0] din; |
| 929 | input en; |
| 930 | input l1clk; |
| 931 | input scan_in; |
| 932 | |
| 933 | |
| 934 | input siclk; |
| 935 | input soclk; |
| 936 | |
| 937 | output [0:0] dout; |
| 938 | output scan_out; |
| 939 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); |
| 940 | |
| 941 | |
| 942 | |
| 943 | // dff #(1) d0_0 ( |
| 944 | cl_a1_msff_syrst_1x d0_0 ( |
| 945 | .reset(reset), |
| 946 | .l1clk(l1clk), |
| 947 | .siclk(siclk), |
| 948 | .soclk(soclk), |
| 949 | .d(fdin[0:0]), |
| 950 | .si(scan_in), |
| 951 | .so(scan_out), |
| 952 | .q(dout[0:0]) |
| 953 | ); |
| 954 | |
| 955 | |
| 956 | |
| 957 | endmodule |
| 958 | |
| 959 | |
| 960 | |
| 961 | // *********************************************** |
| 962 | // any PARAMS parms go into naming of macro |
| 963 | // *********************************************** |
| 964 | |
| 965 | module msff_en_width_4 ( |
| 966 | reset, |
| 967 | din, |
| 968 | en, |
| 969 | l1clk, |
| 970 | scan_in, |
| 971 | siclk, |
| 972 | soclk, |
| 973 | dout, |
| 974 | scan_out); |
| 975 | wire [3:0] fdin; |
| 976 | wire [2:0] so; |
| 977 | |
| 978 | input reset; |
| 979 | input [3:0] din; |
| 980 | input en; |
| 981 | input l1clk; |
| 982 | input scan_in; |
| 983 | |
| 984 | |
| 985 | input siclk; |
| 986 | input soclk; |
| 987 | |
| 988 | output [3:0] dout; |
| 989 | output scan_out; |
| 990 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); |
| 991 | |
| 992 | |
| 993 | /* |
| 994 | dff #(4) d0_0 ( |
| 995 | .l1clk(l1clk), |
| 996 | .siclk(siclk), |
| 997 | .soclk(soclk), |
| 998 | .d(fdin[3:0]), |
| 999 | .si({scan_in,so[2:0]}), |
| 1000 | .so({so[2:0],scan_out}), |
| 1001 | .q(dout[3:0]) |
| 1002 | ); |
| 1003 | */ |
| 1004 | |
| 1005 | ccu_msff_syrst_1x_4 U0 ( |
| 1006 | .reset(reset), |
| 1007 | .l1clk(l1clk), |
| 1008 | .siclk(siclk), |
| 1009 | .soclk(soclk), |
| 1010 | .d(fdin[3:0]), |
| 1011 | .si(scan_in), |
| 1012 | .so(scan_out), |
| 1013 | .q(dout[3:0]) |
| 1014 | ); |
| 1015 | |
| 1016 | endmodule |
| 1017 | |
| 1018 | |
| 1019 | |
| 1020 | // *********************************************** |
| 1021 | // any PARAMS parms go into naming of macro |
| 1022 | // *********************************************** |
| 1023 | |
| 1024 | module msff_width_1 ( |
| 1025 | reset, |
| 1026 | din, |
| 1027 | l1clk, |
| 1028 | scan_in, |
| 1029 | siclk, |
| 1030 | soclk, |
| 1031 | dout, |
| 1032 | scan_out); |
| 1033 | wire [0:0] fdin; |
| 1034 | |
| 1035 | input [0:0] din; |
| 1036 | input l1clk; |
| 1037 | input reset; |
| 1038 | input scan_in; |
| 1039 | |
| 1040 | |
| 1041 | input siclk; |
| 1042 | input soclk; |
| 1043 | |
| 1044 | output [0:0] dout; |
| 1045 | output scan_out; |
| 1046 | assign fdin[0:0] = din[0:0]; |
| 1047 | |
| 1048 | // dff #(1) d0_0 ( |
| 1049 | cl_a1_msff_syrst_1x U0 ( |
| 1050 | .reset(reset), |
| 1051 | .l1clk(l1clk), |
| 1052 | .siclk(siclk), |
| 1053 | .soclk(soclk), |
| 1054 | .d(fdin[0:0]), |
| 1055 | .si(scan_in), |
| 1056 | .so(scan_out), |
| 1057 | .q(dout[0:0]) |
| 1058 | ); |
| 1059 | |
| 1060 | |
| 1061 | endmodule |
| 1062 | |
| 1063 | |
| 1064 | |
| 1065 | // *********************************************** |
| 1066 | // any PARAMS parms go into naming of macro |
| 1067 | // *********************************************** |
| 1068 | |
| 1069 | module msff_en_width_32 ( |
| 1070 | reset, |
| 1071 | din, |
| 1072 | en, |
| 1073 | l1clk, |
| 1074 | scan_in, |
| 1075 | siclk, |
| 1076 | soclk, |
| 1077 | dout, |
| 1078 | scan_out); |
| 1079 | wire [31:0] fdin; |
| 1080 | wire [30:0] so; |
| 1081 | |
| 1082 | input [31:0] din; |
| 1083 | input reset; |
| 1084 | input en; |
| 1085 | input l1clk; |
| 1086 | input scan_in; |
| 1087 | |
| 1088 | |
| 1089 | input siclk; |
| 1090 | input soclk; |
| 1091 | |
| 1092 | output [31:0] dout; |
| 1093 | output scan_out; |
| 1094 | assign fdin[31:0] = (din[31:0] & {32{en}}) | (dout[31:0] & ~{32{en}}); |
| 1095 | |
| 1096 | // dff #(32) d0_0 ( |
| 1097 | ccu_msff_syrst_1x_32 U0 ( |
| 1098 | .reset(reset), |
| 1099 | .l1clk(l1clk), |
| 1100 | .siclk(siclk), |
| 1101 | .soclk(soclk), |
| 1102 | .d(fdin[31:0]), |
| 1103 | .si(scan_in), // .si({scan_in,so[30:0]}), |
| 1104 | .so(scan_out),// .so({so[30:0],scan_out}), |
| 1105 | .q(dout[31:0]) |
| 1106 | ); |
| 1107 | |
| 1108 | |
| 1109 | endmodule |
| 1110 | |
| 1111 | |
| 1112 | // *********************************************** |
| 1113 | // any PARAMS parms go into naming of macro |
| 1114 | // *********************************************** |
| 1115 | |
| 1116 | |
| 1117 | module msff_en_width_128 ( |
| 1118 | reset, |
| 1119 | din, |
| 1120 | en, |
| 1121 | l1clk, |
| 1122 | scan_in, |
| 1123 | siclk, |
| 1124 | soclk, |
| 1125 | dout, |
| 1126 | scan_out); |
| 1127 | wire [127:0] fdin; |
| 1128 | wire [126:0] so; |
| 1129 | |
| 1130 | input [127:0] din; |
| 1131 | input en; |
| 1132 | input reset; |
| 1133 | input l1clk; |
| 1134 | input scan_in; |
| 1135 | |
| 1136 | |
| 1137 | input siclk; |
| 1138 | input soclk; |
| 1139 | |
| 1140 | output [127:0] dout; |
| 1141 | output scan_out; |
| 1142 | assign fdin[127:0] = (din[127:0] & {128{en}}) | (dout[127:0] & ~{128{en}}); |
| 1143 | |
| 1144 | /* |
| 1145 | dff #(128) d0_0 ( |
| 1146 | .l1clk(l1clk), |
| 1147 | .siclk(siclk), |
| 1148 | .soclk(soclk), |
| 1149 | .d(fdin[127:0]), |
| 1150 | .si({scan_in,so[126:0]}), |
| 1151 | .so({so[126:0],scan_out}), |
| 1152 | .q(dout[127:0]) |
| 1153 | ); |
| 1154 | */ |
| 1155 | |
| 1156 | ccu_msff_syrst_1x_128 U0 ( |
| 1157 | .reset(reset), |
| 1158 | .l1clk(l1clk), |
| 1159 | .siclk(siclk), |
| 1160 | .soclk(soclk), |
| 1161 | .d(fdin[127:0]), |
| 1162 | .si(scan_in), |
| 1163 | .so(scan_out), |
| 1164 | .q(dout[127:0]) |
| 1165 | ); |
| 1166 | |
| 1167 | endmodule |
| 1168 | |
| 1169 | |
| 1170 | |
| 1171 | |
| 1172 | |
| 1173 | // *********************************************** |
| 1174 | // any PARAMS parms go into naming of macro |
| 1175 | // *********************************************** |
| 1176 | |
| 1177 | module l1clkhdr_wrapper ( |
| 1178 | l2clk, |
| 1179 | l1en, |
| 1180 | pce_ov, |
| 1181 | stop, |
| 1182 | se, |
| 1183 | l1clk); |
| 1184 | |
| 1185 | |
| 1186 | input l2clk; |
| 1187 | input l1en; |
| 1188 | input pce_ov; |
| 1189 | input stop; |
| 1190 | input se; |
| 1191 | output l1clk; |
| 1192 | |
| 1193 | |
| 1194 | |
| 1195 | // cl_sc1_l1hdr_8x c_0 ( |
| 1196 | cl_a1_l1hdr_8x c_0 ( // using different l1 - mhassan |
| 1197 | .l2clk(l2clk), |
| 1198 | .pce(l1en), |
| 1199 | .l1clk(l1clk), |
| 1200 | .se(se), |
| 1201 | .pce_ov(pce_ov), |
| 1202 | .stop(stop) |
| 1203 | ); |
| 1204 | |
| 1205 | |
| 1206 | |
| 1207 | endmodule |
| 1208 | |
| 1209 | |
| 1210 | // *********************************************** |
| 1211 | // any PARAMS parms go into naming of macro |
| 1212 | // *********************************************** |
| 1213 | |
| 1214 | module msff_en_width_117 ( |
| 1215 | reset, |
| 1216 | din, |
| 1217 | en, |
| 1218 | l1clk, |
| 1219 | scan_in, |
| 1220 | siclk, |
| 1221 | soclk, |
| 1222 | dout, |
| 1223 | scan_out); |
| 1224 | wire [116:0] fdin; |
| 1225 | wire [115:0] so; |
| 1226 | |
| 1227 | input [116:0] din; |
| 1228 | input reset; |
| 1229 | input en; |
| 1230 | input l1clk; |
| 1231 | input scan_in; |
| 1232 | |
| 1233 | |
| 1234 | input siclk; |
| 1235 | input soclk; |
| 1236 | |
| 1237 | output [116:0] dout; |
| 1238 | output scan_out; |
| 1239 | |
| 1240 | assign fdin[116:0] = (din[116:0] & {117{en}}) | (dout[116:0] & ~{117{en}}); |
| 1241 | |
| 1242 | /* |
| 1243 | dff #(117) d0_0 ( |
| 1244 | .l1clk(l1clk), |
| 1245 | .siclk(siclk), |
| 1246 | .soclk(soclk), |
| 1247 | .d(fdin[116:0]), |
| 1248 | .si({scan_in,so[115:0]}), |
| 1249 | .so({so[115:0],scan_out}), |
| 1250 | .q(dout[116:0]) |
| 1251 | ); |
| 1252 | */ |
| 1253 | |
| 1254 | |
| 1255 | ccu_msff_syrst_1x_117 U0 ( |
| 1256 | .reset(reset), |
| 1257 | .l1clk(l1clk), |
| 1258 | .siclk(siclk), |
| 1259 | .soclk(soclk), |
| 1260 | .d(fdin[116:0]), |
| 1261 | .si(scan_in), |
| 1262 | .so(scan_out), |
| 1263 | .q(dout[116:0]) |
| 1264 | ); |
| 1265 | |
| 1266 | |
| 1267 | |
| 1268 | endmodule |
| 1269 | |
| 1270 | |
| 1271 | // *********************************************** |
| 1272 | // any PARAMS parms go into naming of macro |
| 1273 | // *********************************************** |
| 1274 | |
| 1275 | module msff_en_width_76 ( |
| 1276 | reset, |
| 1277 | din, |
| 1278 | en, |
| 1279 | l1clk, |
| 1280 | scan_in, |
| 1281 | siclk, |
| 1282 | soclk, |
| 1283 | dout, |
| 1284 | scan_out); |
| 1285 | wire [75:0] fdin; |
| 1286 | wire [74:0] so; |
| 1287 | |
| 1288 | input [75:0] din; |
| 1289 | input en; |
| 1290 | input reset; |
| 1291 | input l1clk; |
| 1292 | input scan_in; |
| 1293 | |
| 1294 | |
| 1295 | input siclk; |
| 1296 | input soclk; |
| 1297 | |
| 1298 | output [75:0] dout; |
| 1299 | output scan_out; |
| 1300 | assign fdin[75:0] = (din[75:0] & {76{en}}) | (dout[75:0] & ~{76{en}}); |
| 1301 | |
| 1302 | |
| 1303 | /* |
| 1304 | dff #(76) d0_0 ( |
| 1305 | .l1clk(l1clk), |
| 1306 | .siclk(siclk), |
| 1307 | .soclk(soclk), |
| 1308 | .d(fdin[75:0]), |
| 1309 | .si({scan_in,so[74:0]}), |
| 1310 | .so({so[74:0],scan_out}), |
| 1311 | .q(dout[75:0]) |
| 1312 | ); |
| 1313 | */ |
| 1314 | |
| 1315 | ccu_msff_syrst_1x_76 U0 ( |
| 1316 | .reset(reset), |
| 1317 | .l1clk(l1clk), |
| 1318 | .siclk(siclk), |
| 1319 | .soclk(soclk), |
| 1320 | .d(fdin[75:0]), |
| 1321 | .si(scan_in), |
| 1322 | .so(scan_out), |
| 1323 | .q(dout[75:0]) |
| 1324 | ); |
| 1325 | |
| 1326 | |
| 1327 | endmodule |
| 1328 | |
| 1329 | |
| 1330 | |
| 1331 | |
| 1332 | // Verilog define statements for ccu_ucbbusin4_ctl.sv and ccu_ucbbusout4_ctl.sv: |
| 1333 | |
| 1334 | `define UCB_BUS_WIDTH 4 |
| 1335 | `define UCB_BUS_WIDTH_M1 3 |
| 1336 | `define CYC_NUM 32 |
| 1337 | `define CYC_NUM_M1 31 |
| 1338 | |
| 1339 | |
| 1340 | // `define UCB_BUS_WIDTH 4 |
| 1341 | // `define UCB_BUS_WIDTH_M1 3 |
| 1342 | // `define CYC_NUM 32 |
| 1343 | // `define CYC_NUM_M1 31 |
| 1344 | |
| 1345 | module ccu_ucbbusout4_ctl ( |
| 1346 | rst_n, |
| 1347 | iol2clk, |
| 1348 | scan_in, |
| 1349 | scan_out, |
| 1350 | tcu_pce_ov, |
| 1351 | tcu_clk_stop, |
| 1352 | tcu_aclk, |
| 1353 | tcu_bclk, |
| 1354 | tcu_scan_en, |
| 1355 | vld, |
| 1356 | data, |
| 1357 | stall, |
| 1358 | outdata_buf_busy, |
| 1359 | outdata_buf_in, |
| 1360 | outdata_vec_in, |
| 1361 | outdata_buf_wr) ; |
| 1362 | wire [31:0] outdata_vec; |
| 1363 | wire [127:0] outdata_buf; |
| 1364 | wire stall_d1_ff_scanin; |
| 1365 | wire stall_d1_ff_scanout; |
| 1366 | wire stall_d1; |
| 1367 | wire l1clk; |
| 1368 | wire load_outdata; |
| 1369 | wire shift_outdata; |
| 1370 | wire [31:0] outdata_vec_next; |
| 1371 | wire outdata_vec_ff_scanin; |
| 1372 | wire outdata_vec_ff_scanout; |
| 1373 | wire [127:0] outdata_buf_next; |
| 1374 | wire outdata_buf_ff_scanin; |
| 1375 | wire outdata_buf_ff_scanout; |
| 1376 | wire siclk; |
| 1377 | wire soclk; |
| 1378 | wire pce_ov; |
| 1379 | wire stop; |
| 1380 | wire se; |
| 1381 | |
| 1382 | |
| 1383 | // Globals |
| 1384 | input rst_n; |
| 1385 | input iol2clk; |
| 1386 | input scan_in; |
| 1387 | output scan_out; |
| 1388 | input tcu_pce_ov; |
| 1389 | input tcu_clk_stop; |
| 1390 | input tcu_aclk ; |
| 1391 | input tcu_bclk ; |
| 1392 | input tcu_scan_en ; |
| 1393 | |
| 1394 | // UCB bus interface |
| 1395 | output vld; |
| 1396 | output [`UCB_BUS_WIDTH_M1 :0] data; |
| 1397 | input stall; |
| 1398 | |
| 1399 | // Local interface |
| 1400 | output outdata_buf_busy; |
| 1401 | input [127:0] outdata_buf_in; |
| 1402 | input [`CYC_NUM_M1 :0] outdata_vec_in; |
| 1403 | input outdata_buf_wr; |
| 1404 | |
| 1405 | // Local signals |
| 1406 | |
| 1407 | //////////////////////////////////////////////////////////////////////// |
| 1408 | // Code starts here |
| 1409 | //////////////////////////////////////////////////////////////////////// |
| 1410 | /************************************************************ |
| 1411 | * UCB bus interface flops |
| 1412 | ************************************************************/ |
| 1413 | assign vld = outdata_vec[0]; |
| 1414 | assign data[`UCB_BUS_WIDTH_M1 :0] = outdata_buf[`UCB_BUS_WIDTH_M1 :0]; |
| 1415 | |
| 1416 | msff_width_1 stall_d1_ff |
| 1417 | ( |
| 1418 | .scan_in(stall_d1_ff_scanin), |
| 1419 | .scan_out(stall_d1_ff_scanout), |
| 1420 | .dout (stall_d1), |
| 1421 | .l1clk (l1clk), |
| 1422 | .din (stall), |
| 1423 | .reset(rst_n), |
| 1424 | .siclk(siclk), |
| 1425 | .soclk(soclk) |
| 1426 | ); |
| 1427 | |
| 1428 | /************************************************************ |
| 1429 | * Outbound Data |
| 1430 | ************************************************************/ |
| 1431 | // accept new data only if there is none being processed |
| 1432 | assign load_outdata = outdata_buf_wr & ~outdata_buf_busy; |
| 1433 | |
| 1434 | assign outdata_buf_busy = outdata_vec[0] | stall_d1; |
| 1435 | |
| 1436 | assign shift_outdata = outdata_vec[0] & ~stall_d1; |
| 1437 | |
| 1438 | assign outdata_vec_next[`CYC_NUM_M1 :0] = |
| 1439 | load_outdata ? outdata_vec_in[`CYC_NUM_M1 :0] : |
| 1440 | shift_outdata ? {1'b0,outdata_vec[`CYC_NUM_M1 :1]} : |
| 1441 | outdata_vec[`CYC_NUM_M1 :0] ; |
| 1442 | |
| 1443 | msff_width_32 outdata_vec_ff |
| 1444 | ( |
| 1445 | .scan_in(outdata_vec_ff_scanin), |
| 1446 | .scan_out(outdata_vec_ff_scanout), |
| 1447 | .dout (outdata_vec[`CYC_NUM_M1 :0]), |
| 1448 | .l1clk (l1clk), |
| 1449 | .din (outdata_vec_next[`CYC_NUM_M1 :0]), |
| 1450 | .reset(rst_n), |
| 1451 | .siclk(siclk), |
| 1452 | .soclk(soclk) |
| 1453 | ); |
| 1454 | |
| 1455 | assign outdata_buf_next[127:0] = load_outdata ? outdata_buf_in[127:0] : |
| 1456 | shift_outdata ? (outdata_buf[127:0] >> `UCB_BUS_WIDTH ) : |
| 1457 | outdata_buf[127:0] ; |
| 1458 | |
| 1459 | msff_width_128 outdata_buf_ff |
| 1460 | ( |
| 1461 | .scan_in(outdata_buf_ff_scanin), |
| 1462 | .scan_out(outdata_buf_ff_scanout), |
| 1463 | .dout (outdata_buf[127:0]), |
| 1464 | .l1clk (l1clk), |
| 1465 | .din (outdata_buf_next[127:0]), |
| 1466 | .reset(rst_n), |
| 1467 | .siclk(siclk), |
| 1468 | .soclk(soclk) |
| 1469 | ); |
| 1470 | |
| 1471 | |
| 1472 | |
| 1473 | /**** adding clock header ****/ |
| 1474 | l1clkhdr_wrapper clkgen ( |
| 1475 | .l2clk (iol2clk), |
| 1476 | .l1en (1'b1), |
| 1477 | // .pce_ov (1'b0 ), |
| 1478 | .stop (1'b0 ), |
| 1479 | // .se (1'b0 ), |
| 1480 | .l1clk (l1clk), |
| 1481 | .pce_ov(pce_ov), |
| 1482 | .se(se) |
| 1483 | ); |
| 1484 | |
| 1485 | /*** building tcu port ***/ |
| 1486 | assign siclk = tcu_aclk ; |
| 1487 | assign soclk = tcu_bclk ; |
| 1488 | assign pce_ov = tcu_pce_ov ; |
| 1489 | assign stop = tcu_clk_stop; |
| 1490 | // scan renames |
| 1491 | assign se = tcu_scan_en ; |
| 1492 | // end scan |
| 1493 | |
| 1494 | // fixscan start: |
| 1495 | assign stall_d1_ff_scanin = scan_in ; |
| 1496 | assign outdata_vec_ff_scanin = stall_d1_ff_scanout ; |
| 1497 | assign outdata_buf_ff_scanin = outdata_vec_ff_scanout ; |
| 1498 | assign scan_out = outdata_buf_ff_scanout ; |
| 1499 | // fixscan end: |
| 1500 | endmodule // ucb_bus_out |
| 1501 | |
| 1502 | |
| 1503 | |
| 1504 | |
| 1505 | // *********************************************** |
| 1506 | // any PARAMS parms go into naming of macro |
| 1507 | // *********************************************** |
| 1508 | |
| 1509 | module msff_width_32 ( |
| 1510 | reset, |
| 1511 | din, |
| 1512 | l1clk, |
| 1513 | scan_in, |
| 1514 | siclk, |
| 1515 | soclk, |
| 1516 | dout, |
| 1517 | scan_out); |
| 1518 | wire [31:0] fdin; |
| 1519 | wire [30:0] so; |
| 1520 | |
| 1521 | input reset; |
| 1522 | input [31:0] din; |
| 1523 | input l1clk; |
| 1524 | input scan_in; |
| 1525 | |
| 1526 | |
| 1527 | input siclk; |
| 1528 | input soclk; |
| 1529 | |
| 1530 | output [31:0] dout; |
| 1531 | output scan_out; |
| 1532 | assign fdin[31:0] = din[31:0]; |
| 1533 | |
| 1534 | |
| 1535 | /* |
| 1536 | dff #(32) d0_0 ( |
| 1537 | .l1clk(l1clk), |
| 1538 | .siclk(siclk), |
| 1539 | .soclk(soclk), |
| 1540 | .d(fdin[31:0]), |
| 1541 | .si({scan_in,so[30:0]}), |
| 1542 | .so({so[30:0],scan_out}), |
| 1543 | .q(dout[31:0]) |
| 1544 | ); |
| 1545 | |
| 1546 | */ |
| 1547 | |
| 1548 | ccu_msff_syrst_1x_32 U0 ( |
| 1549 | .reset(reset), |
| 1550 | .l1clk(l1clk), |
| 1551 | .siclk(siclk), |
| 1552 | .soclk(soclk), |
| 1553 | .d(fdin[31:0]), |
| 1554 | .si(scan_in), // .si({scan_in,so[30:0]}), |
| 1555 | .so(scan_out),// .so({so[30:0],scan_out}), |
| 1556 | .q(dout[31:0]) |
| 1557 | ); |
| 1558 | |
| 1559 | |
| 1560 | |
| 1561 | endmodule |
| 1562 | |
| 1563 | |
| 1564 | |
| 1565 | // *********************************************** |
| 1566 | // any PARAMS parms go into naming of macro |
| 1567 | // *********************************************** |
| 1568 | |
| 1569 | module msff_width_128 ( |
| 1570 | reset, |
| 1571 | din, |
| 1572 | l1clk, |
| 1573 | scan_in, |
| 1574 | siclk, |
| 1575 | soclk, |
| 1576 | dout, |
| 1577 | scan_out); |
| 1578 | wire [127:0] fdin; |
| 1579 | wire [126:0] so; |
| 1580 | |
| 1581 | input reset; |
| 1582 | input [127:0] din; |
| 1583 | input l1clk; |
| 1584 | input scan_in; |
| 1585 | |
| 1586 | |
| 1587 | input siclk; |
| 1588 | input soclk; |
| 1589 | |
| 1590 | output [127:0] dout; |
| 1591 | output scan_out; |
| 1592 | assign fdin[127:0] = din[127:0]; |
| 1593 | |
| 1594 | |
| 1595 | |
| 1596 | /* |
| 1597 | dff #(128) d0_0 ( |
| 1598 | .l1clk(l1clk), |
| 1599 | .siclk(siclk), |
| 1600 | .soclk(soclk), |
| 1601 | .d(fdin[127:0]), |
| 1602 | .si({scan_in,so[126:0]}), |
| 1603 | .so({so[126:0],scan_out}), |
| 1604 | .q(dout[127:0]) |
| 1605 | ); |
| 1606 | */ |
| 1607 | |
| 1608 | ccu_msff_syrst_1x_128 U0 ( |
| 1609 | .reset(reset), |
| 1610 | .l1clk(l1clk), |
| 1611 | .siclk(siclk), |
| 1612 | .soclk(soclk), |
| 1613 | .d(fdin[127:0]), |
| 1614 | .si(scan_in), |
| 1615 | .so(scan_out), |
| 1616 | .q(dout[127:0]) |
| 1617 | ); |
| 1618 | |
| 1619 | |
| 1620 | endmodule |
| 1621 | |
| 1622 | |