| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_clu_debug.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_clu_debug |
| 36 | ( |
| 37 | // clock |
| 38 | clk, |
| 39 | rst_l, |
| 40 | |
| 41 | // cru : debug ports |
| 42 | cl2cr_dbg_a, |
| 43 | cl2cr_dbg_b, |
| 44 | cr2cl_dbg_sel_a, |
| 45 | cr2cl_dbg_sel_b, |
| 46 | |
| 47 | // ctm : debug ports |
| 48 | ctm_dbg0_bus_a, |
| 49 | ctm_dbg0_bus_b, |
| 50 | ctm_dbg1_bus_a, |
| 51 | ctm_dbg1_bus_b, |
| 52 | |
| 53 | // crm : debug ports |
| 54 | crm_dbg0_bus_a, |
| 55 | crm_dbg0_bus_b, |
| 56 | crm_dbg1_bus_a, |
| 57 | crm_dbg1_bus_b |
| 58 | ); |
| 59 | |
| 60 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 61 | |
| 62 | // -------------------------------------------------------- |
| 63 | // Clock Signal |
| 64 | // -------------------------------------------------------- |
| 65 | |
| 66 | input clk; |
| 67 | input rst_l; |
| 68 | |
| 69 | // -------------------------------------------------------- |
| 70 | // CSR Interface |
| 71 | // -------------------------------------------------------- |
| 72 | |
| 73 | // ----- Debug Ports ----- |
| 74 | output [`FIRE_DBG_DATA_BITS] cl2cr_dbg_a; |
| 75 | output [`FIRE_DBG_DATA_BITS] cl2cr_dbg_b; |
| 76 | input [2:0] cr2cl_dbg_sel_a; |
| 77 | input [2:0] cr2cl_dbg_sel_b; |
| 78 | |
| 79 | // -------------------------------------------------------- |
| 80 | // Debug Ports Sub-block Interface |
| 81 | // -------------------------------------------------------- |
| 82 | |
| 83 | // debug: debug ports |
| 84 | input [`FIRE_DBG_DATA_BITS] ctm_dbg0_bus_a; |
| 85 | input [`FIRE_DBG_DATA_BITS] ctm_dbg0_bus_b; |
| 86 | input [`FIRE_DBG_DATA_BITS] ctm_dbg1_bus_a; |
| 87 | input [`FIRE_DBG_DATA_BITS] ctm_dbg1_bus_b; |
| 88 | input [`FIRE_DBG_DATA_BITS] crm_dbg0_bus_a; |
| 89 | input [`FIRE_DBG_DATA_BITS] crm_dbg0_bus_b; |
| 90 | input [`FIRE_DBG_DATA_BITS] crm_dbg1_bus_a; |
| 91 | input [`FIRE_DBG_DATA_BITS] crm_dbg1_bus_b; |
| 92 | |
| 93 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 94 | |
| 95 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTERS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 96 | |
| 97 | // ********** Flops ********** |
| 98 | |
| 99 | reg [`FIRE_DBG_DATA_BITS] cl2cr_dbg_a; |
| 100 | reg [`FIRE_DBG_DATA_BITS] cl2cr_dbg_b; |
| 101 | |
| 102 | // ********** Non-Flops ****** |
| 103 | |
| 104 | reg [`FIRE_DBG_DATA_BITS] nxt_dbg_bus_a; |
| 105 | reg [`FIRE_DBG_DATA_BITS] nxt_dbg_bus_b; |
| 106 | |
| 107 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 108 | |
| 109 | // -------------------------------------------------------- |
| 110 | // Debug Port Block Level Logic |
| 111 | // -------------------------------------------------------- |
| 112 | |
| 113 | // ----- sub-block debug bus select ----- |
| 114 | |
| 115 | // debug_bus_a sub-block select |
| 116 | always @(cr2cl_dbg_sel_a or ctm_dbg0_bus_a or ctm_dbg1_bus_a or |
| 117 | crm_dbg0_bus_a or crm_dbg1_bus_a) |
| 118 | begin |
| 119 | case (cr2cl_dbg_sel_a) // synopsys infer_mux |
| 120 | 3'b000: nxt_dbg_bus_a = ctm_dbg0_bus_a; |
| 121 | 3'b001: nxt_dbg_bus_a = ctm_dbg1_bus_a; |
| 122 | 3'b010: nxt_dbg_bus_a = crm_dbg0_bus_a; |
| 123 | 3'b011: nxt_dbg_bus_a = crm_dbg1_bus_a; |
| 124 | 3'b100: nxt_dbg_bus_a = 8'h0; |
| 125 | 3'b101: nxt_dbg_bus_a = 8'h0; |
| 126 | 3'b110: nxt_dbg_bus_a = 8'h0; |
| 127 | 3'b111: nxt_dbg_bus_a = 8'h0; |
| 128 | endcase |
| 129 | end |
| 130 | |
| 131 | // debug_bus_b sub-block select |
| 132 | always @(cr2cl_dbg_sel_b or ctm_dbg0_bus_b or ctm_dbg1_bus_b or |
| 133 | crm_dbg0_bus_b or crm_dbg1_bus_b) |
| 134 | begin |
| 135 | case (cr2cl_dbg_sel_b) // synopsys infer_mux |
| 136 | 3'b000: nxt_dbg_bus_b = ctm_dbg0_bus_b; |
| 137 | 3'b001: nxt_dbg_bus_b = ctm_dbg1_bus_b; |
| 138 | 3'b010: nxt_dbg_bus_b = crm_dbg0_bus_b; |
| 139 | 3'b011: nxt_dbg_bus_b = crm_dbg1_bus_b; |
| 140 | 3'b100: nxt_dbg_bus_b = 8'h0; |
| 141 | 3'b101: nxt_dbg_bus_b = 8'h0; |
| 142 | 3'b110: nxt_dbg_bus_b = 8'h0; |
| 143 | 3'b111: nxt_dbg_bus_b = 8'h0; |
| 144 | endcase |
| 145 | end |
| 146 | |
| 147 | // register debug_a/b busses |
| 148 | always @(posedge clk) |
| 149 | if (~rst_l) begin |
| 150 | cl2cr_dbg_a <= `FIRE_DEBUG_WDTH'b0; |
| 151 | cl2cr_dbg_b <= `FIRE_DEBUG_WDTH'b0; |
| 152 | end |
| 153 | else begin |
| 154 | cl2cr_dbg_a <= nxt_dbg_bus_a; |
| 155 | cl2cr_dbg_b <= nxt_dbg_bus_b; |
| 156 | end |
| 157 | |
| 158 | endmodule // dmu_clu_debug |