| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_eqs.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_eqs ( |
| 36 | |
| 37 | // Clock and Reset |
| 38 | |
| 39 | clk, |
| 40 | rst_l, |
| 41 | |
| 42 | // EQ Int signals Outputs to the ISS |
| 43 | |
| 44 | eqs2iss_eq_int_l, |
| 45 | |
| 46 | // EQ Lookup Request Inputs from the RDS |
| 47 | |
| 48 | rds2eqs_eq_sel, |
| 49 | rds2eqs_eq, |
| 50 | |
| 51 | // EQ Lookup Results to the SCS |
| 52 | |
| 53 | eqs2scs_eq_ok, |
| 54 | eqs2scs_eq_not_en, |
| 55 | |
| 56 | // EQ Lookup Address to the ORS |
| 57 | |
| 58 | eqs2ors_eq_addr, |
| 59 | eqs2ors_sel, |
| 60 | |
| 61 | // BP 7-25-06 n2 bug 118163 |
| 62 | eq_base_address_63, |
| 63 | |
| 64 | // Error Interupt |
| 65 | |
| 66 | eqs2ics_eq_over_error, |
| 67 | eqs2ics_error_data, |
| 68 | |
| 69 | |
| 70 | // CSR Bus Signals |
| 71 | |
| 72 | csrbus_valid, |
| 73 | csrbus_done, |
| 74 | csrbus_mapped, |
| 75 | csrbus_wr_data, |
| 76 | csrbus_wr, |
| 77 | csrbus_read_data, |
| 78 | csrbus_addr, |
| 79 | csrbus_src_bus, |
| 80 | csrbus_acc_vio, |
| 81 | |
| 82 | // Static ID Sel |
| 83 | |
| 84 | j2d_instance_id, |
| 85 | |
| 86 | |
| 87 | // Debug Ports |
| 88 | |
| 89 | dbg2eqs_dbg_sel_a, |
| 90 | dbg2eqs_dbg_sel_b, |
| 91 | eqs2dbg_dbg_a, |
| 92 | eqs2dbg_dbg_b |
| 93 | |
| 94 | |
| 95 | ); |
| 96 | |
| 97 | |
| 98 | //############################################################################ |
| 99 | // PORT DECLARATIONS |
| 100 | //############################################################################ |
| 101 | |
| 102 | |
| 103 | //------------------------------------------------------------------------ |
| 104 | // Clock and Reset Signals |
| 105 | //------------------------------------------------------------------------ |
| 106 | input clk; |
| 107 | input rst_l; |
| 108 | |
| 109 | //------------------------------------------------------------------------ |
| 110 | // EQ Int signals Outputs to the ISS |
| 111 | //------------------------------------------------------------------------ |
| 112 | output [35:0] eqs2iss_eq_int_l; |
| 113 | |
| 114 | //------------------------------------------------------------------------ |
| 115 | // EQ Lookup Request Inputs from the RDS |
| 116 | //------------------------------------------------------------------------ |
| 117 | input [5:0] rds2eqs_eq; |
| 118 | input rds2eqs_eq_sel; |
| 119 | |
| 120 | //------------------------------------------------------------------------ |
| 121 | // EQ Lookup Results to the SCS |
| 122 | //------------------------------------------------------------------------ |
| 123 | output eqs2scs_eq_ok; |
| 124 | output eqs2scs_eq_not_en; |
| 125 | |
| 126 | |
| 127 | //------------------------------------------------------------------------ |
| 128 | // EQ Lookup Address to the ORS |
| 129 | //------------------------------------------------------------------------ |
| 130 | |
| 131 | output [61:0] eqs2ors_eq_addr; |
| 132 | output eqs2ors_sel; |
| 133 | |
| 134 | //BP N2 bu 118163 7-24-06 |
| 135 | output eq_base_address_63; |
| 136 | |
| 137 | output eqs2ics_eq_over_error; |
| 138 | output [63:0] eqs2ics_error_data; |
| 139 | |
| 140 | //------------------------------------------------------------------------ |
| 141 | // CSR Bus Signals |
| 142 | //------------------------------------------------------------------------ |
| 143 | input csrbus_valid; |
| 144 | output csrbus_done; |
| 145 | output csrbus_mapped; |
| 146 | |
| 147 | input [`FIRE_CSR_DATA_WIDTH-1:0] csrbus_wr_data; |
| 148 | input csrbus_wr; |
| 149 | |
| 150 | output [`FIRE_CSR_DATA_WIDTH-1:0] csrbus_read_data; |
| 151 | |
| 152 | input [`FIRE_CSR_ADDR_MAX_WIDTH-1:0] csrbus_addr; |
| 153 | |
| 154 | input [`FIRE_CSR_SRC_BUS_ID_WIDTH-1:0] csrbus_src_bus; |
| 155 | output csrbus_acc_vio; |
| 156 | |
| 157 | input [`FIRE_J2D_INSTANCE_ID_WDTH-1:0] j2d_instance_id; |
| 158 | |
| 159 | //------------------------------------------------------------------------ |
| 160 | // Debug Ports |
| 161 | //------------------------------------------------------------------------ |
| 162 | |
| 163 | input [2:0] dbg2eqs_dbg_sel_a; |
| 164 | input [2:0] dbg2eqs_dbg_sel_b; |
| 165 | output [`FIRE_DEBUG_WDTH-1:0] eqs2dbg_dbg_a; |
| 166 | output [`FIRE_DEBUG_WDTH-1:0] eqs2dbg_dbg_b; |
| 167 | |
| 168 | //############################################################################ |
| 169 | // PARAMETERS |
| 170 | //############################################################################ |
| 171 | |
| 172 | //------------------------------------------------------------------------ |
| 173 | // Parameters for the Value of the FSM States |
| 174 | //------------------------------------------------------------------------ |
| 175 | parameter IDLE = 0; |
| 176 | parameter ACTIVE = 1; |
| 177 | //parameter ERROR = 3; |
| 178 | |
| 179 | //############################################################################ |
| 180 | // SIGNAL DECLARATIONS |
| 181 | //############################################################################ |
| 182 | |
| 183 | //************************************************** |
| 184 | // Wires |
| 185 | //************************************************** |
| 186 | wire eq_base_address_63; |
| 187 | |
| 188 | //------------------------------------------------------------------------ |
| 189 | // Wires for the CSR access |
| 190 | //------------------------------------------------------------------------ |
| 191 | wire ext_wr; |
| 192 | wire set_enoverr_ext_wr_data; |
| 193 | wire clr_coverr_ext_wr_data; |
| 194 | wire clr_e2i_ext_wr_data; |
| 195 | wire set_en_ext_wr_data; |
| 196 | |
| 197 | |
| 198 | //------------- |
| 199 | //HEAD POINTER |
| 200 | //------------- |
| 201 | wire [6:0] h_ptr_0, h_ptr_1, h_ptr_2, h_ptr_3, h_ptr_4, h_ptr_5, h_ptr_6, h_ptr_7; |
| 202 | wire [6:0] h_ptr_8, h_ptr_9, h_ptr_10, h_ptr_11, h_ptr_12, h_ptr_13, h_ptr_14, h_ptr_15; |
| 203 | wire [6:0] h_ptr_16, h_ptr_17, h_ptr_18, h_ptr_19, h_ptr_20, h_ptr_21, h_ptr_22, h_ptr_23; |
| 204 | wire [6:0] h_ptr_24, h_ptr_25, h_ptr_26, h_ptr_27, h_ptr_28, h_ptr_29, h_ptr_30, h_ptr_31; |
| 205 | wire [6:0] h_ptr_32, h_ptr_33, h_ptr_34, h_ptr_35; |
| 206 | |
| 207 | //------------- |
| 208 | //TAIL POINTER |
| 209 | //------------- |
| 210 | wire [6:0] t_ptr_0, t_ptr_1, t_ptr_2, t_ptr_3, t_ptr_4, t_ptr_5, t_ptr_6, t_ptr_7; |
| 211 | wire [6:0] t_ptr_8, t_ptr_9, t_ptr_10, t_ptr_11, t_ptr_12, t_ptr_13, t_ptr_14, t_ptr_15; |
| 212 | wire [6:0] t_ptr_16, t_ptr_17, t_ptr_18, t_ptr_19, t_ptr_20, t_ptr_21, t_ptr_22, t_ptr_23; |
| 213 | wire [6:0] t_ptr_24, t_ptr_25, t_ptr_26, t_ptr_27, t_ptr_28, t_ptr_29, t_ptr_30, t_ptr_31; |
| 214 | wire [6:0] t_ptr_32, t_ptr_33, t_ptr_34, t_ptr_35; |
| 215 | |
| 216 | |
| 217 | //------------------------------------------ |
| 218 | //Signals used as to indicate EQ's are OK |
| 219 | // to issue an EQ write to |
| 220 | //------------------------------------------ |
| 221 | wire eq_ok_0, eq_ok_1, eq_ok_2, eq_ok_3, eq_ok_4, eq_ok_5, eq_ok_6, eq_ok_7; |
| 222 | wire eq_ok_8, eq_ok_9, eq_ok_10, eq_ok_11, eq_ok_12, eq_ok_13, eq_ok_14, eq_ok_15; |
| 223 | wire eq_ok_16, eq_ok_17, eq_ok_18, eq_ok_19, eq_ok_20, eq_ok_21, eq_ok_22, eq_ok_23; |
| 224 | wire eq_ok_24, eq_ok_25, eq_ok_26, eq_ok_27, eq_ok_28, eq_ok_29, eq_ok_30, eq_ok_31; |
| 225 | wire eq_ok_32, eq_ok_33, eq_ok_34, eq_ok_35; |
| 226 | |
| 227 | |
| 228 | |
| 229 | //------------------------------------------ |
| 230 | // Signals used as to indicate when to set |
| 231 | // the OVER FLOW ERROR bit |
| 232 | //------------------------------------------ |
| 233 | wire load_over_err_eq_0, load_over_err_eq_1, load_over_err_eq_2, load_over_err_eq_3, load_over_err_eq_4, load_over_err_eq_5, load_over_err_eq_6, load_over_err_eq_7; |
| 234 | wire load_over_err_eq_8, load_over_err_eq_9, load_over_err_eq_10, load_over_err_eq_11, load_over_err_eq_12, load_over_err_eq_13, load_over_err_eq_14, load_over_err_eq_15; |
| 235 | wire load_over_err_eq_16, load_over_err_eq_17, load_over_err_eq_18, load_over_err_eq_19, load_over_err_eq_20, load_over_err_eq_21, load_over_err_eq_22, load_over_err_eq_23; |
| 236 | wire load_over_err_eq_24, load_over_err_eq_25, load_over_err_eq_26, load_over_err_eq_27, load_over_err_eq_28, load_over_err_eq_29, load_over_err_eq_30, load_over_err_eq_31; |
| 237 | wire load_over_err_eq_32, load_over_err_eq_33, load_over_err_eq_34, load_over_err_eq_35; |
| 238 | |
| 239 | wire set_over_err_eq_0, set_over_err_eq_1, set_over_err_eq_2, set_over_err_eq_3, set_over_err_eq_4, set_over_err_eq_5, set_over_err_eq_6, set_over_err_eq_7; |
| 240 | wire set_over_err_eq_8, set_over_err_eq_9, set_over_err_eq_10, set_over_err_eq_11, set_over_err_eq_12, set_over_err_eq_13, set_over_err_eq_14, set_over_err_eq_15; |
| 241 | wire set_over_err_eq_16, set_over_err_eq_17, set_over_err_eq_18, set_over_err_eq_19, set_over_err_eq_20, set_over_err_eq_21, set_over_err_eq_22, set_over_err_eq_23; |
| 242 | wire set_over_err_eq_24, set_over_err_eq_25, set_over_err_eq_26, set_over_err_eq_27, set_over_err_eq_28, set_over_err_eq_29, set_over_err_eq_30, set_over_err_eq_31; |
| 243 | wire set_over_err_eq_32, set_over_err_eq_33, set_over_err_eq_34, set_over_err_eq_35; |
| 244 | |
| 245 | wire data_over_err_eq_0, data_over_err_eq_1, data_over_err_eq_2, data_over_err_eq_3, data_over_err_eq_4, data_over_err_eq_5, data_over_err_eq_6, data_over_err_eq_7; |
| 246 | wire data_over_err_eq_8, data_over_err_eq_9, data_over_err_eq_10, data_over_err_eq_11, data_over_err_eq_12, data_over_err_eq_13, data_over_err_eq_14, data_over_err_eq_15; |
| 247 | wire data_over_err_eq_16, data_over_err_eq_17, data_over_err_eq_18, data_over_err_eq_19, data_over_err_eq_20, data_over_err_eq_21, data_over_err_eq_22, data_over_err_eq_23; |
| 248 | wire data_over_err_eq_24, data_over_err_eq_25, data_over_err_eq_26, data_over_err_eq_27, data_over_err_eq_28, data_over_err_eq_29, data_over_err_eq_30, data_over_err_eq_31; |
| 249 | wire data_over_err_eq_32, data_over_err_eq_33, data_over_err_eq_34, data_over_err_eq_35; |
| 250 | |
| 251 | wire hw_set_over_err_eq_0, hw_set_over_err_eq_1, hw_set_over_err_eq_2, hw_set_over_err_eq_3, hw_set_over_err_eq_4, hw_set_over_err_eq_5, hw_set_over_err_eq_6, hw_set_over_err_eq_7; |
| 252 | wire hw_set_over_err_eq_8, hw_set_over_err_eq_9, hw_set_over_err_eq_10, hw_set_over_err_eq_11, hw_set_over_err_eq_12, hw_set_over_err_eq_13, hw_set_over_err_eq_14, hw_set_over_err_eq_15; |
| 253 | wire hw_set_over_err_eq_16, hw_set_over_err_eq_17, hw_set_over_err_eq_18, hw_set_over_err_eq_19, hw_set_over_err_eq_20, hw_set_over_err_eq_21, hw_set_over_err_eq_22, hw_set_over_err_eq_23; |
| 254 | wire hw_set_over_err_eq_24, hw_set_over_err_eq_25, hw_set_over_err_eq_26, hw_set_over_err_eq_27, hw_set_over_err_eq_28, hw_set_over_err_eq_29, hw_set_over_err_eq_30, hw_set_over_err_eq_31; |
| 255 | wire hw_set_over_err_eq_32, hw_set_over_err_eq_33, hw_set_over_err_eq_34, hw_set_over_err_eq_35; |
| 256 | |
| 257 | wire sw_set_over_err_eq_0, sw_set_over_err_eq_1, sw_set_over_err_eq_2, sw_set_over_err_eq_3, sw_set_over_err_eq_4, sw_set_over_err_eq_5, sw_set_over_err_eq_6, sw_set_over_err_eq_7; |
| 258 | wire sw_set_over_err_eq_8, sw_set_over_err_eq_9, sw_set_over_err_eq_10, sw_set_over_err_eq_11, sw_set_over_err_eq_12, sw_set_over_err_eq_13, sw_set_over_err_eq_14, sw_set_over_err_eq_15; |
| 259 | wire sw_set_over_err_eq_16, sw_set_over_err_eq_17, sw_set_over_err_eq_18, sw_set_over_err_eq_19, sw_set_over_err_eq_20, sw_set_over_err_eq_21, sw_set_over_err_eq_22, sw_set_over_err_eq_23; |
| 260 | wire sw_set_over_err_eq_24, sw_set_over_err_eq_25, sw_set_over_err_eq_26, sw_set_over_err_eq_27, sw_set_over_err_eq_28, sw_set_over_err_eq_29, sw_set_over_err_eq_30, sw_set_over_err_eq_31; |
| 261 | wire sw_set_over_err_eq_32, sw_set_over_err_eq_33, sw_set_over_err_eq_34, sw_set_over_err_eq_35; |
| 262 | |
| 263 | wire sw_clr_over_err_eq_0, sw_clr_over_err_eq_1, sw_clr_over_err_eq_2, sw_clr_over_err_eq_3, sw_clr_over_err_eq_4, sw_clr_over_err_eq_5, sw_clr_over_err_eq_6, sw_clr_over_err_eq_7; |
| 264 | wire sw_clr_over_err_eq_8, sw_clr_over_err_eq_9, sw_clr_over_err_eq_10, sw_clr_over_err_eq_11, sw_clr_over_err_eq_12, sw_clr_over_err_eq_13, sw_clr_over_err_eq_14, sw_clr_over_err_eq_15; |
| 265 | wire sw_clr_over_err_eq_16, sw_clr_over_err_eq_17, sw_clr_over_err_eq_18, sw_clr_over_err_eq_19, sw_clr_over_err_eq_20, sw_clr_over_err_eq_21, sw_clr_over_err_eq_22, sw_clr_over_err_eq_23; |
| 266 | wire sw_clr_over_err_eq_24, sw_clr_over_err_eq_25, sw_clr_over_err_eq_26, sw_clr_over_err_eq_27, sw_clr_over_err_eq_28, sw_clr_over_err_eq_29, sw_clr_over_err_eq_30, sw_clr_over_err_eq_31; |
| 267 | wire sw_clr_over_err_eq_32, sw_clr_over_err_eq_33, sw_clr_over_err_eq_34, sw_clr_over_err_eq_35; |
| 268 | |
| 269 | wire sw_clr_addr_sel_eq_0, sw_clr_addr_sel_eq_1, sw_clr_addr_sel_eq_2, sw_clr_addr_sel_eq_3, sw_clr_addr_sel_eq_4, sw_clr_addr_sel_eq_5, sw_clr_addr_sel_eq_6, sw_clr_addr_sel_eq_7; |
| 270 | wire sw_clr_addr_sel_eq_8, sw_clr_addr_sel_eq_9, sw_clr_addr_sel_eq_10, sw_clr_addr_sel_eq_11, sw_clr_addr_sel_eq_12, sw_clr_addr_sel_eq_13, sw_clr_addr_sel_eq_14, sw_clr_addr_sel_eq_15; |
| 271 | wire sw_clr_addr_sel_eq_16, sw_clr_addr_sel_eq_17, sw_clr_addr_sel_eq_18, sw_clr_addr_sel_eq_19, sw_clr_addr_sel_eq_20, sw_clr_addr_sel_eq_21, sw_clr_addr_sel_eq_22, sw_clr_addr_sel_eq_23; |
| 272 | wire sw_clr_addr_sel_eq_24, sw_clr_addr_sel_eq_25, sw_clr_addr_sel_eq_26, sw_clr_addr_sel_eq_27, sw_clr_addr_sel_eq_28, sw_clr_addr_sel_eq_29, sw_clr_addr_sel_eq_30, sw_clr_addr_sel_eq_31; |
| 273 | wire sw_clr_addr_sel_eq_32, sw_clr_addr_sel_eq_33, sw_clr_addr_sel_eq_34, sw_clr_addr_sel_eq_35; |
| 274 | |
| 275 | wire sw_set_addr_sel_eq_0, sw_set_addr_sel_eq_1, sw_set_addr_sel_eq_2, sw_set_addr_sel_eq_3, sw_set_addr_sel_eq_4, sw_set_addr_sel_eq_5, sw_set_addr_sel_eq_6, sw_set_addr_sel_eq_7; |
| 276 | wire sw_set_addr_sel_eq_8, sw_set_addr_sel_eq_9, sw_set_addr_sel_eq_10, sw_set_addr_sel_eq_11, sw_set_addr_sel_eq_12, sw_set_addr_sel_eq_13, sw_set_addr_sel_eq_14, sw_set_addr_sel_eq_15; |
| 277 | wire sw_set_addr_sel_eq_16, sw_set_addr_sel_eq_17, sw_set_addr_sel_eq_18, sw_set_addr_sel_eq_19, sw_set_addr_sel_eq_20, sw_set_addr_sel_eq_21, sw_set_addr_sel_eq_22, sw_set_addr_sel_eq_23; |
| 278 | wire sw_set_addr_sel_eq_24, sw_set_addr_sel_eq_25, sw_set_addr_sel_eq_26, sw_set_addr_sel_eq_27, sw_set_addr_sel_eq_28, sw_set_addr_sel_eq_29, sw_set_addr_sel_eq_30, sw_set_addr_sel_eq_31; |
| 279 | wire sw_set_addr_sel_eq_32, sw_set_addr_sel_eq_33, sw_set_addr_sel_eq_34, sw_set_addr_sel_eq_35; |
| 280 | |
| 281 | |
| 282 | |
| 283 | //------------------------------------------ |
| 284 | //Signals used as to indicate EQ's are full |
| 285 | //------------------------------------------ |
| 286 | wire full_eq_0, full_eq_1, full_eq_2, full_eq_3, full_eq_4, full_eq_5, full_eq_6, full_eq_7; |
| 287 | wire full_eq_8, full_eq_9, full_eq_10, full_eq_11, full_eq_12, full_eq_13, full_eq_14, full_eq_15; |
| 288 | wire full_eq_16, full_eq_17, full_eq_18, full_eq_19, full_eq_20, full_eq_21, full_eq_22, full_eq_23; |
| 289 | wire full_eq_24, full_eq_25, full_eq_26, full_eq_27, full_eq_28, full_eq_29, full_eq_30, full_eq_31; |
| 290 | wire full_eq_32, full_eq_33, full_eq_34, full_eq_35; |
| 291 | |
| 292 | |
| 293 | //-------------------------------------------------- |
| 294 | //Signals used for Incrementing Tail Pointers |
| 295 | //--------------------------------------------------- |
| 296 | |
| 297 | wire [6:0] t_ptr_inc_0, t_ptr_inc_1, t_ptr_inc_2, t_ptr_inc_3, t_ptr_inc_4, t_ptr_inc_5, t_ptr_inc_6, t_ptr_inc_7; |
| 298 | wire [6:0] t_ptr_inc_8, t_ptr_inc_9, t_ptr_inc_10, t_ptr_inc_11, t_ptr_inc_12, t_ptr_inc_13, t_ptr_inc_14, t_ptr_inc_15; |
| 299 | wire [6:0] t_ptr_inc_16, t_ptr_inc_17, t_ptr_inc_18, t_ptr_inc_19, t_ptr_inc_20, t_ptr_inc_21, t_ptr_inc_22, t_ptr_inc_23; |
| 300 | wire [6:0] t_ptr_inc_24, t_ptr_inc_25, t_ptr_inc_26, t_ptr_inc_27, t_ptr_inc_28, t_ptr_inc_29, t_ptr_inc_30, t_ptr_inc_31; |
| 301 | wire [6:0] t_ptr_inc_32, t_ptr_inc_33, t_ptr_inc_34, t_ptr_inc_35; |
| 302 | |
| 303 | wire t_ptr_inc_sel_0, t_ptr_inc_sel_1, t_ptr_inc_sel_2, t_ptr_inc_sel_3, t_ptr_inc_sel_4, t_ptr_inc_sel_5, t_ptr_inc_sel_6, t_ptr_inc_sel_7; |
| 304 | wire t_ptr_inc_sel_8, t_ptr_inc_sel_9, t_ptr_inc_sel_10, t_ptr_inc_sel_11, t_ptr_inc_sel_12, t_ptr_inc_sel_13, t_ptr_inc_sel_14, t_ptr_inc_sel_15; |
| 305 | wire t_ptr_inc_sel_16, t_ptr_inc_sel_17, t_ptr_inc_sel_18, t_ptr_inc_sel_19, t_ptr_inc_sel_20, t_ptr_inc_sel_21, t_ptr_inc_sel_22, t_ptr_inc_sel_23; |
| 306 | wire t_ptr_inc_sel_24, t_ptr_inc_sel_25, t_ptr_inc_sel_26, t_ptr_inc_sel_27, t_ptr_inc_sel_28, t_ptr_inc_sel_29, t_ptr_inc_sel_30, t_ptr_inc_sel_31; |
| 307 | wire t_ptr_inc_sel_32, t_ptr_inc_sel_33, t_ptr_inc_sel_34, t_ptr_inc_sel_35; |
| 308 | |
| 309 | |
| 310 | //------------------------------------------ |
| 311 | //Signals used as to indicate when each EQ |
| 312 | // has been selected to be sent for a write |
| 313 | //------------------------------------------ |
| 314 | |
| 315 | wire eq_num_sel_0, eq_num_sel_1, eq_num_sel_2, eq_num_sel_3, eq_num_sel_4, eq_num_sel_5, eq_num_sel_6, eq_num_sel_7; |
| 316 | wire eq_num_sel_8, eq_num_sel_9, eq_num_sel_10, eq_num_sel_11, eq_num_sel_12, eq_num_sel_13, eq_num_sel_14, eq_num_sel_15; |
| 317 | wire eq_num_sel_16, eq_num_sel_17, eq_num_sel_18, eq_num_sel_19, eq_num_sel_20, eq_num_sel_21, eq_num_sel_22, eq_num_sel_23; |
| 318 | wire eq_num_sel_24, eq_num_sel_25, eq_num_sel_26, eq_num_sel_27, eq_num_sel_28, eq_num_sel_29, eq_num_sel_30, eq_num_sel_31; |
| 319 | wire eq_num_sel_32, eq_num_sel_33, eq_num_sel_34, eq_num_sel_35; |
| 320 | |
| 321 | //------------------------- |
| 322 | // Eq State (One Hot) |
| 323 | // [2] -- Error State |
| 324 | // [1] -- Active State |
| 325 | // [0] -- Idle State |
| 326 | //------------------------- |
| 327 | |
| 328 | wire [2:0] eq_state_0, eq_state_1, eq_state_2, eq_state_3, eq_state_4, eq_state_5, eq_state_6, eq_state_7; |
| 329 | wire [2:0] eq_state_8, eq_state_9, eq_state_10, eq_state_11, eq_state_12, eq_state_13, eq_state_14, eq_state_15; |
| 330 | wire [2:0] eq_state_16, eq_state_17, eq_state_18, eq_state_19, eq_state_20, eq_state_21, eq_state_22, eq_state_23; |
| 331 | wire [2:0] eq_state_24, eq_state_25, eq_state_26, eq_state_27, eq_state_28, eq_state_29, eq_state_30, eq_state_31; |
| 332 | wire [2:0] eq_state_32, eq_state_33, eq_state_34, eq_state_35; |
| 333 | |
| 334 | |
| 335 | //------------------------------------------------------------- |
| 336 | // Wires used to indicated EQ requires a Mondo to be generated |
| 337 | //------------------------------------------------------------- |
| 338 | wire [35:0] hw_mondo_trig; |
| 339 | |
| 340 | //------------------------------------------------------------- |
| 341 | // Wires used to For EQ base address |
| 342 | //------------------------------------------------------------- |
| 343 | wire [44:0] eq_base_address; |
| 344 | |
| 345 | //------------------------------------------------------------- |
| 346 | // Wire for Exteranl write data |
| 347 | //------------------------------------------------------------- |
| 348 | wire eq_fsm_wr; |
| 349 | wire [1:0] eq_fsm_wr_data; |
| 350 | |
| 351 | |
| 352 | //************************************************** |
| 353 | // Registers that Are Not Flops |
| 354 | //************************************************** |
| 355 | reg [6:0] eq_address_mux; |
| 356 | reg eq_ok_mux; |
| 357 | reg eq_state_mux; |
| 358 | reg [`FIRE_DEBUG_WDTH-1:0] n_dbg_a; |
| 359 | reg [`FIRE_DEBUG_WDTH-1:0] n_dbg_b; |
| 360 | |
| 361 | |
| 362 | //************************************************** |
| 363 | // Registers that Are Flops |
| 364 | //************************************************** |
| 365 | |
| 366 | reg [61:0] eqs2ors_eq_addr; |
| 367 | reg eqs2ors_sel; |
| 368 | reg [35:0] eqs2iss_eq_int_l; |
| 369 | reg [`FIRE_DEBUG_WDTH-1:0] dbg_a; |
| 370 | reg [`FIRE_DEBUG_WDTH-1:0] dbg_b; |
| 371 | |
| 372 | //############################################################################ |
| 373 | // ZERO IN CHECKERS |
| 374 | //############################################################################ |
| 375 | //-------------------------------- |
| 376 | // Make sure EQ is never over 35 |
| 377 | //-------------------------------- |
| 378 | |
| 379 | //0in maximum -var rds2eqs_eq -val 35 |
| 380 | |
| 381 | //---------------------------------- |
| 382 | // Make sure EQ is decoded properly |
| 383 | //---------------------------------- |
| 384 | |
| 385 | |
| 386 | /* 0in decoder -in rds2eqs_eq |
| 387 | -out {28'h0, |
| 388 | eq_num_sel_35, eq_num_sel_34, eq_num_sel_33, eq_num_sel_32, eq_num_sel_31, eq_num_sel_30, |
| 389 | eq_num_sel_29, eq_num_sel_28, eq_num_sel_27, eq_num_sel_26, eq_num_sel_25, eq_num_sel_24, |
| 390 | eq_num_sel_23, eq_num_sel_22, eq_num_sel_21, eq_num_sel_20, eq_num_sel_19, eq_num_sel_18, |
| 391 | eq_num_sel_17, eq_num_sel_16, eq_num_sel_15, eq_num_sel_14, eq_num_sel_13, eq_num_sel_12, |
| 392 | eq_num_sel_11, eq_num_sel_10, eq_num_sel_9, eq_num_sel_8, eq_num_sel_7, eq_num_sel_6, |
| 393 | eq_num_sel_5, eq_num_sel_4, eq_num_sel_3, eq_num_sel_2, eq_num_sel_1, eq_num_sel_0 |
| 394 | } |
| 395 | |
| 396 | */ |
| 397 | |
| 398 | //--------------------------------------- |
| 399 | // Make sure only 1 EQ selected at a time |
| 400 | //--------------------------------------- |
| 401 | |
| 402 | /*0in bits_on -var {eq_num_sel_35, eq_num_sel_34, eq_num_sel_33, eq_num_sel_32, eq_num_sel_31, eq_num_sel_30, |
| 403 | eq_num_sel_29, eq_num_sel_28, eq_num_sel_27, eq_num_sel_26, eq_num_sel_25, eq_num_sel_24, |
| 404 | eq_num_sel_23, eq_num_sel_22, eq_num_sel_21, eq_num_sel_20, eq_num_sel_19, eq_num_sel_18, |
| 405 | eq_num_sel_17, eq_num_sel_16, eq_num_sel_15, eq_num_sel_14, eq_num_sel_13, eq_num_sel_12, |
| 406 | eq_num_sel_11, eq_num_sel_10, eq_num_sel_9, eq_num_sel_8, eq_num_sel_7, eq_num_sel_6, |
| 407 | eq_num_sel_5, eq_num_sel_4, eq_num_sel_3, eq_num_sel_2, eq_num_sel_1, eq_num_sel_0 |
| 408 | } |
| 409 | -max 1 |
| 410 | */ |
| 411 | |
| 412 | //############################################################################ |
| 413 | // COMBINATIONAL LOGIC |
| 414 | //############################################################################ |
| 415 | |
| 416 | |
| 417 | //------------------------------------------------------- |
| 418 | // Assigning the external signals from DCM to names for FSM's |
| 419 | //------------------------------------------------------- |
| 420 | assign eq_fsm_wr = ext_wr; |
| 421 | assign eq_fsm_wr_data = {clr_e2i_ext_wr_data,set_en_ext_wr_data}; // The en/dis bit and the e2i bit |
| 422 | |
| 423 | |
| 424 | //------------------------------------------------------- |
| 425 | // Decode the EQ that is comming in |
| 426 | // |
| 427 | // The EQ number comming in is a 6 bit encoded value |
| 428 | // the logic below makes it in to a 1 of 36 select |
| 429 | //------------------------------------------------------- |
| 430 | |
| 431 | assign eq_num_sel_0 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 432 | assign eq_num_sel_1 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 433 | assign eq_num_sel_2 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & (rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 434 | assign eq_num_sel_3 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & (rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 435 | assign eq_num_sel_4 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & (rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 436 | assign eq_num_sel_5 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & (rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 437 | assign eq_num_sel_6 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & (rds2eqs_eq[2]) & (rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 438 | assign eq_num_sel_7 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & (rds2eqs_eq[2]) & (rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 439 | assign eq_num_sel_8 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & (rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 440 | assign eq_num_sel_9 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & (rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 441 | assign eq_num_sel_10 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & (rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & (rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 442 | assign eq_num_sel_11 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & (rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & (rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 443 | assign eq_num_sel_12 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & (rds2eqs_eq[3]) & (rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 444 | assign eq_num_sel_13 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & (rds2eqs_eq[3]) & (rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 445 | assign eq_num_sel_14 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & (rds2eqs_eq[3]) & (rds2eqs_eq[2]) & (rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 446 | assign eq_num_sel_15 = ~(rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & (rds2eqs_eq[3]) & (rds2eqs_eq[2]) & (rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 447 | assign eq_num_sel_16 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 448 | assign eq_num_sel_17 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 449 | assign eq_num_sel_18 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & (rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 450 | assign eq_num_sel_19 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & (rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 451 | assign eq_num_sel_20 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & (rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 452 | assign eq_num_sel_21 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & (rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 453 | assign eq_num_sel_22 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & (rds2eqs_eq[2]) & (rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 454 | assign eq_num_sel_23 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & (rds2eqs_eq[2]) & (rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 455 | assign eq_num_sel_24 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & (rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 456 | assign eq_num_sel_25 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & (rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 457 | assign eq_num_sel_26 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & (rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & (rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 458 | assign eq_num_sel_27 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & (rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & (rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 459 | assign eq_num_sel_28 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & (rds2eqs_eq[3]) & (rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 460 | assign eq_num_sel_29 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & (rds2eqs_eq[3]) & (rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 461 | assign eq_num_sel_30 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & (rds2eqs_eq[3]) & (rds2eqs_eq[2]) & (rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 462 | assign eq_num_sel_31 = ~(rds2eqs_eq[5]) & (rds2eqs_eq[4]) & (rds2eqs_eq[3]) & (rds2eqs_eq[2]) & (rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 463 | assign eq_num_sel_32 = (rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 464 | assign eq_num_sel_33 = (rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & ~(rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 465 | assign eq_num_sel_34 = (rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & (rds2eqs_eq[1]) & ~(rds2eqs_eq[0]); |
| 466 | assign eq_num_sel_35 = (rds2eqs_eq[5]) & ~(rds2eqs_eq[4]) & ~(rds2eqs_eq[3]) & ~(rds2eqs_eq[2]) & (rds2eqs_eq[1]) & (rds2eqs_eq[0]); |
| 467 | |
| 468 | |
| 469 | //----------------------------------------------------------------------------- |
| 470 | // Mux the results of the adders using rds2eqs_eq as the select to select which of |
| 471 | // the 32 EQ's the write is for |
| 472 | //----------------------------------------------------------------------------- |
| 473 | |
| 474 | always @ (t_ptr_0 or t_ptr_1 or t_ptr_2 or t_ptr_3 or t_ptr_4 or t_ptr_5 or t_ptr_6 or t_ptr_7 or |
| 475 | t_ptr_8 or t_ptr_9 or t_ptr_10 or t_ptr_11 or t_ptr_12 or t_ptr_13 or t_ptr_14 or t_ptr_15 or |
| 476 | t_ptr_16 or t_ptr_17 or t_ptr_18 or t_ptr_19 or t_ptr_20 or t_ptr_21 or t_ptr_22 or t_ptr_23 or t_ptr_24 or |
| 477 | t_ptr_25 or t_ptr_26 or t_ptr_27 or t_ptr_28 or t_ptr_29 or t_ptr_30 or t_ptr_31 or t_ptr_32 or t_ptr_33 or |
| 478 | t_ptr_34 or t_ptr_35 or rds2eqs_eq) |
| 479 | |
| 480 | case (rds2eqs_eq) // synopsys parallel_case full_case infer_mux |
| 481 | 6'b000000 : eq_address_mux = t_ptr_0; |
| 482 | 6'b000001 : eq_address_mux = t_ptr_1; |
| 483 | 6'b000010 : eq_address_mux = t_ptr_2; |
| 484 | 6'b000011 : eq_address_mux = t_ptr_3; |
| 485 | 6'b000100 : eq_address_mux = t_ptr_4; |
| 486 | 6'b000101 : eq_address_mux = t_ptr_5; |
| 487 | 6'b000110 : eq_address_mux = t_ptr_6; |
| 488 | 6'b000111 : eq_address_mux = t_ptr_7; |
| 489 | |
| 490 | 6'b001000 : eq_address_mux = t_ptr_8; |
| 491 | 6'b001001 : eq_address_mux = t_ptr_9; |
| 492 | 6'b001010 : eq_address_mux = t_ptr_10; |
| 493 | 6'b001011 : eq_address_mux = t_ptr_11; |
| 494 | 6'b001100 : eq_address_mux = t_ptr_12; |
| 495 | 6'b001101 : eq_address_mux = t_ptr_13; |
| 496 | 6'b001110 : eq_address_mux = t_ptr_14; |
| 497 | 6'b001111 : eq_address_mux = t_ptr_15; |
| 498 | |
| 499 | 6'b010000 : eq_address_mux = t_ptr_16; |
| 500 | 6'b010001 : eq_address_mux = t_ptr_17; |
| 501 | 6'b010010 : eq_address_mux = t_ptr_18; |
| 502 | 6'b010011 : eq_address_mux = t_ptr_19; |
| 503 | 6'b010100 : eq_address_mux = t_ptr_20; |
| 504 | 6'b010101 : eq_address_mux = t_ptr_21; |
| 505 | 6'b010110 : eq_address_mux = t_ptr_22; |
| 506 | 6'b010111 : eq_address_mux = t_ptr_23; |
| 507 | |
| 508 | 6'b011000 : eq_address_mux = t_ptr_24; |
| 509 | 6'b011001 : eq_address_mux = t_ptr_25; |
| 510 | 6'b011010 : eq_address_mux = t_ptr_26; |
| 511 | 6'b011011 : eq_address_mux = t_ptr_27; |
| 512 | 6'b011100 : eq_address_mux = t_ptr_28; |
| 513 | 6'b011101 : eq_address_mux = t_ptr_29; |
| 514 | 6'b011110 : eq_address_mux = t_ptr_30; |
| 515 | 6'b011111 : eq_address_mux = t_ptr_31; |
| 516 | |
| 517 | 6'b100000 : eq_address_mux = t_ptr_32; |
| 518 | 6'b100001 : eq_address_mux = t_ptr_33; |
| 519 | 6'b100010 : eq_address_mux = t_ptr_34; |
| 520 | 6'b100011 : eq_address_mux = t_ptr_35; |
| 521 | endcase |
| 522 | |
| 523 | |
| 524 | |
| 525 | |
| 526 | //-------------------------------------------------------------------------------- |
| 527 | // Need to notify software when there are items in the EQ which need to be processed |
| 528 | // |
| 529 | // Since when the tail pointer equals the head pointer the EQ is empty |
| 530 | // when they are not equal it is safe to say that there are entries in the EQ |
| 531 | // |
| 532 | // When this happen we need to notify software so that they may processes these |
| 533 | // entries. We also only notify software when we are in the active state. |
| 534 | // |
| 535 | //------------------------------------------------------------------------------- |
| 536 | |
| 537 | assign hw_mondo_trig[0] = (t_ptr_0 != h_ptr_0) & eq_state_0[ACTIVE]; |
| 538 | assign hw_mondo_trig[1] = (t_ptr_1 != h_ptr_1) & eq_state_1[ACTIVE]; |
| 539 | assign hw_mondo_trig[2] = (t_ptr_2 != h_ptr_2) & eq_state_2[ACTIVE]; |
| 540 | assign hw_mondo_trig[3] = (t_ptr_3 != h_ptr_3) & eq_state_3[ACTIVE]; |
| 541 | assign hw_mondo_trig[4] = (t_ptr_4 != h_ptr_4) & eq_state_4[ACTIVE]; |
| 542 | assign hw_mondo_trig[5] = (t_ptr_5 != h_ptr_5) & eq_state_5[ACTIVE]; |
| 543 | assign hw_mondo_trig[6] = (t_ptr_6 != h_ptr_6) & eq_state_6[ACTIVE]; |
| 544 | assign hw_mondo_trig[7] = (t_ptr_7 != h_ptr_7) & eq_state_7[ACTIVE]; |
| 545 | assign hw_mondo_trig[8] = (t_ptr_8 != h_ptr_8) & eq_state_8[ACTIVE]; |
| 546 | assign hw_mondo_trig[9] = (t_ptr_9 != h_ptr_9) & eq_state_9[ACTIVE]; |
| 547 | assign hw_mondo_trig[10] = (t_ptr_10 != h_ptr_10) & eq_state_10[ACTIVE]; |
| 548 | assign hw_mondo_trig[11] = (t_ptr_11 != h_ptr_11) & eq_state_11[ACTIVE]; |
| 549 | assign hw_mondo_trig[12] = (t_ptr_12 != h_ptr_12) & eq_state_12[ACTIVE]; |
| 550 | assign hw_mondo_trig[13] = (t_ptr_13 != h_ptr_13) & eq_state_13[ACTIVE]; |
| 551 | assign hw_mondo_trig[14] = (t_ptr_14 != h_ptr_14) & eq_state_14[ACTIVE]; |
| 552 | assign hw_mondo_trig[15] = (t_ptr_15 != h_ptr_15) & eq_state_15[ACTIVE]; |
| 553 | assign hw_mondo_trig[16] = (t_ptr_16 != h_ptr_16) & eq_state_16[ACTIVE]; |
| 554 | assign hw_mondo_trig[17] = (t_ptr_17 != h_ptr_17) & eq_state_17[ACTIVE]; |
| 555 | assign hw_mondo_trig[18] = (t_ptr_18 != h_ptr_18) & eq_state_18[ACTIVE]; |
| 556 | assign hw_mondo_trig[19] = (t_ptr_19 != h_ptr_19) & eq_state_19[ACTIVE]; |
| 557 | assign hw_mondo_trig[20] = (t_ptr_20 != h_ptr_20) & eq_state_20[ACTIVE]; |
| 558 | assign hw_mondo_trig[21] = (t_ptr_21 != h_ptr_21) & eq_state_21[ACTIVE]; |
| 559 | assign hw_mondo_trig[22] = (t_ptr_22 != h_ptr_22) & eq_state_22[ACTIVE]; |
| 560 | assign hw_mondo_trig[23] = (t_ptr_23 != h_ptr_23) & eq_state_23[ACTIVE]; |
| 561 | assign hw_mondo_trig[24] = (t_ptr_24 != h_ptr_24) & eq_state_24[ACTIVE]; |
| 562 | assign hw_mondo_trig[25] = (t_ptr_25 != h_ptr_25) & eq_state_25[ACTIVE]; |
| 563 | assign hw_mondo_trig[26] = (t_ptr_26 != h_ptr_26) & eq_state_26[ACTIVE]; |
| 564 | assign hw_mondo_trig[27] = (t_ptr_27 != h_ptr_27) & eq_state_27[ACTIVE]; |
| 565 | assign hw_mondo_trig[28] = (t_ptr_28 != h_ptr_28) & eq_state_28[ACTIVE]; |
| 566 | assign hw_mondo_trig[29] = (t_ptr_29 != h_ptr_29) & eq_state_29[ACTIVE]; |
| 567 | assign hw_mondo_trig[30] = (t_ptr_30 != h_ptr_30) & eq_state_30[ACTIVE]; |
| 568 | assign hw_mondo_trig[31] = (t_ptr_31 != h_ptr_31) & eq_state_31[ACTIVE]; |
| 569 | assign hw_mondo_trig[32] = (t_ptr_32 != h_ptr_32) & eq_state_32[ACTIVE]; |
| 570 | assign hw_mondo_trig[33] = (t_ptr_33 != h_ptr_33) & eq_state_33[ACTIVE]; |
| 571 | assign hw_mondo_trig[34] = (t_ptr_34 != h_ptr_34) & eq_state_34[ACTIVE]; |
| 572 | assign hw_mondo_trig[35] = (t_ptr_35 != h_ptr_35) & eq_state_35[ACTIVE]; |
| 573 | |
| 574 | |
| 575 | |
| 576 | //************************ |
| 577 | // EQ FULL DETECTION |
| 578 | //************************ |
| 579 | |
| 580 | //----------------------------------------------------------------------------- |
| 581 | // Increment the tail pointers |
| 582 | // We do the addition prior to any request |
| 583 | // |
| 584 | //----------------------------------------------------------------------------- |
| 585 | assign t_ptr_inc_0 = t_ptr_0 + 1; |
| 586 | assign t_ptr_inc_1 = t_ptr_1 + 1; |
| 587 | assign t_ptr_inc_2 = t_ptr_2 + 1; |
| 588 | assign t_ptr_inc_3 = t_ptr_3 + 1; |
| 589 | assign t_ptr_inc_4 = t_ptr_4 + 1; |
| 590 | assign t_ptr_inc_5 = t_ptr_5 + 1; |
| 591 | assign t_ptr_inc_6 = t_ptr_6 + 1; |
| 592 | assign t_ptr_inc_7 = t_ptr_7 + 1; |
| 593 | assign t_ptr_inc_8 = t_ptr_8 + 1; |
| 594 | assign t_ptr_inc_9 = t_ptr_9 + 1; |
| 595 | assign t_ptr_inc_10 = t_ptr_10 + 1; |
| 596 | assign t_ptr_inc_11 = t_ptr_11 + 1; |
| 597 | assign t_ptr_inc_12 = t_ptr_12 + 1; |
| 598 | assign t_ptr_inc_13 = t_ptr_13 + 1; |
| 599 | assign t_ptr_inc_14 = t_ptr_14 + 1; |
| 600 | assign t_ptr_inc_15 = t_ptr_15 + 1; |
| 601 | assign t_ptr_inc_16 = t_ptr_16 + 1; |
| 602 | assign t_ptr_inc_17 = t_ptr_17 + 1; |
| 603 | assign t_ptr_inc_18 = t_ptr_18 + 1; |
| 604 | assign t_ptr_inc_19 = t_ptr_19 + 1; |
| 605 | assign t_ptr_inc_20 = t_ptr_20 + 1; |
| 606 | assign t_ptr_inc_21 = t_ptr_21 + 1; |
| 607 | assign t_ptr_inc_22 = t_ptr_22 + 1; |
| 608 | assign t_ptr_inc_23 = t_ptr_23 + 1; |
| 609 | assign t_ptr_inc_24 = t_ptr_24 + 1; |
| 610 | assign t_ptr_inc_25 = t_ptr_25 + 1; |
| 611 | assign t_ptr_inc_26 = t_ptr_26 + 1; |
| 612 | assign t_ptr_inc_27 = t_ptr_27 + 1; |
| 613 | assign t_ptr_inc_28 = t_ptr_28 + 1; |
| 614 | assign t_ptr_inc_29 = t_ptr_29 + 1; |
| 615 | assign t_ptr_inc_30 = t_ptr_30 + 1; |
| 616 | assign t_ptr_inc_31 = t_ptr_31 + 1; |
| 617 | assign t_ptr_inc_32 = t_ptr_32 + 1; |
| 618 | assign t_ptr_inc_33 = t_ptr_33 + 1; |
| 619 | assign t_ptr_inc_34 = t_ptr_34 + 1; |
| 620 | assign t_ptr_inc_35 = t_ptr_35 + 1; |
| 621 | |
| 622 | //----------------------------------------------------------------------------- |
| 623 | // Now determine if the EQ is Full and can't accept anymore writes |
| 624 | // |
| 625 | // Check if Full If head = tail +1 it is |
| 626 | //----------------------------------------------------------------------------- |
| 627 | |
| 628 | assign full_eq_0 = t_ptr_inc_0 == h_ptr_0; |
| 629 | assign full_eq_1 = t_ptr_inc_1 == h_ptr_1; |
| 630 | assign full_eq_2 = t_ptr_inc_2 == h_ptr_2; |
| 631 | assign full_eq_3 = t_ptr_inc_3 == h_ptr_3; |
| 632 | assign full_eq_4 = t_ptr_inc_4 == h_ptr_4; |
| 633 | assign full_eq_5 = t_ptr_inc_5 == h_ptr_5; |
| 634 | assign full_eq_6 = t_ptr_inc_6 == h_ptr_6; |
| 635 | assign full_eq_7 = t_ptr_inc_7 == h_ptr_7; |
| 636 | assign full_eq_8 = t_ptr_inc_8 == h_ptr_8; |
| 637 | assign full_eq_9 = t_ptr_inc_9 == h_ptr_9; |
| 638 | assign full_eq_10 = t_ptr_inc_10 == h_ptr_10; |
| 639 | assign full_eq_11 = t_ptr_inc_11 == h_ptr_11; |
| 640 | assign full_eq_12 = t_ptr_inc_12 == h_ptr_12; |
| 641 | assign full_eq_13 = t_ptr_inc_13 == h_ptr_13; |
| 642 | assign full_eq_14 = t_ptr_inc_14 == h_ptr_14; |
| 643 | assign full_eq_15 = t_ptr_inc_15 == h_ptr_15; |
| 644 | assign full_eq_16 = t_ptr_inc_16 == h_ptr_16; |
| 645 | assign full_eq_17 = t_ptr_inc_17 == h_ptr_17; |
| 646 | assign full_eq_18 = t_ptr_inc_18 == h_ptr_18; |
| 647 | assign full_eq_19 = t_ptr_inc_19 == h_ptr_19; |
| 648 | assign full_eq_20 = t_ptr_inc_20 == h_ptr_20; |
| 649 | assign full_eq_21 = t_ptr_inc_21 == h_ptr_21; |
| 650 | assign full_eq_22 = t_ptr_inc_22 == h_ptr_22; |
| 651 | assign full_eq_23 = t_ptr_inc_23 == h_ptr_23; |
| 652 | assign full_eq_24 = t_ptr_inc_24 == h_ptr_24; |
| 653 | assign full_eq_25 = t_ptr_inc_25 == h_ptr_25; |
| 654 | assign full_eq_26 = t_ptr_inc_26 == h_ptr_26; |
| 655 | assign full_eq_27 = t_ptr_inc_27 == h_ptr_27; |
| 656 | assign full_eq_28 = t_ptr_inc_28 == h_ptr_28; |
| 657 | assign full_eq_29 = t_ptr_inc_29 == h_ptr_29; |
| 658 | assign full_eq_30 = t_ptr_inc_30 == h_ptr_30; |
| 659 | assign full_eq_31 = t_ptr_inc_31 == h_ptr_31; |
| 660 | assign full_eq_32 = t_ptr_inc_32 == h_ptr_32; |
| 661 | assign full_eq_33 = t_ptr_inc_33 == h_ptr_33; |
| 662 | assign full_eq_34 = t_ptr_inc_34 == h_ptr_34; |
| 663 | assign full_eq_35 = t_ptr_inc_35 == h_ptr_35; |
| 664 | |
| 665 | |
| 666 | //************************ |
| 667 | // EQ OVER FLOW DETECTION |
| 668 | //************************ |
| 669 | |
| 670 | //----------------------------------------------------------------------------- |
| 671 | // HW Overflow detection |
| 672 | // |
| 673 | // If full, and a new write comes in and the EQ is in the ACTIVE state. |
| 674 | // |
| 675 | // This signal is used to determine: |
| 676 | // - as part of when to load the EQ overflow error bit (setting it to 1) |
| 677 | // - Input into fsm to change from ACTIVE to ERROR |
| 678 | // |
| 679 | // |
| 680 | // NOTE - eq_state_* variable is not needed here and may be able to be |
| 681 | // removed later if needed to make timing . This can be done since |
| 682 | // this signal is only used by the FSM in the ACTIVE STATE |
| 683 | //----------------------------------------------------------------------------- |
| 684 | |
| 685 | assign hw_set_over_err_eq_0 = rds2eqs_eq_sel & eq_num_sel_0 & full_eq_0 & eq_state_0[ACTIVE]; |
| 686 | assign hw_set_over_err_eq_1 = rds2eqs_eq_sel & eq_num_sel_1 & full_eq_1 & eq_state_1[ACTIVE]; |
| 687 | assign hw_set_over_err_eq_2 = rds2eqs_eq_sel & eq_num_sel_2 & full_eq_2 & eq_state_2[ACTIVE]; |
| 688 | assign hw_set_over_err_eq_3 = rds2eqs_eq_sel & eq_num_sel_3 & full_eq_3 & eq_state_3[ACTIVE]; |
| 689 | assign hw_set_over_err_eq_4 = rds2eqs_eq_sel & eq_num_sel_4 & full_eq_4 & eq_state_4[ACTIVE]; |
| 690 | assign hw_set_over_err_eq_5 = rds2eqs_eq_sel & eq_num_sel_5 & full_eq_5 & eq_state_5[ACTIVE]; |
| 691 | assign hw_set_over_err_eq_6 = rds2eqs_eq_sel & eq_num_sel_6 & full_eq_6 & eq_state_6[ACTIVE]; |
| 692 | assign hw_set_over_err_eq_7 = rds2eqs_eq_sel & eq_num_sel_7 & full_eq_7 & eq_state_7[ACTIVE]; |
| 693 | assign hw_set_over_err_eq_8 = rds2eqs_eq_sel & eq_num_sel_8 & full_eq_8 & eq_state_8[ACTIVE]; |
| 694 | assign hw_set_over_err_eq_9 = rds2eqs_eq_sel & eq_num_sel_9 & full_eq_9 & eq_state_9[ACTIVE]; |
| 695 | assign hw_set_over_err_eq_10 = rds2eqs_eq_sel & eq_num_sel_10 & full_eq_10 & eq_state_10[ACTIVE]; |
| 696 | assign hw_set_over_err_eq_11 = rds2eqs_eq_sel & eq_num_sel_11 & full_eq_11 & eq_state_11[ACTIVE]; |
| 697 | assign hw_set_over_err_eq_12 = rds2eqs_eq_sel & eq_num_sel_12 & full_eq_12 & eq_state_12[ACTIVE]; |
| 698 | assign hw_set_over_err_eq_13 = rds2eqs_eq_sel & eq_num_sel_13 & full_eq_13 & eq_state_13[ACTIVE]; |
| 699 | assign hw_set_over_err_eq_14 = rds2eqs_eq_sel & eq_num_sel_14 & full_eq_14 & eq_state_14[ACTIVE]; |
| 700 | assign hw_set_over_err_eq_15 = rds2eqs_eq_sel & eq_num_sel_15 & full_eq_15 & eq_state_15[ACTIVE]; |
| 701 | assign hw_set_over_err_eq_16 = rds2eqs_eq_sel & eq_num_sel_16 & full_eq_16 & eq_state_16[ACTIVE]; |
| 702 | assign hw_set_over_err_eq_17 = rds2eqs_eq_sel & eq_num_sel_17 & full_eq_17 & eq_state_17[ACTIVE]; |
| 703 | assign hw_set_over_err_eq_18 = rds2eqs_eq_sel & eq_num_sel_18 & full_eq_18 & eq_state_18[ACTIVE]; |
| 704 | assign hw_set_over_err_eq_19 = rds2eqs_eq_sel & eq_num_sel_19 & full_eq_19 & eq_state_19[ACTIVE]; |
| 705 | assign hw_set_over_err_eq_20 = rds2eqs_eq_sel & eq_num_sel_20 & full_eq_20 & eq_state_20[ACTIVE]; |
| 706 | assign hw_set_over_err_eq_21 = rds2eqs_eq_sel & eq_num_sel_21 & full_eq_21 & eq_state_21[ACTIVE]; |
| 707 | assign hw_set_over_err_eq_22 = rds2eqs_eq_sel & eq_num_sel_22 & full_eq_22 & eq_state_22[ACTIVE]; |
| 708 | assign hw_set_over_err_eq_23 = rds2eqs_eq_sel & eq_num_sel_23 & full_eq_23 & eq_state_23[ACTIVE]; |
| 709 | assign hw_set_over_err_eq_24 = rds2eqs_eq_sel & eq_num_sel_24 & full_eq_24 & eq_state_24[ACTIVE]; |
| 710 | assign hw_set_over_err_eq_25 = rds2eqs_eq_sel & eq_num_sel_25 & full_eq_25 & eq_state_25[ACTIVE]; |
| 711 | assign hw_set_over_err_eq_26 = rds2eqs_eq_sel & eq_num_sel_26 & full_eq_26 & eq_state_26[ACTIVE]; |
| 712 | assign hw_set_over_err_eq_27 = rds2eqs_eq_sel & eq_num_sel_27 & full_eq_27 & eq_state_27[ACTIVE]; |
| 713 | assign hw_set_over_err_eq_28 = rds2eqs_eq_sel & eq_num_sel_28 & full_eq_28 & eq_state_28[ACTIVE]; |
| 714 | assign hw_set_over_err_eq_29 = rds2eqs_eq_sel & eq_num_sel_29 & full_eq_29 & eq_state_29[ACTIVE]; |
| 715 | assign hw_set_over_err_eq_30 = rds2eqs_eq_sel & eq_num_sel_30 & full_eq_30 & eq_state_30[ACTIVE]; |
| 716 | assign hw_set_over_err_eq_31 = rds2eqs_eq_sel & eq_num_sel_31 & full_eq_31 & eq_state_31[ACTIVE]; |
| 717 | assign hw_set_over_err_eq_32 = rds2eqs_eq_sel & eq_num_sel_32 & full_eq_32 & eq_state_32[ACTIVE]; |
| 718 | assign hw_set_over_err_eq_33 = rds2eqs_eq_sel & eq_num_sel_33 & full_eq_33 & eq_state_33[ACTIVE]; |
| 719 | assign hw_set_over_err_eq_34 = rds2eqs_eq_sel & eq_num_sel_34 & full_eq_34 & eq_state_34[ACTIVE]; |
| 720 | assign hw_set_over_err_eq_35 = rds2eqs_eq_sel & eq_num_sel_35 & full_eq_35 & eq_state_35[ACTIVE]; |
| 721 | |
| 722 | //----------------------------------------------------------------------------- |
| 723 | // State Transistion in controled by a SW Regs |
| 724 | // |
| 725 | // IDLE -> ACTIVE eq_ctrl_set reg bit 44 |
| 726 | // ACTIVE -> IDLE eq_ctrl_clr reg bit 44 |
| 727 | // ACTIVE -> ERROR eq_ctrl_set reg bit 57 |
| 728 | // ERROR -> IDLE eq_ctrl_clr reg bit 47 |
| 729 | // |
| 730 | // Error Status Bit |
| 731 | // |
| 732 | // Can be set by software eq_ctrl_set reg bit 57 only in ACTIVE STATE |
| 733 | // Can be cleared by software eq_ctrl_clr reg bit 57 in ANY STATE |
| 734 | // |
| 735 | // |
| 736 | //----------------------------------------------------------------------------- |
| 737 | |
| 738 | //----------------------------------------------------------------------------- |
| 739 | // SW Set Overflow |
| 740 | // |
| 741 | // If SW PIO and the EQ is in the ACTIVE state. |
| 742 | // |
| 743 | // This signal is used to determine: |
| 744 | // - as part of when to load the EQ overflow error bit (setting it to 1) |
| 745 | // - Input into fsm to change state from ACTIVE to ERROR |
| 746 | // |
| 747 | // NOTE - eq_state_* variable is not needed here and may be able to be |
| 748 | // removed later if needed to make timing . This can be done since |
| 749 | // this signal is only used by the FSM in the ACTIVE STATE |
| 750 | // |
| 751 | // However if this is done this signal can not be used to set the |
| 752 | // overflow error status bit. Changes will need to be made to the |
| 753 | // load_over_err_eq_* signals to "and" ACTIVE STATE with |
| 754 | // sw_set_over_err_eq_* |
| 755 | //----------------------------------------------------------------------------- |
| 756 | |
| 757 | assign sw_set_over_err_eq_0 = sw_set_addr_sel_eq_0 & ext_wr & set_enoverr_ext_wr_data & eq_state_0[ACTIVE]; |
| 758 | assign sw_set_over_err_eq_1 = sw_set_addr_sel_eq_1 & ext_wr & set_enoverr_ext_wr_data & eq_state_1[ACTIVE]; |
| 759 | assign sw_set_over_err_eq_2 = sw_set_addr_sel_eq_2 & ext_wr & set_enoverr_ext_wr_data & eq_state_2[ACTIVE]; |
| 760 | assign sw_set_over_err_eq_3 = sw_set_addr_sel_eq_3 & ext_wr & set_enoverr_ext_wr_data & eq_state_3[ACTIVE]; |
| 761 | assign sw_set_over_err_eq_4 = sw_set_addr_sel_eq_4 & ext_wr & set_enoverr_ext_wr_data & eq_state_4[ACTIVE]; |
| 762 | assign sw_set_over_err_eq_5 = sw_set_addr_sel_eq_5 & ext_wr & set_enoverr_ext_wr_data & eq_state_5[ACTIVE]; |
| 763 | assign sw_set_over_err_eq_6 = sw_set_addr_sel_eq_6 & ext_wr & set_enoverr_ext_wr_data & eq_state_6[ACTIVE]; |
| 764 | assign sw_set_over_err_eq_7 = sw_set_addr_sel_eq_7 & ext_wr & set_enoverr_ext_wr_data & eq_state_7[ACTIVE]; |
| 765 | assign sw_set_over_err_eq_8 = sw_set_addr_sel_eq_8 & ext_wr & set_enoverr_ext_wr_data & eq_state_8[ACTIVE]; |
| 766 | assign sw_set_over_err_eq_9 = sw_set_addr_sel_eq_9 & ext_wr & set_enoverr_ext_wr_data & eq_state_9[ACTIVE]; |
| 767 | assign sw_set_over_err_eq_10 = sw_set_addr_sel_eq_10 & ext_wr & set_enoverr_ext_wr_data & eq_state_10[ACTIVE]; |
| 768 | assign sw_set_over_err_eq_11 = sw_set_addr_sel_eq_11 & ext_wr & set_enoverr_ext_wr_data & eq_state_11[ACTIVE]; |
| 769 | assign sw_set_over_err_eq_12 = sw_set_addr_sel_eq_12 & ext_wr & set_enoverr_ext_wr_data & eq_state_12[ACTIVE]; |
| 770 | assign sw_set_over_err_eq_13 = sw_set_addr_sel_eq_13 & ext_wr & set_enoverr_ext_wr_data & eq_state_13[ACTIVE]; |
| 771 | assign sw_set_over_err_eq_14 = sw_set_addr_sel_eq_14 & ext_wr & set_enoverr_ext_wr_data & eq_state_14[ACTIVE]; |
| 772 | assign sw_set_over_err_eq_15 = sw_set_addr_sel_eq_15 & ext_wr & set_enoverr_ext_wr_data & eq_state_15[ACTIVE]; |
| 773 | assign sw_set_over_err_eq_16 = sw_set_addr_sel_eq_16 & ext_wr & set_enoverr_ext_wr_data & eq_state_16[ACTIVE]; |
| 774 | assign sw_set_over_err_eq_17 = sw_set_addr_sel_eq_17 & ext_wr & set_enoverr_ext_wr_data & eq_state_17[ACTIVE]; |
| 775 | assign sw_set_over_err_eq_18 = sw_set_addr_sel_eq_18 & ext_wr & set_enoverr_ext_wr_data & eq_state_18[ACTIVE]; |
| 776 | assign sw_set_over_err_eq_19 = sw_set_addr_sel_eq_19 & ext_wr & set_enoverr_ext_wr_data & eq_state_19[ACTIVE]; |
| 777 | assign sw_set_over_err_eq_20 = sw_set_addr_sel_eq_20 & ext_wr & set_enoverr_ext_wr_data & eq_state_20[ACTIVE]; |
| 778 | assign sw_set_over_err_eq_21 = sw_set_addr_sel_eq_21 & ext_wr & set_enoverr_ext_wr_data & eq_state_21[ACTIVE]; |
| 779 | assign sw_set_over_err_eq_22 = sw_set_addr_sel_eq_22 & ext_wr & set_enoverr_ext_wr_data & eq_state_22[ACTIVE]; |
| 780 | assign sw_set_over_err_eq_23 = sw_set_addr_sel_eq_23 & ext_wr & set_enoverr_ext_wr_data & eq_state_23[ACTIVE]; |
| 781 | assign sw_set_over_err_eq_24 = sw_set_addr_sel_eq_24 & ext_wr & set_enoverr_ext_wr_data & eq_state_24[ACTIVE]; |
| 782 | assign sw_set_over_err_eq_25 = sw_set_addr_sel_eq_25 & ext_wr & set_enoverr_ext_wr_data & eq_state_25[ACTIVE]; |
| 783 | assign sw_set_over_err_eq_26 = sw_set_addr_sel_eq_26 & ext_wr & set_enoverr_ext_wr_data & eq_state_26[ACTIVE]; |
| 784 | assign sw_set_over_err_eq_27 = sw_set_addr_sel_eq_27 & ext_wr & set_enoverr_ext_wr_data & eq_state_27[ACTIVE]; |
| 785 | assign sw_set_over_err_eq_28 = sw_set_addr_sel_eq_28 & ext_wr & set_enoverr_ext_wr_data & eq_state_28[ACTIVE]; |
| 786 | assign sw_set_over_err_eq_29 = sw_set_addr_sel_eq_29 & ext_wr & set_enoverr_ext_wr_data & eq_state_29[ACTIVE]; |
| 787 | assign sw_set_over_err_eq_30 = sw_set_addr_sel_eq_30 & ext_wr & set_enoverr_ext_wr_data & eq_state_30[ACTIVE]; |
| 788 | assign sw_set_over_err_eq_31 = sw_set_addr_sel_eq_31 & ext_wr & set_enoverr_ext_wr_data & eq_state_31[ACTIVE]; |
| 789 | assign sw_set_over_err_eq_32 = sw_set_addr_sel_eq_32 & ext_wr & set_enoverr_ext_wr_data & eq_state_32[ACTIVE]; |
| 790 | assign sw_set_over_err_eq_33 = sw_set_addr_sel_eq_33 & ext_wr & set_enoverr_ext_wr_data & eq_state_33[ACTIVE]; |
| 791 | assign sw_set_over_err_eq_34 = sw_set_addr_sel_eq_34 & ext_wr & set_enoverr_ext_wr_data & eq_state_34[ACTIVE]; |
| 792 | assign sw_set_over_err_eq_35 = sw_set_addr_sel_eq_35 & ext_wr & set_enoverr_ext_wr_data & eq_state_35[ACTIVE]; |
| 793 | |
| 794 | //----------------------------------------------------------------------------- |
| 795 | // SW Clr Overflow |
| 796 | // |
| 797 | // If SW PIO and the EQ is in the ANY state. |
| 798 | // |
| 799 | // This signal is used to determine: |
| 800 | // - as part of when to load the EQ overflow error bit (clearing it to 0) |
| 801 | // |
| 802 | //----------------------------------------------------------------------------- |
| 803 | |
| 804 | assign sw_clr_over_err_eq_0 = sw_clr_addr_sel_eq_0 & ext_wr & clr_coverr_ext_wr_data; |
| 805 | assign sw_clr_over_err_eq_1 = sw_clr_addr_sel_eq_1 & ext_wr & clr_coverr_ext_wr_data; |
| 806 | assign sw_clr_over_err_eq_2 = sw_clr_addr_sel_eq_2 & ext_wr & clr_coverr_ext_wr_data; |
| 807 | assign sw_clr_over_err_eq_3 = sw_clr_addr_sel_eq_3 & ext_wr & clr_coverr_ext_wr_data; |
| 808 | assign sw_clr_over_err_eq_4 = sw_clr_addr_sel_eq_4 & ext_wr & clr_coverr_ext_wr_data; |
| 809 | assign sw_clr_over_err_eq_5 = sw_clr_addr_sel_eq_5 & ext_wr & clr_coverr_ext_wr_data; |
| 810 | assign sw_clr_over_err_eq_6 = sw_clr_addr_sel_eq_6 & ext_wr & clr_coverr_ext_wr_data; |
| 811 | assign sw_clr_over_err_eq_7 = sw_clr_addr_sel_eq_7 & ext_wr & clr_coverr_ext_wr_data; |
| 812 | assign sw_clr_over_err_eq_8 = sw_clr_addr_sel_eq_8 & ext_wr & clr_coverr_ext_wr_data; |
| 813 | assign sw_clr_over_err_eq_9 = sw_clr_addr_sel_eq_9 & ext_wr & clr_coverr_ext_wr_data; |
| 814 | assign sw_clr_over_err_eq_10 = sw_clr_addr_sel_eq_10 & ext_wr & clr_coverr_ext_wr_data; |
| 815 | assign sw_clr_over_err_eq_11 = sw_clr_addr_sel_eq_11 & ext_wr & clr_coverr_ext_wr_data; |
| 816 | assign sw_clr_over_err_eq_12 = sw_clr_addr_sel_eq_12 & ext_wr & clr_coverr_ext_wr_data; |
| 817 | assign sw_clr_over_err_eq_13 = sw_clr_addr_sel_eq_13 & ext_wr & clr_coverr_ext_wr_data; |
| 818 | assign sw_clr_over_err_eq_14 = sw_clr_addr_sel_eq_14 & ext_wr & clr_coverr_ext_wr_data; |
| 819 | assign sw_clr_over_err_eq_15 = sw_clr_addr_sel_eq_15 & ext_wr & clr_coverr_ext_wr_data; |
| 820 | assign sw_clr_over_err_eq_16 = sw_clr_addr_sel_eq_16 & ext_wr & clr_coverr_ext_wr_data; |
| 821 | assign sw_clr_over_err_eq_17 = sw_clr_addr_sel_eq_17 & ext_wr & clr_coverr_ext_wr_data; |
| 822 | assign sw_clr_over_err_eq_18 = sw_clr_addr_sel_eq_18 & ext_wr & clr_coverr_ext_wr_data; |
| 823 | assign sw_clr_over_err_eq_19 = sw_clr_addr_sel_eq_19 & ext_wr & clr_coverr_ext_wr_data; |
| 824 | assign sw_clr_over_err_eq_20 = sw_clr_addr_sel_eq_20 & ext_wr & clr_coverr_ext_wr_data; |
| 825 | assign sw_clr_over_err_eq_21 = sw_clr_addr_sel_eq_21 & ext_wr & clr_coverr_ext_wr_data; |
| 826 | assign sw_clr_over_err_eq_22 = sw_clr_addr_sel_eq_22 & ext_wr & clr_coverr_ext_wr_data; |
| 827 | assign sw_clr_over_err_eq_23 = sw_clr_addr_sel_eq_23 & ext_wr & clr_coverr_ext_wr_data; |
| 828 | assign sw_clr_over_err_eq_24 = sw_clr_addr_sel_eq_24 & ext_wr & clr_coverr_ext_wr_data; |
| 829 | assign sw_clr_over_err_eq_25 = sw_clr_addr_sel_eq_25 & ext_wr & clr_coverr_ext_wr_data; |
| 830 | assign sw_clr_over_err_eq_26 = sw_clr_addr_sel_eq_26 & ext_wr & clr_coverr_ext_wr_data; |
| 831 | assign sw_clr_over_err_eq_27 = sw_clr_addr_sel_eq_27 & ext_wr & clr_coverr_ext_wr_data; |
| 832 | assign sw_clr_over_err_eq_28 = sw_clr_addr_sel_eq_28 & ext_wr & clr_coverr_ext_wr_data; |
| 833 | assign sw_clr_over_err_eq_29 = sw_clr_addr_sel_eq_29 & ext_wr & clr_coverr_ext_wr_data; |
| 834 | assign sw_clr_over_err_eq_30 = sw_clr_addr_sel_eq_30 & ext_wr & clr_coverr_ext_wr_data; |
| 835 | assign sw_clr_over_err_eq_31 = sw_clr_addr_sel_eq_31 & ext_wr & clr_coverr_ext_wr_data; |
| 836 | assign sw_clr_over_err_eq_32 = sw_clr_addr_sel_eq_32 & ext_wr & clr_coverr_ext_wr_data; |
| 837 | assign sw_clr_over_err_eq_33 = sw_clr_addr_sel_eq_33 & ext_wr & clr_coverr_ext_wr_data; |
| 838 | assign sw_clr_over_err_eq_34 = sw_clr_addr_sel_eq_34 & ext_wr & clr_coverr_ext_wr_data; |
| 839 | assign sw_clr_over_err_eq_35 = sw_clr_addr_sel_eq_35 & ext_wr & clr_coverr_ext_wr_data; |
| 840 | |
| 841 | |
| 842 | |
| 843 | |
| 844 | |
| 845 | //----------------------------------------------------------------------------- |
| 846 | // Set the Error Bit Signal |
| 847 | // |
| 848 | // Combination of SW Set Overflow PIO , HW Set overflow error , |
| 849 | //----------------------------------------------------------------------------- |
| 850 | assign set_over_err_eq_0 = hw_set_over_err_eq_0 | sw_set_over_err_eq_0; |
| 851 | assign set_over_err_eq_1 = hw_set_over_err_eq_1 | sw_set_over_err_eq_1; |
| 852 | assign set_over_err_eq_2 = hw_set_over_err_eq_2 | sw_set_over_err_eq_2; |
| 853 | assign set_over_err_eq_3 = hw_set_over_err_eq_3 | sw_set_over_err_eq_3; |
| 854 | assign set_over_err_eq_4 = hw_set_over_err_eq_4 | sw_set_over_err_eq_4; |
| 855 | assign set_over_err_eq_5 = hw_set_over_err_eq_5 | sw_set_over_err_eq_5; |
| 856 | assign set_over_err_eq_6 = hw_set_over_err_eq_6 | sw_set_over_err_eq_6; |
| 857 | assign set_over_err_eq_7 = hw_set_over_err_eq_7 | sw_set_over_err_eq_7; |
| 858 | assign set_over_err_eq_8 = hw_set_over_err_eq_8 | sw_set_over_err_eq_8; |
| 859 | assign set_over_err_eq_9 = hw_set_over_err_eq_9 | sw_set_over_err_eq_9; |
| 860 | assign set_over_err_eq_10 = hw_set_over_err_eq_10 | sw_set_over_err_eq_10; |
| 861 | assign set_over_err_eq_11 = hw_set_over_err_eq_11 | sw_set_over_err_eq_11; |
| 862 | assign set_over_err_eq_12 = hw_set_over_err_eq_12 | sw_set_over_err_eq_12; |
| 863 | assign set_over_err_eq_13 = hw_set_over_err_eq_13 | sw_set_over_err_eq_13; |
| 864 | assign set_over_err_eq_14 = hw_set_over_err_eq_14 | sw_set_over_err_eq_14; |
| 865 | assign set_over_err_eq_15 = hw_set_over_err_eq_15 | sw_set_over_err_eq_15; |
| 866 | assign set_over_err_eq_16 = hw_set_over_err_eq_16 | sw_set_over_err_eq_16; |
| 867 | assign set_over_err_eq_17 = hw_set_over_err_eq_17 | sw_set_over_err_eq_17; |
| 868 | assign set_over_err_eq_18 = hw_set_over_err_eq_18 | sw_set_over_err_eq_18; |
| 869 | assign set_over_err_eq_19 = hw_set_over_err_eq_19 | sw_set_over_err_eq_19; |
| 870 | assign set_over_err_eq_20 = hw_set_over_err_eq_20 | sw_set_over_err_eq_20; |
| 871 | assign set_over_err_eq_21 = hw_set_over_err_eq_21 | sw_set_over_err_eq_21; |
| 872 | assign set_over_err_eq_22 = hw_set_over_err_eq_22 | sw_set_over_err_eq_22; |
| 873 | assign set_over_err_eq_23 = hw_set_over_err_eq_23 | sw_set_over_err_eq_23; |
| 874 | assign set_over_err_eq_24 = hw_set_over_err_eq_24 | sw_set_over_err_eq_24; |
| 875 | assign set_over_err_eq_25 = hw_set_over_err_eq_25 | sw_set_over_err_eq_25; |
| 876 | assign set_over_err_eq_26 = hw_set_over_err_eq_26 | sw_set_over_err_eq_26; |
| 877 | assign set_over_err_eq_27 = hw_set_over_err_eq_27 | sw_set_over_err_eq_27; |
| 878 | assign set_over_err_eq_28 = hw_set_over_err_eq_28 | sw_set_over_err_eq_28; |
| 879 | assign set_over_err_eq_29 = hw_set_over_err_eq_29 | sw_set_over_err_eq_29; |
| 880 | assign set_over_err_eq_30 = hw_set_over_err_eq_30 | sw_set_over_err_eq_30; |
| 881 | assign set_over_err_eq_31 = hw_set_over_err_eq_31 | sw_set_over_err_eq_31; |
| 882 | assign set_over_err_eq_32 = hw_set_over_err_eq_32 | sw_set_over_err_eq_32; |
| 883 | assign set_over_err_eq_33 = hw_set_over_err_eq_33 | sw_set_over_err_eq_33; |
| 884 | assign set_over_err_eq_34 = hw_set_over_err_eq_34 | sw_set_over_err_eq_34; |
| 885 | assign set_over_err_eq_35 = hw_set_over_err_eq_35 | sw_set_over_err_eq_35; |
| 886 | |
| 887 | |
| 888 | |
| 889 | //----------------------------------------------------------------------------- |
| 890 | // Load Signal |
| 891 | // |
| 892 | // Combination of SW Overflow PIO , HW overflow error , or SW clear error |
| 893 | //----------------------------------------------------------------------------- |
| 894 | assign load_over_err_eq_0 = set_over_err_eq_0 | sw_clr_over_err_eq_0; |
| 895 | assign load_over_err_eq_1 = set_over_err_eq_1 | sw_clr_over_err_eq_1; |
| 896 | assign load_over_err_eq_2 = set_over_err_eq_2 | sw_clr_over_err_eq_2; |
| 897 | assign load_over_err_eq_3 = set_over_err_eq_3 | sw_clr_over_err_eq_3; |
| 898 | assign load_over_err_eq_4 = set_over_err_eq_4 | sw_clr_over_err_eq_4; |
| 899 | assign load_over_err_eq_5 = set_over_err_eq_5 | sw_clr_over_err_eq_5; |
| 900 | assign load_over_err_eq_6 = set_over_err_eq_6 | sw_clr_over_err_eq_6; |
| 901 | assign load_over_err_eq_7 = set_over_err_eq_7 | sw_clr_over_err_eq_7; |
| 902 | assign load_over_err_eq_8 = set_over_err_eq_8 | sw_clr_over_err_eq_8; |
| 903 | assign load_over_err_eq_9 = set_over_err_eq_9 | sw_clr_over_err_eq_9; |
| 904 | assign load_over_err_eq_10 = set_over_err_eq_10 | sw_clr_over_err_eq_10; |
| 905 | assign load_over_err_eq_11 = set_over_err_eq_11 | sw_clr_over_err_eq_11; |
| 906 | assign load_over_err_eq_12 = set_over_err_eq_12 | sw_clr_over_err_eq_12; |
| 907 | assign load_over_err_eq_13 = set_over_err_eq_13 | sw_clr_over_err_eq_13; |
| 908 | assign load_over_err_eq_14 = set_over_err_eq_14 | sw_clr_over_err_eq_14; |
| 909 | assign load_over_err_eq_15 = set_over_err_eq_15 | sw_clr_over_err_eq_15; |
| 910 | assign load_over_err_eq_16 = set_over_err_eq_16 | sw_clr_over_err_eq_16; |
| 911 | assign load_over_err_eq_17 = set_over_err_eq_17 | sw_clr_over_err_eq_17; |
| 912 | assign load_over_err_eq_18 = set_over_err_eq_18 | sw_clr_over_err_eq_18; |
| 913 | assign load_over_err_eq_19 = set_over_err_eq_19 | sw_clr_over_err_eq_19; |
| 914 | assign load_over_err_eq_20 = set_over_err_eq_20 | sw_clr_over_err_eq_20; |
| 915 | assign load_over_err_eq_21 = set_over_err_eq_21 | sw_clr_over_err_eq_21; |
| 916 | assign load_over_err_eq_22 = set_over_err_eq_22 | sw_clr_over_err_eq_22; |
| 917 | assign load_over_err_eq_23 = set_over_err_eq_23 | sw_clr_over_err_eq_23; |
| 918 | assign load_over_err_eq_24 = set_over_err_eq_24 | sw_clr_over_err_eq_24; |
| 919 | assign load_over_err_eq_25 = set_over_err_eq_25 | sw_clr_over_err_eq_25; |
| 920 | assign load_over_err_eq_26 = set_over_err_eq_26 | sw_clr_over_err_eq_26; |
| 921 | assign load_over_err_eq_27 = set_over_err_eq_27 | sw_clr_over_err_eq_27; |
| 922 | assign load_over_err_eq_28 = set_over_err_eq_28 | sw_clr_over_err_eq_28; |
| 923 | assign load_over_err_eq_29 = set_over_err_eq_29 | sw_clr_over_err_eq_29; |
| 924 | assign load_over_err_eq_30 = set_over_err_eq_30 | sw_clr_over_err_eq_30; |
| 925 | assign load_over_err_eq_31 = set_over_err_eq_31 | sw_clr_over_err_eq_31; |
| 926 | assign load_over_err_eq_32 = set_over_err_eq_32 | sw_clr_over_err_eq_32; |
| 927 | assign load_over_err_eq_33 = set_over_err_eq_33 | sw_clr_over_err_eq_33; |
| 928 | assign load_over_err_eq_34 = set_over_err_eq_34 | sw_clr_over_err_eq_34; |
| 929 | assign load_over_err_eq_35 = set_over_err_eq_35 | sw_clr_over_err_eq_35; |
| 930 | |
| 931 | |
| 932 | //----------------------------------------------------------------------------- |
| 933 | // Data to load into the over_flow error |
| 934 | // |
| 935 | //----------------------------------------------------------------------------- |
| 936 | |
| 937 | |
| 938 | assign data_over_err_eq_0 = ~sw_clr_over_err_eq_0; |
| 939 | assign data_over_err_eq_1 = ~sw_clr_over_err_eq_1; |
| 940 | assign data_over_err_eq_2 = ~sw_clr_over_err_eq_2; |
| 941 | assign data_over_err_eq_3 = ~sw_clr_over_err_eq_3; |
| 942 | assign data_over_err_eq_4 = ~sw_clr_over_err_eq_4; |
| 943 | assign data_over_err_eq_5 = ~sw_clr_over_err_eq_5; |
| 944 | assign data_over_err_eq_6 = ~sw_clr_over_err_eq_6; |
| 945 | assign data_over_err_eq_7 = ~sw_clr_over_err_eq_7; |
| 946 | assign data_over_err_eq_8 = ~sw_clr_over_err_eq_8; |
| 947 | assign data_over_err_eq_9 = ~sw_clr_over_err_eq_9; |
| 948 | assign data_over_err_eq_10 = ~sw_clr_over_err_eq_10; |
| 949 | assign data_over_err_eq_11 = ~sw_clr_over_err_eq_11; |
| 950 | assign data_over_err_eq_12 = ~sw_clr_over_err_eq_12; |
| 951 | assign data_over_err_eq_13 = ~sw_clr_over_err_eq_13; |
| 952 | assign data_over_err_eq_14 = ~sw_clr_over_err_eq_14; |
| 953 | assign data_over_err_eq_15 = ~sw_clr_over_err_eq_15; |
| 954 | assign data_over_err_eq_16 = ~sw_clr_over_err_eq_16; |
| 955 | assign data_over_err_eq_17 = ~sw_clr_over_err_eq_17; |
| 956 | assign data_over_err_eq_18 = ~sw_clr_over_err_eq_18; |
| 957 | assign data_over_err_eq_19 = ~sw_clr_over_err_eq_19; |
| 958 | assign data_over_err_eq_20 = ~sw_clr_over_err_eq_20; |
| 959 | assign data_over_err_eq_21 = ~sw_clr_over_err_eq_21; |
| 960 | assign data_over_err_eq_22 = ~sw_clr_over_err_eq_22; |
| 961 | assign data_over_err_eq_23 = ~sw_clr_over_err_eq_23; |
| 962 | assign data_over_err_eq_24 = ~sw_clr_over_err_eq_24; |
| 963 | assign data_over_err_eq_25 = ~sw_clr_over_err_eq_25; |
| 964 | assign data_over_err_eq_26 = ~sw_clr_over_err_eq_26; |
| 965 | assign data_over_err_eq_27 = ~sw_clr_over_err_eq_27; |
| 966 | assign data_over_err_eq_28 = ~sw_clr_over_err_eq_28; |
| 967 | assign data_over_err_eq_29 = ~sw_clr_over_err_eq_29; |
| 968 | assign data_over_err_eq_30 = ~sw_clr_over_err_eq_30; |
| 969 | assign data_over_err_eq_31 = ~sw_clr_over_err_eq_31; |
| 970 | assign data_over_err_eq_32 = ~sw_clr_over_err_eq_32; |
| 971 | assign data_over_err_eq_33 = ~sw_clr_over_err_eq_33; |
| 972 | assign data_over_err_eq_34 = ~sw_clr_over_err_eq_34; |
| 973 | assign data_over_err_eq_35 = ~sw_clr_over_err_eq_35; |
| 974 | |
| 975 | |
| 976 | |
| 977 | //----------------------------------------------------------------------------- |
| 978 | // Create Error Interrupt Signal |
| 979 | //----------------------------------------------------------------------------- |
| 980 | |
| 981 | |
| 982 | assign eqs2ics_eq_over_error = set_over_err_eq_0 | |
| 983 | set_over_err_eq_1 | |
| 984 | set_over_err_eq_2 | |
| 985 | set_over_err_eq_3 | |
| 986 | set_over_err_eq_4 | |
| 987 | set_over_err_eq_5 | |
| 988 | set_over_err_eq_6 | |
| 989 | set_over_err_eq_7 | |
| 990 | set_over_err_eq_8 | |
| 991 | set_over_err_eq_9 | |
| 992 | set_over_err_eq_10 | |
| 993 | set_over_err_eq_11 | |
| 994 | set_over_err_eq_12 | |
| 995 | set_over_err_eq_13 | |
| 996 | set_over_err_eq_14 | |
| 997 | set_over_err_eq_15 | |
| 998 | set_over_err_eq_16 | |
| 999 | set_over_err_eq_17 | |
| 1000 | set_over_err_eq_18 | |
| 1001 | set_over_err_eq_19 | |
| 1002 | set_over_err_eq_20 | |
| 1003 | set_over_err_eq_21 | |
| 1004 | set_over_err_eq_22 | |
| 1005 | set_over_err_eq_23 | |
| 1006 | set_over_err_eq_24 | |
| 1007 | set_over_err_eq_25 | |
| 1008 | set_over_err_eq_26 | |
| 1009 | set_over_err_eq_27 | |
| 1010 | set_over_err_eq_28 | |
| 1011 | set_over_err_eq_29 | |
| 1012 | set_over_err_eq_30 | |
| 1013 | set_over_err_eq_31 | |
| 1014 | set_over_err_eq_32 | |
| 1015 | set_over_err_eq_33 | |
| 1016 | set_over_err_eq_34 | |
| 1017 | set_over_err_eq_35; |
| 1018 | |
| 1019 | |
| 1020 | assign eqs2ics_error_data = {58'h0, rds2eqs_eq}; |
| 1021 | |
| 1022 | |
| 1023 | //************************ |
| 1024 | // Tail Pointer Update |
| 1025 | //************************ |
| 1026 | |
| 1027 | //----------------------------------------------------------------------------- |
| 1028 | // Select signals to know when to update the tail pointer |
| 1029 | // |
| 1030 | // Only update when |
| 1031 | // - The pipe line is selected |
| 1032 | // - It is the proper tail pointer to update |
| 1033 | // - And the EQ is ok and did not have an error. |
| 1034 | //----------------------------------------------------------------------------- |
| 1035 | |
| 1036 | |
| 1037 | assign t_ptr_inc_sel_0 = rds2eqs_eq_sel & eq_ok_0 & eq_num_sel_0; |
| 1038 | assign t_ptr_inc_sel_1 = rds2eqs_eq_sel & eq_ok_1 & eq_num_sel_1; |
| 1039 | assign t_ptr_inc_sel_2 = rds2eqs_eq_sel & eq_ok_2 & eq_num_sel_2; |
| 1040 | assign t_ptr_inc_sel_3 = rds2eqs_eq_sel & eq_ok_3 & eq_num_sel_3; |
| 1041 | assign t_ptr_inc_sel_4 = rds2eqs_eq_sel & eq_ok_4 & eq_num_sel_4; |
| 1042 | assign t_ptr_inc_sel_5 = rds2eqs_eq_sel & eq_ok_5 & eq_num_sel_5; |
| 1043 | assign t_ptr_inc_sel_6 = rds2eqs_eq_sel & eq_ok_6 & eq_num_sel_6; |
| 1044 | assign t_ptr_inc_sel_7 = rds2eqs_eq_sel & eq_ok_7 & eq_num_sel_7; |
| 1045 | assign t_ptr_inc_sel_8 = rds2eqs_eq_sel & eq_ok_8 & eq_num_sel_8; |
| 1046 | assign t_ptr_inc_sel_9 = rds2eqs_eq_sel & eq_ok_9 & eq_num_sel_9; |
| 1047 | assign t_ptr_inc_sel_10 = rds2eqs_eq_sel & eq_ok_10 & eq_num_sel_10; |
| 1048 | assign t_ptr_inc_sel_11 = rds2eqs_eq_sel & eq_ok_11 & eq_num_sel_11; |
| 1049 | assign t_ptr_inc_sel_12 = rds2eqs_eq_sel & eq_ok_12 & eq_num_sel_12; |
| 1050 | assign t_ptr_inc_sel_13 = rds2eqs_eq_sel & eq_ok_13 & eq_num_sel_13; |
| 1051 | assign t_ptr_inc_sel_14 = rds2eqs_eq_sel & eq_ok_14 & eq_num_sel_14; |
| 1052 | assign t_ptr_inc_sel_15 = rds2eqs_eq_sel & eq_ok_15 & eq_num_sel_15; |
| 1053 | assign t_ptr_inc_sel_16 = rds2eqs_eq_sel & eq_ok_16 & eq_num_sel_16; |
| 1054 | assign t_ptr_inc_sel_17 = rds2eqs_eq_sel & eq_ok_17 & eq_num_sel_17; |
| 1055 | assign t_ptr_inc_sel_18 = rds2eqs_eq_sel & eq_ok_18 & eq_num_sel_18; |
| 1056 | assign t_ptr_inc_sel_19 = rds2eqs_eq_sel & eq_ok_19 & eq_num_sel_19; |
| 1057 | assign t_ptr_inc_sel_20 = rds2eqs_eq_sel & eq_ok_20 & eq_num_sel_20; |
| 1058 | assign t_ptr_inc_sel_21 = rds2eqs_eq_sel & eq_ok_21 & eq_num_sel_21; |
| 1059 | assign t_ptr_inc_sel_22 = rds2eqs_eq_sel & eq_ok_22 & eq_num_sel_22; |
| 1060 | assign t_ptr_inc_sel_23 = rds2eqs_eq_sel & eq_ok_23 & eq_num_sel_23; |
| 1061 | assign t_ptr_inc_sel_24 = rds2eqs_eq_sel & eq_ok_24 & eq_num_sel_24; |
| 1062 | assign t_ptr_inc_sel_25 = rds2eqs_eq_sel & eq_ok_25 & eq_num_sel_25; |
| 1063 | assign t_ptr_inc_sel_26 = rds2eqs_eq_sel & eq_ok_26 & eq_num_sel_26; |
| 1064 | assign t_ptr_inc_sel_27 = rds2eqs_eq_sel & eq_ok_27 & eq_num_sel_27; |
| 1065 | assign t_ptr_inc_sel_28 = rds2eqs_eq_sel & eq_ok_28 & eq_num_sel_28; |
| 1066 | assign t_ptr_inc_sel_29 = rds2eqs_eq_sel & eq_ok_29 & eq_num_sel_29; |
| 1067 | assign t_ptr_inc_sel_30 = rds2eqs_eq_sel & eq_ok_30 & eq_num_sel_30; |
| 1068 | assign t_ptr_inc_sel_31 = rds2eqs_eq_sel & eq_ok_31 & eq_num_sel_31; |
| 1069 | assign t_ptr_inc_sel_32 = rds2eqs_eq_sel & eq_ok_32 & eq_num_sel_32; |
| 1070 | assign t_ptr_inc_sel_33 = rds2eqs_eq_sel & eq_ok_33 & eq_num_sel_33; |
| 1071 | assign t_ptr_inc_sel_34 = rds2eqs_eq_sel & eq_ok_34 & eq_num_sel_34; |
| 1072 | assign t_ptr_inc_sel_35 = rds2eqs_eq_sel & eq_ok_35 & eq_num_sel_35; |
| 1073 | |
| 1074 | |
| 1075 | |
| 1076 | |
| 1077 | |
| 1078 | //----------------------------------------------------------------------------- |
| 1079 | // EQ OK OUTPUT GENERATION |
| 1080 | // |
| 1081 | // To find out if it is OK to issue an EQ write we must check three things |
| 1082 | // 1) Is the EQ Full |
| 1083 | // 2) Is the EQ Enabled (Has SW made it active and ready to accept writes) |
| 1084 | // 3) Is the EQ in Error State |
| 1085 | // |
| 1086 | // ?) Or conversly we can just check to make sure it is in the ACTIVE STATE |
| 1087 | // |
| 1088 | //---- ------------------------------------------------------------------------ |
| 1089 | |
| 1090 | |
| 1091 | //********************* |
| 1092 | // EQ ACTIVE DETECTION |
| 1093 | //********************* |
| 1094 | |
| 1095 | //----------------------------------------------------------------------------- |
| 1096 | // Find out if the EQ is Active we must check the state to make sure that |
| 1097 | // It is in the ACTIVE state and not in the ERROR or IDLE states. |
| 1098 | // To do this we can take the 1-hot active bit directly from the state machine |
| 1099 | //----------------------------------------------------------------------------- |
| 1100 | |
| 1101 | //************************ |
| 1102 | // EQ Ok Wire Assignmeent |
| 1103 | //************************ |
| 1104 | |
| 1105 | //----------------------------------------------------------------------------- |
| 1106 | // The EQ is ok to send a write to if it is not full and the State is ACTIVE |
| 1107 | //----------------------------------------------------------------------------- |
| 1108 | |
| 1109 | assign eq_ok_0 = !(full_eq_0) & eq_state_0[ACTIVE]; |
| 1110 | assign eq_ok_1 = !(full_eq_1) & eq_state_1[ACTIVE]; |
| 1111 | assign eq_ok_2 = !(full_eq_2) & eq_state_2[ACTIVE]; |
| 1112 | assign eq_ok_3 = !(full_eq_3) & eq_state_3[ACTIVE]; |
| 1113 | assign eq_ok_4 = !(full_eq_4) & eq_state_4[ACTIVE]; |
| 1114 | assign eq_ok_5 = !(full_eq_5) & eq_state_5[ACTIVE]; |
| 1115 | assign eq_ok_6 = !(full_eq_6) & eq_state_6[ACTIVE]; |
| 1116 | assign eq_ok_7 = !(full_eq_7) & eq_state_7[ACTIVE]; |
| 1117 | assign eq_ok_8 = !(full_eq_8) & eq_state_8[ACTIVE]; |
| 1118 | assign eq_ok_9 = !(full_eq_9) & eq_state_9[ACTIVE]; |
| 1119 | assign eq_ok_10 = !(full_eq_10) & eq_state_10[ACTIVE]; |
| 1120 | assign eq_ok_11 = !(full_eq_11) & eq_state_11[ACTIVE]; |
| 1121 | assign eq_ok_12 = !(full_eq_12) & eq_state_12[ACTIVE]; |
| 1122 | assign eq_ok_13 = !(full_eq_13) & eq_state_13[ACTIVE]; |
| 1123 | assign eq_ok_14 = !(full_eq_14) & eq_state_14[ACTIVE]; |
| 1124 | assign eq_ok_15 = !(full_eq_15) & eq_state_15[ACTIVE]; |
| 1125 | assign eq_ok_16 = !(full_eq_16) & eq_state_16[ACTIVE]; |
| 1126 | assign eq_ok_17 = !(full_eq_17) & eq_state_17[ACTIVE]; |
| 1127 | assign eq_ok_18 = !(full_eq_18) & eq_state_18[ACTIVE]; |
| 1128 | assign eq_ok_19 = !(full_eq_19) & eq_state_19[ACTIVE]; |
| 1129 | assign eq_ok_20 = !(full_eq_20) & eq_state_20[ACTIVE]; |
| 1130 | assign eq_ok_21 = !(full_eq_21) & eq_state_21[ACTIVE]; |
| 1131 | assign eq_ok_22 = !(full_eq_22) & eq_state_22[ACTIVE]; |
| 1132 | assign eq_ok_23 = !(full_eq_23) & eq_state_23[ACTIVE]; |
| 1133 | assign eq_ok_24 = !(full_eq_24) & eq_state_24[ACTIVE]; |
| 1134 | assign eq_ok_25 = !(full_eq_25) & eq_state_25[ACTIVE]; |
| 1135 | assign eq_ok_26 = !(full_eq_26) & eq_state_26[ACTIVE]; |
| 1136 | assign eq_ok_27 = !(full_eq_27) & eq_state_27[ACTIVE]; |
| 1137 | assign eq_ok_28 = !(full_eq_28) & eq_state_28[ACTIVE]; |
| 1138 | assign eq_ok_29 = !(full_eq_29) & eq_state_29[ACTIVE]; |
| 1139 | assign eq_ok_30 = !(full_eq_30) & eq_state_30[ACTIVE]; |
| 1140 | assign eq_ok_31 = !(full_eq_31) & eq_state_31[ACTIVE]; |
| 1141 | assign eq_ok_32 = !(full_eq_32) & eq_state_32[ACTIVE]; |
| 1142 | assign eq_ok_33 = !(full_eq_33) & eq_state_33[ACTIVE]; |
| 1143 | assign eq_ok_34 = !(full_eq_34) & eq_state_34[ACTIVE]; |
| 1144 | assign eq_ok_35 = !(full_eq_35) & eq_state_35[ACTIVE]; |
| 1145 | |
| 1146 | //******************* |
| 1147 | // EQ OK Muxing |
| 1148 | //******************* |
| 1149 | |
| 1150 | //----------------------------------------------------------------------------- |
| 1151 | // Mux the results of the 36 eq ok signals using rds2eqs_eq as the select to select |
| 1152 | // which of the EQ's the write is for |
| 1153 | //----------------------------------------------------------------------------- |
| 1154 | |
| 1155 | always @ (eq_ok_0 or eq_ok_1 or eq_ok_2 or eq_ok_3 or eq_ok_4 or eq_ok_5 or eq_ok_6 or eq_ok_7 or |
| 1156 | eq_ok_8 or eq_ok_9 or eq_ok_10 or eq_ok_11 or eq_ok_12 or eq_ok_13 or eq_ok_14 or eq_ok_15 or |
| 1157 | eq_ok_16 or eq_ok_17 or eq_ok_18 or eq_ok_19 or eq_ok_20 or eq_ok_21 or eq_ok_22 or eq_ok_23 or eq_ok_24 or |
| 1158 | eq_ok_25 or eq_ok_26 or eq_ok_27 or eq_ok_28 or eq_ok_29 or eq_ok_30 or eq_ok_31 or eq_ok_32 or eq_ok_33 or |
| 1159 | eq_ok_34 or eq_ok_35 or rds2eqs_eq) |
| 1160 | |
| 1161 | case (rds2eqs_eq) // synopsys parallel_case full_case infer_mux |
| 1162 | 6'b000000 : eq_ok_mux = eq_ok_0; |
| 1163 | 6'b000001 : eq_ok_mux = eq_ok_1; |
| 1164 | 6'b000010 : eq_ok_mux = eq_ok_2; |
| 1165 | 6'b000011 : eq_ok_mux = eq_ok_3; |
| 1166 | 6'b000100 : eq_ok_mux = eq_ok_4; |
| 1167 | 6'b000101 : eq_ok_mux = eq_ok_5; |
| 1168 | 6'b000110 : eq_ok_mux = eq_ok_6; |
| 1169 | 6'b000111 : eq_ok_mux = eq_ok_7; |
| 1170 | |
| 1171 | 6'b001000 : eq_ok_mux = eq_ok_8; |
| 1172 | 6'b001001 : eq_ok_mux = eq_ok_9; |
| 1173 | 6'b001010 : eq_ok_mux = eq_ok_10; |
| 1174 | 6'b001011 : eq_ok_mux = eq_ok_11; |
| 1175 | 6'b001100 : eq_ok_mux = eq_ok_12; |
| 1176 | 6'b001101 : eq_ok_mux = eq_ok_13; |
| 1177 | 6'b001110 : eq_ok_mux = eq_ok_14; |
| 1178 | 6'b001111 : eq_ok_mux = eq_ok_15; |
| 1179 | |
| 1180 | 6'b010000 : eq_ok_mux = eq_ok_16; |
| 1181 | 6'b010001 : eq_ok_mux = eq_ok_17; |
| 1182 | 6'b010010 : eq_ok_mux = eq_ok_18; |
| 1183 | 6'b010011 : eq_ok_mux = eq_ok_19; |
| 1184 | 6'b010100 : eq_ok_mux = eq_ok_20; |
| 1185 | 6'b010101 : eq_ok_mux = eq_ok_21; |
| 1186 | 6'b010110 : eq_ok_mux = eq_ok_22; |
| 1187 | 6'b010111 : eq_ok_mux = eq_ok_23; |
| 1188 | |
| 1189 | 6'b011000 : eq_ok_mux = eq_ok_24; |
| 1190 | 6'b011001 : eq_ok_mux = eq_ok_25; |
| 1191 | 6'b011010 : eq_ok_mux = eq_ok_26; |
| 1192 | 6'b011011 : eq_ok_mux = eq_ok_27; |
| 1193 | 6'b011100 : eq_ok_mux = eq_ok_28; |
| 1194 | 6'b011101 : eq_ok_mux = eq_ok_29; |
| 1195 | 6'b011110 : eq_ok_mux = eq_ok_30; |
| 1196 | 6'b011111 : eq_ok_mux = eq_ok_31; |
| 1197 | |
| 1198 | 6'b100000 : eq_ok_mux = eq_ok_32; |
| 1199 | 6'b100001 : eq_ok_mux = eq_ok_33; |
| 1200 | 6'b100010 : eq_ok_mux = eq_ok_34; |
| 1201 | 6'b100011 : eq_ok_mux = eq_ok_35; |
| 1202 | |
| 1203 | |
| 1204 | endcase |
| 1205 | |
| 1206 | //********************** |
| 1207 | // EQ IDLE State Muxing |
| 1208 | //********************** |
| 1209 | |
| 1210 | //----------------------------------------------------------------------------- |
| 1211 | // Mux the results of the 36 eq ok signals using rds2eqs_eq as the select to select |
| 1212 | // which of the EQ's the write is for |
| 1213 | //----------------------------------------------------------------------------- |
| 1214 | |
| 1215 | always @ (eq_state_0 or eq_state_1 or eq_state_2 or eq_state_3 or eq_state_4 or eq_state_5 or eq_state_6 or eq_state_7 or |
| 1216 | eq_state_8 or eq_state_9 or eq_state_10 or eq_state_11 or eq_state_12 or eq_state_13 or eq_state_14 or eq_state_15 or |
| 1217 | eq_state_16 or eq_state_17 or eq_state_18 or eq_state_19 or eq_state_20 or eq_state_21 or eq_state_22 or eq_state_23 or eq_state_24 or |
| 1218 | eq_state_25 or eq_state_26 or eq_state_27 or eq_state_28 or eq_state_29 or eq_state_30 or eq_state_31 or eq_state_32 or eq_state_33 or |
| 1219 | eq_state_34 or eq_state_35 or rds2eqs_eq) |
| 1220 | |
| 1221 | case (rds2eqs_eq) // synopsys parallel_case full_case infer_mux |
| 1222 | 6'b000000 : eq_state_mux = eq_state_0[IDLE]; |
| 1223 | 6'b000001 : eq_state_mux = eq_state_1[IDLE]; |
| 1224 | 6'b000010 : eq_state_mux = eq_state_2[IDLE]; |
| 1225 | 6'b000011 : eq_state_mux = eq_state_3[IDLE]; |
| 1226 | 6'b000100 : eq_state_mux = eq_state_4[IDLE]; |
| 1227 | 6'b000101 : eq_state_mux = eq_state_5[IDLE]; |
| 1228 | 6'b000110 : eq_state_mux = eq_state_6[IDLE]; |
| 1229 | 6'b000111 : eq_state_mux = eq_state_7[IDLE]; |
| 1230 | |
| 1231 | 6'b001000 : eq_state_mux = eq_state_8[IDLE]; |
| 1232 | 6'b001001 : eq_state_mux = eq_state_9[IDLE]; |
| 1233 | 6'b001010 : eq_state_mux = eq_state_10[IDLE]; |
| 1234 | 6'b001011 : eq_state_mux = eq_state_11[IDLE]; |
| 1235 | 6'b001100 : eq_state_mux = eq_state_12[IDLE]; |
| 1236 | 6'b001101 : eq_state_mux = eq_state_13[IDLE]; |
| 1237 | 6'b001110 : eq_state_mux = eq_state_14[IDLE]; |
| 1238 | 6'b001111 : eq_state_mux = eq_state_15[IDLE]; |
| 1239 | |
| 1240 | 6'b010000 : eq_state_mux = eq_state_16[IDLE]; |
| 1241 | 6'b010001 : eq_state_mux = eq_state_17[IDLE]; |
| 1242 | 6'b010010 : eq_state_mux = eq_state_18[IDLE]; |
| 1243 | 6'b010011 : eq_state_mux = eq_state_19[IDLE]; |
| 1244 | 6'b010100 : eq_state_mux = eq_state_20[IDLE]; |
| 1245 | 6'b010101 : eq_state_mux = eq_state_21[IDLE]; |
| 1246 | 6'b010110 : eq_state_mux = eq_state_22[IDLE]; |
| 1247 | 6'b010111 : eq_state_mux = eq_state_23[IDLE]; |
| 1248 | |
| 1249 | 6'b011000 : eq_state_mux = eq_state_24[IDLE]; |
| 1250 | 6'b011001 : eq_state_mux = eq_state_25[IDLE]; |
| 1251 | 6'b011010 : eq_state_mux = eq_state_26[IDLE]; |
| 1252 | 6'b011011 : eq_state_mux = eq_state_27[IDLE]; |
| 1253 | 6'b011100 : eq_state_mux = eq_state_28[IDLE]; |
| 1254 | 6'b011101 : eq_state_mux = eq_state_29[IDLE]; |
| 1255 | 6'b011110 : eq_state_mux = eq_state_30[IDLE]; |
| 1256 | 6'b011111 : eq_state_mux = eq_state_31[IDLE]; |
| 1257 | |
| 1258 | 6'b100000 : eq_state_mux = eq_state_32[IDLE]; |
| 1259 | 6'b100001 : eq_state_mux = eq_state_33[IDLE]; |
| 1260 | 6'b100010 : eq_state_mux = eq_state_34[IDLE]; |
| 1261 | 6'b100011 : eq_state_mux = eq_state_35[IDLE]; |
| 1262 | |
| 1263 | |
| 1264 | endcase |
| 1265 | |
| 1266 | |
| 1267 | |
| 1268 | //******************* |
| 1269 | // Assign the Output |
| 1270 | //******************* |
| 1271 | |
| 1272 | //----------------------------------------------------------------------------- |
| 1273 | // Dont flop the out put of eq ok need the signal immediately |
| 1274 | //----------------------------------------------------------------------------- |
| 1275 | |
| 1276 | assign eqs2scs_eq_ok = eq_ok_mux; |
| 1277 | assign eqs2scs_eq_not_en = eq_state_mux; |
| 1278 | |
| 1279 | //############################################################################ |
| 1280 | // SEQUENTIAL LOGIC |
| 1281 | //############################################################################ |
| 1282 | |
| 1283 | //******************* |
| 1284 | // Assign the Output |
| 1285 | //******************* |
| 1286 | |
| 1287 | //----------------------------------------------------------------------------- |
| 1288 | // Flop the output of the block. Load the flop if selected else hold the |
| 1289 | // value. |
| 1290 | //----------------------------------------------------------------------------- |
| 1291 | |
| 1292 | always @ (posedge clk) |
| 1293 | if (!rst_l) |
| 1294 | begin |
| 1295 | eqs2ors_eq_addr <= 62'h0; |
| 1296 | eqs2ors_sel <= 1'b0; |
| 1297 | end |
| 1298 | else if (rds2eqs_eq_sel & eqs2scs_eq_ok) |
| 1299 | begin |
| 1300 | eqs2ors_eq_addr <= {eq_base_address,rds2eqs_eq,eq_address_mux,4'h0} ; |
| 1301 | eqs2ors_sel <= rds2eqs_eq_sel; |
| 1302 | end |
| 1303 | else |
| 1304 | begin |
| 1305 | eqs2ors_eq_addr <= eqs2ors_eq_addr; |
| 1306 | eqs2ors_sel <= rds2eqs_eq_sel; |
| 1307 | end |
| 1308 | |
| 1309 | //BP 7-25-06 N2 bug 118163, eq_base_address_63 to tmu for msi decode |
| 1310 | assign eq_base_address_63 = eq_base_address[44]; |
| 1311 | |
| 1312 | //----------------------------------------------------------------------------- |
| 1313 | // Flop the output of the block. |
| 1314 | // |
| 1315 | // This is for the interrupt requests to the ISS |
| 1316 | // |
| 1317 | // Signal is active low thats why it is inverted |
| 1318 | //----------------------------------------------------------------------------- |
| 1319 | |
| 1320 | always @ (posedge clk) |
| 1321 | if (!rst_l) |
| 1322 | eqs2iss_eq_int_l <= 36'hFFFF_FFFF_F; |
| 1323 | else |
| 1324 | eqs2iss_eq_int_l <= ~hw_mondo_trig; |
| 1325 | |
| 1326 | |
| 1327 | |
| 1328 | //----------------------------------------------------- |
| 1329 | // Debug Ports |
| 1330 | //----------------------------------------------------- |
| 1331 | |
| 1332 | always @ (dbg2eqs_dbg_sel_a or rds2eqs_eq_sel or rds2eqs_eq[5:0] or eqs2ics_eq_over_error or |
| 1333 | eqs2scs_eq_ok or eqs2scs_eq_not_en or eqs2ors_sel or eqs2iss_eq_int_l or |
| 1334 | eq_fsm_wr or eq_fsm_wr_data) |
| 1335 | begin |
| 1336 | case (dbg2eqs_dbg_sel_a) // synopsys infer_mux |
| 1337 | 3'b000: n_dbg_a = {rds2eqs_eq_sel, rds2eqs_eq[5:0], eqs2ics_eq_over_error}; |
| 1338 | 3'b001: n_dbg_a = {1'b0, eqs2scs_eq_ok, eqs2scs_eq_not_en, eqs2ors_sel, eqs2iss_eq_int_l[35:32]}; |
| 1339 | 3'b010: n_dbg_a = {eqs2iss_eq_int_l[7:0]}; |
| 1340 | 3'b011: n_dbg_a = {eqs2iss_eq_int_l[15:8]}; |
| 1341 | 3'b100: n_dbg_a = {eqs2iss_eq_int_l[23:16]}; |
| 1342 | 3'b101: n_dbg_a = {eqs2iss_eq_int_l[31:24]}; |
| 1343 | 3'b110: n_dbg_a = {5'h0, eq_fsm_wr, eq_fsm_wr_data[1:0]}; |
| 1344 | 3'b111: n_dbg_a = 8'h00; |
| 1345 | endcase |
| 1346 | end |
| 1347 | |
| 1348 | always @ (dbg2eqs_dbg_sel_b or rds2eqs_eq_sel or rds2eqs_eq[5:0] or eqs2ics_eq_over_error or |
| 1349 | eqs2scs_eq_ok or eqs2scs_eq_not_en or eqs2ors_sel or eqs2iss_eq_int_l or |
| 1350 | eq_fsm_wr or eq_fsm_wr_data ) |
| 1351 | begin |
| 1352 | case (dbg2eqs_dbg_sel_b) // synopsys infer_mux |
| 1353 | 3'b000: n_dbg_b = {rds2eqs_eq_sel, rds2eqs_eq[5:0], eqs2ics_eq_over_error}; |
| 1354 | 3'b001: n_dbg_b = {1'b0, eqs2scs_eq_ok, eqs2scs_eq_not_en, eqs2ors_sel, eqs2iss_eq_int_l[35:32]}; |
| 1355 | 3'b010: n_dbg_b = {eqs2iss_eq_int_l[7:0]}; |
| 1356 | 3'b011: n_dbg_b = {eqs2iss_eq_int_l[15:8]}; |
| 1357 | 3'b100: n_dbg_b = {eqs2iss_eq_int_l[23:16]}; |
| 1358 | 3'b101: n_dbg_b = {eqs2iss_eq_int_l[31:24]}; |
| 1359 | 3'b110: n_dbg_b = {5'h0, eq_fsm_wr, eq_fsm_wr_data[1:0]}; |
| 1360 | 3'b111: n_dbg_b = 8'h00; |
| 1361 | endcase |
| 1362 | end |
| 1363 | |
| 1364 | |
| 1365 | always @ (posedge clk) |
| 1366 | begin |
| 1367 | if (~rst_l ) begin |
| 1368 | dbg_a <= `FIRE_DEBUG_WDTH'b0; |
| 1369 | dbg_b <= `FIRE_DEBUG_WDTH'b0; |
| 1370 | end |
| 1371 | else begin |
| 1372 | dbg_a <= n_dbg_a; |
| 1373 | dbg_b <= n_dbg_b; |
| 1374 | end |
| 1375 | end |
| 1376 | |
| 1377 | |
| 1378 | assign eqs2dbg_dbg_a = dbg_a; |
| 1379 | assign eqs2dbg_dbg_b = dbg_b; |
| 1380 | |
| 1381 | |
| 1382 | //############################################################################ |
| 1383 | // MODULE INSTANTIATIONS |
| 1384 | //############################################################################ |
| 1385 | |
| 1386 | dmu_imu_eqs_csr csr ( |
| 1387 | |
| 1388 | .clk (clk), |
| 1389 | .csrbus_valid (csrbus_valid), |
| 1390 | .csrbus_done (csrbus_done), |
| 1391 | .csrbus_mapped (csrbus_mapped), |
| 1392 | .csrbus_wr_data (csrbus_wr_data), |
| 1393 | .csrbus_wr (csrbus_wr), |
| 1394 | .csrbus_read_data (csrbus_read_data), |
| 1395 | .csrbus_addr (csrbus_addr), |
| 1396 | .rst_l (rst_l), |
| 1397 | |
| 1398 | .csrbus_src_bus (csrbus_src_bus), |
| 1399 | .csrbus_acc_vio (csrbus_acc_vio), |
| 1400 | .instance_id (j2d_instance_id), |
| 1401 | |
| 1402 | .ext_wr (ext_wr), |
| 1403 | |
| 1404 | .eq_ctrl_set_enoverr_ext_wr_data (set_enoverr_ext_wr_data), |
| 1405 | .eq_ctrl_set_en_ext_wr_data (set_en_ext_wr_data), |
| 1406 | .eq_ctrl_clr_coverr_ext_wr_data (clr_coverr_ext_wr_data), |
| 1407 | .eq_ctrl_clr_e2i_ext_wr_data (clr_e2i_ext_wr_data), |
| 1408 | |
| 1409 | // Dont need anything here same as set_en_ext_wr_data |
| 1410 | // csrtool quork spits out twice for same data bitI only need 1 to pass to fsm's |
| 1411 | .eq_ctrl_clr_dis_ext_wr_data (), |
| 1412 | |
| 1413 | .eq_base_address_address_hw_read (eq_base_address), |
| 1414 | |
| 1415 | .eq_ctrl_set_ext_select_0 (sw_set_addr_sel_eq_0), |
| 1416 | .eq_ctrl_set_ext_select_1 (sw_set_addr_sel_eq_1), |
| 1417 | .eq_ctrl_set_ext_select_2 (sw_set_addr_sel_eq_2), |
| 1418 | .eq_ctrl_set_ext_select_3 (sw_set_addr_sel_eq_3), |
| 1419 | .eq_ctrl_set_ext_select_4 (sw_set_addr_sel_eq_4), |
| 1420 | .eq_ctrl_set_ext_select_5 (sw_set_addr_sel_eq_5), |
| 1421 | .eq_ctrl_set_ext_select_6 (sw_set_addr_sel_eq_6), |
| 1422 | .eq_ctrl_set_ext_select_7 (sw_set_addr_sel_eq_7), |
| 1423 | .eq_ctrl_set_ext_select_8 (sw_set_addr_sel_eq_8), |
| 1424 | .eq_ctrl_set_ext_select_9 (sw_set_addr_sel_eq_9), |
| 1425 | .eq_ctrl_set_ext_select_10 (sw_set_addr_sel_eq_10), |
| 1426 | .eq_ctrl_set_ext_select_11 (sw_set_addr_sel_eq_11), |
| 1427 | .eq_ctrl_set_ext_select_12 (sw_set_addr_sel_eq_12), |
| 1428 | .eq_ctrl_set_ext_select_13 (sw_set_addr_sel_eq_13), |
| 1429 | .eq_ctrl_set_ext_select_14 (sw_set_addr_sel_eq_14), |
| 1430 | .eq_ctrl_set_ext_select_15 (sw_set_addr_sel_eq_15), |
| 1431 | .eq_ctrl_set_ext_select_16 (sw_set_addr_sel_eq_16), |
| 1432 | .eq_ctrl_set_ext_select_17 (sw_set_addr_sel_eq_17), |
| 1433 | .eq_ctrl_set_ext_select_18 (sw_set_addr_sel_eq_18), |
| 1434 | .eq_ctrl_set_ext_select_19 (sw_set_addr_sel_eq_19), |
| 1435 | .eq_ctrl_set_ext_select_20 (sw_set_addr_sel_eq_20), |
| 1436 | .eq_ctrl_set_ext_select_21 (sw_set_addr_sel_eq_21), |
| 1437 | .eq_ctrl_set_ext_select_22 (sw_set_addr_sel_eq_22), |
| 1438 | .eq_ctrl_set_ext_select_23 (sw_set_addr_sel_eq_23), |
| 1439 | .eq_ctrl_set_ext_select_24 (sw_set_addr_sel_eq_24), |
| 1440 | .eq_ctrl_set_ext_select_25 (sw_set_addr_sel_eq_25), |
| 1441 | .eq_ctrl_set_ext_select_26 (sw_set_addr_sel_eq_26), |
| 1442 | .eq_ctrl_set_ext_select_27 (sw_set_addr_sel_eq_27), |
| 1443 | .eq_ctrl_set_ext_select_28 (sw_set_addr_sel_eq_28), |
| 1444 | .eq_ctrl_set_ext_select_29 (sw_set_addr_sel_eq_29), |
| 1445 | .eq_ctrl_set_ext_select_30 (sw_set_addr_sel_eq_30), |
| 1446 | .eq_ctrl_set_ext_select_31 (sw_set_addr_sel_eq_31), |
| 1447 | .eq_ctrl_set_ext_select_32 (sw_set_addr_sel_eq_32), |
| 1448 | .eq_ctrl_set_ext_select_33 (sw_set_addr_sel_eq_33), |
| 1449 | .eq_ctrl_set_ext_select_34 (sw_set_addr_sel_eq_34), |
| 1450 | .eq_ctrl_set_ext_select_35 (sw_set_addr_sel_eq_35), |
| 1451 | |
| 1452 | |
| 1453 | .eq_ctrl_clr_ext_select_0 (sw_clr_addr_sel_eq_0), |
| 1454 | .eq_ctrl_clr_ext_select_1 (sw_clr_addr_sel_eq_1), |
| 1455 | .eq_ctrl_clr_ext_select_2 (sw_clr_addr_sel_eq_2), |
| 1456 | .eq_ctrl_clr_ext_select_3 (sw_clr_addr_sel_eq_3), |
| 1457 | .eq_ctrl_clr_ext_select_4 (sw_clr_addr_sel_eq_4), |
| 1458 | .eq_ctrl_clr_ext_select_5 (sw_clr_addr_sel_eq_5), |
| 1459 | .eq_ctrl_clr_ext_select_6 (sw_clr_addr_sel_eq_6), |
| 1460 | .eq_ctrl_clr_ext_select_7 (sw_clr_addr_sel_eq_7), |
| 1461 | .eq_ctrl_clr_ext_select_8 (sw_clr_addr_sel_eq_8), |
| 1462 | .eq_ctrl_clr_ext_select_9 (sw_clr_addr_sel_eq_9), |
| 1463 | .eq_ctrl_clr_ext_select_10 (sw_clr_addr_sel_eq_10), |
| 1464 | .eq_ctrl_clr_ext_select_11 (sw_clr_addr_sel_eq_11), |
| 1465 | .eq_ctrl_clr_ext_select_12 (sw_clr_addr_sel_eq_12), |
| 1466 | .eq_ctrl_clr_ext_select_13 (sw_clr_addr_sel_eq_13), |
| 1467 | .eq_ctrl_clr_ext_select_14 (sw_clr_addr_sel_eq_14), |
| 1468 | .eq_ctrl_clr_ext_select_15 (sw_clr_addr_sel_eq_15), |
| 1469 | .eq_ctrl_clr_ext_select_16 (sw_clr_addr_sel_eq_16), |
| 1470 | .eq_ctrl_clr_ext_select_17 (sw_clr_addr_sel_eq_17), |
| 1471 | .eq_ctrl_clr_ext_select_18 (sw_clr_addr_sel_eq_18), |
| 1472 | .eq_ctrl_clr_ext_select_19 (sw_clr_addr_sel_eq_19), |
| 1473 | .eq_ctrl_clr_ext_select_20 (sw_clr_addr_sel_eq_20), |
| 1474 | .eq_ctrl_clr_ext_select_21 (sw_clr_addr_sel_eq_21), |
| 1475 | .eq_ctrl_clr_ext_select_22 (sw_clr_addr_sel_eq_22), |
| 1476 | .eq_ctrl_clr_ext_select_23 (sw_clr_addr_sel_eq_23), |
| 1477 | .eq_ctrl_clr_ext_select_24 (sw_clr_addr_sel_eq_24), |
| 1478 | .eq_ctrl_clr_ext_select_25 (sw_clr_addr_sel_eq_25), |
| 1479 | .eq_ctrl_clr_ext_select_26 (sw_clr_addr_sel_eq_26), |
| 1480 | .eq_ctrl_clr_ext_select_27 (sw_clr_addr_sel_eq_27), |
| 1481 | .eq_ctrl_clr_ext_select_28 (sw_clr_addr_sel_eq_28), |
| 1482 | .eq_ctrl_clr_ext_select_29 (sw_clr_addr_sel_eq_29), |
| 1483 | .eq_ctrl_clr_ext_select_30 (sw_clr_addr_sel_eq_30), |
| 1484 | .eq_ctrl_clr_ext_select_31 (sw_clr_addr_sel_eq_31), |
| 1485 | .eq_ctrl_clr_ext_select_32 (sw_clr_addr_sel_eq_32), |
| 1486 | .eq_ctrl_clr_ext_select_33 (sw_clr_addr_sel_eq_33), |
| 1487 | .eq_ctrl_clr_ext_select_34 (sw_clr_addr_sel_eq_34), |
| 1488 | .eq_ctrl_clr_ext_select_35 (sw_clr_addr_sel_eq_35), |
| 1489 | |
| 1490 | |
| 1491 | .eq_state_state_ext_read_data_0 (eq_state_0), |
| 1492 | .eq_state_state_ext_read_data_1 (eq_state_1), |
| 1493 | .eq_state_state_ext_read_data_2 (eq_state_2), |
| 1494 | .eq_state_state_ext_read_data_3 (eq_state_3), |
| 1495 | .eq_state_state_ext_read_data_4 (eq_state_4), |
| 1496 | .eq_state_state_ext_read_data_5 (eq_state_5), |
| 1497 | .eq_state_state_ext_read_data_6 (eq_state_6), |
| 1498 | .eq_state_state_ext_read_data_7 (eq_state_7), |
| 1499 | .eq_state_state_ext_read_data_8 (eq_state_8), |
| 1500 | .eq_state_state_ext_read_data_9 (eq_state_9), |
| 1501 | .eq_state_state_ext_read_data_10 (eq_state_10), |
| 1502 | .eq_state_state_ext_read_data_11 (eq_state_11), |
| 1503 | .eq_state_state_ext_read_data_12 (eq_state_12), |
| 1504 | .eq_state_state_ext_read_data_13 (eq_state_13), |
| 1505 | .eq_state_state_ext_read_data_14 (eq_state_14), |
| 1506 | .eq_state_state_ext_read_data_15 (eq_state_15), |
| 1507 | .eq_state_state_ext_read_data_16 (eq_state_16), |
| 1508 | .eq_state_state_ext_read_data_17 (eq_state_17), |
| 1509 | .eq_state_state_ext_read_data_18 (eq_state_18), |
| 1510 | .eq_state_state_ext_read_data_19 (eq_state_19), |
| 1511 | .eq_state_state_ext_read_data_20 (eq_state_20), |
| 1512 | .eq_state_state_ext_read_data_21 (eq_state_21), |
| 1513 | .eq_state_state_ext_read_data_22 (eq_state_22), |
| 1514 | .eq_state_state_ext_read_data_23 (eq_state_23), |
| 1515 | .eq_state_state_ext_read_data_24 (eq_state_24), |
| 1516 | .eq_state_state_ext_read_data_25 (eq_state_25), |
| 1517 | .eq_state_state_ext_read_data_26 (eq_state_26), |
| 1518 | .eq_state_state_ext_read_data_27 (eq_state_27), |
| 1519 | .eq_state_state_ext_read_data_28 (eq_state_28), |
| 1520 | .eq_state_state_ext_read_data_29 (eq_state_29), |
| 1521 | .eq_state_state_ext_read_data_30 (eq_state_30), |
| 1522 | .eq_state_state_ext_read_data_31 (eq_state_31), |
| 1523 | .eq_state_state_ext_read_data_32 (eq_state_32), |
| 1524 | .eq_state_state_ext_read_data_33 (eq_state_33), |
| 1525 | .eq_state_state_ext_read_data_34 (eq_state_34), |
| 1526 | .eq_state_state_ext_read_data_35 (eq_state_35), |
| 1527 | |
| 1528 | |
| 1529 | .eq_tail_overr_hw_ld_0 (load_over_err_eq_0), |
| 1530 | .eq_tail_overr_hw_ld_1 (load_over_err_eq_1), |
| 1531 | .eq_tail_overr_hw_ld_2 (load_over_err_eq_2), |
| 1532 | .eq_tail_overr_hw_ld_3 (load_over_err_eq_3), |
| 1533 | .eq_tail_overr_hw_ld_4 (load_over_err_eq_4), |
| 1534 | .eq_tail_overr_hw_ld_5 (load_over_err_eq_5), |
| 1535 | .eq_tail_overr_hw_ld_6 (load_over_err_eq_6), |
| 1536 | .eq_tail_overr_hw_ld_7 (load_over_err_eq_7), |
| 1537 | .eq_tail_overr_hw_ld_8 (load_over_err_eq_8), |
| 1538 | .eq_tail_overr_hw_ld_9 (load_over_err_eq_9), |
| 1539 | .eq_tail_overr_hw_ld_10 (load_over_err_eq_10), |
| 1540 | .eq_tail_overr_hw_ld_11 (load_over_err_eq_11), |
| 1541 | .eq_tail_overr_hw_ld_12 (load_over_err_eq_12), |
| 1542 | .eq_tail_overr_hw_ld_13 (load_over_err_eq_13), |
| 1543 | .eq_tail_overr_hw_ld_14 (load_over_err_eq_14), |
| 1544 | .eq_tail_overr_hw_ld_15 (load_over_err_eq_15), |
| 1545 | .eq_tail_overr_hw_ld_16 (load_over_err_eq_16), |
| 1546 | .eq_tail_overr_hw_ld_17 (load_over_err_eq_17), |
| 1547 | .eq_tail_overr_hw_ld_18 (load_over_err_eq_18), |
| 1548 | .eq_tail_overr_hw_ld_19 (load_over_err_eq_19), |
| 1549 | .eq_tail_overr_hw_ld_20 (load_over_err_eq_20), |
| 1550 | .eq_tail_overr_hw_ld_21 (load_over_err_eq_21), |
| 1551 | .eq_tail_overr_hw_ld_22 (load_over_err_eq_22), |
| 1552 | .eq_tail_overr_hw_ld_23 (load_over_err_eq_23), |
| 1553 | .eq_tail_overr_hw_ld_24 (load_over_err_eq_24), |
| 1554 | .eq_tail_overr_hw_ld_25 (load_over_err_eq_25), |
| 1555 | .eq_tail_overr_hw_ld_26 (load_over_err_eq_26), |
| 1556 | .eq_tail_overr_hw_ld_27 (load_over_err_eq_27), |
| 1557 | .eq_tail_overr_hw_ld_28 (load_over_err_eq_28), |
| 1558 | .eq_tail_overr_hw_ld_29 (load_over_err_eq_29), |
| 1559 | .eq_tail_overr_hw_ld_30 (load_over_err_eq_30), |
| 1560 | .eq_tail_overr_hw_ld_31 (load_over_err_eq_31), |
| 1561 | .eq_tail_overr_hw_ld_32 (load_over_err_eq_32), |
| 1562 | .eq_tail_overr_hw_ld_33 (load_over_err_eq_33), |
| 1563 | .eq_tail_overr_hw_ld_34 (load_over_err_eq_34), |
| 1564 | .eq_tail_overr_hw_ld_35 (load_over_err_eq_35), |
| 1565 | |
| 1566 | |
| 1567 | .eq_tail_overr_hw_write_0 (data_over_err_eq_0), |
| 1568 | .eq_tail_overr_hw_write_1 (data_over_err_eq_1), |
| 1569 | .eq_tail_overr_hw_write_2 (data_over_err_eq_2), |
| 1570 | .eq_tail_overr_hw_write_3 (data_over_err_eq_3), |
| 1571 | .eq_tail_overr_hw_write_4 (data_over_err_eq_4), |
| 1572 | .eq_tail_overr_hw_write_5 (data_over_err_eq_5), |
| 1573 | .eq_tail_overr_hw_write_6 (data_over_err_eq_6), |
| 1574 | .eq_tail_overr_hw_write_7 (data_over_err_eq_7), |
| 1575 | .eq_tail_overr_hw_write_8 (data_over_err_eq_8), |
| 1576 | .eq_tail_overr_hw_write_9 (data_over_err_eq_9), |
| 1577 | .eq_tail_overr_hw_write_10 (data_over_err_eq_10), |
| 1578 | .eq_tail_overr_hw_write_11 (data_over_err_eq_11), |
| 1579 | .eq_tail_overr_hw_write_12 (data_over_err_eq_12), |
| 1580 | .eq_tail_overr_hw_write_13 (data_over_err_eq_13), |
| 1581 | .eq_tail_overr_hw_write_14 (data_over_err_eq_14), |
| 1582 | .eq_tail_overr_hw_write_15 (data_over_err_eq_15), |
| 1583 | .eq_tail_overr_hw_write_16 (data_over_err_eq_16), |
| 1584 | .eq_tail_overr_hw_write_17 (data_over_err_eq_17), |
| 1585 | .eq_tail_overr_hw_write_18 (data_over_err_eq_18), |
| 1586 | .eq_tail_overr_hw_write_19 (data_over_err_eq_19), |
| 1587 | .eq_tail_overr_hw_write_20 (data_over_err_eq_20), |
| 1588 | .eq_tail_overr_hw_write_21 (data_over_err_eq_21), |
| 1589 | .eq_tail_overr_hw_write_22 (data_over_err_eq_22), |
| 1590 | .eq_tail_overr_hw_write_23 (data_over_err_eq_23), |
| 1591 | .eq_tail_overr_hw_write_24 (data_over_err_eq_24), |
| 1592 | .eq_tail_overr_hw_write_25 (data_over_err_eq_25), |
| 1593 | .eq_tail_overr_hw_write_26 (data_over_err_eq_26), |
| 1594 | .eq_tail_overr_hw_write_27 (data_over_err_eq_27), |
| 1595 | .eq_tail_overr_hw_write_28 (data_over_err_eq_28), |
| 1596 | .eq_tail_overr_hw_write_29 (data_over_err_eq_29), |
| 1597 | .eq_tail_overr_hw_write_30 (data_over_err_eq_30), |
| 1598 | .eq_tail_overr_hw_write_31 (data_over_err_eq_31), |
| 1599 | .eq_tail_overr_hw_write_32 (data_over_err_eq_32), |
| 1600 | .eq_tail_overr_hw_write_33 (data_over_err_eq_33), |
| 1601 | .eq_tail_overr_hw_write_34 (data_over_err_eq_34), |
| 1602 | .eq_tail_overr_hw_write_35 (data_over_err_eq_35), |
| 1603 | |
| 1604 | |
| 1605 | .eq_tail_tail_hw_ld_0 (t_ptr_inc_sel_0), |
| 1606 | .eq_tail_tail_hw_ld_1 (t_ptr_inc_sel_1), |
| 1607 | .eq_tail_tail_hw_ld_2 (t_ptr_inc_sel_2), |
| 1608 | .eq_tail_tail_hw_ld_3 (t_ptr_inc_sel_3), |
| 1609 | .eq_tail_tail_hw_ld_4 (t_ptr_inc_sel_4), |
| 1610 | .eq_tail_tail_hw_ld_5 (t_ptr_inc_sel_5), |
| 1611 | .eq_tail_tail_hw_ld_6 (t_ptr_inc_sel_6), |
| 1612 | .eq_tail_tail_hw_ld_7 (t_ptr_inc_sel_7), |
| 1613 | .eq_tail_tail_hw_ld_8 (t_ptr_inc_sel_8), |
| 1614 | .eq_tail_tail_hw_ld_9 (t_ptr_inc_sel_9), |
| 1615 | .eq_tail_tail_hw_ld_10 (t_ptr_inc_sel_10), |
| 1616 | .eq_tail_tail_hw_ld_11 (t_ptr_inc_sel_11), |
| 1617 | .eq_tail_tail_hw_ld_12 (t_ptr_inc_sel_12), |
| 1618 | .eq_tail_tail_hw_ld_13 (t_ptr_inc_sel_13), |
| 1619 | .eq_tail_tail_hw_ld_14 (t_ptr_inc_sel_14), |
| 1620 | .eq_tail_tail_hw_ld_15 (t_ptr_inc_sel_15), |
| 1621 | .eq_tail_tail_hw_ld_16 (t_ptr_inc_sel_16), |
| 1622 | .eq_tail_tail_hw_ld_17 (t_ptr_inc_sel_17), |
| 1623 | .eq_tail_tail_hw_ld_18 (t_ptr_inc_sel_18), |
| 1624 | .eq_tail_tail_hw_ld_19 (t_ptr_inc_sel_19), |
| 1625 | .eq_tail_tail_hw_ld_20 (t_ptr_inc_sel_20), |
| 1626 | .eq_tail_tail_hw_ld_21 (t_ptr_inc_sel_21), |
| 1627 | .eq_tail_tail_hw_ld_22 (t_ptr_inc_sel_22), |
| 1628 | .eq_tail_tail_hw_ld_23 (t_ptr_inc_sel_23), |
| 1629 | .eq_tail_tail_hw_ld_24 (t_ptr_inc_sel_24), |
| 1630 | .eq_tail_tail_hw_ld_25 (t_ptr_inc_sel_25), |
| 1631 | .eq_tail_tail_hw_ld_26 (t_ptr_inc_sel_26), |
| 1632 | .eq_tail_tail_hw_ld_27 (t_ptr_inc_sel_27), |
| 1633 | .eq_tail_tail_hw_ld_28 (t_ptr_inc_sel_28), |
| 1634 | .eq_tail_tail_hw_ld_29 (t_ptr_inc_sel_29), |
| 1635 | .eq_tail_tail_hw_ld_30 (t_ptr_inc_sel_30), |
| 1636 | .eq_tail_tail_hw_ld_31 (t_ptr_inc_sel_31), |
| 1637 | .eq_tail_tail_hw_ld_32 (t_ptr_inc_sel_32), |
| 1638 | .eq_tail_tail_hw_ld_33 (t_ptr_inc_sel_33), |
| 1639 | .eq_tail_tail_hw_ld_34 (t_ptr_inc_sel_34), |
| 1640 | .eq_tail_tail_hw_ld_35 (t_ptr_inc_sel_35), |
| 1641 | |
| 1642 | |
| 1643 | .eq_tail_tail_hw_write_0 (t_ptr_inc_0), |
| 1644 | .eq_tail_tail_hw_write_1 (t_ptr_inc_1), |
| 1645 | .eq_tail_tail_hw_write_2 (t_ptr_inc_2), |
| 1646 | .eq_tail_tail_hw_write_3 (t_ptr_inc_3), |
| 1647 | .eq_tail_tail_hw_write_4 (t_ptr_inc_4), |
| 1648 | .eq_tail_tail_hw_write_5 (t_ptr_inc_5), |
| 1649 | .eq_tail_tail_hw_write_6 (t_ptr_inc_6), |
| 1650 | .eq_tail_tail_hw_write_7 (t_ptr_inc_7), |
| 1651 | .eq_tail_tail_hw_write_8 (t_ptr_inc_8), |
| 1652 | .eq_tail_tail_hw_write_9 (t_ptr_inc_9), |
| 1653 | .eq_tail_tail_hw_write_10 (t_ptr_inc_10), |
| 1654 | .eq_tail_tail_hw_write_11 (t_ptr_inc_11), |
| 1655 | .eq_tail_tail_hw_write_12 (t_ptr_inc_12), |
| 1656 | .eq_tail_tail_hw_write_13 (t_ptr_inc_13), |
| 1657 | .eq_tail_tail_hw_write_14 (t_ptr_inc_14), |
| 1658 | .eq_tail_tail_hw_write_15 (t_ptr_inc_15), |
| 1659 | .eq_tail_tail_hw_write_16 (t_ptr_inc_16), |
| 1660 | .eq_tail_tail_hw_write_17 (t_ptr_inc_17), |
| 1661 | .eq_tail_tail_hw_write_18 (t_ptr_inc_18), |
| 1662 | .eq_tail_tail_hw_write_19 (t_ptr_inc_19), |
| 1663 | .eq_tail_tail_hw_write_20 (t_ptr_inc_20), |
| 1664 | .eq_tail_tail_hw_write_21 (t_ptr_inc_21), |
| 1665 | .eq_tail_tail_hw_write_22 (t_ptr_inc_22), |
| 1666 | .eq_tail_tail_hw_write_23 (t_ptr_inc_23), |
| 1667 | .eq_tail_tail_hw_write_24 (t_ptr_inc_24), |
| 1668 | .eq_tail_tail_hw_write_25 (t_ptr_inc_25), |
| 1669 | .eq_tail_tail_hw_write_26 (t_ptr_inc_26), |
| 1670 | .eq_tail_tail_hw_write_27 (t_ptr_inc_27), |
| 1671 | .eq_tail_tail_hw_write_28 (t_ptr_inc_28), |
| 1672 | .eq_tail_tail_hw_write_29 (t_ptr_inc_29), |
| 1673 | .eq_tail_tail_hw_write_30 (t_ptr_inc_30), |
| 1674 | .eq_tail_tail_hw_write_31 (t_ptr_inc_31), |
| 1675 | .eq_tail_tail_hw_write_32 (t_ptr_inc_32), |
| 1676 | .eq_tail_tail_hw_write_33 (t_ptr_inc_33), |
| 1677 | .eq_tail_tail_hw_write_34 (t_ptr_inc_34), |
| 1678 | .eq_tail_tail_hw_write_35 (t_ptr_inc_35), |
| 1679 | |
| 1680 | |
| 1681 | .eq_tail_tail_hw_read_0 (t_ptr_0), |
| 1682 | .eq_tail_tail_hw_read_1 (t_ptr_1), |
| 1683 | .eq_tail_tail_hw_read_2 (t_ptr_2), |
| 1684 | .eq_tail_tail_hw_read_3 (t_ptr_3), |
| 1685 | .eq_tail_tail_hw_read_4 (t_ptr_4), |
| 1686 | .eq_tail_tail_hw_read_5 (t_ptr_5), |
| 1687 | .eq_tail_tail_hw_read_6 (t_ptr_6), |
| 1688 | .eq_tail_tail_hw_read_7 (t_ptr_7), |
| 1689 | .eq_tail_tail_hw_read_8 (t_ptr_8), |
| 1690 | .eq_tail_tail_hw_read_9 (t_ptr_9), |
| 1691 | .eq_tail_tail_hw_read_10 (t_ptr_10), |
| 1692 | .eq_tail_tail_hw_read_11 (t_ptr_11), |
| 1693 | .eq_tail_tail_hw_read_12 (t_ptr_12), |
| 1694 | .eq_tail_tail_hw_read_13 (t_ptr_13), |
| 1695 | .eq_tail_tail_hw_read_14 (t_ptr_14), |
| 1696 | .eq_tail_tail_hw_read_15 (t_ptr_15), |
| 1697 | .eq_tail_tail_hw_read_16 (t_ptr_16), |
| 1698 | .eq_tail_tail_hw_read_17 (t_ptr_17), |
| 1699 | .eq_tail_tail_hw_read_18 (t_ptr_18), |
| 1700 | .eq_tail_tail_hw_read_19 (t_ptr_19), |
| 1701 | .eq_tail_tail_hw_read_20 (t_ptr_20), |
| 1702 | .eq_tail_tail_hw_read_21 (t_ptr_21), |
| 1703 | .eq_tail_tail_hw_read_22 (t_ptr_22), |
| 1704 | .eq_tail_tail_hw_read_23 (t_ptr_23), |
| 1705 | .eq_tail_tail_hw_read_24 (t_ptr_24), |
| 1706 | .eq_tail_tail_hw_read_25 (t_ptr_25), |
| 1707 | .eq_tail_tail_hw_read_26 (t_ptr_26), |
| 1708 | .eq_tail_tail_hw_read_27 (t_ptr_27), |
| 1709 | .eq_tail_tail_hw_read_28 (t_ptr_28), |
| 1710 | .eq_tail_tail_hw_read_29 (t_ptr_29), |
| 1711 | .eq_tail_tail_hw_read_30 (t_ptr_30), |
| 1712 | .eq_tail_tail_hw_read_31 (t_ptr_31), |
| 1713 | .eq_tail_tail_hw_read_32 (t_ptr_32), |
| 1714 | .eq_tail_tail_hw_read_33 (t_ptr_33), |
| 1715 | .eq_tail_tail_hw_read_34 (t_ptr_34), |
| 1716 | .eq_tail_tail_hw_read_35 (t_ptr_35), |
| 1717 | |
| 1718 | |
| 1719 | .eq_head_head_hw_read_0 (h_ptr_0), |
| 1720 | .eq_head_head_hw_read_1 (h_ptr_1), |
| 1721 | .eq_head_head_hw_read_2 (h_ptr_2), |
| 1722 | .eq_head_head_hw_read_3 (h_ptr_3), |
| 1723 | .eq_head_head_hw_read_4 (h_ptr_4), |
| 1724 | .eq_head_head_hw_read_5 (h_ptr_5), |
| 1725 | .eq_head_head_hw_read_6 (h_ptr_6), |
| 1726 | .eq_head_head_hw_read_7 (h_ptr_7), |
| 1727 | .eq_head_head_hw_read_8 (h_ptr_8), |
| 1728 | .eq_head_head_hw_read_9 (h_ptr_9), |
| 1729 | .eq_head_head_hw_read_10 (h_ptr_10), |
| 1730 | .eq_head_head_hw_read_11 (h_ptr_11), |
| 1731 | .eq_head_head_hw_read_12 (h_ptr_12), |
| 1732 | .eq_head_head_hw_read_13 (h_ptr_13), |
| 1733 | .eq_head_head_hw_read_14 (h_ptr_14), |
| 1734 | .eq_head_head_hw_read_15 (h_ptr_15), |
| 1735 | .eq_head_head_hw_read_16 (h_ptr_16), |
| 1736 | .eq_head_head_hw_read_17 (h_ptr_17), |
| 1737 | .eq_head_head_hw_read_18 (h_ptr_18), |
| 1738 | .eq_head_head_hw_read_19 (h_ptr_19), |
| 1739 | .eq_head_head_hw_read_20 (h_ptr_20), |
| 1740 | .eq_head_head_hw_read_21 (h_ptr_21), |
| 1741 | .eq_head_head_hw_read_22 (h_ptr_22), |
| 1742 | .eq_head_head_hw_read_23 (h_ptr_23), |
| 1743 | .eq_head_head_hw_read_24 (h_ptr_24), |
| 1744 | .eq_head_head_hw_read_25 (h_ptr_25), |
| 1745 | .eq_head_head_hw_read_26 (h_ptr_26), |
| 1746 | .eq_head_head_hw_read_27 (h_ptr_27), |
| 1747 | .eq_head_head_hw_read_28 (h_ptr_28), |
| 1748 | .eq_head_head_hw_read_29 (h_ptr_29), |
| 1749 | .eq_head_head_hw_read_30 (h_ptr_30), |
| 1750 | .eq_head_head_hw_read_31 (h_ptr_31), |
| 1751 | .eq_head_head_hw_read_32 (h_ptr_32), |
| 1752 | .eq_head_head_hw_read_33 (h_ptr_33), |
| 1753 | .eq_head_head_hw_read_34 (h_ptr_34), |
| 1754 | .eq_head_head_hw_read_35 (h_ptr_35) |
| 1755 | |
| 1756 | ); |
| 1757 | |
| 1758 | |
| 1759 | dmu_imu_eqs_fsm fsm_0 ( //------ |
| 1760 | // EQ 0 |
| 1761 | .clk (clk), //------ |
| 1762 | .rst_l (rst_l), |
| 1763 | |
| 1764 | .set_over_err (set_over_err_eq_0), |
| 1765 | |
| 1766 | |
| 1767 | .sw_wr (eq_fsm_wr), |
| 1768 | .sw_set_addr_sel (sw_set_addr_sel_eq_0), |
| 1769 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_0), |
| 1770 | .sw_wr_data (eq_fsm_wr_data), |
| 1771 | |
| 1772 | .eq_state (eq_state_0)); |
| 1773 | |
| 1774 | |
| 1775 | dmu_imu_eqs_fsm fsm_1 ( //------ |
| 1776 | // EQ 1 |
| 1777 | .clk (clk), //------ |
| 1778 | .rst_l (rst_l), |
| 1779 | |
| 1780 | .set_over_err (set_over_err_eq_1), |
| 1781 | |
| 1782 | |
| 1783 | .sw_wr (eq_fsm_wr), |
| 1784 | .sw_set_addr_sel (sw_set_addr_sel_eq_1), |
| 1785 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_1), |
| 1786 | .sw_wr_data (eq_fsm_wr_data), |
| 1787 | |
| 1788 | .eq_state (eq_state_1)); |
| 1789 | |
| 1790 | dmu_imu_eqs_fsm fsm_2 ( //------ |
| 1791 | // EQ 2 |
| 1792 | .clk (clk), //------ |
| 1793 | .rst_l (rst_l), |
| 1794 | |
| 1795 | .set_over_err (set_over_err_eq_2), |
| 1796 | |
| 1797 | .sw_wr (eq_fsm_wr), |
| 1798 | .sw_set_addr_sel (sw_set_addr_sel_eq_2), |
| 1799 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_2), |
| 1800 | .sw_wr_data (eq_fsm_wr_data), |
| 1801 | |
| 1802 | .eq_state (eq_state_2)); |
| 1803 | |
| 1804 | |
| 1805 | dmu_imu_eqs_fsm fsm_3 ( //------ |
| 1806 | // EQ 3 |
| 1807 | .clk (clk), //------ |
| 1808 | .rst_l (rst_l), |
| 1809 | |
| 1810 | .set_over_err (set_over_err_eq_3), |
| 1811 | |
| 1812 | .sw_wr (eq_fsm_wr), |
| 1813 | .sw_set_addr_sel (sw_set_addr_sel_eq_3), |
| 1814 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_3), |
| 1815 | .sw_wr_data (eq_fsm_wr_data), |
| 1816 | |
| 1817 | .eq_state (eq_state_3)); |
| 1818 | |
| 1819 | |
| 1820 | dmu_imu_eqs_fsm fsm_4 ( //------ |
| 1821 | // EQ 4 |
| 1822 | .clk (clk), //------ |
| 1823 | .rst_l (rst_l), |
| 1824 | |
| 1825 | .set_over_err (set_over_err_eq_4), |
| 1826 | |
| 1827 | .sw_wr (eq_fsm_wr), |
| 1828 | .sw_set_addr_sel (sw_set_addr_sel_eq_4), |
| 1829 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_4), |
| 1830 | .sw_wr_data (eq_fsm_wr_data), |
| 1831 | |
| 1832 | .eq_state (eq_state_4)); |
| 1833 | |
| 1834 | dmu_imu_eqs_fsm fsm_5 ( //------ |
| 1835 | // EQ 5 |
| 1836 | .clk (clk), //------ |
| 1837 | .rst_l (rst_l), |
| 1838 | |
| 1839 | .set_over_err (set_over_err_eq_5), |
| 1840 | |
| 1841 | .sw_wr (eq_fsm_wr), |
| 1842 | .sw_set_addr_sel (sw_set_addr_sel_eq_5), |
| 1843 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_5), |
| 1844 | .sw_wr_data (eq_fsm_wr_data), |
| 1845 | |
| 1846 | .eq_state (eq_state_5)); |
| 1847 | |
| 1848 | dmu_imu_eqs_fsm fsm_6 ( //------ |
| 1849 | // EQ 6 |
| 1850 | .clk (clk), //------ |
| 1851 | .rst_l (rst_l), |
| 1852 | |
| 1853 | .set_over_err (set_over_err_eq_6), |
| 1854 | |
| 1855 | .sw_wr (eq_fsm_wr), |
| 1856 | .sw_set_addr_sel (sw_set_addr_sel_eq_6), |
| 1857 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_6), |
| 1858 | .sw_wr_data (eq_fsm_wr_data), |
| 1859 | |
| 1860 | .eq_state (eq_state_6)); |
| 1861 | |
| 1862 | |
| 1863 | dmu_imu_eqs_fsm fsm_7 ( //------ |
| 1864 | // EQ 7 |
| 1865 | .clk (clk), //------ |
| 1866 | .rst_l (rst_l), |
| 1867 | |
| 1868 | .set_over_err (set_over_err_eq_7), |
| 1869 | |
| 1870 | .sw_wr (eq_fsm_wr), |
| 1871 | .sw_set_addr_sel (sw_set_addr_sel_eq_7), |
| 1872 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_7), |
| 1873 | .sw_wr_data (eq_fsm_wr_data), |
| 1874 | |
| 1875 | .eq_state (eq_state_7)); |
| 1876 | |
| 1877 | dmu_imu_eqs_fsm fsm_8 ( //------ |
| 1878 | // EQ 8 |
| 1879 | .clk (clk), //------ |
| 1880 | .rst_l (rst_l), |
| 1881 | |
| 1882 | .set_over_err (set_over_err_eq_8), |
| 1883 | |
| 1884 | .sw_wr (eq_fsm_wr), |
| 1885 | .sw_set_addr_sel (sw_set_addr_sel_eq_8), |
| 1886 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_8), |
| 1887 | .sw_wr_data (eq_fsm_wr_data), |
| 1888 | |
| 1889 | .eq_state (eq_state_8)); |
| 1890 | |
| 1891 | dmu_imu_eqs_fsm fsm_9 ( //------ |
| 1892 | // EQ 9 |
| 1893 | .clk (clk), //------ |
| 1894 | .rst_l (rst_l), |
| 1895 | |
| 1896 | .set_over_err (set_over_err_eq_9), |
| 1897 | |
| 1898 | .sw_wr (eq_fsm_wr), |
| 1899 | .sw_set_addr_sel (sw_set_addr_sel_eq_9), |
| 1900 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_9), |
| 1901 | .sw_wr_data (eq_fsm_wr_data), |
| 1902 | |
| 1903 | .eq_state (eq_state_9)); |
| 1904 | |
| 1905 | |
| 1906 | dmu_imu_eqs_fsm fsm_10 ( //------ |
| 1907 | // EQ 10 |
| 1908 | .clk (clk), //------ |
| 1909 | .rst_l (rst_l), |
| 1910 | |
| 1911 | .set_over_err (set_over_err_eq_10), |
| 1912 | |
| 1913 | .sw_wr (eq_fsm_wr), |
| 1914 | .sw_set_addr_sel (sw_set_addr_sel_eq_10), |
| 1915 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_10), |
| 1916 | .sw_wr_data (eq_fsm_wr_data), |
| 1917 | |
| 1918 | .eq_state (eq_state_10)); |
| 1919 | |
| 1920 | dmu_imu_eqs_fsm fsm_11 ( //------ |
| 1921 | // EQ 11 |
| 1922 | .clk (clk), //------ |
| 1923 | .rst_l (rst_l), |
| 1924 | |
| 1925 | .set_over_err (set_over_err_eq_11), |
| 1926 | |
| 1927 | .sw_wr (eq_fsm_wr), |
| 1928 | .sw_set_addr_sel (sw_set_addr_sel_eq_11), |
| 1929 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_11), |
| 1930 | .sw_wr_data (eq_fsm_wr_data), |
| 1931 | |
| 1932 | .eq_state (eq_state_11)); |
| 1933 | |
| 1934 | dmu_imu_eqs_fsm fsm_12 ( //------ |
| 1935 | // EQ 12 |
| 1936 | .clk (clk), //------ |
| 1937 | .rst_l (rst_l), |
| 1938 | |
| 1939 | .set_over_err (set_over_err_eq_12), |
| 1940 | |
| 1941 | .sw_wr (eq_fsm_wr), |
| 1942 | .sw_set_addr_sel (sw_set_addr_sel_eq_12), |
| 1943 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_12), |
| 1944 | .sw_wr_data (eq_fsm_wr_data), |
| 1945 | |
| 1946 | .eq_state (eq_state_12)); |
| 1947 | |
| 1948 | |
| 1949 | dmu_imu_eqs_fsm fsm_13 ( //------ |
| 1950 | // EQ 13 |
| 1951 | .clk (clk), //------ |
| 1952 | .rst_l (rst_l), |
| 1953 | |
| 1954 | .set_over_err (set_over_err_eq_13), |
| 1955 | |
| 1956 | .sw_wr (eq_fsm_wr), |
| 1957 | .sw_set_addr_sel (sw_set_addr_sel_eq_13), |
| 1958 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_13), |
| 1959 | .sw_wr_data (eq_fsm_wr_data), |
| 1960 | |
| 1961 | .eq_state (eq_state_13)); |
| 1962 | |
| 1963 | dmu_imu_eqs_fsm fsm_14 ( //------ |
| 1964 | // EQ 14 |
| 1965 | .clk (clk), //------ |
| 1966 | .rst_l (rst_l), |
| 1967 | |
| 1968 | .set_over_err (set_over_err_eq_14), |
| 1969 | |
| 1970 | .sw_wr (eq_fsm_wr), |
| 1971 | .sw_set_addr_sel (sw_set_addr_sel_eq_14), |
| 1972 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_14), |
| 1973 | .sw_wr_data (eq_fsm_wr_data), |
| 1974 | |
| 1975 | .eq_state (eq_state_14)); |
| 1976 | |
| 1977 | dmu_imu_eqs_fsm fsm_15 ( //------ |
| 1978 | // EQ 15 |
| 1979 | .clk (clk), //------ |
| 1980 | .rst_l (rst_l), |
| 1981 | |
| 1982 | .set_over_err (set_over_err_eq_15), |
| 1983 | |
| 1984 | .sw_wr (eq_fsm_wr), |
| 1985 | .sw_set_addr_sel (sw_set_addr_sel_eq_15), |
| 1986 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_15), |
| 1987 | .sw_wr_data (eq_fsm_wr_data), |
| 1988 | |
| 1989 | .eq_state (eq_state_15)); |
| 1990 | |
| 1991 | |
| 1992 | |
| 1993 | dmu_imu_eqs_fsm fsm_16 ( //------ |
| 1994 | // EQ 16 |
| 1995 | .clk (clk), //------ |
| 1996 | .rst_l (rst_l), |
| 1997 | |
| 1998 | .set_over_err (set_over_err_eq_16), |
| 1999 | |
| 2000 | .sw_wr (eq_fsm_wr), |
| 2001 | .sw_set_addr_sel (sw_set_addr_sel_eq_16), |
| 2002 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_16), |
| 2003 | .sw_wr_data (eq_fsm_wr_data), |
| 2004 | |
| 2005 | .eq_state (eq_state_16)); |
| 2006 | |
| 2007 | |
| 2008 | dmu_imu_eqs_fsm fsm_17 ( //------ |
| 2009 | // EQ 17 |
| 2010 | .clk (clk), //------ |
| 2011 | .rst_l (rst_l), |
| 2012 | |
| 2013 | .set_over_err (set_over_err_eq_17), |
| 2014 | |
| 2015 | .sw_wr (eq_fsm_wr), |
| 2016 | .sw_set_addr_sel (sw_set_addr_sel_eq_17), |
| 2017 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_17), |
| 2018 | .sw_wr_data (eq_fsm_wr_data), |
| 2019 | |
| 2020 | .eq_state (eq_state_17)); |
| 2021 | |
| 2022 | dmu_imu_eqs_fsm fsm_18 ( //------ |
| 2023 | // EQ 18 |
| 2024 | .clk (clk), //------ |
| 2025 | .rst_l (rst_l), |
| 2026 | |
| 2027 | .set_over_err (set_over_err_eq_18), |
| 2028 | |
| 2029 | .sw_wr (eq_fsm_wr), |
| 2030 | .sw_set_addr_sel (sw_set_addr_sel_eq_18), |
| 2031 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_18), |
| 2032 | .sw_wr_data (eq_fsm_wr_data), |
| 2033 | |
| 2034 | .eq_state (eq_state_18)); |
| 2035 | |
| 2036 | dmu_imu_eqs_fsm fsm_19 ( //------ |
| 2037 | // EQ 19 |
| 2038 | .clk (clk), //------ |
| 2039 | .rst_l (rst_l), |
| 2040 | |
| 2041 | .set_over_err (set_over_err_eq_19), |
| 2042 | |
| 2043 | .sw_wr (eq_fsm_wr), |
| 2044 | .sw_set_addr_sel (sw_set_addr_sel_eq_19), |
| 2045 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_19), |
| 2046 | .sw_wr_data (eq_fsm_wr_data), |
| 2047 | |
| 2048 | .eq_state (eq_state_19)); |
| 2049 | |
| 2050 | |
| 2051 | |
| 2052 | dmu_imu_eqs_fsm fsm_20 ( //------ |
| 2053 | // EQ 20 |
| 2054 | .clk (clk), //------ |
| 2055 | .rst_l (rst_l), |
| 2056 | |
| 2057 | .set_over_err (set_over_err_eq_20), |
| 2058 | |
| 2059 | |
| 2060 | .sw_wr (eq_fsm_wr), |
| 2061 | .sw_set_addr_sel (sw_set_addr_sel_eq_20), |
| 2062 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_20), |
| 2063 | .sw_wr_data (eq_fsm_wr_data), |
| 2064 | |
| 2065 | .eq_state (eq_state_20)); |
| 2066 | |
| 2067 | |
| 2068 | dmu_imu_eqs_fsm fsm_21 ( //------ |
| 2069 | // EQ 21 |
| 2070 | .clk (clk), //------ |
| 2071 | .rst_l (rst_l), |
| 2072 | |
| 2073 | .set_over_err (set_over_err_eq_21), |
| 2074 | |
| 2075 | |
| 2076 | .sw_wr (eq_fsm_wr), |
| 2077 | .sw_set_addr_sel (sw_set_addr_sel_eq_21), |
| 2078 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_21), |
| 2079 | .sw_wr_data (eq_fsm_wr_data), |
| 2080 | |
| 2081 | .eq_state (eq_state_21)); |
| 2082 | |
| 2083 | dmu_imu_eqs_fsm fsm_22 ( //------ |
| 2084 | // EQ 22 |
| 2085 | .clk (clk), //------ |
| 2086 | .rst_l (rst_l), |
| 2087 | |
| 2088 | .set_over_err (set_over_err_eq_22), |
| 2089 | |
| 2090 | .sw_wr (eq_fsm_wr), |
| 2091 | .sw_set_addr_sel (sw_set_addr_sel_eq_22), |
| 2092 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_22), |
| 2093 | .sw_wr_data (eq_fsm_wr_data), |
| 2094 | |
| 2095 | .eq_state (eq_state_22)); |
| 2096 | |
| 2097 | |
| 2098 | dmu_imu_eqs_fsm fsm_23 ( //------ |
| 2099 | // EQ 23 |
| 2100 | .clk (clk), //------ |
| 2101 | .rst_l (rst_l), |
| 2102 | |
| 2103 | .set_over_err (set_over_err_eq_23), |
| 2104 | |
| 2105 | .sw_wr (eq_fsm_wr), |
| 2106 | .sw_set_addr_sel (sw_set_addr_sel_eq_23), |
| 2107 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_23), |
| 2108 | .sw_wr_data (eq_fsm_wr_data), |
| 2109 | |
| 2110 | .eq_state (eq_state_23)); |
| 2111 | |
| 2112 | |
| 2113 | dmu_imu_eqs_fsm fsm_24 ( //------ |
| 2114 | // EQ 24 |
| 2115 | .clk (clk), //------ |
| 2116 | .rst_l (rst_l), |
| 2117 | |
| 2118 | .set_over_err (set_over_err_eq_24), |
| 2119 | |
| 2120 | .sw_wr (eq_fsm_wr), |
| 2121 | .sw_set_addr_sel (sw_set_addr_sel_eq_24), |
| 2122 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_24), |
| 2123 | .sw_wr_data (eq_fsm_wr_data), |
| 2124 | |
| 2125 | .eq_state (eq_state_24)); |
| 2126 | |
| 2127 | dmu_imu_eqs_fsm fsm_25 ( //------ |
| 2128 | // EQ 25 |
| 2129 | .clk (clk), //------ |
| 2130 | .rst_l (rst_l), |
| 2131 | |
| 2132 | .set_over_err (set_over_err_eq_25), |
| 2133 | |
| 2134 | .sw_wr (eq_fsm_wr), |
| 2135 | .sw_set_addr_sel (sw_set_addr_sel_eq_25), |
| 2136 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_25), |
| 2137 | .sw_wr_data (eq_fsm_wr_data), |
| 2138 | |
| 2139 | .eq_state (eq_state_25)); |
| 2140 | |
| 2141 | dmu_imu_eqs_fsm fsm_26 ( //------ |
| 2142 | // EQ 26 |
| 2143 | .clk (clk), //------ |
| 2144 | .rst_l (rst_l), |
| 2145 | |
| 2146 | .set_over_err (set_over_err_eq_26), |
| 2147 | |
| 2148 | .sw_wr (eq_fsm_wr), |
| 2149 | .sw_set_addr_sel (sw_set_addr_sel_eq_26), |
| 2150 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_26), |
| 2151 | .sw_wr_data (eq_fsm_wr_data), |
| 2152 | |
| 2153 | .eq_state (eq_state_26)); |
| 2154 | |
| 2155 | |
| 2156 | dmu_imu_eqs_fsm fsm_27 ( //------ |
| 2157 | // EQ 27 |
| 2158 | .clk (clk), //------ |
| 2159 | .rst_l (rst_l), |
| 2160 | |
| 2161 | .set_over_err (set_over_err_eq_27), |
| 2162 | |
| 2163 | .sw_wr (eq_fsm_wr), |
| 2164 | .sw_set_addr_sel (sw_set_addr_sel_eq_27), |
| 2165 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_27), |
| 2166 | .sw_wr_data (eq_fsm_wr_data), |
| 2167 | |
| 2168 | .eq_state (eq_state_27)); |
| 2169 | |
| 2170 | dmu_imu_eqs_fsm fsm_28 ( //------ |
| 2171 | // EQ 28 |
| 2172 | .clk (clk), //------ |
| 2173 | .rst_l (rst_l), |
| 2174 | |
| 2175 | .set_over_err (set_over_err_eq_28), |
| 2176 | |
| 2177 | .sw_wr (eq_fsm_wr), |
| 2178 | .sw_set_addr_sel (sw_set_addr_sel_eq_28), |
| 2179 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_28), |
| 2180 | .sw_wr_data (eq_fsm_wr_data), |
| 2181 | |
| 2182 | .eq_state (eq_state_28)); |
| 2183 | |
| 2184 | dmu_imu_eqs_fsm fsm_29 ( //------ |
| 2185 | // EQ 29 |
| 2186 | .clk (clk), //------ |
| 2187 | .rst_l (rst_l), |
| 2188 | |
| 2189 | .set_over_err (set_over_err_eq_29), |
| 2190 | |
| 2191 | .sw_wr (eq_fsm_wr), |
| 2192 | .sw_set_addr_sel (sw_set_addr_sel_eq_29), |
| 2193 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_29), |
| 2194 | .sw_wr_data (eq_fsm_wr_data), |
| 2195 | |
| 2196 | .eq_state (eq_state_29)); |
| 2197 | |
| 2198 | |
| 2199 | |
| 2200 | |
| 2201 | dmu_imu_eqs_fsm fsm_30 ( //------ |
| 2202 | // EQ 30 |
| 2203 | .clk (clk), //------ |
| 2204 | .rst_l (rst_l), |
| 2205 | |
| 2206 | .set_over_err (set_over_err_eq_30), |
| 2207 | |
| 2208 | |
| 2209 | .sw_wr (eq_fsm_wr), |
| 2210 | .sw_set_addr_sel (sw_set_addr_sel_eq_30), |
| 2211 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_30), |
| 2212 | .sw_wr_data (eq_fsm_wr_data), |
| 2213 | |
| 2214 | .eq_state (eq_state_30)); |
| 2215 | |
| 2216 | |
| 2217 | dmu_imu_eqs_fsm fsm_31 ( //------ |
| 2218 | // EQ 31 |
| 2219 | .clk (clk), //------ |
| 2220 | .rst_l (rst_l), |
| 2221 | |
| 2222 | .set_over_err (set_over_err_eq_31), |
| 2223 | |
| 2224 | |
| 2225 | .sw_wr (eq_fsm_wr), |
| 2226 | .sw_set_addr_sel (sw_set_addr_sel_eq_31), |
| 2227 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_31), |
| 2228 | .sw_wr_data (eq_fsm_wr_data), |
| 2229 | |
| 2230 | .eq_state (eq_state_31)); |
| 2231 | |
| 2232 | dmu_imu_eqs_fsm fsm_32 ( //------ |
| 2233 | // EQ 32 |
| 2234 | .clk (clk), //------ |
| 2235 | .rst_l (rst_l), |
| 2236 | |
| 2237 | .set_over_err (set_over_err_eq_32), |
| 2238 | |
| 2239 | .sw_wr (eq_fsm_wr), |
| 2240 | .sw_set_addr_sel (sw_set_addr_sel_eq_32), |
| 2241 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_32), |
| 2242 | .sw_wr_data (eq_fsm_wr_data), |
| 2243 | |
| 2244 | .eq_state (eq_state_32)); |
| 2245 | |
| 2246 | |
| 2247 | dmu_imu_eqs_fsm fsm_33 ( //------ |
| 2248 | // EQ 33 |
| 2249 | .clk (clk), //------ |
| 2250 | .rst_l (rst_l), |
| 2251 | |
| 2252 | .set_over_err (set_over_err_eq_33), |
| 2253 | |
| 2254 | .sw_wr (eq_fsm_wr), |
| 2255 | .sw_set_addr_sel (sw_set_addr_sel_eq_33), |
| 2256 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_33), |
| 2257 | .sw_wr_data (eq_fsm_wr_data), |
| 2258 | |
| 2259 | .eq_state (eq_state_33)); |
| 2260 | |
| 2261 | |
| 2262 | dmu_imu_eqs_fsm fsm_34 ( //------ |
| 2263 | // EQ 34 |
| 2264 | .clk (clk), //------ |
| 2265 | .rst_l (rst_l), |
| 2266 | |
| 2267 | .set_over_err (set_over_err_eq_34), |
| 2268 | |
| 2269 | .sw_wr (eq_fsm_wr), |
| 2270 | .sw_set_addr_sel (sw_set_addr_sel_eq_34), |
| 2271 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_34), |
| 2272 | .sw_wr_data (eq_fsm_wr_data), |
| 2273 | |
| 2274 | .eq_state (eq_state_34)); |
| 2275 | |
| 2276 | dmu_imu_eqs_fsm fsm_35 ( //------ |
| 2277 | // EQ 35 |
| 2278 | .clk (clk), //------ |
| 2279 | .rst_l (rst_l), |
| 2280 | |
| 2281 | .set_over_err (set_over_err_eq_35), |
| 2282 | |
| 2283 | .sw_wr (eq_fsm_wr), |
| 2284 | .sw_set_addr_sel (sw_set_addr_sel_eq_35), |
| 2285 | .sw_clr_addr_sel (sw_clr_addr_sel_eq_35), |
| 2286 | .sw_wr_data (eq_fsm_wr_data), |
| 2287 | |
| 2288 | .eq_state (eq_state_35)); |
| 2289 | |
| 2290 | |
| 2291 | |
| 2292 | endmodule |