| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_gcs_gc_cnt.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_gcs_gc_cnt ( |
| 36 | |
| 37 | // Clock and Reset |
| 38 | |
| 39 | clk, |
| 40 | rst_l, |
| 41 | |
| 42 | // Interface for Interrupt Retry Timer |
| 43 | |
| 44 | timer_start, |
| 45 | timer_done, |
| 46 | |
| 47 | // Interface for Static Value for Counter |
| 48 | |
| 49 | iss2gcs_counter_limit |
| 50 | |
| 51 | ); |
| 52 | |
| 53 | |
| 54 | //############################################################################ |
| 55 | // PORT DECLARATIONS |
| 56 | //############################################################################ |
| 57 | |
| 58 | //------------------------------------------------------------------------ |
| 59 | // Clock and Reset Signals |
| 60 | //------------------------------------------------------------------------ |
| 61 | |
| 62 | input clk; |
| 63 | input rst_l; |
| 64 | |
| 65 | |
| 66 | //----------------------------------------------------- |
| 67 | // Interface for Interrupt Retry Timer |
| 68 | //----------------------------------------------------- |
| 69 | |
| 70 | input timer_start; // Signal to start retry timer |
| 71 | output timer_done; // SIgnal showing the retry timer is done |
| 72 | |
| 73 | //----------------------------------------------------- |
| 74 | // Interface for Static Value for Counter |
| 75 | //----------------------------------------------------- |
| 76 | |
| 77 | input [24:0] iss2gcs_counter_limit; // Limit the counter counts down from |
| 78 | |
| 79 | //############################################################################ |
| 80 | // SIGNAL DECLARATIONS |
| 81 | //############################################################################ |
| 82 | |
| 83 | //------------------------ |
| 84 | // Regs that are flops |
| 85 | //------------------------ |
| 86 | |
| 87 | reg counter_armed; |
| 88 | reg [24:0] cnt; |
| 89 | |
| 90 | |
| 91 | //############################################################################ |
| 92 | // ZERO IN CHECKERS |
| 93 | //############################################################################ |
| 94 | // 0in req_ack -req timer_start -ack timer_done -max_ack 1 |
| 95 | |
| 96 | |
| 97 | //############################################################################ |
| 98 | // COMBINATIONAL LOGIC |
| 99 | //############################################################################ |
| 100 | |
| 101 | //----------------------------------------------------------------------- |
| 102 | // Assign the output going back to the group controller state machine |
| 103 | // - When the counter reaches zero and the counter is armed |
| 104 | // - This takes care of reset |
| 105 | //----------------------------------------------------------------------- |
| 106 | |
| 107 | assign timer_done = counter_armed & (cnt == 25'h00000); |
| 108 | |
| 109 | //############################################################################ |
| 110 | // SEQUENTIAL LOGIC |
| 111 | //############################################################################ |
| 112 | |
| 113 | |
| 114 | //----------------------------------------------------------------------- |
| 115 | // Counter Arm logic to prevent false firing of counter_done |
| 116 | // - Counter is only armed when counter start is pulsed |
| 117 | // - COunter is unarmed when counter reaches zero |
| 118 | //----------------------------------------------------------------------- |
| 119 | always @(posedge clk) |
| 120 | begin |
| 121 | if (~rst_l | timer_done) // When the timer reaches zero dis-arm itor at reset |
| 122 | begin |
| 123 | counter_armed <= 1'b0; |
| 124 | end |
| 125 | else if (timer_start) // When group control says start, arm timer |
| 126 | begin |
| 127 | counter_armed <= 1'b1; |
| 128 | end |
| 129 | else |
| 130 | begin |
| 131 | counter_armed <= counter_armed; // Hold the current value |
| 132 | end |
| 133 | end |
| 134 | |
| 135 | //----------------------------------------------------------------------- |
| 136 | // Counter Logic |
| 137 | // - When timer_start pulses the limit is loaded into the counter |
| 138 | // and the counter is started |
| 139 | // - The counter counts down and will continue until it reaches zero |
| 140 | //----------------------------------------------------------------------- |
| 141 | always @(posedge clk) |
| 142 | begin |
| 143 | if (~rst_l) // Reset the counter to zero |
| 144 | begin |
| 145 | cnt <= 25'h0; |
| 146 | end |
| 147 | else if (timer_start) // WHen started load the CSR count down value |
| 148 | begin |
| 149 | cnt <= iss2gcs_counter_limit; |
| 150 | end |
| 151 | else |
| 152 | begin |
| 153 | if(counter_armed & (|cnt)) // Decrement if armed and above zero |
| 154 | cnt <= cnt - 1; //0in < decrement -var cnt |
| 155 | else |
| 156 | cnt <= cnt; |
| 157 | end |
| 158 | end |
| 159 | |
| 160 | |
| 161 | endmodule |