| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_ics_csr_mem_64_pcie_offset_reg.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_ics_csr_mem_64_pcie_offset_reg |
| 36 | ( |
| 37 | clk, |
| 38 | rst_l, |
| 39 | mem_64_pcie_offset_reg_w_ld, |
| 40 | csrbus_wr_data, |
| 41 | mem_64_pcie_offset_reg_csrbus_read_data, |
| 42 | mem_64_pcie_offset_reg_addr_hw_read, |
| 43 | mem_64_pcie_offset_reg_spare_control_load_7_hw_ld, |
| 44 | mem_64_pcie_offset_reg_spare_control_load_7_hw_write, |
| 45 | mem_64_pcie_offset_reg_spare_control_load_7_hw_read, |
| 46 | mem_64_pcie_offset_reg_spare_control_load_6_hw_ld, |
| 47 | mem_64_pcie_offset_reg_spare_control_load_6_hw_write, |
| 48 | mem_64_pcie_offset_reg_spare_control_load_6_hw_read, |
| 49 | mem_64_pcie_offset_reg_spare_control_load_5_hw_ld, |
| 50 | mem_64_pcie_offset_reg_spare_control_load_5_hw_write, |
| 51 | mem_64_pcie_offset_reg_spare_control_load_5_hw_read, |
| 52 | mem_64_pcie_offset_reg_spare_control_load_4_hw_ld, |
| 53 | mem_64_pcie_offset_reg_spare_control_load_4_hw_write, |
| 54 | mem_64_pcie_offset_reg_spare_control_load_4_hw_read, |
| 55 | mem_64_pcie_offset_reg_spare_control_load_3_hw_ld, |
| 56 | mem_64_pcie_offset_reg_spare_control_load_3_hw_write, |
| 57 | mem_64_pcie_offset_reg_spare_control_load_3_hw_read, |
| 58 | mem_64_pcie_offset_reg_spare_control_load_2_hw_ld, |
| 59 | mem_64_pcie_offset_reg_spare_control_load_2_hw_write, |
| 60 | mem_64_pcie_offset_reg_spare_control_load_2_hw_read, |
| 61 | mem_64_pcie_offset_reg_spare_control_load_1_hw_ld, |
| 62 | mem_64_pcie_offset_reg_spare_control_load_1_hw_write, |
| 63 | mem_64_pcie_offset_reg_spare_control_load_1_hw_read, |
| 64 | mem_64_pcie_offset_reg_spare_control_load_0_hw_ld, |
| 65 | mem_64_pcie_offset_reg_spare_control_load_0_hw_write, |
| 66 | mem_64_pcie_offset_reg_spare_control_load_0_hw_read, |
| 67 | mem_64_pcie_offset_reg_spare_control_hw_write, |
| 68 | mem_64_pcie_offset_reg_spare_control_hw_read, |
| 69 | mem_64_pcie_offset_reg_spare_status_hw_read |
| 70 | ); |
| 71 | |
| 72 | //==================================================================== |
| 73 | // Polarity declarations |
| 74 | //==================================================================== |
| 75 | input clk; // Clock |
| 76 | input rst_l; // Reset signal |
| 77 | input mem_64_pcie_offset_reg_w_ld; // SW load bus |
| 78 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 79 | output [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WIDTH-1:0] mem_64_pcie_offset_reg_csrbus_read_data; |
| 80 | // SW read data |
| 81 | output [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_INT_SLC] mem_64_pcie_offset_reg_addr_hw_read; |
| 82 | // This signal provides the current value of mem_64_pcie_offset_reg_addr. |
| 83 | input mem_64_pcie_offset_reg_spare_control_load_7_hw_ld; // Hardware load |
| 84 | // enable for |
| 85 | // mem_64_pcie_offset_reg_spare_control_load_7. |
| 86 | // When set, <hw |
| 87 | // write signal> |
| 88 | // will be loaded |
| 89 | // into |
| 90 | // mem_64_pcie_offset_reg. |
| 91 | input mem_64_pcie_offset_reg_spare_control_load_7_hw_write; // data bus for hw |
| 92 | // loading of |
| 93 | // mem_64_pcie_offset_reg_spare_control_load_7. |
| 94 | output mem_64_pcie_offset_reg_spare_control_load_7_hw_read; // This signal |
| 95 | // provides the |
| 96 | // current value of |
| 97 | // mem_64_pcie_offset_reg_spare_control_load_7. |
| 98 | input mem_64_pcie_offset_reg_spare_control_load_6_hw_ld; // Hardware load |
| 99 | // enable for |
| 100 | // mem_64_pcie_offset_reg_spare_control_load_6. |
| 101 | // When set, <hw |
| 102 | // write signal> |
| 103 | // will be loaded |
| 104 | // into |
| 105 | // mem_64_pcie_offset_reg. |
| 106 | input mem_64_pcie_offset_reg_spare_control_load_6_hw_write; // data bus for hw |
| 107 | // loading of |
| 108 | // mem_64_pcie_offset_reg_spare_control_load_6. |
| 109 | output mem_64_pcie_offset_reg_spare_control_load_6_hw_read; // This signal |
| 110 | // provides the |
| 111 | // current value of |
| 112 | // mem_64_pcie_offset_reg_spare_control_load_6. |
| 113 | input mem_64_pcie_offset_reg_spare_control_load_5_hw_ld; // Hardware load |
| 114 | // enable for |
| 115 | // mem_64_pcie_offset_reg_spare_control_load_5. |
| 116 | // When set, <hw |
| 117 | // write signal> |
| 118 | // will be loaded |
| 119 | // into |
| 120 | // mem_64_pcie_offset_reg. |
| 121 | input mem_64_pcie_offset_reg_spare_control_load_5_hw_write; // data bus for hw |
| 122 | // loading of |
| 123 | // mem_64_pcie_offset_reg_spare_control_load_5. |
| 124 | output mem_64_pcie_offset_reg_spare_control_load_5_hw_read; // This signal |
| 125 | // provides the |
| 126 | // current value of |
| 127 | // mem_64_pcie_offset_reg_spare_control_load_5. |
| 128 | input mem_64_pcie_offset_reg_spare_control_load_4_hw_ld; // Hardware load |
| 129 | // enable for |
| 130 | // mem_64_pcie_offset_reg_spare_control_load_4. |
| 131 | // When set, <hw |
| 132 | // write signal> |
| 133 | // will be loaded |
| 134 | // into |
| 135 | // mem_64_pcie_offset_reg. |
| 136 | input mem_64_pcie_offset_reg_spare_control_load_4_hw_write; // data bus for hw |
| 137 | // loading of |
| 138 | // mem_64_pcie_offset_reg_spare_control_load_4. |
| 139 | output mem_64_pcie_offset_reg_spare_control_load_4_hw_read; // This signal |
| 140 | // provides the |
| 141 | // current value of |
| 142 | // mem_64_pcie_offset_reg_spare_control_load_4. |
| 143 | input mem_64_pcie_offset_reg_spare_control_load_3_hw_ld; // Hardware load |
| 144 | // enable for |
| 145 | // mem_64_pcie_offset_reg_spare_control_load_3. |
| 146 | // When set, <hw |
| 147 | // write signal> |
| 148 | // will be loaded |
| 149 | // into |
| 150 | // mem_64_pcie_offset_reg. |
| 151 | input mem_64_pcie_offset_reg_spare_control_load_3_hw_write; // data bus for hw |
| 152 | // loading of |
| 153 | // mem_64_pcie_offset_reg_spare_control_load_3. |
| 154 | output mem_64_pcie_offset_reg_spare_control_load_3_hw_read; // This signal |
| 155 | // provides the |
| 156 | // current value of |
| 157 | // mem_64_pcie_offset_reg_spare_control_load_3. |
| 158 | input mem_64_pcie_offset_reg_spare_control_load_2_hw_ld; // Hardware load |
| 159 | // enable for |
| 160 | // mem_64_pcie_offset_reg_spare_control_load_2. |
| 161 | // When set, <hw |
| 162 | // write signal> |
| 163 | // will be loaded |
| 164 | // into |
| 165 | // mem_64_pcie_offset_reg. |
| 166 | input mem_64_pcie_offset_reg_spare_control_load_2_hw_write; // data bus for hw |
| 167 | // loading of |
| 168 | // mem_64_pcie_offset_reg_spare_control_load_2. |
| 169 | output mem_64_pcie_offset_reg_spare_control_load_2_hw_read; // This signal |
| 170 | // provides the |
| 171 | // current value of |
| 172 | // mem_64_pcie_offset_reg_spare_control_load_2. |
| 173 | input mem_64_pcie_offset_reg_spare_control_load_1_hw_ld; // Hardware load |
| 174 | // enable for |
| 175 | // mem_64_pcie_offset_reg_spare_control_load_1. |
| 176 | // When set, <hw |
| 177 | // write signal> |
| 178 | // will be loaded |
| 179 | // into |
| 180 | // mem_64_pcie_offset_reg. |
| 181 | input mem_64_pcie_offset_reg_spare_control_load_1_hw_write; // data bus for hw |
| 182 | // loading of |
| 183 | // mem_64_pcie_offset_reg_spare_control_load_1. |
| 184 | output mem_64_pcie_offset_reg_spare_control_load_1_hw_read; // This signal |
| 185 | // provides the |
| 186 | // current value of |
| 187 | // mem_64_pcie_offset_reg_spare_control_load_1. |
| 188 | input mem_64_pcie_offset_reg_spare_control_load_0_hw_ld; // Hardware load |
| 189 | // enable for |
| 190 | // mem_64_pcie_offset_reg_spare_control_load_0. |
| 191 | // When set, <hw |
| 192 | // write signal> |
| 193 | // will be loaded |
| 194 | // into |
| 195 | // mem_64_pcie_offset_reg. |
| 196 | input mem_64_pcie_offset_reg_spare_control_load_0_hw_write; // data bus for hw |
| 197 | // loading of |
| 198 | // mem_64_pcie_offset_reg_spare_control_load_0. |
| 199 | output mem_64_pcie_offset_reg_spare_control_load_0_hw_read; // This signal |
| 200 | // provides the |
| 201 | // current value of |
| 202 | // mem_64_pcie_offset_reg_spare_control_load_0. |
| 203 | input [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC] |
| 204 | mem_64_pcie_offset_reg_spare_control_hw_write; // data bus for hw loading of |
| 205 | // mem_64_pcie_offset_reg_spare_control. |
| 206 | output [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC] |
| 207 | mem_64_pcie_offset_reg_spare_control_hw_read; // This signal provides the |
| 208 | // current value of |
| 209 | // mem_64_pcie_offset_reg_spare_control. |
| 210 | output [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_INT_SLC] mem_64_pcie_offset_reg_spare_status_hw_read; |
| 211 | // This signal provides the current value of |
| 212 | // mem_64_pcie_offset_reg_spare_status. |
| 213 | |
| 214 | //==================================================================== |
| 215 | // Type declarations |
| 216 | //==================================================================== |
| 217 | wire clk; // Clock |
| 218 | wire rst_l; // Reset signal |
| 219 | wire mem_64_pcie_offset_reg_w_ld; // SW load bus |
| 220 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 221 | wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WIDTH-1:0] mem_64_pcie_offset_reg_csrbus_read_data; |
| 222 | // SW read data |
| 223 | wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_INT_SLC] mem_64_pcie_offset_reg_addr_hw_read; |
| 224 | // This signal provides the current value of mem_64_pcie_offset_reg_addr. |
| 225 | wire mem_64_pcie_offset_reg_spare_control_load_7_hw_ld; // Hardware load enable |
| 226 | // for |
| 227 | // mem_64_pcie_offset_reg_spare_control_load_7. |
| 228 | // When set, <hw write |
| 229 | // signal> will be |
| 230 | // loaded into |
| 231 | // mem_64_pcie_offset_reg. |
| 232 | wire mem_64_pcie_offset_reg_spare_control_load_7_hw_write; // data bus for hw |
| 233 | // loading of |
| 234 | // mem_64_pcie_offset_reg_spare_control_load_7. |
| 235 | wire mem_64_pcie_offset_reg_spare_control_load_7_hw_read; // This signal |
| 236 | // provides the |
| 237 | // current value of |
| 238 | // mem_64_pcie_offset_reg_spare_control_load_7. |
| 239 | wire mem_64_pcie_offset_reg_spare_control_load_6_hw_ld; // Hardware load enable |
| 240 | // for |
| 241 | // mem_64_pcie_offset_reg_spare_control_load_6. |
| 242 | // When set, <hw write |
| 243 | // signal> will be |
| 244 | // loaded into |
| 245 | // mem_64_pcie_offset_reg. |
| 246 | wire mem_64_pcie_offset_reg_spare_control_load_6_hw_write; // data bus for hw |
| 247 | // loading of |
| 248 | // mem_64_pcie_offset_reg_spare_control_load_6. |
| 249 | wire mem_64_pcie_offset_reg_spare_control_load_6_hw_read; // This signal |
| 250 | // provides the |
| 251 | // current value of |
| 252 | // mem_64_pcie_offset_reg_spare_control_load_6. |
| 253 | wire mem_64_pcie_offset_reg_spare_control_load_5_hw_ld; // Hardware load enable |
| 254 | // for |
| 255 | // mem_64_pcie_offset_reg_spare_control_load_5. |
| 256 | // When set, <hw write |
| 257 | // signal> will be |
| 258 | // loaded into |
| 259 | // mem_64_pcie_offset_reg. |
| 260 | wire mem_64_pcie_offset_reg_spare_control_load_5_hw_write; // data bus for hw |
| 261 | // loading of |
| 262 | // mem_64_pcie_offset_reg_spare_control_load_5. |
| 263 | wire mem_64_pcie_offset_reg_spare_control_load_5_hw_read; // This signal |
| 264 | // provides the |
| 265 | // current value of |
| 266 | // mem_64_pcie_offset_reg_spare_control_load_5. |
| 267 | wire mem_64_pcie_offset_reg_spare_control_load_4_hw_ld; // Hardware load enable |
| 268 | // for |
| 269 | // mem_64_pcie_offset_reg_spare_control_load_4. |
| 270 | // When set, <hw write |
| 271 | // signal> will be |
| 272 | // loaded into |
| 273 | // mem_64_pcie_offset_reg. |
| 274 | wire mem_64_pcie_offset_reg_spare_control_load_4_hw_write; // data bus for hw |
| 275 | // loading of |
| 276 | // mem_64_pcie_offset_reg_spare_control_load_4. |
| 277 | wire mem_64_pcie_offset_reg_spare_control_load_4_hw_read; // This signal |
| 278 | // provides the |
| 279 | // current value of |
| 280 | // mem_64_pcie_offset_reg_spare_control_load_4. |
| 281 | wire mem_64_pcie_offset_reg_spare_control_load_3_hw_ld; // Hardware load enable |
| 282 | // for |
| 283 | // mem_64_pcie_offset_reg_spare_control_load_3. |
| 284 | // When set, <hw write |
| 285 | // signal> will be |
| 286 | // loaded into |
| 287 | // mem_64_pcie_offset_reg. |
| 288 | wire mem_64_pcie_offset_reg_spare_control_load_3_hw_write; // data bus for hw |
| 289 | // loading of |
| 290 | // mem_64_pcie_offset_reg_spare_control_load_3. |
| 291 | wire mem_64_pcie_offset_reg_spare_control_load_3_hw_read; // This signal |
| 292 | // provides the |
| 293 | // current value of |
| 294 | // mem_64_pcie_offset_reg_spare_control_load_3. |
| 295 | wire mem_64_pcie_offset_reg_spare_control_load_2_hw_ld; // Hardware load enable |
| 296 | // for |
| 297 | // mem_64_pcie_offset_reg_spare_control_load_2. |
| 298 | // When set, <hw write |
| 299 | // signal> will be |
| 300 | // loaded into |
| 301 | // mem_64_pcie_offset_reg. |
| 302 | wire mem_64_pcie_offset_reg_spare_control_load_2_hw_write; // data bus for hw |
| 303 | // loading of |
| 304 | // mem_64_pcie_offset_reg_spare_control_load_2. |
| 305 | wire mem_64_pcie_offset_reg_spare_control_load_2_hw_read; // This signal |
| 306 | // provides the |
| 307 | // current value of |
| 308 | // mem_64_pcie_offset_reg_spare_control_load_2. |
| 309 | wire mem_64_pcie_offset_reg_spare_control_load_1_hw_ld; // Hardware load enable |
| 310 | // for |
| 311 | // mem_64_pcie_offset_reg_spare_control_load_1. |
| 312 | // When set, <hw write |
| 313 | // signal> will be |
| 314 | // loaded into |
| 315 | // mem_64_pcie_offset_reg. |
| 316 | wire mem_64_pcie_offset_reg_spare_control_load_1_hw_write; // data bus for hw |
| 317 | // loading of |
| 318 | // mem_64_pcie_offset_reg_spare_control_load_1. |
| 319 | wire mem_64_pcie_offset_reg_spare_control_load_1_hw_read; // This signal |
| 320 | // provides the |
| 321 | // current value of |
| 322 | // mem_64_pcie_offset_reg_spare_control_load_1. |
| 323 | wire mem_64_pcie_offset_reg_spare_control_load_0_hw_ld; // Hardware load enable |
| 324 | // for |
| 325 | // mem_64_pcie_offset_reg_spare_control_load_0. |
| 326 | // When set, <hw write |
| 327 | // signal> will be |
| 328 | // loaded into |
| 329 | // mem_64_pcie_offset_reg. |
| 330 | wire mem_64_pcie_offset_reg_spare_control_load_0_hw_write; // data bus for hw |
| 331 | // loading of |
| 332 | // mem_64_pcie_offset_reg_spare_control_load_0. |
| 333 | wire mem_64_pcie_offset_reg_spare_control_load_0_hw_read; // This signal |
| 334 | // provides the |
| 335 | // current value of |
| 336 | // mem_64_pcie_offset_reg_spare_control_load_0. |
| 337 | wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC] mem_64_pcie_offset_reg_spare_control_hw_write; |
| 338 | // data bus for hw loading of mem_64_pcie_offset_reg_spare_control. |
| 339 | wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC] mem_64_pcie_offset_reg_spare_control_hw_read; |
| 340 | // This signal provides the current value of |
| 341 | // mem_64_pcie_offset_reg_spare_control. |
| 342 | wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_INT_SLC] mem_64_pcie_offset_reg_spare_status_hw_read; |
| 343 | // This signal provides the current value of |
| 344 | // mem_64_pcie_offset_reg_spare_status. |
| 345 | |
| 346 | //==================================================================== |
| 347 | // Logic |
| 348 | //==================================================================== |
| 349 | |
| 350 | // synopsys translate_off |
| 351 | // verilint 123 off |
| 352 | // verilint 498 off |
| 353 | reg omni_ld; |
| 354 | reg [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WIDTH-1:0] omni_data; |
| 355 | |
| 356 | // vlint flag_unsynthesizable_initial off |
| 357 | initial |
| 358 | begin |
| 359 | omni_ld = 1'b0; |
| 360 | omni_data = `FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WIDTH'b0; |
| 361 | end// vlint flag_unsynthesizable_initial on |
| 362 | |
| 363 | // verilint 123 on |
| 364 | // verilint 498 on |
| 365 | // synopsys translate_on |
| 366 | |
| 367 | //----- Hardware Data Out Mux Assignments |
| 368 | assign mem_64_pcie_offset_reg_addr_hw_read= |
| 369 | mem_64_pcie_offset_reg_csrbus_read_data |
| 370 | [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_SLC]; |
| 371 | assign mem_64_pcie_offset_reg_spare_control_load_7_hw_read= |
| 372 | mem_64_pcie_offset_reg_csrbus_read_data [23]; |
| 373 | assign mem_64_pcie_offset_reg_spare_control_load_6_hw_read= |
| 374 | mem_64_pcie_offset_reg_csrbus_read_data [22]; |
| 375 | assign mem_64_pcie_offset_reg_spare_control_load_5_hw_read= |
| 376 | mem_64_pcie_offset_reg_csrbus_read_data [21]; |
| 377 | assign mem_64_pcie_offset_reg_spare_control_load_4_hw_read= |
| 378 | mem_64_pcie_offset_reg_csrbus_read_data [20]; |
| 379 | assign mem_64_pcie_offset_reg_spare_control_load_3_hw_read= |
| 380 | mem_64_pcie_offset_reg_csrbus_read_data [19]; |
| 381 | assign mem_64_pcie_offset_reg_spare_control_load_2_hw_read= |
| 382 | mem_64_pcie_offset_reg_csrbus_read_data [18]; |
| 383 | assign mem_64_pcie_offset_reg_spare_control_load_1_hw_read= |
| 384 | mem_64_pcie_offset_reg_csrbus_read_data [17]; |
| 385 | assign mem_64_pcie_offset_reg_spare_control_load_0_hw_read= |
| 386 | mem_64_pcie_offset_reg_csrbus_read_data [16]; |
| 387 | assign mem_64_pcie_offset_reg_spare_control_hw_read= |
| 388 | mem_64_pcie_offset_reg_csrbus_read_data |
| 389 | [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_SLC]; |
| 390 | assign mem_64_pcie_offset_reg_spare_status_hw_read= |
| 391 | mem_64_pcie_offset_reg_csrbus_read_data |
| 392 | [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_SLC]; |
| 393 | |
| 394 | //==================================================================== |
| 395 | // Instantiation of entries |
| 396 | //==================================================================== |
| 397 | |
| 398 | //----- Entry 0 |
| 399 | dmu_imu_ics_csr_mem_64_pcie_offset_reg_entry mem_64_pcie_offset_reg_0 |
| 400 | ( |
| 401 | // synopsys translate_off |
| 402 | .omni_ld (omni_ld), |
| 403 | .omni_data (omni_data), |
| 404 | // synopsys translate_on |
| 405 | .clk (clk), |
| 406 | .rst_l (rst_l), |
| 407 | .w_ld (mem_64_pcie_offset_reg_w_ld), |
| 408 | .csrbus_wr_data (csrbus_wr_data), |
| 409 | .mem_64_pcie_offset_reg_csrbus_read_data (mem_64_pcie_offset_reg_csrbus_read_data), |
| 410 | .mem_64_pcie_offset_reg_spare_control_load_7_hw_ld (mem_64_pcie_offset_reg_spare_control_load_7_hw_ld), |
| 411 | .mem_64_pcie_offset_reg_spare_control_load_7_hw_write (mem_64_pcie_offset_reg_spare_control_load_7_hw_write), |
| 412 | .mem_64_pcie_offset_reg_spare_control_load_6_hw_ld (mem_64_pcie_offset_reg_spare_control_load_6_hw_ld), |
| 413 | .mem_64_pcie_offset_reg_spare_control_load_6_hw_write (mem_64_pcie_offset_reg_spare_control_load_6_hw_write), |
| 414 | .mem_64_pcie_offset_reg_spare_control_load_5_hw_ld (mem_64_pcie_offset_reg_spare_control_load_5_hw_ld), |
| 415 | .mem_64_pcie_offset_reg_spare_control_load_5_hw_write (mem_64_pcie_offset_reg_spare_control_load_5_hw_write), |
| 416 | .mem_64_pcie_offset_reg_spare_control_load_4_hw_ld (mem_64_pcie_offset_reg_spare_control_load_4_hw_ld), |
| 417 | .mem_64_pcie_offset_reg_spare_control_load_4_hw_write (mem_64_pcie_offset_reg_spare_control_load_4_hw_write), |
| 418 | .mem_64_pcie_offset_reg_spare_control_load_3_hw_ld (mem_64_pcie_offset_reg_spare_control_load_3_hw_ld), |
| 419 | .mem_64_pcie_offset_reg_spare_control_load_3_hw_write (mem_64_pcie_offset_reg_spare_control_load_3_hw_write), |
| 420 | .mem_64_pcie_offset_reg_spare_control_load_2_hw_ld (mem_64_pcie_offset_reg_spare_control_load_2_hw_ld), |
| 421 | .mem_64_pcie_offset_reg_spare_control_load_2_hw_write (mem_64_pcie_offset_reg_spare_control_load_2_hw_write), |
| 422 | .mem_64_pcie_offset_reg_spare_control_load_1_hw_ld (mem_64_pcie_offset_reg_spare_control_load_1_hw_ld), |
| 423 | .mem_64_pcie_offset_reg_spare_control_load_1_hw_write (mem_64_pcie_offset_reg_spare_control_load_1_hw_write), |
| 424 | .mem_64_pcie_offset_reg_spare_control_load_0_hw_ld (mem_64_pcie_offset_reg_spare_control_load_0_hw_ld), |
| 425 | .mem_64_pcie_offset_reg_spare_control_load_0_hw_write (mem_64_pcie_offset_reg_spare_control_load_0_hw_write), |
| 426 | .mem_64_pcie_offset_reg_spare_control_hw_write (mem_64_pcie_offset_reg_spare_control_hw_write) |
| 427 | ); |
| 428 | |
| 429 | endmodule // dmu_imu_ics_csr_mem_64_pcie_offset_reg |