| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_ics_csr_msi_64_addr_reg_entry.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_ics_csr_msi_64_addr_reg_entry |
| 36 | ( |
| 37 | // synopsys translate_off |
| 38 | omni_ld, |
| 39 | omni_data, |
| 40 | // synopsys translate_on |
| 41 | clk, |
| 42 | rst_l, |
| 43 | w_ld, |
| 44 | csrbus_wr_data, |
| 45 | msi_64_addr_reg_csrbus_read_data |
| 46 | ); |
| 47 | |
| 48 | //==================================================================== |
| 49 | // Polarity declarations |
| 50 | //==================================================================== |
| 51 | // synopsys translate_off |
| 52 | input omni_ld; // Omni load |
| 53 | // vlint flag_input_port_not_connected off |
| 54 | input [`FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_WIDTH - 1:0] omni_data; |
| 55 | // Omni write data |
| 56 | // synopsys translate_on |
| 57 | // vlint flag_input_port_not_connected on |
| 58 | input clk; // Clock signal |
| 59 | input rst_l; // Reset signal |
| 60 | input w_ld; // SW load |
| 61 | // vlint flag_input_port_not_connected off |
| 62 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 63 | // vlint flag_input_port_not_connected on |
| 64 | output [`FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_WIDTH-1:0] msi_64_addr_reg_csrbus_read_data; |
| 65 | // SW read data |
| 66 | |
| 67 | //==================================================================== |
| 68 | // Type declarations |
| 69 | //==================================================================== |
| 70 | // synopsys translate_off |
| 71 | wire omni_ld; // Omni load |
| 72 | // vlint flag_dangling_net_within_module off |
| 73 | // vlint flag_net_has_no_load off |
| 74 | wire [`FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_WIDTH - 1:0] omni_data; |
| 75 | // Omni write data |
| 76 | // synopsys translate_on |
| 77 | // vlint flag_dangling_net_within_module on |
| 78 | // vlint flag_net_has_no_load on |
| 79 | wire clk; // Clock signal |
| 80 | wire rst_l; // Reset signal |
| 81 | wire w_ld; // SW load |
| 82 | // vlint flag_dangling_net_within_module off |
| 83 | // vlint flag_net_has_no_load off |
| 84 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 85 | // vlint flag_dangling_net_within_module on |
| 86 | // vlint flag_net_has_no_load on |
| 87 | wire [`FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_WIDTH-1:0] msi_64_addr_reg_csrbus_read_data; |
| 88 | // SW read data |
| 89 | |
| 90 | //==================================================================== |
| 91 | // Logic |
| 92 | //==================================================================== |
| 93 | |
| 94 | //----- Reset values |
| 95 | // verilint 531 off |
| 96 | wire [47:0] reset_addr = 48'h0; |
| 97 | // verilint 531 on |
| 98 | |
| 99 | //----- Active high reset wires |
| 100 | wire rst_l_active_high = ~rst_l; |
| 101 | |
| 102 | //==================================================== |
| 103 | // Instantiation of flops |
| 104 | //==================================================== |
| 105 | |
| 106 | assign msi_64_addr_reg_csrbus_read_data[0] = 1'b0; // bit 0 |
| 107 | assign msi_64_addr_reg_csrbus_read_data[1] = 1'b0; // bit 1 |
| 108 | assign msi_64_addr_reg_csrbus_read_data[2] = 1'b0; // bit 2 |
| 109 | assign msi_64_addr_reg_csrbus_read_data[3] = 1'b0; // bit 3 |
| 110 | assign msi_64_addr_reg_csrbus_read_data[4] = 1'b0; // bit 4 |
| 111 | assign msi_64_addr_reg_csrbus_read_data[5] = 1'b0; // bit 5 |
| 112 | assign msi_64_addr_reg_csrbus_read_data[6] = 1'b0; // bit 6 |
| 113 | assign msi_64_addr_reg_csrbus_read_data[7] = 1'b0; // bit 7 |
| 114 | assign msi_64_addr_reg_csrbus_read_data[8] = 1'b0; // bit 8 |
| 115 | assign msi_64_addr_reg_csrbus_read_data[9] = 1'b0; // bit 9 |
| 116 | assign msi_64_addr_reg_csrbus_read_data[10] = 1'b0; // bit 10 |
| 117 | assign msi_64_addr_reg_csrbus_read_data[11] = 1'b0; // bit 11 |
| 118 | assign msi_64_addr_reg_csrbus_read_data[12] = 1'b0; // bit 12 |
| 119 | assign msi_64_addr_reg_csrbus_read_data[13] = 1'b0; // bit 13 |
| 120 | assign msi_64_addr_reg_csrbus_read_data[14] = 1'b0; // bit 14 |
| 121 | assign msi_64_addr_reg_csrbus_read_data[15] = 1'b0; // bit 15 |
| 122 | // bit 16 |
| 123 | csr_sw csr_sw_16 |
| 124 | ( |
| 125 | // synopsys translate_off |
| 126 | .omni_ld (omni_ld), |
| 127 | .omni_data (omni_data[16]), |
| 128 | .omni_rw_alias (1'b1), |
| 129 | .omni_rw1c_alias (1'b0), |
| 130 | .omni_rw1s_alias (1'b0), |
| 131 | // synopsys translate_on |
| 132 | .rst (rst_l_active_high), |
| 133 | .rst_val (reset_addr[0]), |
| 134 | .csr_ld (w_ld), |
| 135 | .csr_data (csrbus_wr_data[16]), |
| 136 | .rw_alias (1'b1), |
| 137 | .rw1c_alias (1'b0), |
| 138 | .rw1s_alias (1'b0), |
| 139 | .hw_ld (1'b0), |
| 140 | .hw_data (1'b0), |
| 141 | .cp (clk), |
| 142 | .q (msi_64_addr_reg_csrbus_read_data[16]) |
| 143 | ); |
| 144 | |
| 145 | // bit 17 |
| 146 | csr_sw csr_sw_17 |
| 147 | ( |
| 148 | // synopsys translate_off |
| 149 | .omni_ld (omni_ld), |
| 150 | .omni_data (omni_data[17]), |
| 151 | .omni_rw_alias (1'b1), |
| 152 | .omni_rw1c_alias (1'b0), |
| 153 | .omni_rw1s_alias (1'b0), |
| 154 | // synopsys translate_on |
| 155 | .rst (rst_l_active_high), |
| 156 | .rst_val (reset_addr[1]), |
| 157 | .csr_ld (w_ld), |
| 158 | .csr_data (csrbus_wr_data[17]), |
| 159 | .rw_alias (1'b1), |
| 160 | .rw1c_alias (1'b0), |
| 161 | .rw1s_alias (1'b0), |
| 162 | .hw_ld (1'b0), |
| 163 | .hw_data (1'b0), |
| 164 | .cp (clk), |
| 165 | .q (msi_64_addr_reg_csrbus_read_data[17]) |
| 166 | ); |
| 167 | |
| 168 | // bit 18 |
| 169 | csr_sw csr_sw_18 |
| 170 | ( |
| 171 | // synopsys translate_off |
| 172 | .omni_ld (omni_ld), |
| 173 | .omni_data (omni_data[18]), |
| 174 | .omni_rw_alias (1'b1), |
| 175 | .omni_rw1c_alias (1'b0), |
| 176 | .omni_rw1s_alias (1'b0), |
| 177 | // synopsys translate_on |
| 178 | .rst (rst_l_active_high), |
| 179 | .rst_val (reset_addr[2]), |
| 180 | .csr_ld (w_ld), |
| 181 | .csr_data (csrbus_wr_data[18]), |
| 182 | .rw_alias (1'b1), |
| 183 | .rw1c_alias (1'b0), |
| 184 | .rw1s_alias (1'b0), |
| 185 | .hw_ld (1'b0), |
| 186 | .hw_data (1'b0), |
| 187 | .cp (clk), |
| 188 | .q (msi_64_addr_reg_csrbus_read_data[18]) |
| 189 | ); |
| 190 | |
| 191 | // bit 19 |
| 192 | csr_sw csr_sw_19 |
| 193 | ( |
| 194 | // synopsys translate_off |
| 195 | .omni_ld (omni_ld), |
| 196 | .omni_data (omni_data[19]), |
| 197 | .omni_rw_alias (1'b1), |
| 198 | .omni_rw1c_alias (1'b0), |
| 199 | .omni_rw1s_alias (1'b0), |
| 200 | // synopsys translate_on |
| 201 | .rst (rst_l_active_high), |
| 202 | .rst_val (reset_addr[3]), |
| 203 | .csr_ld (w_ld), |
| 204 | .csr_data (csrbus_wr_data[19]), |
| 205 | .rw_alias (1'b1), |
| 206 | .rw1c_alias (1'b0), |
| 207 | .rw1s_alias (1'b0), |
| 208 | .hw_ld (1'b0), |
| 209 | .hw_data (1'b0), |
| 210 | .cp (clk), |
| 211 | .q (msi_64_addr_reg_csrbus_read_data[19]) |
| 212 | ); |
| 213 | |
| 214 | // bit 20 |
| 215 | csr_sw csr_sw_20 |
| 216 | ( |
| 217 | // synopsys translate_off |
| 218 | .omni_ld (omni_ld), |
| 219 | .omni_data (omni_data[20]), |
| 220 | .omni_rw_alias (1'b1), |
| 221 | .omni_rw1c_alias (1'b0), |
| 222 | .omni_rw1s_alias (1'b0), |
| 223 | // synopsys translate_on |
| 224 | .rst (rst_l_active_high), |
| 225 | .rst_val (reset_addr[4]), |
| 226 | .csr_ld (w_ld), |
| 227 | .csr_data (csrbus_wr_data[20]), |
| 228 | .rw_alias (1'b1), |
| 229 | .rw1c_alias (1'b0), |
| 230 | .rw1s_alias (1'b0), |
| 231 | .hw_ld (1'b0), |
| 232 | .hw_data (1'b0), |
| 233 | .cp (clk), |
| 234 | .q (msi_64_addr_reg_csrbus_read_data[20]) |
| 235 | ); |
| 236 | |
| 237 | // bit 21 |
| 238 | csr_sw csr_sw_21 |
| 239 | ( |
| 240 | // synopsys translate_off |
| 241 | .omni_ld (omni_ld), |
| 242 | .omni_data (omni_data[21]), |
| 243 | .omni_rw_alias (1'b1), |
| 244 | .omni_rw1c_alias (1'b0), |
| 245 | .omni_rw1s_alias (1'b0), |
| 246 | // synopsys translate_on |
| 247 | .rst (rst_l_active_high), |
| 248 | .rst_val (reset_addr[5]), |
| 249 | .csr_ld (w_ld), |
| 250 | .csr_data (csrbus_wr_data[21]), |
| 251 | .rw_alias (1'b1), |
| 252 | .rw1c_alias (1'b0), |
| 253 | .rw1s_alias (1'b0), |
| 254 | .hw_ld (1'b0), |
| 255 | .hw_data (1'b0), |
| 256 | .cp (clk), |
| 257 | .q (msi_64_addr_reg_csrbus_read_data[21]) |
| 258 | ); |
| 259 | |
| 260 | // bit 22 |
| 261 | csr_sw csr_sw_22 |
| 262 | ( |
| 263 | // synopsys translate_off |
| 264 | .omni_ld (omni_ld), |
| 265 | .omni_data (omni_data[22]), |
| 266 | .omni_rw_alias (1'b1), |
| 267 | .omni_rw1c_alias (1'b0), |
| 268 | .omni_rw1s_alias (1'b0), |
| 269 | // synopsys translate_on |
| 270 | .rst (rst_l_active_high), |
| 271 | .rst_val (reset_addr[6]), |
| 272 | .csr_ld (w_ld), |
| 273 | .csr_data (csrbus_wr_data[22]), |
| 274 | .rw_alias (1'b1), |
| 275 | .rw1c_alias (1'b0), |
| 276 | .rw1s_alias (1'b0), |
| 277 | .hw_ld (1'b0), |
| 278 | .hw_data (1'b0), |
| 279 | .cp (clk), |
| 280 | .q (msi_64_addr_reg_csrbus_read_data[22]) |
| 281 | ); |
| 282 | |
| 283 | // bit 23 |
| 284 | csr_sw csr_sw_23 |
| 285 | ( |
| 286 | // synopsys translate_off |
| 287 | .omni_ld (omni_ld), |
| 288 | .omni_data (omni_data[23]), |
| 289 | .omni_rw_alias (1'b1), |
| 290 | .omni_rw1c_alias (1'b0), |
| 291 | .omni_rw1s_alias (1'b0), |
| 292 | // synopsys translate_on |
| 293 | .rst (rst_l_active_high), |
| 294 | .rst_val (reset_addr[7]), |
| 295 | .csr_ld (w_ld), |
| 296 | .csr_data (csrbus_wr_data[23]), |
| 297 | .rw_alias (1'b1), |
| 298 | .rw1c_alias (1'b0), |
| 299 | .rw1s_alias (1'b0), |
| 300 | .hw_ld (1'b0), |
| 301 | .hw_data (1'b0), |
| 302 | .cp (clk), |
| 303 | .q (msi_64_addr_reg_csrbus_read_data[23]) |
| 304 | ); |
| 305 | |
| 306 | // bit 24 |
| 307 | csr_sw csr_sw_24 |
| 308 | ( |
| 309 | // synopsys translate_off |
| 310 | .omni_ld (omni_ld), |
| 311 | .omni_data (omni_data[24]), |
| 312 | .omni_rw_alias (1'b1), |
| 313 | .omni_rw1c_alias (1'b0), |
| 314 | .omni_rw1s_alias (1'b0), |
| 315 | // synopsys translate_on |
| 316 | .rst (rst_l_active_high), |
| 317 | .rst_val (reset_addr[8]), |
| 318 | .csr_ld (w_ld), |
| 319 | .csr_data (csrbus_wr_data[24]), |
| 320 | .rw_alias (1'b1), |
| 321 | .rw1c_alias (1'b0), |
| 322 | .rw1s_alias (1'b0), |
| 323 | .hw_ld (1'b0), |
| 324 | .hw_data (1'b0), |
| 325 | .cp (clk), |
| 326 | .q (msi_64_addr_reg_csrbus_read_data[24]) |
| 327 | ); |
| 328 | |
| 329 | // bit 25 |
| 330 | csr_sw csr_sw_25 |
| 331 | ( |
| 332 | // synopsys translate_off |
| 333 | .omni_ld (omni_ld), |
| 334 | .omni_data (omni_data[25]), |
| 335 | .omni_rw_alias (1'b1), |
| 336 | .omni_rw1c_alias (1'b0), |
| 337 | .omni_rw1s_alias (1'b0), |
| 338 | // synopsys translate_on |
| 339 | .rst (rst_l_active_high), |
| 340 | .rst_val (reset_addr[9]), |
| 341 | .csr_ld (w_ld), |
| 342 | .csr_data (csrbus_wr_data[25]), |
| 343 | .rw_alias (1'b1), |
| 344 | .rw1c_alias (1'b0), |
| 345 | .rw1s_alias (1'b0), |
| 346 | .hw_ld (1'b0), |
| 347 | .hw_data (1'b0), |
| 348 | .cp (clk), |
| 349 | .q (msi_64_addr_reg_csrbus_read_data[25]) |
| 350 | ); |
| 351 | |
| 352 | // bit 26 |
| 353 | csr_sw csr_sw_26 |
| 354 | ( |
| 355 | // synopsys translate_off |
| 356 | .omni_ld (omni_ld), |
| 357 | .omni_data (omni_data[26]), |
| 358 | .omni_rw_alias (1'b1), |
| 359 | .omni_rw1c_alias (1'b0), |
| 360 | .omni_rw1s_alias (1'b0), |
| 361 | // synopsys translate_on |
| 362 | .rst (rst_l_active_high), |
| 363 | .rst_val (reset_addr[10]), |
| 364 | .csr_ld (w_ld), |
| 365 | .csr_data (csrbus_wr_data[26]), |
| 366 | .rw_alias (1'b1), |
| 367 | .rw1c_alias (1'b0), |
| 368 | .rw1s_alias (1'b0), |
| 369 | .hw_ld (1'b0), |
| 370 | .hw_data (1'b0), |
| 371 | .cp (clk), |
| 372 | .q (msi_64_addr_reg_csrbus_read_data[26]) |
| 373 | ); |
| 374 | |
| 375 | // bit 27 |
| 376 | csr_sw csr_sw_27 |
| 377 | ( |
| 378 | // synopsys translate_off |
| 379 | .omni_ld (omni_ld), |
| 380 | .omni_data (omni_data[27]), |
| 381 | .omni_rw_alias (1'b1), |
| 382 | .omni_rw1c_alias (1'b0), |
| 383 | .omni_rw1s_alias (1'b0), |
| 384 | // synopsys translate_on |
| 385 | .rst (rst_l_active_high), |
| 386 | .rst_val (reset_addr[11]), |
| 387 | .csr_ld (w_ld), |
| 388 | .csr_data (csrbus_wr_data[27]), |
| 389 | .rw_alias (1'b1), |
| 390 | .rw1c_alias (1'b0), |
| 391 | .rw1s_alias (1'b0), |
| 392 | .hw_ld (1'b0), |
| 393 | .hw_data (1'b0), |
| 394 | .cp (clk), |
| 395 | .q (msi_64_addr_reg_csrbus_read_data[27]) |
| 396 | ); |
| 397 | |
| 398 | // bit 28 |
| 399 | csr_sw csr_sw_28 |
| 400 | ( |
| 401 | // synopsys translate_off |
| 402 | .omni_ld (omni_ld), |
| 403 | .omni_data (omni_data[28]), |
| 404 | .omni_rw_alias (1'b1), |
| 405 | .omni_rw1c_alias (1'b0), |
| 406 | .omni_rw1s_alias (1'b0), |
| 407 | // synopsys translate_on |
| 408 | .rst (rst_l_active_high), |
| 409 | .rst_val (reset_addr[12]), |
| 410 | .csr_ld (w_ld), |
| 411 | .csr_data (csrbus_wr_data[28]), |
| 412 | .rw_alias (1'b1), |
| 413 | .rw1c_alias (1'b0), |
| 414 | .rw1s_alias (1'b0), |
| 415 | .hw_ld (1'b0), |
| 416 | .hw_data (1'b0), |
| 417 | .cp (clk), |
| 418 | .q (msi_64_addr_reg_csrbus_read_data[28]) |
| 419 | ); |
| 420 | |
| 421 | // bit 29 |
| 422 | csr_sw csr_sw_29 |
| 423 | ( |
| 424 | // synopsys translate_off |
| 425 | .omni_ld (omni_ld), |
| 426 | .omni_data (omni_data[29]), |
| 427 | .omni_rw_alias (1'b1), |
| 428 | .omni_rw1c_alias (1'b0), |
| 429 | .omni_rw1s_alias (1'b0), |
| 430 | // synopsys translate_on |
| 431 | .rst (rst_l_active_high), |
| 432 | .rst_val (reset_addr[13]), |
| 433 | .csr_ld (w_ld), |
| 434 | .csr_data (csrbus_wr_data[29]), |
| 435 | .rw_alias (1'b1), |
| 436 | .rw1c_alias (1'b0), |
| 437 | .rw1s_alias (1'b0), |
| 438 | .hw_ld (1'b0), |
| 439 | .hw_data (1'b0), |
| 440 | .cp (clk), |
| 441 | .q (msi_64_addr_reg_csrbus_read_data[29]) |
| 442 | ); |
| 443 | |
| 444 | // bit 30 |
| 445 | csr_sw csr_sw_30 |
| 446 | ( |
| 447 | // synopsys translate_off |
| 448 | .omni_ld (omni_ld), |
| 449 | .omni_data (omni_data[30]), |
| 450 | .omni_rw_alias (1'b1), |
| 451 | .omni_rw1c_alias (1'b0), |
| 452 | .omni_rw1s_alias (1'b0), |
| 453 | // synopsys translate_on |
| 454 | .rst (rst_l_active_high), |
| 455 | .rst_val (reset_addr[14]), |
| 456 | .csr_ld (w_ld), |
| 457 | .csr_data (csrbus_wr_data[30]), |
| 458 | .rw_alias (1'b1), |
| 459 | .rw1c_alias (1'b0), |
| 460 | .rw1s_alias (1'b0), |
| 461 | .hw_ld (1'b0), |
| 462 | .hw_data (1'b0), |
| 463 | .cp (clk), |
| 464 | .q (msi_64_addr_reg_csrbus_read_data[30]) |
| 465 | ); |
| 466 | |
| 467 | // bit 31 |
| 468 | csr_sw csr_sw_31 |
| 469 | ( |
| 470 | // synopsys translate_off |
| 471 | .omni_ld (omni_ld), |
| 472 | .omni_data (omni_data[31]), |
| 473 | .omni_rw_alias (1'b1), |
| 474 | .omni_rw1c_alias (1'b0), |
| 475 | .omni_rw1s_alias (1'b0), |
| 476 | // synopsys translate_on |
| 477 | .rst (rst_l_active_high), |
| 478 | .rst_val (reset_addr[15]), |
| 479 | .csr_ld (w_ld), |
| 480 | .csr_data (csrbus_wr_data[31]), |
| 481 | .rw_alias (1'b1), |
| 482 | .rw1c_alias (1'b0), |
| 483 | .rw1s_alias (1'b0), |
| 484 | .hw_ld (1'b0), |
| 485 | .hw_data (1'b0), |
| 486 | .cp (clk), |
| 487 | .q (msi_64_addr_reg_csrbus_read_data[31]) |
| 488 | ); |
| 489 | |
| 490 | // bit 32 |
| 491 | csr_sw csr_sw_32 |
| 492 | ( |
| 493 | // synopsys translate_off |
| 494 | .omni_ld (omni_ld), |
| 495 | .omni_data (omni_data[32]), |
| 496 | .omni_rw_alias (1'b1), |
| 497 | .omni_rw1c_alias (1'b0), |
| 498 | .omni_rw1s_alias (1'b0), |
| 499 | // synopsys translate_on |
| 500 | .rst (rst_l_active_high), |
| 501 | .rst_val (reset_addr[16]), |
| 502 | .csr_ld (w_ld), |
| 503 | .csr_data (csrbus_wr_data[32]), |
| 504 | .rw_alias (1'b1), |
| 505 | .rw1c_alias (1'b0), |
| 506 | .rw1s_alias (1'b0), |
| 507 | .hw_ld (1'b0), |
| 508 | .hw_data (1'b0), |
| 509 | .cp (clk), |
| 510 | .q (msi_64_addr_reg_csrbus_read_data[32]) |
| 511 | ); |
| 512 | |
| 513 | // bit 33 |
| 514 | csr_sw csr_sw_33 |
| 515 | ( |
| 516 | // synopsys translate_off |
| 517 | .omni_ld (omni_ld), |
| 518 | .omni_data (omni_data[33]), |
| 519 | .omni_rw_alias (1'b1), |
| 520 | .omni_rw1c_alias (1'b0), |
| 521 | .omni_rw1s_alias (1'b0), |
| 522 | // synopsys translate_on |
| 523 | .rst (rst_l_active_high), |
| 524 | .rst_val (reset_addr[17]), |
| 525 | .csr_ld (w_ld), |
| 526 | .csr_data (csrbus_wr_data[33]), |
| 527 | .rw_alias (1'b1), |
| 528 | .rw1c_alias (1'b0), |
| 529 | .rw1s_alias (1'b0), |
| 530 | .hw_ld (1'b0), |
| 531 | .hw_data (1'b0), |
| 532 | .cp (clk), |
| 533 | .q (msi_64_addr_reg_csrbus_read_data[33]) |
| 534 | ); |
| 535 | |
| 536 | // bit 34 |
| 537 | csr_sw csr_sw_34 |
| 538 | ( |
| 539 | // synopsys translate_off |
| 540 | .omni_ld (omni_ld), |
| 541 | .omni_data (omni_data[34]), |
| 542 | .omni_rw_alias (1'b1), |
| 543 | .omni_rw1c_alias (1'b0), |
| 544 | .omni_rw1s_alias (1'b0), |
| 545 | // synopsys translate_on |
| 546 | .rst (rst_l_active_high), |
| 547 | .rst_val (reset_addr[18]), |
| 548 | .csr_ld (w_ld), |
| 549 | .csr_data (csrbus_wr_data[34]), |
| 550 | .rw_alias (1'b1), |
| 551 | .rw1c_alias (1'b0), |
| 552 | .rw1s_alias (1'b0), |
| 553 | .hw_ld (1'b0), |
| 554 | .hw_data (1'b0), |
| 555 | .cp (clk), |
| 556 | .q (msi_64_addr_reg_csrbus_read_data[34]) |
| 557 | ); |
| 558 | |
| 559 | // bit 35 |
| 560 | csr_sw csr_sw_35 |
| 561 | ( |
| 562 | // synopsys translate_off |
| 563 | .omni_ld (omni_ld), |
| 564 | .omni_data (omni_data[35]), |
| 565 | .omni_rw_alias (1'b1), |
| 566 | .omni_rw1c_alias (1'b0), |
| 567 | .omni_rw1s_alias (1'b0), |
| 568 | // synopsys translate_on |
| 569 | .rst (rst_l_active_high), |
| 570 | .rst_val (reset_addr[19]), |
| 571 | .csr_ld (w_ld), |
| 572 | .csr_data (csrbus_wr_data[35]), |
| 573 | .rw_alias (1'b1), |
| 574 | .rw1c_alias (1'b0), |
| 575 | .rw1s_alias (1'b0), |
| 576 | .hw_ld (1'b0), |
| 577 | .hw_data (1'b0), |
| 578 | .cp (clk), |
| 579 | .q (msi_64_addr_reg_csrbus_read_data[35]) |
| 580 | ); |
| 581 | |
| 582 | // bit 36 |
| 583 | csr_sw csr_sw_36 |
| 584 | ( |
| 585 | // synopsys translate_off |
| 586 | .omni_ld (omni_ld), |
| 587 | .omni_data (omni_data[36]), |
| 588 | .omni_rw_alias (1'b1), |
| 589 | .omni_rw1c_alias (1'b0), |
| 590 | .omni_rw1s_alias (1'b0), |
| 591 | // synopsys translate_on |
| 592 | .rst (rst_l_active_high), |
| 593 | .rst_val (reset_addr[20]), |
| 594 | .csr_ld (w_ld), |
| 595 | .csr_data (csrbus_wr_data[36]), |
| 596 | .rw_alias (1'b1), |
| 597 | .rw1c_alias (1'b0), |
| 598 | .rw1s_alias (1'b0), |
| 599 | .hw_ld (1'b0), |
| 600 | .hw_data (1'b0), |
| 601 | .cp (clk), |
| 602 | .q (msi_64_addr_reg_csrbus_read_data[36]) |
| 603 | ); |
| 604 | |
| 605 | // bit 37 |
| 606 | csr_sw csr_sw_37 |
| 607 | ( |
| 608 | // synopsys translate_off |
| 609 | .omni_ld (omni_ld), |
| 610 | .omni_data (omni_data[37]), |
| 611 | .omni_rw_alias (1'b1), |
| 612 | .omni_rw1c_alias (1'b0), |
| 613 | .omni_rw1s_alias (1'b0), |
| 614 | // synopsys translate_on |
| 615 | .rst (rst_l_active_high), |
| 616 | .rst_val (reset_addr[21]), |
| 617 | .csr_ld (w_ld), |
| 618 | .csr_data (csrbus_wr_data[37]), |
| 619 | .rw_alias (1'b1), |
| 620 | .rw1c_alias (1'b0), |
| 621 | .rw1s_alias (1'b0), |
| 622 | .hw_ld (1'b0), |
| 623 | .hw_data (1'b0), |
| 624 | .cp (clk), |
| 625 | .q (msi_64_addr_reg_csrbus_read_data[37]) |
| 626 | ); |
| 627 | |
| 628 | // bit 38 |
| 629 | csr_sw csr_sw_38 |
| 630 | ( |
| 631 | // synopsys translate_off |
| 632 | .omni_ld (omni_ld), |
| 633 | .omni_data (omni_data[38]), |
| 634 | .omni_rw_alias (1'b1), |
| 635 | .omni_rw1c_alias (1'b0), |
| 636 | .omni_rw1s_alias (1'b0), |
| 637 | // synopsys translate_on |
| 638 | .rst (rst_l_active_high), |
| 639 | .rst_val (reset_addr[22]), |
| 640 | .csr_ld (w_ld), |
| 641 | .csr_data (csrbus_wr_data[38]), |
| 642 | .rw_alias (1'b1), |
| 643 | .rw1c_alias (1'b0), |
| 644 | .rw1s_alias (1'b0), |
| 645 | .hw_ld (1'b0), |
| 646 | .hw_data (1'b0), |
| 647 | .cp (clk), |
| 648 | .q (msi_64_addr_reg_csrbus_read_data[38]) |
| 649 | ); |
| 650 | |
| 651 | // bit 39 |
| 652 | csr_sw csr_sw_39 |
| 653 | ( |
| 654 | // synopsys translate_off |
| 655 | .omni_ld (omni_ld), |
| 656 | .omni_data (omni_data[39]), |
| 657 | .omni_rw_alias (1'b1), |
| 658 | .omni_rw1c_alias (1'b0), |
| 659 | .omni_rw1s_alias (1'b0), |
| 660 | // synopsys translate_on |
| 661 | .rst (rst_l_active_high), |
| 662 | .rst_val (reset_addr[23]), |
| 663 | .csr_ld (w_ld), |
| 664 | .csr_data (csrbus_wr_data[39]), |
| 665 | .rw_alias (1'b1), |
| 666 | .rw1c_alias (1'b0), |
| 667 | .rw1s_alias (1'b0), |
| 668 | .hw_ld (1'b0), |
| 669 | .hw_data (1'b0), |
| 670 | .cp (clk), |
| 671 | .q (msi_64_addr_reg_csrbus_read_data[39]) |
| 672 | ); |
| 673 | |
| 674 | // bit 40 |
| 675 | csr_sw csr_sw_40 |
| 676 | ( |
| 677 | // synopsys translate_off |
| 678 | .omni_ld (omni_ld), |
| 679 | .omni_data (omni_data[40]), |
| 680 | .omni_rw_alias (1'b1), |
| 681 | .omni_rw1c_alias (1'b0), |
| 682 | .omni_rw1s_alias (1'b0), |
| 683 | // synopsys translate_on |
| 684 | .rst (rst_l_active_high), |
| 685 | .rst_val (reset_addr[24]), |
| 686 | .csr_ld (w_ld), |
| 687 | .csr_data (csrbus_wr_data[40]), |
| 688 | .rw_alias (1'b1), |
| 689 | .rw1c_alias (1'b0), |
| 690 | .rw1s_alias (1'b0), |
| 691 | .hw_ld (1'b0), |
| 692 | .hw_data (1'b0), |
| 693 | .cp (clk), |
| 694 | .q (msi_64_addr_reg_csrbus_read_data[40]) |
| 695 | ); |
| 696 | |
| 697 | // bit 41 |
| 698 | csr_sw csr_sw_41 |
| 699 | ( |
| 700 | // synopsys translate_off |
| 701 | .omni_ld (omni_ld), |
| 702 | .omni_data (omni_data[41]), |
| 703 | .omni_rw_alias (1'b1), |
| 704 | .omni_rw1c_alias (1'b0), |
| 705 | .omni_rw1s_alias (1'b0), |
| 706 | // synopsys translate_on |
| 707 | .rst (rst_l_active_high), |
| 708 | .rst_val (reset_addr[25]), |
| 709 | .csr_ld (w_ld), |
| 710 | .csr_data (csrbus_wr_data[41]), |
| 711 | .rw_alias (1'b1), |
| 712 | .rw1c_alias (1'b0), |
| 713 | .rw1s_alias (1'b0), |
| 714 | .hw_ld (1'b0), |
| 715 | .hw_data (1'b0), |
| 716 | .cp (clk), |
| 717 | .q (msi_64_addr_reg_csrbus_read_data[41]) |
| 718 | ); |
| 719 | |
| 720 | // bit 42 |
| 721 | csr_sw csr_sw_42 |
| 722 | ( |
| 723 | // synopsys translate_off |
| 724 | .omni_ld (omni_ld), |
| 725 | .omni_data (omni_data[42]), |
| 726 | .omni_rw_alias (1'b1), |
| 727 | .omni_rw1c_alias (1'b0), |
| 728 | .omni_rw1s_alias (1'b0), |
| 729 | // synopsys translate_on |
| 730 | .rst (rst_l_active_high), |
| 731 | .rst_val (reset_addr[26]), |
| 732 | .csr_ld (w_ld), |
| 733 | .csr_data (csrbus_wr_data[42]), |
| 734 | .rw_alias (1'b1), |
| 735 | .rw1c_alias (1'b0), |
| 736 | .rw1s_alias (1'b0), |
| 737 | .hw_ld (1'b0), |
| 738 | .hw_data (1'b0), |
| 739 | .cp (clk), |
| 740 | .q (msi_64_addr_reg_csrbus_read_data[42]) |
| 741 | ); |
| 742 | |
| 743 | // bit 43 |
| 744 | csr_sw csr_sw_43 |
| 745 | ( |
| 746 | // synopsys translate_off |
| 747 | .omni_ld (omni_ld), |
| 748 | .omni_data (omni_data[43]), |
| 749 | .omni_rw_alias (1'b1), |
| 750 | .omni_rw1c_alias (1'b0), |
| 751 | .omni_rw1s_alias (1'b0), |
| 752 | // synopsys translate_on |
| 753 | .rst (rst_l_active_high), |
| 754 | .rst_val (reset_addr[27]), |
| 755 | .csr_ld (w_ld), |
| 756 | .csr_data (csrbus_wr_data[43]), |
| 757 | .rw_alias (1'b1), |
| 758 | .rw1c_alias (1'b0), |
| 759 | .rw1s_alias (1'b0), |
| 760 | .hw_ld (1'b0), |
| 761 | .hw_data (1'b0), |
| 762 | .cp (clk), |
| 763 | .q (msi_64_addr_reg_csrbus_read_data[43]) |
| 764 | ); |
| 765 | |
| 766 | // bit 44 |
| 767 | csr_sw csr_sw_44 |
| 768 | ( |
| 769 | // synopsys translate_off |
| 770 | .omni_ld (omni_ld), |
| 771 | .omni_data (omni_data[44]), |
| 772 | .omni_rw_alias (1'b1), |
| 773 | .omni_rw1c_alias (1'b0), |
| 774 | .omni_rw1s_alias (1'b0), |
| 775 | // synopsys translate_on |
| 776 | .rst (rst_l_active_high), |
| 777 | .rst_val (reset_addr[28]), |
| 778 | .csr_ld (w_ld), |
| 779 | .csr_data (csrbus_wr_data[44]), |
| 780 | .rw_alias (1'b1), |
| 781 | .rw1c_alias (1'b0), |
| 782 | .rw1s_alias (1'b0), |
| 783 | .hw_ld (1'b0), |
| 784 | .hw_data (1'b0), |
| 785 | .cp (clk), |
| 786 | .q (msi_64_addr_reg_csrbus_read_data[44]) |
| 787 | ); |
| 788 | |
| 789 | // bit 45 |
| 790 | csr_sw csr_sw_45 |
| 791 | ( |
| 792 | // synopsys translate_off |
| 793 | .omni_ld (omni_ld), |
| 794 | .omni_data (omni_data[45]), |
| 795 | .omni_rw_alias (1'b1), |
| 796 | .omni_rw1c_alias (1'b0), |
| 797 | .omni_rw1s_alias (1'b0), |
| 798 | // synopsys translate_on |
| 799 | .rst (rst_l_active_high), |
| 800 | .rst_val (reset_addr[29]), |
| 801 | .csr_ld (w_ld), |
| 802 | .csr_data (csrbus_wr_data[45]), |
| 803 | .rw_alias (1'b1), |
| 804 | .rw1c_alias (1'b0), |
| 805 | .rw1s_alias (1'b0), |
| 806 | .hw_ld (1'b0), |
| 807 | .hw_data (1'b0), |
| 808 | .cp (clk), |
| 809 | .q (msi_64_addr_reg_csrbus_read_data[45]) |
| 810 | ); |
| 811 | |
| 812 | // bit 46 |
| 813 | csr_sw csr_sw_46 |
| 814 | ( |
| 815 | // synopsys translate_off |
| 816 | .omni_ld (omni_ld), |
| 817 | .omni_data (omni_data[46]), |
| 818 | .omni_rw_alias (1'b1), |
| 819 | .omni_rw1c_alias (1'b0), |
| 820 | .omni_rw1s_alias (1'b0), |
| 821 | // synopsys translate_on |
| 822 | .rst (rst_l_active_high), |
| 823 | .rst_val (reset_addr[30]), |
| 824 | .csr_ld (w_ld), |
| 825 | .csr_data (csrbus_wr_data[46]), |
| 826 | .rw_alias (1'b1), |
| 827 | .rw1c_alias (1'b0), |
| 828 | .rw1s_alias (1'b0), |
| 829 | .hw_ld (1'b0), |
| 830 | .hw_data (1'b0), |
| 831 | .cp (clk), |
| 832 | .q (msi_64_addr_reg_csrbus_read_data[46]) |
| 833 | ); |
| 834 | |
| 835 | // bit 47 |
| 836 | csr_sw csr_sw_47 |
| 837 | ( |
| 838 | // synopsys translate_off |
| 839 | .omni_ld (omni_ld), |
| 840 | .omni_data (omni_data[47]), |
| 841 | .omni_rw_alias (1'b1), |
| 842 | .omni_rw1c_alias (1'b0), |
| 843 | .omni_rw1s_alias (1'b0), |
| 844 | // synopsys translate_on |
| 845 | .rst (rst_l_active_high), |
| 846 | .rst_val (reset_addr[31]), |
| 847 | .csr_ld (w_ld), |
| 848 | .csr_data (csrbus_wr_data[47]), |
| 849 | .rw_alias (1'b1), |
| 850 | .rw1c_alias (1'b0), |
| 851 | .rw1s_alias (1'b0), |
| 852 | .hw_ld (1'b0), |
| 853 | .hw_data (1'b0), |
| 854 | .cp (clk), |
| 855 | .q (msi_64_addr_reg_csrbus_read_data[47]) |
| 856 | ); |
| 857 | |
| 858 | // bit 48 |
| 859 | csr_sw csr_sw_48 |
| 860 | ( |
| 861 | // synopsys translate_off |
| 862 | .omni_ld (omni_ld), |
| 863 | .omni_data (omni_data[48]), |
| 864 | .omni_rw_alias (1'b1), |
| 865 | .omni_rw1c_alias (1'b0), |
| 866 | .omni_rw1s_alias (1'b0), |
| 867 | // synopsys translate_on |
| 868 | .rst (rst_l_active_high), |
| 869 | .rst_val (reset_addr[32]), |
| 870 | .csr_ld (w_ld), |
| 871 | .csr_data (csrbus_wr_data[48]), |
| 872 | .rw_alias (1'b1), |
| 873 | .rw1c_alias (1'b0), |
| 874 | .rw1s_alias (1'b0), |
| 875 | .hw_ld (1'b0), |
| 876 | .hw_data (1'b0), |
| 877 | .cp (clk), |
| 878 | .q (msi_64_addr_reg_csrbus_read_data[48]) |
| 879 | ); |
| 880 | |
| 881 | // bit 49 |
| 882 | csr_sw csr_sw_49 |
| 883 | ( |
| 884 | // synopsys translate_off |
| 885 | .omni_ld (omni_ld), |
| 886 | .omni_data (omni_data[49]), |
| 887 | .omni_rw_alias (1'b1), |
| 888 | .omni_rw1c_alias (1'b0), |
| 889 | .omni_rw1s_alias (1'b0), |
| 890 | // synopsys translate_on |
| 891 | .rst (rst_l_active_high), |
| 892 | .rst_val (reset_addr[33]), |
| 893 | .csr_ld (w_ld), |
| 894 | .csr_data (csrbus_wr_data[49]), |
| 895 | .rw_alias (1'b1), |
| 896 | .rw1c_alias (1'b0), |
| 897 | .rw1s_alias (1'b0), |
| 898 | .hw_ld (1'b0), |
| 899 | .hw_data (1'b0), |
| 900 | .cp (clk), |
| 901 | .q (msi_64_addr_reg_csrbus_read_data[49]) |
| 902 | ); |
| 903 | |
| 904 | // bit 50 |
| 905 | csr_sw csr_sw_50 |
| 906 | ( |
| 907 | // synopsys translate_off |
| 908 | .omni_ld (omni_ld), |
| 909 | .omni_data (omni_data[50]), |
| 910 | .omni_rw_alias (1'b1), |
| 911 | .omni_rw1c_alias (1'b0), |
| 912 | .omni_rw1s_alias (1'b0), |
| 913 | // synopsys translate_on |
| 914 | .rst (rst_l_active_high), |
| 915 | .rst_val (reset_addr[34]), |
| 916 | .csr_ld (w_ld), |
| 917 | .csr_data (csrbus_wr_data[50]), |
| 918 | .rw_alias (1'b1), |
| 919 | .rw1c_alias (1'b0), |
| 920 | .rw1s_alias (1'b0), |
| 921 | .hw_ld (1'b0), |
| 922 | .hw_data (1'b0), |
| 923 | .cp (clk), |
| 924 | .q (msi_64_addr_reg_csrbus_read_data[50]) |
| 925 | ); |
| 926 | |
| 927 | // bit 51 |
| 928 | csr_sw csr_sw_51 |
| 929 | ( |
| 930 | // synopsys translate_off |
| 931 | .omni_ld (omni_ld), |
| 932 | .omni_data (omni_data[51]), |
| 933 | .omni_rw_alias (1'b1), |
| 934 | .omni_rw1c_alias (1'b0), |
| 935 | .omni_rw1s_alias (1'b0), |
| 936 | // synopsys translate_on |
| 937 | .rst (rst_l_active_high), |
| 938 | .rst_val (reset_addr[35]), |
| 939 | .csr_ld (w_ld), |
| 940 | .csr_data (csrbus_wr_data[51]), |
| 941 | .rw_alias (1'b1), |
| 942 | .rw1c_alias (1'b0), |
| 943 | .rw1s_alias (1'b0), |
| 944 | .hw_ld (1'b0), |
| 945 | .hw_data (1'b0), |
| 946 | .cp (clk), |
| 947 | .q (msi_64_addr_reg_csrbus_read_data[51]) |
| 948 | ); |
| 949 | |
| 950 | // bit 52 |
| 951 | csr_sw csr_sw_52 |
| 952 | ( |
| 953 | // synopsys translate_off |
| 954 | .omni_ld (omni_ld), |
| 955 | .omni_data (omni_data[52]), |
| 956 | .omni_rw_alias (1'b1), |
| 957 | .omni_rw1c_alias (1'b0), |
| 958 | .omni_rw1s_alias (1'b0), |
| 959 | // synopsys translate_on |
| 960 | .rst (rst_l_active_high), |
| 961 | .rst_val (reset_addr[36]), |
| 962 | .csr_ld (w_ld), |
| 963 | .csr_data (csrbus_wr_data[52]), |
| 964 | .rw_alias (1'b1), |
| 965 | .rw1c_alias (1'b0), |
| 966 | .rw1s_alias (1'b0), |
| 967 | .hw_ld (1'b0), |
| 968 | .hw_data (1'b0), |
| 969 | .cp (clk), |
| 970 | .q (msi_64_addr_reg_csrbus_read_data[52]) |
| 971 | ); |
| 972 | |
| 973 | // bit 53 |
| 974 | csr_sw csr_sw_53 |
| 975 | ( |
| 976 | // synopsys translate_off |
| 977 | .omni_ld (omni_ld), |
| 978 | .omni_data (omni_data[53]), |
| 979 | .omni_rw_alias (1'b1), |
| 980 | .omni_rw1c_alias (1'b0), |
| 981 | .omni_rw1s_alias (1'b0), |
| 982 | // synopsys translate_on |
| 983 | .rst (rst_l_active_high), |
| 984 | .rst_val (reset_addr[37]), |
| 985 | .csr_ld (w_ld), |
| 986 | .csr_data (csrbus_wr_data[53]), |
| 987 | .rw_alias (1'b1), |
| 988 | .rw1c_alias (1'b0), |
| 989 | .rw1s_alias (1'b0), |
| 990 | .hw_ld (1'b0), |
| 991 | .hw_data (1'b0), |
| 992 | .cp (clk), |
| 993 | .q (msi_64_addr_reg_csrbus_read_data[53]) |
| 994 | ); |
| 995 | |
| 996 | // bit 54 |
| 997 | csr_sw csr_sw_54 |
| 998 | ( |
| 999 | // synopsys translate_off |
| 1000 | .omni_ld (omni_ld), |
| 1001 | .omni_data (omni_data[54]), |
| 1002 | .omni_rw_alias (1'b1), |
| 1003 | .omni_rw1c_alias (1'b0), |
| 1004 | .omni_rw1s_alias (1'b0), |
| 1005 | // synopsys translate_on |
| 1006 | .rst (rst_l_active_high), |
| 1007 | .rst_val (reset_addr[38]), |
| 1008 | .csr_ld (w_ld), |
| 1009 | .csr_data (csrbus_wr_data[54]), |
| 1010 | .rw_alias (1'b1), |
| 1011 | .rw1c_alias (1'b0), |
| 1012 | .rw1s_alias (1'b0), |
| 1013 | .hw_ld (1'b0), |
| 1014 | .hw_data (1'b0), |
| 1015 | .cp (clk), |
| 1016 | .q (msi_64_addr_reg_csrbus_read_data[54]) |
| 1017 | ); |
| 1018 | |
| 1019 | // bit 55 |
| 1020 | csr_sw csr_sw_55 |
| 1021 | ( |
| 1022 | // synopsys translate_off |
| 1023 | .omni_ld (omni_ld), |
| 1024 | .omni_data (omni_data[55]), |
| 1025 | .omni_rw_alias (1'b1), |
| 1026 | .omni_rw1c_alias (1'b0), |
| 1027 | .omni_rw1s_alias (1'b0), |
| 1028 | // synopsys translate_on |
| 1029 | .rst (rst_l_active_high), |
| 1030 | .rst_val (reset_addr[39]), |
| 1031 | .csr_ld (w_ld), |
| 1032 | .csr_data (csrbus_wr_data[55]), |
| 1033 | .rw_alias (1'b1), |
| 1034 | .rw1c_alias (1'b0), |
| 1035 | .rw1s_alias (1'b0), |
| 1036 | .hw_ld (1'b0), |
| 1037 | .hw_data (1'b0), |
| 1038 | .cp (clk), |
| 1039 | .q (msi_64_addr_reg_csrbus_read_data[55]) |
| 1040 | ); |
| 1041 | |
| 1042 | // bit 56 |
| 1043 | csr_sw csr_sw_56 |
| 1044 | ( |
| 1045 | // synopsys translate_off |
| 1046 | .omni_ld (omni_ld), |
| 1047 | .omni_data (omni_data[56]), |
| 1048 | .omni_rw_alias (1'b1), |
| 1049 | .omni_rw1c_alias (1'b0), |
| 1050 | .omni_rw1s_alias (1'b0), |
| 1051 | // synopsys translate_on |
| 1052 | .rst (rst_l_active_high), |
| 1053 | .rst_val (reset_addr[40]), |
| 1054 | .csr_ld (w_ld), |
| 1055 | .csr_data (csrbus_wr_data[56]), |
| 1056 | .rw_alias (1'b1), |
| 1057 | .rw1c_alias (1'b0), |
| 1058 | .rw1s_alias (1'b0), |
| 1059 | .hw_ld (1'b0), |
| 1060 | .hw_data (1'b0), |
| 1061 | .cp (clk), |
| 1062 | .q (msi_64_addr_reg_csrbus_read_data[56]) |
| 1063 | ); |
| 1064 | |
| 1065 | // bit 57 |
| 1066 | csr_sw csr_sw_57 |
| 1067 | ( |
| 1068 | // synopsys translate_off |
| 1069 | .omni_ld (omni_ld), |
| 1070 | .omni_data (omni_data[57]), |
| 1071 | .omni_rw_alias (1'b1), |
| 1072 | .omni_rw1c_alias (1'b0), |
| 1073 | .omni_rw1s_alias (1'b0), |
| 1074 | // synopsys translate_on |
| 1075 | .rst (rst_l_active_high), |
| 1076 | .rst_val (reset_addr[41]), |
| 1077 | .csr_ld (w_ld), |
| 1078 | .csr_data (csrbus_wr_data[57]), |
| 1079 | .rw_alias (1'b1), |
| 1080 | .rw1c_alias (1'b0), |
| 1081 | .rw1s_alias (1'b0), |
| 1082 | .hw_ld (1'b0), |
| 1083 | .hw_data (1'b0), |
| 1084 | .cp (clk), |
| 1085 | .q (msi_64_addr_reg_csrbus_read_data[57]) |
| 1086 | ); |
| 1087 | |
| 1088 | // bit 58 |
| 1089 | csr_sw csr_sw_58 |
| 1090 | ( |
| 1091 | // synopsys translate_off |
| 1092 | .omni_ld (omni_ld), |
| 1093 | .omni_data (omni_data[58]), |
| 1094 | .omni_rw_alias (1'b1), |
| 1095 | .omni_rw1c_alias (1'b0), |
| 1096 | .omni_rw1s_alias (1'b0), |
| 1097 | // synopsys translate_on |
| 1098 | .rst (rst_l_active_high), |
| 1099 | .rst_val (reset_addr[42]), |
| 1100 | .csr_ld (w_ld), |
| 1101 | .csr_data (csrbus_wr_data[58]), |
| 1102 | .rw_alias (1'b1), |
| 1103 | .rw1c_alias (1'b0), |
| 1104 | .rw1s_alias (1'b0), |
| 1105 | .hw_ld (1'b0), |
| 1106 | .hw_data (1'b0), |
| 1107 | .cp (clk), |
| 1108 | .q (msi_64_addr_reg_csrbus_read_data[58]) |
| 1109 | ); |
| 1110 | |
| 1111 | // bit 59 |
| 1112 | csr_sw csr_sw_59 |
| 1113 | ( |
| 1114 | // synopsys translate_off |
| 1115 | .omni_ld (omni_ld), |
| 1116 | .omni_data (omni_data[59]), |
| 1117 | .omni_rw_alias (1'b1), |
| 1118 | .omni_rw1c_alias (1'b0), |
| 1119 | .omni_rw1s_alias (1'b0), |
| 1120 | // synopsys translate_on |
| 1121 | .rst (rst_l_active_high), |
| 1122 | .rst_val (reset_addr[43]), |
| 1123 | .csr_ld (w_ld), |
| 1124 | .csr_data (csrbus_wr_data[59]), |
| 1125 | .rw_alias (1'b1), |
| 1126 | .rw1c_alias (1'b0), |
| 1127 | .rw1s_alias (1'b0), |
| 1128 | .hw_ld (1'b0), |
| 1129 | .hw_data (1'b0), |
| 1130 | .cp (clk), |
| 1131 | .q (msi_64_addr_reg_csrbus_read_data[59]) |
| 1132 | ); |
| 1133 | |
| 1134 | // bit 60 |
| 1135 | csr_sw csr_sw_60 |
| 1136 | ( |
| 1137 | // synopsys translate_off |
| 1138 | .omni_ld (omni_ld), |
| 1139 | .omni_data (omni_data[60]), |
| 1140 | .omni_rw_alias (1'b1), |
| 1141 | .omni_rw1c_alias (1'b0), |
| 1142 | .omni_rw1s_alias (1'b0), |
| 1143 | // synopsys translate_on |
| 1144 | .rst (rst_l_active_high), |
| 1145 | .rst_val (reset_addr[44]), |
| 1146 | .csr_ld (w_ld), |
| 1147 | .csr_data (csrbus_wr_data[60]), |
| 1148 | .rw_alias (1'b1), |
| 1149 | .rw1c_alias (1'b0), |
| 1150 | .rw1s_alias (1'b0), |
| 1151 | .hw_ld (1'b0), |
| 1152 | .hw_data (1'b0), |
| 1153 | .cp (clk), |
| 1154 | .q (msi_64_addr_reg_csrbus_read_data[60]) |
| 1155 | ); |
| 1156 | |
| 1157 | // bit 61 |
| 1158 | csr_sw csr_sw_61 |
| 1159 | ( |
| 1160 | // synopsys translate_off |
| 1161 | .omni_ld (omni_ld), |
| 1162 | .omni_data (omni_data[61]), |
| 1163 | .omni_rw_alias (1'b1), |
| 1164 | .omni_rw1c_alias (1'b0), |
| 1165 | .omni_rw1s_alias (1'b0), |
| 1166 | // synopsys translate_on |
| 1167 | .rst (rst_l_active_high), |
| 1168 | .rst_val (reset_addr[45]), |
| 1169 | .csr_ld (w_ld), |
| 1170 | .csr_data (csrbus_wr_data[61]), |
| 1171 | .rw_alias (1'b1), |
| 1172 | .rw1c_alias (1'b0), |
| 1173 | .rw1s_alias (1'b0), |
| 1174 | .hw_ld (1'b0), |
| 1175 | .hw_data (1'b0), |
| 1176 | .cp (clk), |
| 1177 | .q (msi_64_addr_reg_csrbus_read_data[61]) |
| 1178 | ); |
| 1179 | |
| 1180 | // bit 62 |
| 1181 | csr_sw csr_sw_62 |
| 1182 | ( |
| 1183 | // synopsys translate_off |
| 1184 | .omni_ld (omni_ld), |
| 1185 | .omni_data (omni_data[62]), |
| 1186 | .omni_rw_alias (1'b1), |
| 1187 | .omni_rw1c_alias (1'b0), |
| 1188 | .omni_rw1s_alias (1'b0), |
| 1189 | // synopsys translate_on |
| 1190 | .rst (rst_l_active_high), |
| 1191 | .rst_val (reset_addr[46]), |
| 1192 | .csr_ld (w_ld), |
| 1193 | .csr_data (csrbus_wr_data[62]), |
| 1194 | .rw_alias (1'b1), |
| 1195 | .rw1c_alias (1'b0), |
| 1196 | .rw1s_alias (1'b0), |
| 1197 | .hw_ld (1'b0), |
| 1198 | .hw_data (1'b0), |
| 1199 | .cp (clk), |
| 1200 | .q (msi_64_addr_reg_csrbus_read_data[62]) |
| 1201 | ); |
| 1202 | |
| 1203 | // bit 63 |
| 1204 | csr_sw csr_sw_63 |
| 1205 | ( |
| 1206 | // synopsys translate_off |
| 1207 | .omni_ld (omni_ld), |
| 1208 | .omni_data (omni_data[63]), |
| 1209 | .omni_rw_alias (1'b1), |
| 1210 | .omni_rw1c_alias (1'b0), |
| 1211 | .omni_rw1s_alias (1'b0), |
| 1212 | // synopsys translate_on |
| 1213 | .rst (rst_l_active_high), |
| 1214 | .rst_val (reset_addr[47]), |
| 1215 | .csr_ld (w_ld), |
| 1216 | .csr_data (csrbus_wr_data[63]), |
| 1217 | .rw_alias (1'b1), |
| 1218 | .rw1c_alias (1'b0), |
| 1219 | .rw1s_alias (1'b0), |
| 1220 | .hw_ld (1'b0), |
| 1221 | .hw_data (1'b0), |
| 1222 | .cp (clk), |
| 1223 | .q (msi_64_addr_reg_csrbus_read_data[63]) |
| 1224 | ); |
| 1225 | |
| 1226 | |
| 1227 | endmodule // dmu_imu_ics_csr_msi_64_addr_reg_entry |