| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_pmu_prm.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_pmu_prm ( |
| 36 | clk, |
| 37 | rst_l, |
| 38 | |
| 39 | // Debug |
| 40 | cr2pm_dbg_sel_a, |
| 41 | cr2pm_dbg_sel_b, |
| 42 | pm2cr_dbg_a, |
| 43 | pm2cr_dbg_b, |
| 44 | |
| 45 | cm2pm_rcd_enq, |
| 46 | cm2pm_rcd, |
| 47 | pm2cm_rcd_full, |
| 48 | pm2cl_rcd_enq, |
| 49 | pm2cl_rcd, |
| 50 | cl2pm_rcd_full, |
| 51 | pm2ps_i_req, |
| 52 | ps2pm_i_gnt, |
| 53 | pm2ps_i_trn, |
| 54 | ps2pm_i_n_trn, |
| 55 | pm2ps_i_cmd_type, |
| 56 | ps2pm_i_full, |
| 57 | pm2ps_i_wr_data, |
| 58 | ps2pm_i_rd_data |
| 59 | ); |
| 60 | |
| 61 | //************************************************ |
| 62 | // PARAMETERS |
| 63 | //************************************************ |
| 64 | |
| 65 | // Ingress Packet Record Field Widths |
| 66 | |
| 67 | // parameter CM2PM_WDTH = `FIRE_DLC_IPR_REC_WDTH, //93 |
| 68 | |
| 69 | parameter IPRMSB = `FIRE_DLC_IPR_MSB; // CM2PM_WDTH -1 |
| 70 | |
| 71 | parameter PRTYP_WDTH = `FIRE_DLC_IPR_TYP_WDTH, // 7 |
| 72 | PRLEN_WDTH = `FIRE_DLC_IPR_LEN_WDTH, //10 |
| 73 | PRBYTCNT_WDTH = `FIRE_DLC_IPR_BYTCNT_WDTH, //12 |
| 74 | PRCNTXTNUM_WDTH = `FIRE_DLC_IPR_CNTXTNUM_WDTH, // 5 |
| 75 | PRPKSEQNUM_WDTH = `FIRE_DLC_IPR_PKSEQNUM_WDTH, // 5 |
| 76 | PRADDR_WDTH = `FIRE_DLC_IPR_ADDR_WDTH, //41 |
| 77 | PRADDRERR_WDTH = `FIRE_DLC_IPR_ADDRERR_WDTH, // 1 |
| 78 | PRDPTR_WDTH = `FIRE_DLC_IPR_DPTR_WDTH, // 7 |
| 79 | PRSBDTAG_WDTH = `FIRE_DLC_IPR_SBDTAG_WDTH; // 5 |
| 80 | |
| 81 | parameter PRTYPMSB = PRTYP_WDTH -1, |
| 82 | PRLENMSB = PRLEN_WDTH -1, |
| 83 | PRBYTCNTMSB = PRBYTCNT_WDTH -1, |
| 84 | PRCNTXTNUMMSB = PRCNTXTNUM_WDTH -1, |
| 85 | PRPKSEQNUMMSB = PRPKSEQNUM_WDTH -1, |
| 86 | PRADDRMSB = PRADDR_WDTH -1, |
| 87 | PRADDRERRMSB = PRADDRERR_WDTH -1, |
| 88 | PRDPTRMSB = PRDPTR_WDTH -1, |
| 89 | PRSBDTAGMSB = PRSBDTAG_WDTH -1; |
| 90 | |
| 91 | // Ingress Command Record Field Widths |
| 92 | // parameter PM2CL_WDTH = `FIRE_DLC_ICR_REC_WDTH, //60 |
| 93 | |
| 94 | parameter ICRMSB = `FIRE_DLC_ICR_MSB; // PM2CL_WDTH -1; |
| 95 | |
| 96 | parameter CRTYP_WDTH = `FIRE_DLC_ICR_TYP_WDTH, // 7 |
| 97 | // CRCLSTS_WDTH = `FIRE_DLC_ICR_CLSTS_WDTH, // 1 |
| 98 | CRADDR_WDTH = `FIRE_DLC_ICR_ADDR_WDTH, //37 |
| 99 | CRSTAT_WDTH = `FIRE_DLC_ICR_STAT_WDTH, // 3 |
| 100 | CRDPTR_WDTH = `FIRE_DLC_ICR_DPTR_WDTH, // 7 |
| 101 | CRSBDTAG_WDTH = `FIRE_DLC_ICR_SBDTAG_WDTH; // 5 |
| 102 | |
| 103 | parameter CRTYPMSB = CRTYP_WDTH -1, |
| 104 | CRADDRMSB = CRADDR_WDTH -1, |
| 105 | CRSTATMSB = CRSTAT_WDTH -1, |
| 106 | CRDPTRMSB = CRDPTR_WDTH -1, |
| 107 | CRSBDTAGMSB = CRSBDTAG_WDTH -1; |
| 108 | |
| 109 | |
| 110 | // Packet Scoreboard (PSB) Record Field Widths |
| 111 | parameter PM2PS_RCDWDTH = 41; |
| 112 | |
| 113 | parameter PSRCDMSB = PM2PS_RCDWDTH -1; |
| 114 | |
| 115 | parameter PSCMDTYPE_WDTH = 4, |
| 116 | PSCMDTRN_WDTH = 5, |
| 117 | PSITRN_WDTH = 5, |
| 118 | //BP n2 5-24-04 |
| 119 | // PSRDWDTH = 6, |
| 120 | PSRDWDTH = 7, |
| 121 | CLTOT_WDTH = 4; |
| 122 | |
| 123 | parameter PSCMDTYPMSB = PSCMDTYPE_WDTH -1; |
| 124 | parameter PSCMDTRNMSB = PSCMDTRN_WDTH -1; |
| 125 | parameter PSRDMSB = PSRDWDTH -1; |
| 126 | parameter PSITRNMSB = PSITRN_WDTH -1; |
| 127 | parameter CLTOTMSB = CLTOT_WDTH -1; |
| 128 | |
| 129 | //************************************************ |
| 130 | // PORTS |
| 131 | //************************************************ |
| 132 | |
| 133 | input clk; // input clock |
| 134 | input rst_l; // synopsys sync_set_reset "rst_l" |
| 135 | input cm2pm_rcd_enq; // enqueue to packet record queue |
| 136 | input [IPRMSB :0] cm2pm_rcd; // packet record in |
| 137 | output pm2cm_rcd_full; // packet record queue is full |
| 138 | |
| 139 | output pm2cl_rcd_enq; // enqueue output command record |
| 140 | output [ICRMSB :0] pm2cl_rcd; // command record out |
| 141 | input cl2pm_rcd_full; // CLU record fifo full |
| 142 | |
| 143 | output pm2ps_i_req; // PSB request |
| 144 | input ps2pm_i_gnt; // PSB grant |
| 145 | output [PSITRNMSB :0] pm2ps_i_trn; // pk_tag to look up |
| 146 | |
| 147 | input [PSCMDTRNMSB :0] ps2pm_i_n_trn; // carries pk_tag from PSB |
| 148 | output [PSCMDTYPMSB :0] pm2ps_i_cmd_type; // command for PSB to run |
| 149 | input ps2pm_i_full; // PSB full indicator |
| 150 | output [PSRCDMSB :0] pm2ps_i_wr_data; // PSB record data |
| 151 | |
| 152 | input [PSRDMSB :0] ps2pm_i_rd_data; |
| 153 | |
| 154 | // Debug Ports |
| 155 | input [`FIRE_DLC_PMU_DS_BITS] cr2pm_dbg_sel_a; // PMU debug select a |
| 156 | input [`FIRE_DLC_PMU_DS_BITS] cr2pm_dbg_sel_b; // PMU debug select b |
| 157 | |
| 158 | output [`FIRE_DBG_DATA_BITS] pm2cr_dbg_a; // PMU debug output a |
| 159 | output [`FIRE_DBG_DATA_BITS] pm2cr_dbg_b; // PMU debug output b |
| 160 | |
| 161 | //************************************************ |
| 162 | // SIGNALS |
| 163 | //************************************************ |
| 164 | |
| 165 | // Packet Record queue signals |
| 166 | wire pkmpty; |
| 167 | |
| 168 | // Packet Record field assignments to PRM signals |
| 169 | wire [PRTYPMSB :0] pkttyp; |
| 170 | wire [PRLENMSB :0] pktlen; |
| 171 | wire [PRBYTCNTMSB :0] pktbyt_cnt; |
| 172 | wire [PRCNTXTNUMMSB :0] pktcntxt_num; |
| 173 | wire [PRPKSEQNUMMSB :0] pktseq_num; |
| 174 | wire [PRADDRMSB :0] pktaddr; |
| 175 | wire [PRADDRERRMSB :0] pktaddr_err; |
| 176 | wire [PRDPTRMSB :0] pktdptr; |
| 177 | wire [PRSBDTAGMSB :0] pkttr_tag; |
| 178 | |
| 179 | reg ld_pipe; |
| 180 | reg ld_ptr; |
| 181 | |
| 182 | // Command Record field assignments to PRM signals |
| 183 | |
| 184 | reg [CLTOTMSB :0] pipe_cltot; |
| 185 | reg [3:0] pipe_clastyp; |
| 186 | reg [CRTYPMSB :0] pipe_typ; |
| 187 | //BP n2 5-24-04 |
| 188 | // reg [CRADDRMSB :6] pipe_addr_hi; |
| 189 | reg [CRADDRMSB :7] pipe_addr_hi; |
| 190 | //BP n2 5-24-04 |
| 191 | // reg [5 :0] pipe_addr_lo; |
| 192 | reg [6 :0] pipe_addr_lo; |
| 193 | reg pipe_clsts; |
| 194 | reg [CRSTATMSB :0] pipe_stat; |
| 195 | reg [CRDPTRMSB :0] pipe_dptr; |
| 196 | reg [CRSBDTAGMSB :0] pipe_sbdtag; |
| 197 | reg [PRLENMSB :0] pipe_pktlen; |
| 198 | reg [PRBYTCNTMSB :0] pipe_pktbyt_cnt; |
| 199 | reg pipe_multicycle; |
| 200 | reg pipe_full; |
| 201 | |
| 202 | wire [CLTOTMSB :0] new_pktlen; |
| 203 | wire [PRLENMSB :0] offset_len; |
| 204 | wire [PRLENMSB :0] rem_len; |
| 205 | wire [CLTOTMSB :0] trail; |
| 206 | |
| 207 | // alignment |
| 208 | wire [PRLENMSB :0] real_size; |
| 209 | wire [PRLENMSB :0] align_size; |
| 210 | wire align_adj; |
| 211 | wire [PRLENMSB :0] block_size; |
| 212 | wire block_adj; |
| 213 | wire last_clsts; |
| 214 | reg line_clsts; |
| 215 | reg [3 :0] persist_last_dwbe; |
| 216 | |
| 217 | // Packet Scoreboard record field assignments |
| 218 | wire [PSRCDMSB :0] next_pm2ps_i_wr_data; // next PSB record data |
| 219 | wire [PRLENMSB :0] cacheline; |
| 220 | |
| 221 | // Registers |
| 222 | reg pm2cl_rcd_enq; |
| 223 | reg next_gen_crcd, gen_crcd; |
| 224 | reg next_deq_rcd; |
| 225 | reg next_gen_trn; |
| 226 | |
| 227 | reg [1:0] deq_state; |
| 228 | reg [1:0] deq_next; |
| 229 | |
| 230 | reg [1:0] bld_state; |
| 231 | reg [1:0] bld_next; |
| 232 | |
| 233 | reg [CRTYPMSB :0] cmd_typ; |
| 234 | reg cmd_clsts; |
| 235 | reg [3:0] cmd_clastyp; |
| 236 | //BP n2 5-24-04 |
| 237 | // reg [CRADDRMSB :6] cmd_addr_hi; |
| 238 | reg [CRADDRMSB :7] cmd_addr_hi; |
| 239 | //BP n2 5-24-04 |
| 240 | // reg [5 :0] cmd_addr_lo; |
| 241 | reg [6 :0] cmd_addr_lo; |
| 242 | reg [CRSTATMSB :0] cmd_stat; |
| 243 | reg [CRDPTRMSB :0] cmd_dptr; |
| 244 | reg [CRSBDTAGMSB :0] cmd_sbdtag; |
| 245 | reg [CLTOTMSB :0] cmd_cltot; |
| 246 | reg [PRLENMSB :0] cmd_pktlen; |
| 247 | reg cmd_multicycle; |
| 248 | |
| 249 | reg [CLTOTMSB :0] num_cmd; |
| 250 | reg [PSCMDTYPMSB :0] next_scbd_fun; |
| 251 | reg [PSCMDTYPMSB :0] pm2ps_i_cmd_type; |
| 252 | reg [PSRCDMSB :0] pm2ps_i_wr_data; // PSB record data |
| 253 | reg pm2ps_i_req; |
| 254 | reg [PSITRNMSB :0] pm2ps_i_trn; |
| 255 | |
| 256 | reg multicycle; |
| 257 | reg [3:0] clastyp; |
| 258 | |
| 259 | reg [PRLENMSB :0] next_pktlen; |
| 260 | reg next_clsts; |
| 261 | |
| 262 | reg [CRSTATMSB :0] next_stat; |
| 263 | reg [CLTOTMSB :0] next_cltot; |
| 264 | reg [PRBYTCNTMSB :0] next_pktbyt_cnt; |
| 265 | |
| 266 | reg pmu_is_idle; |
| 267 | |
| 268 | // Debug |
| 269 | wire [`FIRE_DLC_PMU_PRM_DS_BITS] dbg2prm_dbg_sel_a; |
| 270 | wire [`FIRE_DLC_PMU_PRM_DS_BITS] dbg2prm_dbg_sel_b; |
| 271 | reg [`FIRE_DLC_PMU_PRM_DS_BITS] prm_dbg_sel [0:1]; |
| 272 | |
| 273 | wire [`FIRE_DBG_DATA_BITS] prm2dbg_dbg1_a; |
| 274 | wire [`FIRE_DBG_DATA_BITS] prm2dbg_dbg1_b; |
| 275 | wire [`FIRE_DBG_DATA_BITS] prm2dbg_dbg2_a; |
| 276 | wire [`FIRE_DBG_DATA_BITS] prm2dbg_dbg2_b; |
| 277 | reg [`FIRE_DBG_DATA_BITS] nxt_prm_dbg1_bus [0:1]; |
| 278 | reg [`FIRE_DBG_DATA_BITS] nxt_prm_dbg2_bus [0:1]; |
| 279 | reg [`FIRE_DBG_DATA_BITS] prm_dbg1_bus [0:1]; |
| 280 | reg [`FIRE_DBG_DATA_BITS] prm_dbg2_bus [0:1]; |
| 281 | |
| 282 | reg [`FIRE_DBG_DATA_BITS] dbg_bus [0:1]; |
| 283 | reg [`FIRE_DBG_DATA_BITS] nxt_dbg_bus [0:1]; |
| 284 | integer i, j, k, l; |
| 285 | |
| 286 | // *************** Local Declarations ************************************* |
| 287 | |
| 288 | parameter DEQIDLE = 2'b00, // Idle |
| 289 | DEQGNT = 2'b01, // psb gnt wait state |
| 290 | DEQ = 2'b10; // dequeue packets |
| 291 | |
| 292 | parameter BLDIDLE = 2'b00, // Idle |
| 293 | BLDXFR = 2'b01; // write commands ready |
| 294 | |
| 295 | parameter CLASWR = 4'b0001, |
| 296 | CLASRD = 4'b0010, |
| 297 | CLASRDL = 4'b0000, |
| 298 | CLASPIO = 4'b0011, |
| 299 | CLASUNSP = 4'b0100, |
| 300 | CLASMSG = 4'b0101, |
| 301 | CLASMSI = 4'b0110, |
| 302 | CLASMDO = 4'b0111, |
| 303 | CLASNUL = 4'b1000; |
| 304 | |
| 305 | //************************************************ |
| 306 | // Zero In checkers |
| 307 | //************************************************ |
| 308 | |
| 309 | // Request Grant check |
| 310 | // 0in req_ack -req pm2ps_i_req -ack ps2pm_i_gnt -req_until_ack |
| 311 | |
| 312 | // deq_fsm |
| 313 | //0in state_transition -var deq_state -val DEQIDLE -next DEQIDLE DEQGNT DEQ |
| 314 | //0in state_transition -var deq_state -val DEQGNT -next DEQGNT DEQ |
| 315 | //0in state_transition -var deq_state -val DEQ -next DEQIDLE |
| 316 | |
| 317 | // build_crcd (pipeline staging and command record build) |
| 318 | //0in state_transition -var bld_state -val BLDIDLE -next BLDXFR BLDIDLE |
| 319 | //0in state_transition -var bld_state -val BLDXFR -next BLDXFR BLDIDLE |
| 320 | |
| 321 | // *************** Build Command Record Procedures (build_crcd)*********/ |
| 322 | |
| 323 | // Transaction Type Decode - PSB Function Encoding(typ_dcd) |
| 324 | always @(pkttyp) |
| 325 | begin |
| 326 | clastyp[3:0] = 0; |
| 327 | next_scbd_fun = 4'b0000; |
| 328 | |
| 329 | case (pkttyp) // synopsys parallel_case |
| 330 | 7'b0000000 : begin |
| 331 | clastyp[3:0] = CLASRD; // DMAMR |
| 332 | next_scbd_fun = 4'b0101; |
| 333 | end |
| 334 | 7'b0100000 : begin |
| 335 | clastyp[3:0] = CLASRD; // DMAMR |
| 336 | next_scbd_fun = 4'b0101; |
| 337 | end |
| 338 | 7'b0000001 : begin |
| 339 | clastyp[3:0] = CLASRDL; // DMAMRDLK |
| 340 | next_scbd_fun = 4'b0101; |
| 341 | end |
| 342 | 7'b0100001 : begin |
| 343 | clastyp[3:0] = CLASRDL; // DMARDLK_alt |
| 344 | next_scbd_fun = 4'b0101; |
| 345 | end |
| 346 | 7'b0001001 : begin |
| 347 | clastyp[3:0] = CLASUNSP; // UNSUP |
| 348 | next_scbd_fun = 4'b0101; |
| 349 | end |
| 350 | 7'b1000000 : begin |
| 351 | clastyp[3:0] = CLASWR; // DMAMWR |
| 352 | next_scbd_fun = 4'b0000; |
| 353 | end |
| 354 | 7'b1100000 : begin |
| 355 | clastyp[3:0] = CLASWR; // DMAMWR |
| 356 | next_scbd_fun = 4'b0000; |
| 357 | end |
| 358 | 7'b1111000 : begin |
| 359 | clastyp[3:0] = CLASMSI; // MSIEQWR |
| 360 | next_scbd_fun = 4'b0000; |
| 361 | end |
| 362 | 7'b1011000 : begin |
| 363 | clastyp[3:0] = CLASMSI; // MSIEQWR |
| 364 | next_scbd_fun = 4'b0000; |
| 365 | end |
| 366 | 7'b1110000 : begin |
| 367 | clastyp[3:0] = CLASMSG; // MSGEQWR |
| 368 | next_scbd_fun = 4'b0000; |
| 369 | end |
| 370 | 7'b1010000 : begin |
| 371 | clastyp[3:0] = CLASMSG; // MSGEQWR |
| 372 | next_scbd_fun = 4'b0000; |
| 373 | end |
| 374 | 7'b1111100 : begin |
| 375 | clastyp[3:0] = CLASNUL; // NULL |
| 376 | next_scbd_fun = 4'b0000; |
| 377 | end |
| 378 | 7'b1111010 : begin |
| 379 | clastyp[3:0] = CLASMDO; // MDO |
| 380 | next_scbd_fun = 4'b0000; |
| 381 | end |
| 382 | 7'b0001010 : begin |
| 383 | clastyp[3:0] = CLASPIO; // PIOCP |
| 384 | next_scbd_fun = 4'b1001; |
| 385 | end |
| 386 | 7'b1001010 : begin |
| 387 | clastyp[3:0] = CLASPIO; // PIOCPLD |
| 388 | next_scbd_fun = 4'b1001; |
| 389 | end |
| 390 | default : begin |
| 391 | clastyp[3:0] = 4'b1111; // to satisfy vlint |
| 392 | next_scbd_fun = 4'b0000; |
| 393 | end |
| 394 | endcase // case(pkttyp) |
| 395 | end // always @ (pkttyp) |
| 396 | |
| 397 | // Parse Packet Record to issue Command Records |
| 398 | // lengths are represented in DW's |
| 399 | |
| 400 | always @(clastyp or pktaddr_err or pktlen or pktaddr or pktbyt_cnt or |
| 401 | pktcntxt_num or cacheline or new_pktlen or align_adj or |
| 402 | block_adj or rem_len or trail) |
| 403 | begin |
| 404 | next_cltot[CLTOTMSB :0] = 0; |
| 405 | next_pktlen[PRLENMSB :0] = 0; |
| 406 | next_clsts = 0; |
| 407 | next_stat[CRSTATMSB :0] = 0; |
| 408 | multicycle = 0; |
| 409 | |
| 410 | case (clastyp) // synopsys full_case parallel_case |
| 411 | CLASWR: begin // DMA Wr |
| 412 | next_pktbyt_cnt[PRBYTCNTMSB :0] = pktbyt_cnt; |
| 413 | if (pktlen < cacheline) begin //(length LT 16) |
| 414 | if (pktaddr[3:0] == 4'h0) begin // aligned |
| 415 | next_pktlen[PRLENMSB :0] = pktlen[PRLENMSB :0]; // DW's |
| 416 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 417 | if(align_adj) begin |
| 418 | next_cltot[CLTOTMSB :0] = 4'b0010; |
| 419 | multicycle = 1'b1; |
| 420 | |
| 421 | if(pktbyt_cnt[7:0] == 8'hff) next_clsts = 1'b0; |
| 422 | else next_clsts = 1'b1; |
| 423 | |
| 424 | end |
| 425 | else begin |
| 426 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 427 | next_clsts = 1'b1; |
| 428 | multicycle = 1'b0; |
| 429 | end |
| 430 | end // if (pktaddr[3:0] == 4'h0) |
| 431 | else begin // unaligned |
| 432 | next_pktlen[PRLENMSB :0] = pktlen[PRLENMSB :0]; // DW's |
| 433 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 434 | if(align_adj) begin |
| 435 | next_cltot[CLTOTMSB :0] = 4'b0010; |
| 436 | next_clsts = 1'b1; |
| 437 | multicycle = 1'b1; |
| 438 | end |
| 439 | else begin |
| 440 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 441 | next_clsts = 1'b1; |
| 442 | multicycle = 1'b0; |
| 443 | end |
| 444 | end // else: !if(pktaddr[3:0] == 4'h0) |
| 445 | end // if (pktlen < cacheline) |
| 446 | |
| 447 | if (pktlen == cacheline) begin //(length LT 16) |
| 448 | if (pktaddr[3:0] == 4'h0) begin // aligned |
| 449 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 450 | next_pktlen[PRLENMSB :0] = pktlen[PRLENMSB :0]; // DW's |
| 451 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 452 | multicycle = 1'b0; |
| 453 | |
| 454 | if(pktbyt_cnt[7:0] == 8'hff) next_clsts = 1'b0; |
| 455 | else next_clsts = 1'b1; |
| 456 | |
| 457 | end // if ((pktlen[PRLENMSB :0] < 5'h10)... |
| 458 | else begin // unaligned |
| 459 | next_pktlen[PRLENMSB :0] = pktlen[PRLENMSB :0]; // DW's |
| 460 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 461 | if(block_adj) begin |
| 462 | next_cltot[CLTOTMSB :0] = 4'b0010; |
| 463 | next_clsts = 1'b1; |
| 464 | multicycle = 1'b1; |
| 465 | end |
| 466 | else begin |
| 467 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 468 | next_clsts = 1'b0; |
| 469 | multicycle = 1'b0; |
| 470 | end |
| 471 | end // else: !if(pktaddr[3:0] == 4'h0) |
| 472 | end // if (pktlen < cacheline) |
| 473 | |
| 474 | if (pktlen > cacheline) begin |
| 475 | if (pktaddr[3:0] == 4'h0) begin // aligned |
| 476 | next_pktlen[PRLENMSB :0] = pktlen[PRLENMSB :0]; // DW's |
| 477 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 478 | multicycle = 1'b1; |
| 479 | |
| 480 | if(pktbyt_cnt[3:0] == 4'hf) next_clsts = 1'b0; |
| 481 | else next_clsts = 1'b1; |
| 482 | |
| 483 | if(block_adj) begin |
| 484 | next_cltot[CLTOTMSB :0] = new_pktlen[CLTOTMSB :0] + 4'h1; |
| 485 | end |
| 486 | else begin |
| 487 | next_cltot[CLTOTMSB :0] = new_pktlen[CLTOTMSB :0]; |
| 488 | end |
| 489 | end |
| 490 | else begin // unaligned |
| 491 | next_pktlen[PRLENMSB :0] = pktlen[PRLENMSB :0]; // DW's |
| 492 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 493 | next_clsts = 1'b1; |
| 494 | multicycle = 1'b1; |
| 495 | if(block_adj) begin |
| 496 | next_cltot[CLTOTMSB :0] = new_pktlen[CLTOTMSB :0] + 4'h1; |
| 497 | end |
| 498 | else begin |
| 499 | next_cltot[CLTOTMSB :0] = new_pktlen[CLTOTMSB :0]; |
| 500 | end |
| 501 | end // else: !if(pktaddr[3:0] == 4'h0) |
| 502 | end // if (pktlen > cacheline) |
| 503 | end // case: CLASWR |
| 504 | |
| 505 | CLASRD : begin // DMA Rd |
| 506 | next_pktbyt_cnt[PRBYTCNTMSB :0] = pktbyt_cnt; |
| 507 | if (pktlen <= cacheline) begin //(length LE 16) |
| 508 | if (pktaddr[3:0] == 4'h0) begin // aligned |
| 509 | if(pktaddr_err) begin |
| 510 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 511 | next_pktlen[PRLENMSB :0] = 10'h000; // DW's |
| 512 | next_clsts = 1'b1; |
| 513 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 514 | multicycle = 1'b0; |
| 515 | end |
| 516 | else begin |
| 517 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 518 | next_pktlen[PRLENMSB :0] = pktlen[PRLENMSB :0]; // DW's |
| 519 | next_clsts = 1'b1; |
| 520 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 521 | multicycle = 1'b0; |
| 522 | end |
| 523 | end // if (pktaddr[3:0] == 4'h0) |
| 524 | else begin // unaligned |
| 525 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 526 | if(align_adj) begin |
| 527 | if(pktaddr_err) begin |
| 528 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 529 | next_pktlen[PRLENMSB :0] = 10'h000; // DW's |
| 530 | next_clsts = 1'b1; |
| 531 | multicycle = 1'b0; |
| 532 | end |
| 533 | else begin |
| 534 | next_cltot[CLTOTMSB :0] = 4'b0010; |
| 535 | next_pktlen[PRLENMSB :0] = pktlen[PRLENMSB :0]; // DW's |
| 536 | next_clsts = 1'b1; |
| 537 | multicycle = 1'b1; |
| 538 | end // else: !if(pktaddr_err) |
| 539 | end // if (align_adj) |
| 540 | else begin |
| 541 | if(pktaddr_err) begin |
| 542 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 543 | next_pktlen[PRLENMSB :0] = 10'h000; // DW's |
| 544 | next_clsts = 1'b1; |
| 545 | multicycle = 1'b0; |
| 546 | end |
| 547 | else begin |
| 548 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 549 | next_pktlen[PRLENMSB :0] = pktlen[PRLENMSB :0]; // DW's |
| 550 | next_clsts = 1'b1; |
| 551 | multicycle = 1'b0; |
| 552 | end // else: !if(pktaddr_err) |
| 553 | end // else: !if(align_adj) |
| 554 | end // else: !if(pktaddr[3:0] == 4'h0) |
| 555 | end // if (pktlen <= cacheline) |
| 556 | |
| 557 | if (pktlen > cacheline) begin //(length GT 16) |
| 558 | if (pktaddr[3:0] == 4'h0) begin // aligned |
| 559 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 560 | if(pktaddr_err) begin |
| 561 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 562 | next_pktlen[PRLENMSB :0] = 10'h000; // DW's |
| 563 | next_clsts = 1'b1; |
| 564 | multicycle = 1'b0; |
| 565 | end |
| 566 | else begin |
| 567 | next_cltot[CLTOTMSB :0] = 4'h1 + rem_len[7:4] + trail; |
| 568 | next_pktlen[PRLENMSB :0] = pktlen[PRLENMSB :0]; // DW's |
| 569 | next_clsts = 1'b1; |
| 570 | multicycle = 1'b1; |
| 571 | end // else: !if(pktaddr_err) |
| 572 | end // if (pktaddr[3:0] == 4'h0) |
| 573 | else begin // unaligned |
| 574 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 575 | if(pktaddr_err) begin |
| 576 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 577 | next_pktlen[PRLENMSB :0] = 10'h000; // DW's |
| 578 | next_clsts = 1'b1; |
| 579 | multicycle = 1'b0; |
| 580 | end |
| 581 | else begin |
| 582 | next_cltot[CLTOTMSB :0] = 4'h1 + rem_len[7:4] + trail; |
| 583 | next_pktlen[PRLENMSB :0] = pktlen[PRLENMSB :0]; // DW's |
| 584 | next_clsts = 1'b1; |
| 585 | multicycle = 1'b1; |
| 586 | end // else: !if(pktaddr_err) |
| 587 | end // else: !if(pktaddr[3:0] == 4'h0) |
| 588 | end // if (pktlen > cacheline) |
| 589 | end // case: CLASRD |
| 590 | |
| 591 | CLASPIO : begin // PIO CplD |
| 592 | next_pktbyt_cnt[PRBYTCNTMSB :0] = pktbyt_cnt; |
| 593 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 594 | next_pktlen[PRLENMSB :0] = pktlen[PRLENMSB :0]; // DW's |
| 595 | if (pktlen == cacheline) next_clsts = 1'b0; |
| 596 | else next_clsts = 1'b1; |
| 597 | |
| 598 | next_stat[CRSTATMSB :0] = pktcntxt_num[2:0]; |
| 599 | multicycle = 1'b0; |
| 600 | end |
| 601 | |
| 602 | CLASRDL, // DMARdLk |
| 603 | CLASNUL : begin // 'Null |
| 604 | next_pktbyt_cnt[PRBYTCNTMSB :0] = pktbyt_cnt; |
| 605 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 606 | next_pktlen[PRLENMSB :0] = 10'h000; // DW's |
| 607 | next_clsts = 1'b0; |
| 608 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 609 | multicycle = 1'b0; |
| 610 | end |
| 611 | |
| 612 | CLASUNSP : begin // Unsup |
| 613 | next_pktbyt_cnt[PRBYTCNTMSB :0] = 12'h004; |
| 614 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 615 | next_pktlen[PRLENMSB :0] = 10'h000; |
| 616 | next_clsts = 1'b0; |
| 617 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 618 | multicycle = 1'b0; |
| 619 | end |
| 620 | |
| 621 | CLASMSI, |
| 622 | CLASMSG, |
| 623 | CLASMDO : begin // MSI,MSG,Mondo Wr |
| 624 | next_pktbyt_cnt[PRBYTCNTMSB :0] = pktbyt_cnt; |
| 625 | |
| 626 | if ((pktlen == cacheline) //(length EQ 16) |
| 627 | && (pktaddr[3:0] == 4'h0)) |
| 628 | begin |
| 629 | next_cltot[CLTOTMSB :0] = 4'b0001; |
| 630 | next_pktlen[PRLENMSB :0] = pktlen[PRLENMSB :0]; // DW's |
| 631 | next_clsts = 1'b0; |
| 632 | next_stat[CRSTATMSB :0] = {2'b00,pktaddr_err}; |
| 633 | multicycle = 1'b0; |
| 634 | end // if ((pktlen[PRLENMSB :0] == 5'h10)... |
| 635 | end // case: CLASMSI,... |
| 636 | |
| 637 | default begin |
| 638 | next_pktbyt_cnt[PRBYTCNTMSB :0] = 0; |
| 639 | next_cltot[CLTOTMSB :0] = 0; |
| 640 | next_pktlen[PRLENMSB :0] = 0; |
| 641 | next_clsts = 0; |
| 642 | next_stat[CRSTATMSB :0] = 0; |
| 643 | multicycle = 0; |
| 644 | end |
| 645 | endcase // case(clastyp) |
| 646 | end // always @ (clastyp or pktaddr_err or pktlen or pktaddr or pktbyt_cnt... |
| 647 | |
| 648 | // Pipelined computed values for the next multi-command |
| 649 | // build for a given packet record. |
| 650 | |
| 651 | always @(posedge clk) |
| 652 | begin |
| 653 | if (rst_l == 1'b0) begin |
| 654 | num_cmd <= 0; // command counter |
| 655 | end |
| 656 | else begin |
| 657 | case ({bld_state,cmd_multicycle}) // synopsys parallel_case |
| 658 | {BLDIDLE,1'b0}, |
| 659 | {BLDIDLE,1'b1} : num_cmd <= 0; |
| 660 | {BLDXFR, 1'b0} : num_cmd <= 0; |
| 661 | {BLDXFR, 1'b1} : num_cmd <= next_gen_crcd ? (num_cmd + 1'b1) : num_cmd; |
| 662 | default : num_cmd <= num_cmd; |
| 663 | endcase // case({bld_state,pipe_multicycle}) |
| 664 | end // else: !if(rst_l == 1'b0) |
| 665 | end // always @ (posedge clk) |
| 666 | |
| 667 | // Pipeline stages for Command build |
| 668 | always @(posedge clk) |
| 669 | if (rst_l == 1'b0) begin |
| 670 | pipe_clastyp <= 4'b0; |
| 671 | pipe_cltot <= {CLTOT_WDTH{1'b0}}; |
| 672 | pipe_typ <= {CRTYP_WDTH{1'b0}}; |
| 673 | pipe_pktlen <= {PRLEN_WDTH{1'b0}}; |
| 674 | pipe_pktbyt_cnt <= {PRBYTCNT_WDTH{1'b0}}; |
| 675 | pipe_addr_hi <= {(CRADDR_WDTH -7){1'b0}}; |
| 676 | pipe_addr_lo <= 7'b0; |
| 677 | pipe_dptr <= {CRDPTR_WDTH{1'b0}}; |
| 678 | pipe_clsts <= 1'b0; |
| 679 | pipe_stat <= {CRSTAT_WDTH{1'b0}}; |
| 680 | pipe_multicycle <= 1'b0; |
| 681 | pipe_sbdtag <= {CRSBDTAG_WDTH{1'b0}}; |
| 682 | end |
| 683 | else begin |
| 684 | pipe_clastyp <= ld_pipe ? clastyp : pipe_clastyp; |
| 685 | pipe_cltot <= ld_pipe ? next_cltot : pipe_cltot; |
| 686 | pipe_typ <= ld_pipe ? pkttyp : pipe_typ; |
| 687 | pipe_pktlen <= ld_pipe ? next_pktlen : pipe_pktlen; |
| 688 | pipe_pktbyt_cnt <= ld_pipe ? next_pktbyt_cnt : pipe_pktbyt_cnt; |
| 689 | pipe_addr_hi <= ld_pipe ? ((clastyp == CLASPIO) |
| 690 | ? {PRADDRMSB - 9{1'b0}} |
| 691 | : pktaddr[PRADDRMSB :10]) |
| 692 | : pipe_addr_hi; |
| 693 | pipe_addr_lo <= ld_pipe ? ((clastyp == CLASPIO) |
| 694 | ? ps2pm_i_rd_data |
| 695 | //BP n2 5-24-04 |
| 696 | // : pktaddr[9 :4]) |
| 697 | : {1'b0,pktaddr[9 :4]}) |
| 698 | : pipe_addr_lo; |
| 699 | pipe_dptr <= ld_pipe ? ((clastyp == CLASRD) |
| 700 | ? {3'b000,next_cltot} |
| 701 | : pktdptr) |
| 702 | : pipe_dptr; |
| 703 | pipe_clsts <= ld_pipe ? next_clsts : pipe_clsts; |
| 704 | pipe_stat <= ld_pipe ? next_stat : pipe_stat; |
| 705 | |
| 706 | case(clastyp) |
| 707 | CLASRD, |
| 708 | CLASRDL, |
| 709 | CLASUNSP : begin |
| 710 | case({ld_pipe,ps2pm_i_gnt}) |
| 711 | 2'b00 : pipe_sbdtag <= pipe_sbdtag; |
| 712 | 2'b10 : pipe_sbdtag <= ps2pm_i_n_trn; |
| 713 | 2'b01 : pipe_sbdtag <= pipe_sbdtag; |
| 714 | 2'b11 : pipe_sbdtag <= ps2pm_i_n_trn; |
| 715 | endcase // case({ld_pipe,ps2pm_i_gnt}) |
| 716 | end |
| 717 | CLASMDO : begin |
| 718 | pipe_sbdtag <= ld_pipe ? {3'b000,next_pktbyt_cnt[1:0]} : pipe_sbdtag; |
| 719 | end |
| 720 | default : begin |
| 721 | pipe_sbdtag <= ld_pipe ? pkttr_tag : pipe_sbdtag; |
| 722 | end |
| 723 | endcase // case(clastyp) |
| 724 | |
| 725 | pipe_multicycle <= ld_pipe ? multicycle : pipe_multicycle; |
| 726 | |
| 727 | end // always @ (posedge clk) |
| 728 | |
| 729 | // Registered Outputs |
| 730 | //Pipeline stages for next command address, dptr generator |
| 731 | |
| 732 | always @(posedge clk) |
| 733 | if (rst_l == 1'b0) begin |
| 734 | cmd_clastyp <= 4'b0; |
| 735 | end |
| 736 | else begin |
| 737 | case (bld_state) // synopsys parallel_case |
| 738 | BLDIDLE : cmd_clastyp <= ld_ptr ? pipe_clastyp : cmd_clastyp; |
| 739 | BLDXFR : cmd_clastyp <= cmd_clastyp; |
| 740 | default : cmd_clastyp <= cmd_clastyp; |
| 741 | endcase // case(bld_state) |
| 742 | end // always @ (posedge clk) |
| 743 | |
| 744 | always @(posedge clk) |
| 745 | if (rst_l == 1'b0) begin |
| 746 | cmd_typ <= {CRTYP_WDTH{1'b0}}; |
| 747 | cmd_clsts <= 1'b0; |
| 748 | cmd_stat <= {CRSTAT_WDTH{1'b0}}; |
| 749 | cmd_sbdtag <= {CRSBDTAG_WDTH{1'b0}}; |
| 750 | cmd_pktlen <= {PRLEN_WDTH{1'b0}}; |
| 751 | cmd_addr_hi <= {(CRADDR_WDTH -7){1'b0}}; |
| 752 | cmd_addr_lo <= 7'b0; |
| 753 | cmd_dptr <= {CRDPTR_WDTH{1'b0}}; |
| 754 | cmd_cltot <= {CLTOT_WDTH{1'b0}}; |
| 755 | cmd_multicycle <= 1'b0; |
| 756 | end |
| 757 | else begin |
| 758 | case (bld_state) // synopsys parallel_case |
| 759 | BLDIDLE : begin |
| 760 | cmd_typ <= ld_ptr ? pipe_typ : cmd_typ; |
| 761 | cmd_clsts <= ld_ptr ? pipe_clsts : cmd_clsts; |
| 762 | cmd_stat <= ld_ptr ? pipe_stat : cmd_stat; |
| 763 | cmd_sbdtag <= ld_ptr ? pipe_sbdtag : cmd_sbdtag; |
| 764 | cmd_pktlen <= ld_ptr ? pipe_pktlen : cmd_pktlen; |
| 765 | cmd_addr_hi <= ld_ptr ? pipe_addr_hi : cmd_addr_hi; |
| 766 | cmd_addr_lo <= ld_ptr ? pipe_addr_lo : cmd_addr_lo; |
| 767 | cmd_dptr <= ld_ptr ? pipe_dptr : cmd_dptr; |
| 768 | cmd_cltot <= ld_ptr ? pipe_cltot : cmd_cltot; |
| 769 | cmd_multicycle <= ld_ptr ? pipe_multicycle : cmd_multicycle; |
| 770 | end |
| 771 | BLDXFR : begin |
| 772 | case(cmd_multicycle) // synopsys full_case parallel_case |
| 773 | 1'b0 : begin |
| 774 | cmd_typ <= cmd_typ; |
| 775 | cmd_clsts <= cmd_clsts; |
| 776 | cmd_stat <= cmd_stat; |
| 777 | cmd_sbdtag <= cmd_sbdtag; |
| 778 | cmd_pktlen <= cmd_pktlen; |
| 779 | cmd_addr_hi <= cmd_addr_hi; |
| 780 | cmd_addr_lo <= cmd_addr_lo; |
| 781 | cmd_dptr <= cmd_dptr; |
| 782 | cmd_cltot <= cmd_cltot; |
| 783 | cmd_multicycle <= cmd_multicycle; |
| 784 | end |
| 785 | 1'b1 : begin |
| 786 | case (cmd_clastyp) // synopsys parallel_case |
| 787 | CLASPIO, |
| 788 | CLASMSI, |
| 789 | CLASMSG, |
| 790 | CLASMDO, |
| 791 | CLASNUL, |
| 792 | CLASWR : begin |
| 793 | cmd_typ <= ld_ptr ? pipe_typ : cmd_typ; |
| 794 | cmd_clsts <= ld_ptr ? pipe_clsts |
| 795 | : (next_gen_crcd ? last_clsts : cmd_clsts); |
| 796 | cmd_stat <= ld_ptr ? pipe_stat : cmd_stat; |
| 797 | cmd_sbdtag <= ld_ptr ? pipe_sbdtag : cmd_sbdtag; |
| 798 | cmd_pktlen <= ld_ptr ? pipe_pktlen |
| 799 | : (gen_crcd ? (cmd_pktlen - cacheline) |
| 800 | : cmd_pktlen); |
| 801 | cmd_addr_hi <= ld_ptr ? pipe_addr_hi : cmd_addr_hi; |
| 802 | cmd_addr_lo <= ld_ptr ? pipe_addr_lo |
| 803 | : (gen_crcd ? (cmd_addr_lo + 1'b1) |
| 804 | : cmd_addr_lo); |
| 805 | cmd_dptr <= cmd_dptr; |
| 806 | cmd_cltot <= ld_ptr ? pipe_cltot : cmd_cltot; |
| 807 | cmd_multicycle <= ld_ptr ? pipe_multicycle : cmd_multicycle; |
| 808 | end // case: CLASWR |
| 809 | |
| 810 | CLASRD, |
| 811 | CLASRDL, |
| 812 | CLASUNSP : begin |
| 813 | cmd_typ <= ld_ptr ? pipe_typ : cmd_typ; |
| 814 | cmd_clsts <= ld_ptr ? pipe_clsts : (gen_crcd ? 1'b0 : cmd_clsts); |
| 815 | cmd_stat <= ld_ptr ? pipe_stat : cmd_stat; |
| 816 | cmd_sbdtag <= ld_ptr ? pipe_sbdtag : cmd_sbdtag; |
| 817 | cmd_pktlen <= ld_ptr ? pipe_pktlen |
| 818 | : (gen_crcd ? (cmd_pktlen - cacheline) |
| 819 | : cmd_pktlen); |
| 820 | cmd_addr_hi <= ld_ptr ? pipe_addr_hi : cmd_addr_hi; |
| 821 | cmd_addr_lo <= ld_ptr ? pipe_addr_lo |
| 822 | : (gen_crcd ? (cmd_addr_lo + 1'b1) |
| 823 | : cmd_addr_lo); |
| 824 | cmd_dptr <= ld_ptr ? pipe_dptr |
| 825 | : (gen_crcd ? (cmd_dptr - 1'b1) |
| 826 | : cmd_dptr); |
| 827 | |
| 828 | cmd_cltot <= ld_ptr ? pipe_cltot : cmd_cltot; |
| 829 | cmd_multicycle <= ld_ptr ? pipe_multicycle : cmd_multicycle; |
| 830 | end // case: CLASWR |
| 831 | default : begin |
| 832 | cmd_typ <= cmd_typ; |
| 833 | cmd_clsts <= cmd_clsts; |
| 834 | cmd_stat <= cmd_stat; |
| 835 | cmd_sbdtag <= cmd_sbdtag; |
| 836 | cmd_pktlen <= cmd_pktlen; |
| 837 | cmd_addr_hi <= cmd_addr_hi; |
| 838 | cmd_addr_lo <= cmd_addr_lo; |
| 839 | cmd_dptr <= cmd_dptr; |
| 840 | cmd_cltot <= cmd_cltot; |
| 841 | cmd_multicycle <= cmd_multicycle; |
| 842 | end // case: default |
| 843 | endcase // case(cmd_clastyp) |
| 844 | end // case: 1'b1 |
| 845 | endcase // case(cmd_multicycle) |
| 846 | end // case: BLDXFR |
| 847 | |
| 848 | default : begin |
| 849 | cmd_typ <= cmd_typ; |
| 850 | cmd_clsts <= cmd_clsts; |
| 851 | cmd_stat <= cmd_stat; |
| 852 | cmd_sbdtag <= cmd_sbdtag; |
| 853 | cmd_pktlen <= cmd_pktlen; |
| 854 | cmd_addr_hi <= cmd_addr_hi; |
| 855 | cmd_addr_lo <= cmd_addr_lo; |
| 856 | cmd_dptr <= cmd_dptr; |
| 857 | cmd_cltot <= cmd_cltot; |
| 858 | cmd_multicycle <= cmd_multicycle; |
| 859 | end |
| 860 | endcase // case({bld_state,pipe_multicycle}) |
| 861 | end // always @ (posedge clk) |
| 862 | |
| 863 | always @(posedge clk) |
| 864 | begin |
| 865 | if (rst_l == 1'b0) begin |
| 866 | pmu_is_idle <= 1'b1; |
| 867 | end |
| 868 | else begin |
| 869 | pmu_is_idle <= ((pkmpty == 1'b1) && (deq_state == DEQIDLE) && |
| 870 | (pipe_full == 1'b0) && (bld_state == BLDIDLE)) |
| 871 | ? 1'b1 : 1'b0; |
| 872 | end |
| 873 | end |
| 874 | |
| 875 | // ***************State Machine Procedures ********************************/ |
| 876 | |
| 877 | // Record Dequeue |
| 878 | // State machine |
| 879 | |
| 880 | // DEQ next state |
| 881 | always @(deq_state or pkmpty or ps2pm_i_gnt or pipe_full |
| 882 | or clastyp or ps2pm_i_full or cl2pm_rcd_full) |
| 883 | begin |
| 884 | case (deq_state) // synopsys parallel_case |
| 885 | DEQIDLE : begin |
| 886 | case(pkmpty) // synopsys full_case parallel_case |
| 887 | 1'b1: deq_next = DEQIDLE; |
| 888 | 1'b0: begin |
| 889 | case (pipe_full) // synopsys full_case parallel_case |
| 890 | 1'b1 : deq_next = DEQIDLE; |
| 891 | 1'b0 : begin |
| 892 | case (clastyp) // synopsys parallel_case |
| 893 | CLASRD, |
| 894 | CLASRDL, |
| 895 | CLASUNSP : begin |
| 896 | case (ps2pm_i_full) // synopsys full_case parallel_case |
| 897 | 1'b1 : deq_next = DEQIDLE; |
| 898 | 1'b0 : deq_next = DEQGNT; |
| 899 | endcase // case(ps2pm_i_full) |
| 900 | end |
| 901 | CLASPIO : deq_next = DEQGNT; |
| 902 | CLASWR , |
| 903 | CLASMSI, |
| 904 | CLASMSG, |
| 905 | CLASMDO, |
| 906 | CLASNUL : deq_next = DEQ; |
| 907 | default : deq_next = DEQIDLE; |
| 908 | endcase // case(clastyp) |
| 909 | end // case: 1'b0 |
| 910 | endcase // case(pipe_full) |
| 911 | end // case: 1'b0 |
| 912 | endcase // case(pkmpty) |
| 913 | end // case: DEQIDLE |
| 914 | |
| 915 | DEQGNT : begin |
| 916 | case(ps2pm_i_gnt) // synopsys full_case parallel_case |
| 917 | 1'b1: deq_next = DEQ; |
| 918 | 1'b0: deq_next = DEQGNT; |
| 919 | endcase // case(ps2pm_i_gnt) |
| 920 | end |
| 921 | |
| 922 | DEQ : begin |
| 923 | case(cl2pm_rcd_full) // synopsys full_case parallel_case |
| 924 | 1'b1 : deq_next = DEQ; |
| 925 | 1'b0 : deq_next = DEQIDLE; |
| 926 | endcase // case(cl2pm_rcd_full) |
| 927 | end // case: DEQ |
| 928 | |
| 929 | default: deq_next = DEQIDLE; |
| 930 | |
| 931 | endcase // case(deq_state) |
| 932 | end // always @ (deq_state or pkmpty or ps2pm_i_gnt or pipe_full... |
| 933 | |
| 934 | // DEQ state machine outputs |
| 935 | always @(deq_state or pkmpty or pipe_full or ps2pm_i_gnt or |
| 936 | clastyp or ps2pm_i_full or cl2pm_rcd_full) |
| 937 | begin |
| 938 | case (deq_state) // synopsys parallel_case |
| 939 | DEQIDLE : begin |
| 940 | case(pkmpty) // synopsys full_case parallel_case |
| 941 | 1'b1: begin |
| 942 | ld_pipe = 1'b0; |
| 943 | next_gen_trn = 1'b0; |
| 944 | next_deq_rcd = 1'b0; |
| 945 | end |
| 946 | 1'b0: begin |
| 947 | case (pipe_full) // synopsys full_case parallel_case |
| 948 | 1'b1 : begin |
| 949 | ld_pipe = 1'b0; |
| 950 | next_gen_trn = 1'b0; |
| 951 | next_deq_rcd = 1'b0; |
| 952 | end |
| 953 | 1'b0 : begin |
| 954 | case (clastyp) // synopsys parallel_case |
| 955 | CLASRD, |
| 956 | CLASRDL, |
| 957 | CLASUNSP : begin |
| 958 | next_deq_rcd = 1'b0; |
| 959 | ld_pipe = 1'b0; |
| 960 | case (ps2pm_i_full) // synopsys full_case parallel_case |
| 961 | 1'b1 : next_gen_trn = 1'b0; |
| 962 | 1'b0 : next_gen_trn = 1'b1; |
| 963 | endcase // case(ps2pm_i_full) |
| 964 | end |
| 965 | |
| 966 | CLASPIO : begin |
| 967 | next_deq_rcd = 1'b0; |
| 968 | ld_pipe = 1'b0; |
| 969 | next_gen_trn = 1'b1; |
| 970 | end |
| 971 | |
| 972 | CLASWR, |
| 973 | CLASMSI, |
| 974 | CLASMSG, |
| 975 | CLASMDO, |
| 976 | CLASNUL : begin |
| 977 | ld_pipe = 1'b1; |
| 978 | next_gen_trn = 1'b0; |
| 979 | next_deq_rcd = 1'b0; |
| 980 | end |
| 981 | default : begin |
| 982 | ld_pipe = 1'b0; |
| 983 | next_gen_trn = 1'b0; |
| 984 | next_deq_rcd = 1'b0; |
| 985 | end |
| 986 | endcase // case(clastyp) |
| 987 | end // case: 1'b0 |
| 988 | endcase // case(pipe_full | cl2pm_rcd_full) |
| 989 | end // case: 1'b0 |
| 990 | endcase // case(pkmpty) |
| 991 | end // case: DEQIDLE |
| 992 | |
| 993 | DEQGNT : begin |
| 994 | next_gen_trn = 1'b0; |
| 995 | next_deq_rcd = 1'b0; |
| 996 | case(ps2pm_i_gnt) |
| 997 | 1'b1: ld_pipe = 1'b1; |
| 998 | 1'b0: ld_pipe = 1'b0; |
| 999 | endcase // case(ps2pm_i_gnt) |
| 1000 | end |
| 1001 | |
| 1002 | DEQ : begin |
| 1003 | case(cl2pm_rcd_full) // synopsys full_case parallel_case |
| 1004 | 1'b1 : begin |
| 1005 | ld_pipe = 1'b0; |
| 1006 | next_gen_trn = 1'b0; |
| 1007 | next_deq_rcd = 1'b0; |
| 1008 | end |
| 1009 | 1'b0 : begin |
| 1010 | ld_pipe = 1'b0; |
| 1011 | next_gen_trn = 1'b0; |
| 1012 | case (pkmpty) // synopsys full_case parallel_case |
| 1013 | 1'b1 : next_deq_rcd = 1'b0; |
| 1014 | 1'b0 : next_deq_rcd = 1'b1; |
| 1015 | endcase // case(pkmpty) |
| 1016 | end |
| 1017 | endcase // case(cl2pm_rcd_full) |
| 1018 | end // case: DEQ |
| 1019 | |
| 1020 | default: begin |
| 1021 | ld_pipe = 1'b0; |
| 1022 | next_gen_trn = 1'b0; |
| 1023 | next_deq_rcd = 1'b0; |
| 1024 | end |
| 1025 | endcase // case(deq_state) |
| 1026 | end // always @ (deq_state or pkmpty or pipe_full or clastyp or... |
| 1027 | |
| 1028 | // DEQ state transitions |
| 1029 | always @(posedge clk) |
| 1030 | begin |
| 1031 | if (rst_l == 1'b0) |
| 1032 | deq_state <= DEQIDLE; // Synchronous Reset |
| 1033 | else begin |
| 1034 | deq_state <= deq_next; |
| 1035 | end |
| 1036 | end |
| 1037 | |
| 1038 | |
| 1039 | |
| 1040 | // Command Build Process |
| 1041 | // State machine (build_crcd) |
| 1042 | |
| 1043 | // BLD next state |
| 1044 | always @(bld_state or pipe_full or cl2pm_rcd_full or cmd_multicycle |
| 1045 | or num_cmd or cmd_cltot) |
| 1046 | begin |
| 1047 | case (bld_state) // synopsys parallel_case |
| 1048 | BLDIDLE : begin |
| 1049 | case(pipe_full) // synopsys full_case parallel_case |
| 1050 | 1'b0: bld_next = BLDIDLE; |
| 1051 | 1'b1: bld_next = BLDXFR; |
| 1052 | endcase // case(pipe_full) |
| 1053 | end |
| 1054 | |
| 1055 | BLDXFR : begin |
| 1056 | case(cl2pm_rcd_full) // synopsys full_case parallel_case |
| 1057 | 1'b1 : bld_next = BLDXFR; |
| 1058 | 1'b0 : begin |
| 1059 | case(cmd_multicycle) // synopsys full_case parallel_case |
| 1060 | 1'b0 : bld_next = BLDIDLE; |
| 1061 | 1'b1 : begin |
| 1062 | if(num_cmd == cmd_cltot) bld_next = BLDIDLE; |
| 1063 | else bld_next = BLDXFR; |
| 1064 | end |
| 1065 | endcase // case(cmd_multicycle) |
| 1066 | end // case: 1'b0 |
| 1067 | endcase // case(cl2pm_rcd_full) |
| 1068 | end // case: BLDXFR |
| 1069 | |
| 1070 | default: bld_next = BLDIDLE; |
| 1071 | |
| 1072 | endcase // case(bld_state) |
| 1073 | end // always @ (bld_state or pipe_full or cl2pm_rcd_full or pipe_multicycle... |
| 1074 | |
| 1075 | |
| 1076 | // BLD state machine outputs |
| 1077 | always @(bld_state or pipe_full or cl2pm_rcd_full or num_cmd |
| 1078 | or cmd_multicycle or cmd_cltot) |
| 1079 | begin |
| 1080 | case (bld_state) // synopsys parallel_case |
| 1081 | BLDIDLE : begin |
| 1082 | next_gen_crcd = 1'b0; |
| 1083 | |
| 1084 | case (pipe_full) // synopsys full_case parallel_case |
| 1085 | 1'b0 : ld_ptr = 1'b0; |
| 1086 | 1'b1 : ld_ptr = 1'b1; |
| 1087 | endcase // case(pipe_full) |
| 1088 | end // case: BLDIDLE |
| 1089 | |
| 1090 | BLDXFR : begin |
| 1091 | ld_ptr = 1'b0; |
| 1092 | |
| 1093 | case(cl2pm_rcd_full) // synopsys full_case parallel_case |
| 1094 | 1'b1 : next_gen_crcd = 1'b0; |
| 1095 | 1'b0 : begin |
| 1096 | case (cmd_multicycle) // synopsys full_case parallel_case |
| 1097 | 1'b0 : next_gen_crcd = 1'b1; |
| 1098 | 1'b1 : begin |
| 1099 | if(num_cmd == cmd_cltot) next_gen_crcd = 1'b0; |
| 1100 | else next_gen_crcd = 1'b1; |
| 1101 | end |
| 1102 | endcase // case(cmd_multicycle) |
| 1103 | end // case: 1'b0 |
| 1104 | endcase // case(cl2pm_rcd_full) |
| 1105 | end // case: BLDXFR |
| 1106 | |
| 1107 | default: begin |
| 1108 | ld_ptr = 1'b0; |
| 1109 | next_gen_crcd = 1'b0; |
| 1110 | end |
| 1111 | endcase // case(bld_state) |
| 1112 | end // always @ (bld_state or pipe_full or cl2pm_rcd_full or num_cmd... |
| 1113 | |
| 1114 | // BLD state transitions |
| 1115 | always @(posedge clk) |
| 1116 | begin |
| 1117 | if (rst_l == 1'b0) |
| 1118 | bld_state <= BLDIDLE; // Synchronous Reset |
| 1119 | else begin |
| 1120 | bld_state <= bld_next; |
| 1121 | end |
| 1122 | end |
| 1123 | |
| 1124 | |
| 1125 | //************************************************ |
| 1126 | // MODULES |
| 1127 | //************************************************ |
| 1128 | |
| 1129 | dmu_pmu_prcd_q prm_queue ( |
| 1130 | .clk (clk), |
| 1131 | .rst_l (rst_l), |
| 1132 | .enq (cm2pm_rcd_enq), |
| 1133 | .rcd_in (cm2pm_rcd), |
| 1134 | .deq (next_deq_rcd), |
| 1135 | .typ (pkttyp), |
| 1136 | .len(pktlen), |
| 1137 | .byt_cnt(pktbyt_cnt), |
| 1138 | .cntxt_num(pktcntxt_num), |
| 1139 | .pkseq_num(pktseq_num), |
| 1140 | .addr(pktaddr), |
| 1141 | .addr_err(pktaddr_err), |
| 1142 | .dptr(pktdptr), |
| 1143 | .sbd_tag(pkttr_tag), |
| 1144 | .full (pm2cm_rcd_full), |
| 1145 | .overflow(), |
| 1146 | .underflow(), |
| 1147 | .empty (pkmpty) |
| 1148 | ); |
| 1149 | |
| 1150 | // ********************** signal registers *************************/ |
| 1151 | |
| 1152 | always @(posedge clk) |
| 1153 | begin |
| 1154 | if (rst_l == 1'b0) begin |
| 1155 | pm2cl_rcd_enq <= 1'b0; |
| 1156 | gen_crcd <= 1'b0; |
| 1157 | pipe_full <= 0; |
| 1158 | line_clsts <= 0; |
| 1159 | persist_last_dwbe <= 0; |
| 1160 | end |
| 1161 | else begin |
| 1162 | pm2cl_rcd_enq <= next_gen_crcd; |
| 1163 | gen_crcd <= next_gen_crcd; |
| 1164 | pipe_full <= ld_pipe ? 1'b1 : (~ld_ptr & pipe_full); |
| 1165 | persist_last_dwbe <= ld_ptr ? pipe_pktbyt_cnt[7:4] : persist_last_dwbe; |
| 1166 | line_clsts <= ld_ptr ? 1'b0 |
| 1167 | : (((cmd_pktlen[3:0] != 4'h0) || (persist_last_dwbe != 4'hf)) ? 1'b1 : line_clsts); |
| 1168 | end // else: !if(rst_l == 1'b0) |
| 1169 | end // always @ (posedge clk) |
| 1170 | |
| 1171 | |
| 1172 | // ---------------------------------------------------------------------------- |
| 1173 | // Debug |
| 1174 | // ---------------------------------------------------------------------------- |
| 1175 | |
| 1176 | always @ (dbg2prm_dbg_sel_a or dbg2prm_dbg_sel_b) |
| 1177 | begin |
| 1178 | prm_dbg_sel[0] = dbg2prm_dbg_sel_a; |
| 1179 | prm_dbg_sel[1] = dbg2prm_dbg_sel_b; |
| 1180 | end |
| 1181 | |
| 1182 | always @ (prm_dbg_sel[0] or prm_dbg_sel[1] or next_cltot or clastyp or |
| 1183 | pipe_cltot or pipe_clastyp or pipe_multicycle or bld_state or |
| 1184 | cm2pm_rcd_enq or pkmpty or next_deq_rcd or ld_pipe or |
| 1185 | pipe_full or deq_state or ld_ptr or next_gen_trn or |
| 1186 | next_gen_crcd or cl2pm_rcd_full or cmd_multicycle or pm2ps_i_req or |
| 1187 | ps2pm_i_gnt or ps2pm_i_full or pm2ps_i_cmd_type or pm2cl_rcd_enq or |
| 1188 | cmd_clsts or cmd_cltot or pmu_is_idle |
| 1189 | ) |
| 1190 | begin |
| 1191 | for (i = 0; i < 2; i = i + 1) begin |
| 1192 | case (prm_dbg_sel[i]) // synopsys infer_mux |
| 1193 | 3'b000: nxt_prm_dbg1_bus[i] = {pmu_is_idle,next_cltot,clastyp[2:0]}; |
| 1194 | 3'b001: nxt_prm_dbg1_bus[i] = {pipe_cltot,pipe_clastyp}; |
| 1195 | 3'b010: nxt_prm_dbg1_bus[i] = {1'b0,pipe_multicycle,clastyp,bld_state}; |
| 1196 | 3'b011: nxt_prm_dbg1_bus[i] = {1'b0,cm2pm_rcd_enq,pkmpty,next_deq_rcd,ld_pipe,pipe_full,deq_state}; |
| 1197 | 3'b100: nxt_prm_dbg1_bus[i] = {ld_ptr,pipe_full,next_gen_trn,next_gen_crcd,pipe_clastyp}; |
| 1198 | 3'b101: nxt_prm_dbg1_bus[i] = {cl2pm_rcd_full,cmd_multicycle,clastyp,bld_state}; |
| 1199 | 3'b110: nxt_prm_dbg1_bus[i] = {1'b0,pm2ps_i_req,ps2pm_i_gnt,ps2pm_i_full,pm2ps_i_cmd_type}; |
| 1200 | 3'b111: nxt_prm_dbg1_bus[i] = {2'b00,pm2cl_rcd_enq,cmd_clsts,cmd_cltot}; |
| 1201 | endcase // case(prm_dbg_sel[i]) |
| 1202 | end // for (i = 0; i < 2; i = i + 1) |
| 1203 | end // always @ (prm_dbg_sel[0] or prm_dbg_sel[1] or... |
| 1204 | |
| 1205 | always @ (prm_dbg_sel[0] or prm_dbg_sel[1] or num_cmd or |
| 1206 | cmd_clastyp or cmd_typ or cmd_pktlen or cmd_addr_hi or |
| 1207 | cmd_addr_lo or cmd_dptr or rem_len or cmd_sbdtag or |
| 1208 | last_clsts or cmd_cltot or cmd_stat |
| 1209 | ) |
| 1210 | begin |
| 1211 | for (j = 0; j < 2; j = j + 1) begin |
| 1212 | case (prm_dbg_sel[j]) // synopsys infer_mux |
| 1213 | 3'b000: nxt_prm_dbg2_bus[j] = {num_cmd,cmd_clastyp}; |
| 1214 | 3'b001: nxt_prm_dbg2_bus[j] = {1'b0,cmd_typ}; |
| 1215 | 3'b010: nxt_prm_dbg2_bus[j] = {cmd_pktlen[7:0]}; |
| 1216 | //BP n2 5-24-04 |
| 1217 | // 3'b011: nxt_prm_dbg2_bus[j] = {cmd_addr_hi[7:6],cmd_addr_lo}; |
| 1218 | 3'b011: nxt_prm_dbg2_bus[j] = {cmd_addr_hi[8:7],cmd_addr_lo[5:0]}; |
| 1219 | 3'b100: nxt_prm_dbg2_bus[j] = {1'b0,cmd_dptr}; |
| 1220 | 3'b101: nxt_prm_dbg2_bus[j] = {1'b0,rem_len[9:8],cmd_sbdtag}; |
| 1221 | 3'b110: nxt_prm_dbg2_bus[j] = {last_clsts,cmd_cltot, cmd_stat}; |
| 1222 | 3'b111: nxt_prm_dbg2_bus[j] = {8'h00}; |
| 1223 | endcase // case(prm_dbg_sel[i]) |
| 1224 | end // for (j = 0; j < 2; j = j + 1) |
| 1225 | end // always @ (prm_dbg_sel[0] or prm_dbg_sel[1] or... |
| 1226 | |
| 1227 | always @ (cr2pm_dbg_sel_a or prm2dbg_dbg1_a or prm2dbg_dbg2_a) |
| 1228 | begin |
| 1229 | case (cr2pm_dbg_sel_a[5:3]) // synopsys infer_mux |
| 1230 | 3'b000: nxt_dbg_bus[0] = prm2dbg_dbg1_a; |
| 1231 | 3'b001: nxt_dbg_bus[0] = prm2dbg_dbg2_a; |
| 1232 | 3'b010: nxt_dbg_bus[0] = 8'h00; |
| 1233 | 3'b011: nxt_dbg_bus[0] = 8'h00; |
| 1234 | 3'b100: nxt_dbg_bus[0] = 8'h00; |
| 1235 | 3'b101: nxt_dbg_bus[0] = 8'h00; |
| 1236 | 3'b110: nxt_dbg_bus[0] = 8'h00; |
| 1237 | 3'b111: nxt_dbg_bus[0] = 8'h00; |
| 1238 | endcase // case(cr2pm_dbg_sel_a[5:3]) |
| 1239 | end // always @ (cr2pm_dbg_sel_b or prm2dbg_dbg1_a ... |
| 1240 | |
| 1241 | always @ (cr2pm_dbg_sel_b or prm2dbg_dbg1_b or prm2dbg_dbg2_b) |
| 1242 | begin |
| 1243 | case (cr2pm_dbg_sel_b[5:3]) // synopsys infer_mux |
| 1244 | 3'b000: nxt_dbg_bus[1] = prm2dbg_dbg1_b; |
| 1245 | 3'b001: nxt_dbg_bus[1] = prm2dbg_dbg2_b; |
| 1246 | 3'b010: nxt_dbg_bus[1] = 8'h00; |
| 1247 | 3'b011: nxt_dbg_bus[1] = 8'h00; |
| 1248 | 3'b100: nxt_dbg_bus[1] = 8'h00; |
| 1249 | 3'b101: nxt_dbg_bus[1] = 8'h00; |
| 1250 | 3'b110: nxt_dbg_bus[1] = 8'h00; |
| 1251 | 3'b111: nxt_dbg_bus[1] = 8'h00; |
| 1252 | endcase // case(cr2pm_dbg_sel_b[5:3]) |
| 1253 | end // always @ (cr2pm_dbg_sel_b or prm2dbg_db1g_b ... |
| 1254 | |
| 1255 | // ********************** Output Procedures ************************/ |
| 1256 | |
| 1257 | // Debug |
| 1258 | always @ (posedge clk) begin |
| 1259 | if(rst_l == 1'b0) begin |
| 1260 | for (k = 0; k < 2; k = k + 1) begin |
| 1261 | prm_dbg1_bus[k] <= 8'h00; |
| 1262 | prm_dbg2_bus[k] <= 8'h00; |
| 1263 | end |
| 1264 | end |
| 1265 | else begin |
| 1266 | for (k = 0; k < 2; k = k + 1) begin |
| 1267 | prm_dbg1_bus[k] <= nxt_prm_dbg1_bus[k]; |
| 1268 | prm_dbg2_bus[k] <= nxt_prm_dbg2_bus[k]; |
| 1269 | end |
| 1270 | end |
| 1271 | end // always @ (posedge clk) |
| 1272 | |
| 1273 | // Debug |
| 1274 | always @ (posedge clk) begin |
| 1275 | if(rst_l == 1'b0) begin |
| 1276 | for (l = 0; l < 2; l = l + 1) begin |
| 1277 | dbg_bus[l] <= 8'h00; |
| 1278 | end |
| 1279 | end |
| 1280 | else begin |
| 1281 | for (l = 0; l < 2; l = l + 1) begin |
| 1282 | dbg_bus[l] <= nxt_dbg_bus[l]; |
| 1283 | end |
| 1284 | end |
| 1285 | end // always @ (posedge clk) |
| 1286 | |
| 1287 | // PSB outputs |
| 1288 | always @(posedge clk) |
| 1289 | begin |
| 1290 | if (rst_l == 1'b0) begin |
| 1291 | pm2ps_i_req <= 1'b0; |
| 1292 | pm2ps_i_cmd_type[PSCMDTYPMSB : 0] <= 0; |
| 1293 | pm2ps_i_wr_data[PSRCDMSB :0] <= 0; |
| 1294 | pm2ps_i_trn <= 0; |
| 1295 | |
| 1296 | end |
| 1297 | else begin |
| 1298 | pm2ps_i_req <= next_gen_trn ? 1'b1 : (~ps2pm_i_gnt & pm2ps_i_req); |
| 1299 | pm2ps_i_cmd_type[PSCMDTYPMSB:0] <= next_gen_trn |
| 1300 | ? next_scbd_fun[PSCMDTYPMSB:0] |
| 1301 | : pm2ps_i_cmd_type[PSCMDTYPMSB:0]; |
| 1302 | |
| 1303 | pm2ps_i_wr_data[PSRCDMSB :0] <= next_gen_trn |
| 1304 | ? next_pm2ps_i_wr_data[PSRCDMSB:0] |
| 1305 | : pm2ps_i_wr_data[PSRCDMSB:0]; |
| 1306 | |
| 1307 | pm2ps_i_trn <= next_gen_trn ? pkttr_tag[PRSBDTAGMSB :0] : pm2ps_i_trn; |
| 1308 | |
| 1309 | end // else: !if(rst_l == 1'b0) |
| 1310 | end // always @ (posedge clk) |
| 1311 | |
| 1312 | |
| 1313 | // ***********************Assignments *****************************/ |
| 1314 | |
| 1315 | assign cacheline[PRLENMSB :0] = 10'h010; |
| 1316 | |
| 1317 | assign real_size = ({1'b0,pktaddr[8:0]} + pktlen); |
| 1318 | assign align_size = ({1'b0,pktaddr[8:4], 4'b0000} + cacheline); |
| 1319 | assign align_adj = (real_size > align_size) ? 1'b1 : 1'b0; |
| 1320 | |
| 1321 | assign block_size = ({1'b0,pktaddr[8:4], 4'b0000} + {2'b00,new_pktlen,4'b0000}); |
| 1322 | assign block_adj = (real_size > block_size) ? 1'b1 : 1'b0; |
| 1323 | |
| 1324 | assign new_pktlen[CLTOTMSB :0] = pktlen[7 :4]; |
| 1325 | assign offset_len[PRLENMSB :0] = cacheline - {6'h00,pktaddr[3 :0]}; |
| 1326 | assign rem_len = pktlen - offset_len; |
| 1327 | assign trail = (rem_len[3:0] != 4'b0) ? 4'h1 : 4'h0; |
| 1328 | |
| 1329 | |
| 1330 | assign last_clsts = ((num_cmd + 4'h1) == cmd_cltot) ? line_clsts : 1'b0; |
| 1331 | |
| 1332 | assign pm2cl_rcd [ICRMSB :0] = { // CLU Record |
| 1333 | cmd_typ[CRTYPMSB :0], |
| 1334 | cmd_clsts, |
| 1335 | {cmd_addr_hi,cmd_addr_lo}, |
| 1336 | cmd_stat[CRSTATMSB :0], |
| 1337 | cmd_dptr[CRDPTRMSB :0], |
| 1338 | cmd_sbdtag[CRSBDTAGMSB :0] |
| 1339 | }; |
| 1340 | |
| 1341 | assign next_pm2ps_i_wr_data[PSRCDMSB :0] = { // next PSB Record |
| 1342 | pkttr_tag[PRSBDTAGMSB :0], |
| 1343 | pktcntxt_num[PRCNTXTNUMMSB :0], |
| 1344 | pktseq_num[PRPKSEQNUMMSB :0], |
| 1345 | next_cltot[CLTOTMSB :0], |
| 1346 | next_pktlen[PRLENMSB :0], |
| 1347 | next_pktbyt_cnt[PRBYTCNTMSB :0] |
| 1348 | }; |
| 1349 | // debug select and data port distribution |
| 1350 | assign dbg2prm_dbg_sel_a = cr2pm_dbg_sel_a [`FIRE_DLC_PMU_PRM_DS_BITS]; |
| 1351 | assign dbg2prm_dbg_sel_b = cr2pm_dbg_sel_b [`FIRE_DLC_PMU_PRM_DS_BITS]; |
| 1352 | |
| 1353 | // Debug |
| 1354 | assign prm2dbg_dbg1_a = prm_dbg1_bus[0]; |
| 1355 | assign prm2dbg_dbg1_b = prm_dbg1_bus[1]; |
| 1356 | assign prm2dbg_dbg2_a = prm_dbg2_bus[0]; |
| 1357 | assign prm2dbg_dbg2_b = prm_dbg2_bus[1]; |
| 1358 | assign pm2cr_dbg_a = dbg_bus[0]; |
| 1359 | assign pm2cr_dbg_b = dbg_bus[1]; |
| 1360 | |
| 1361 | endmodule |
| 1362 | |
| 1363 | |