| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_rmu_dbg.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_rmu_dbg ( |
| 36 | |
| 37 | // Clock |
| 38 | |
| 39 | clk, |
| 40 | rst_l, |
| 41 | |
| 42 | // Block Level Selects and Output Ports |
| 43 | |
| 44 | cr2rm_dbg_sel_a, |
| 45 | cr2rm_dbg_sel_b, |
| 46 | |
| 47 | rm2cr_dbg_a, |
| 48 | rm2cr_dbg_b, |
| 49 | |
| 50 | // Sub Block Selects and Output Ports |
| 51 | |
| 52 | // RRM sub block |
| 53 | dbg2rrm_dbg_sel_a, |
| 54 | dbg2rrm_dbg_sel_b, |
| 55 | |
| 56 | rrm2dbg_dbg_a, |
| 57 | rrm2dbg_dbg_b, |
| 58 | |
| 59 | // LRM sub block |
| 60 | dbg2lrm_dbg_sel_a, |
| 61 | dbg2lrm_dbg_sel_b, |
| 62 | |
| 63 | lrm2dbg_dbg_a, |
| 64 | lrm2dbg_dbg_b |
| 65 | |
| 66 | ); |
| 67 | |
| 68 | |
| 69 | //############################################################################ |
| 70 | // PORT DECLARATIONS |
| 71 | //############################################################################ |
| 72 | |
| 73 | |
| 74 | //------------------------------------------------------------------------ |
| 75 | // Clock and Reset Signals |
| 76 | //------------------------------------------------------------------------ |
| 77 | input clk; |
| 78 | input rst_l; |
| 79 | |
| 80 | //------------------------------------------------------------------------ |
| 81 | // Block Level Selects and Output Ports |
| 82 | //------------------------------------------------------------------------ |
| 83 | |
| 84 | input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2rm_dbg_sel_a; // 6 bit select |
| 85 | input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2rm_dbg_sel_b; // 6 bit select |
| 86 | |
| 87 | output [`FIRE_DEBUG_WDTH-1:0] rm2cr_dbg_a; // 8 bit debug port |
| 88 | output [`FIRE_DEBUG_WDTH-1:0] rm2cr_dbg_b; // 8 bit debug port |
| 89 | |
| 90 | |
| 91 | //------------------------------------------------------------------------ |
| 92 | // Sub Block Level Selects and Output Ports |
| 93 | //------------------------------------------------------------------------ |
| 94 | |
| 95 | output [2:0] dbg2rrm_dbg_sel_a; // 3 bit selects |
| 96 | output [2:0] dbg2rrm_dbg_sel_b; // 3 bit selects |
| 97 | |
| 98 | input [`FIRE_DEBUG_WDTH-1:0] rrm2dbg_dbg_a; // 8 bit debug port |
| 99 | input [`FIRE_DEBUG_WDTH-1:0] rrm2dbg_dbg_b; // 8 bit debug port |
| 100 | |
| 101 | output [2:0] dbg2lrm_dbg_sel_a; // 3 bit selects |
| 102 | output [2:0] dbg2lrm_dbg_sel_b; // 3 bit selects |
| 103 | |
| 104 | input [`FIRE_DEBUG_WDTH-1:0] lrm2dbg_dbg_a; // 8 bit debug port |
| 105 | input [`FIRE_DEBUG_WDTH-1:0] lrm2dbg_dbg_b; // 8 bit debug port |
| 106 | |
| 107 | |
| 108 | //############################################################################ |
| 109 | // SIGNAL DECLARATIONS |
| 110 | //############################################################################ |
| 111 | |
| 112 | //************************************************** |
| 113 | // Wires |
| 114 | //************************************************** |
| 115 | |
| 116 | |
| 117 | //************************************************** |
| 118 | // Registers that Are Not Flops |
| 119 | //************************************************** |
| 120 | reg [`FIRE_DEBUG_WDTH-1:0] next_rm2cr_dbg_a; |
| 121 | reg [`FIRE_DEBUG_WDTH-1:0] next_rm2cr_dbg_b; |
| 122 | |
| 123 | |
| 124 | //************************************************** |
| 125 | // Registers that Are Flops |
| 126 | //************************************************** |
| 127 | reg [`FIRE_DEBUG_WDTH-1:0] rm2cr_dbg_a; |
| 128 | reg [`FIRE_DEBUG_WDTH-1:0] rm2cr_dbg_b; |
| 129 | |
| 130 | |
| 131 | //############################################################################ |
| 132 | // ZERO IN CHECKERS |
| 133 | //############################################################################ |
| 134 | |
| 135 | |
| 136 | |
| 137 | //############################################################################ |
| 138 | // COMBINATIONAL LOGIC |
| 139 | //############################################################################ |
| 140 | |
| 141 | // RRM sub-block selects (3 bit selects) |
| 142 | assign dbg2rrm_dbg_sel_a = cr2rm_dbg_sel_a[2:0]; |
| 143 | assign dbg2rrm_dbg_sel_b = cr2rm_dbg_sel_b[2:0]; |
| 144 | |
| 145 | // LRM sub-block select (3 bit selects) |
| 146 | assign dbg2lrm_dbg_sel_a = cr2rm_dbg_sel_a[2:0]; |
| 147 | assign dbg2lrm_dbg_sel_b = cr2rm_dbg_sel_b[2:0]; |
| 148 | |
| 149 | // Debug Port A |
| 150 | |
| 151 | always @ (cr2rm_dbg_sel_a or rrm2dbg_dbg_a or lrm2dbg_dbg_a ) |
| 152 | begin |
| 153 | case (cr2rm_dbg_sel_a[5:3]) // synopsys infer_mux |
| 154 | 3'b000: next_rm2cr_dbg_a = rrm2dbg_dbg_a; |
| 155 | 3'b001: next_rm2cr_dbg_a = lrm2dbg_dbg_a; |
| 156 | 3'b010: next_rm2cr_dbg_a = 8'h0; |
| 157 | 3'b011: next_rm2cr_dbg_a = 8'h0; |
| 158 | 3'b100: next_rm2cr_dbg_a = 8'h0; |
| 159 | 3'b101: next_rm2cr_dbg_a = 8'h0; |
| 160 | 3'b110: next_rm2cr_dbg_a = 8'h0; |
| 161 | 3'b111: next_rm2cr_dbg_a = 8'h0; |
| 162 | endcase |
| 163 | end |
| 164 | |
| 165 | |
| 166 | // Debug Port B |
| 167 | |
| 168 | always @ (cr2rm_dbg_sel_b or rrm2dbg_dbg_b or lrm2dbg_dbg_b) |
| 169 | begin |
| 170 | case (cr2rm_dbg_sel_b[5:3]) // synopsys infer_mux |
| 171 | 3'b000: next_rm2cr_dbg_b = rrm2dbg_dbg_b; |
| 172 | 3'b001: next_rm2cr_dbg_b = lrm2dbg_dbg_b; |
| 173 | 3'b010: next_rm2cr_dbg_b = 8'h0; |
| 174 | 3'b011: next_rm2cr_dbg_b = 8'h0; |
| 175 | 3'b100: next_rm2cr_dbg_b = 8'h0; |
| 176 | 3'b101: next_rm2cr_dbg_b = 8'h0; |
| 177 | 3'b110: next_rm2cr_dbg_b = 8'h0; |
| 178 | 3'b111: next_rm2cr_dbg_b = 8'h0; |
| 179 | endcase |
| 180 | end |
| 181 | |
| 182 | |
| 183 | //############################################################################ |
| 184 | // SEQUENTIAL LOGIC |
| 185 | //############################################################################ |
| 186 | |
| 187 | // Registered Output Debug Ports (A and B) |
| 188 | |
| 189 | always @ (posedge clk) |
| 190 | if(~rst_l) begin |
| 191 | rm2cr_dbg_a <= {`FIRE_DEBUG_WDTH{1'b0}}; |
| 192 | rm2cr_dbg_b <= {`FIRE_DEBUG_WDTH{1'b0}}; |
| 193 | end |
| 194 | else begin |
| 195 | rm2cr_dbg_a <= next_rm2cr_dbg_a; |
| 196 | rm2cr_dbg_b <= next_rm2cr_dbg_b; |
| 197 | end |
| 198 | |
| 199 | |
| 200 | //############################################################################ |
| 201 | // MODULE INSTANTIATIONS |
| 202 | //############################################################################ |
| 203 | |
| 204 | |
| 205 | endmodule |