| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_tmu_dim_rcdbldr.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_tmu_dim_rcdbldr ( |
| 36 | clk, |
| 37 | rst_l, |
| 38 | |
| 39 | // ilu <-> dmu-tmu |
| 40 | y2k_rcd, |
| 41 | y2k_rcd_enq, |
| 42 | |
| 43 | // RMU interface |
| 44 | tm2rm_rcd, |
| 45 | |
| 46 | // IMU interface |
| 47 | im2tm_msi32_addr_reg, |
| 48 | im2tm_msi64_addr_reg, |
| 49 | |
| 50 | // internal interface |
| 51 | rcd_deq, |
| 52 | rcd_empty, |
| 53 | |
| 54 | rcd_is_msg, |
| 55 | rcd_is_msi, |
| 56 | rcd_is_cpld, |
| 57 | rcd_is_dmawr, |
| 58 | |
| 59 | align_addr, |
| 60 | payld_len, |
| 61 | d_ptr_out, |
| 62 | |
| 63 | first_dwbe, |
| 64 | last_dwbe, |
| 65 | csr_sun4v_en, |
| 66 | im2tm_eqs_adr_63 |
| 67 | ); |
| 68 | |
| 69 | //synopsys sync_set_reset "rst_l" |
| 70 | |
| 71 | // >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 72 | |
| 73 | // rcd type |
| 74 | parameter |
| 75 | DMA_MRD32 = 7'b0000000, |
| 76 | DMA_MRD64 = 7'b0100000, |
| 77 | DMA_MRDLK32 = 7'b0000001, |
| 78 | DMA_MRDLK64 = 7'b0100001, |
| 79 | DMA_MWR32 = 7'b1000000, |
| 80 | DMA_MWR64 = 7'b1100000, |
| 81 | DMA_UR = 7'b0001001, |
| 82 | DMA_MSG = 7'b0110zzz, |
| 83 | PIO_CPL = 7'b0001010, |
| 84 | PIO_CPLD = 7'b1001010; |
| 85 | |
| 86 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 87 | |
| 88 | //------------------------------------------------------------------------ |
| 89 | // Clock and Reset Signals |
| 90 | //------------------------------------------------------------------------ |
| 91 | input clk; |
| 92 | input rst_l; |
| 93 | |
| 94 | //------------------------------------------------------------------------ |
| 95 | // record interface to ILU |
| 96 | //------------------------------------------------------------------------ |
| 97 | input [`FIRE_DLC_IPE_REC_WDTH-1:0] y2k_rcd; // ingress PEC record |
| 98 | input y2k_rcd_enq; // ingress PEC record enqueue |
| 99 | |
| 100 | //------------------------------------------------------------------------ |
| 101 | // RMU interface |
| 102 | //------------------------------------------------------------------------ |
| 103 | output [`FIRE_DLC_DIM_REC_WDTH-1:0] tm2rm_rcd; |
| 104 | |
| 105 | //------------------------------------------------------------------------ |
| 106 | // IMU interface |
| 107 | //------------------------------------------------------------------------ |
| 108 | input [`FIRE_DLC_SCW_MSI32_WDTH-1:0] im2tm_msi32_addr_reg; |
| 109 | input [`FIRE_DLC_SCW_MSI64_WDTH-1:0] im2tm_msi64_addr_reg; |
| 110 | |
| 111 | //------------------------------------------------------------------------ |
| 112 | // Internal interface |
| 113 | //------------------------------------------------------------------------ |
| 114 | output rcd_empty; // to xfrfsm.v |
| 115 | input rcd_deq; // from xfrfsm.v |
| 116 | |
| 117 | output rcd_is_msg; // to xfrfsm.v, bufmgr.v |
| 118 | output rcd_is_msi; // to xfrfsm.v, bufmgr.v, datafsm.v |
| 119 | output rcd_is_cpld; // to xfrfsm.v, bufmgr.v, datafsm.v |
| 120 | output rcd_is_dmawr; // to xfrfsm.v, bufmgr.v, datafsm.v |
| 121 | |
| 122 | output [5:2] align_addr; // to datafsm.v |
| 123 | output [7:0] payld_len; // to datafsm.v |
| 124 | |
| 125 | input [`FIRE_DLC_DIM_DPTR_WDTH-1:0] d_ptr_out; // from bufmgr.v |
| 126 | |
| 127 | output [3:0] first_dwbe; // to datafsm.v |
| 128 | output [3:0] last_dwbe; // to datafsm.v |
| 129 | |
| 130 | //------------------------------------------------------------------------ |
| 131 | // for sun4v msi_64 compare |
| 132 | //------------------------------------------------------------------------ |
| 133 | input csr_sun4v_en; |
| 134 | input im2tm_eqs_adr_63; |
| 135 | |
| 136 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 137 | |
| 138 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 139 | reg [`FIRE_DLC_DIM_REC_WDTH-1:0] tm2rm_rcd; |
| 140 | |
| 141 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~ |
| 142 | reg rcd_is_msg; // to xfrfsm.v, bufmgr.v |
| 143 | reg rcd_is_msi; // to xfrfsm.v, bufmgr.v, datafsm.v |
| 144 | reg rcd_is_cpld; // to xfrfsm.v, bufmgr.v, datafsm.v |
| 145 | reg rcd_is_dmawr; // to xfrfsm.v, bufmgr.v, datafsm.v |
| 146 | reg rcd_is_cpl; |
| 147 | reg [`FIRE_DLC_DIM_TYPE_WDTH-1:0] out_rcd_type; |
| 148 | |
| 149 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 150 | wire [`FIRE_DLC_IPE_REC_WDTH-1:0] curr_rcd; |
| 151 | wire potential_msi32; |
| 152 | wire potential_msi64; |
| 153 | |
| 154 | //--------------------------------------------------------------------- |
| 155 | // In record fields |
| 156 | //--------------------------------------------------------------------- |
| 157 | wire [`FIRE_DLC_IPE_ADDR_WDTH-1:0] in_rcd_addr; |
| 158 | wire [`FIRE_DLC_IPE_FDWBE_WDTH-1:0] in_rcd_fdwbe; |
| 159 | wire [`FIRE_DLC_IPE_LDWBE_WDTH-1:0] in_rcd_ldwbe; |
| 160 | wire [`FIRE_DLC_IPE_TAG_WDTH-1:0] in_rcd_tag; |
| 161 | wire [`FIRE_DLC_IPE_REQID_WDTH-1:0] in_rcd_reqid; |
| 162 | wire [`FIRE_DLC_IPE_LEN_WDTH-1:0] in_rcd_len; |
| 163 | wire [`FIRE_DLC_IPE_ATR_WDTH-1:0] in_rcd_atr; |
| 164 | wire [`FIRE_DLC_IPE_TC_WDTH-1:0] in_rcd_tc; |
| 165 | wire [`FIRE_DLC_IPE_TYPE_WDTH+`FIRE_DLC_IPE_F_WDTH-1:0] in_rcd_type; |
| 166 | |
| 167 | //--------------------------------------------------------------------- |
| 168 | // Out record fields |
| 169 | //--------------------------------------------------------------------- |
| 170 | wire [`FIRE_DLC_DIM_ADDR_WDTH-1:0] out_rcd_addr; |
| 171 | wire [`FIRE_DLC_DIM_FDWBE_WDTH-1:0] out_rcd_fdwbe; |
| 172 | wire [`FIRE_DLC_DIM_LDWBE_WDTH-1:0] out_rcd_ldwbe; |
| 173 | wire [`FIRE_DLC_DIM_TAG_WDTH-1:0] out_rcd_tag; |
| 174 | wire [`FIRE_DLC_DIM_REQID_WDTH-1:0] out_rcd_reqid; |
| 175 | wire [`FIRE_DLC_DIM_LEN_WDTH-1:0] out_rcd_len; |
| 176 | wire [`FIRE_DLC_DIM_ATR_WDTH-1:0] out_rcd_atr; |
| 177 | wire [`FIRE_DLC_DIM_TC_WDTH-1:0] out_rcd_tc; |
| 178 | |
| 179 | wire [`FIRE_DLC_DIM_REC_WDTH-1:0] n_tm2rm_rcd; |
| 180 | |
| 181 | |
| 182 | // >>>>>>>>>>>>>>>>>>>>>>>>> Zero In Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 183 | |
| 184 | // 0in max -var in_rcd_len -val 128 -active (rcd_is_msi & !rcd_empty) |
| 185 | // 0in max -var in_rcd_len -val 128 -active (rcd_is_dmawr & !rcd_empty) |
| 186 | // 0in max -var in_rcd_len -val 16 -active (rcd_is_cpld & !rcd_empty) |
| 187 | |
| 188 | /* 0in bits_on -var {rcd_is_msi, rcd_is_msg, rcd_is_dmawr, rcd_is_cpld, rcd_is_cpl} |
| 189 | -max 1 -active ~rcd_empty */ |
| 190 | |
| 191 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 192 | |
| 193 | //--------------------------------------------------------------------- |
| 194 | // In record fields |
| 195 | //--------------------------------------------------------------------- |
| 196 | assign in_rcd_addr = curr_rcd[`FIRE_DLC_IPE_ADDR_MSB:`FIRE_DLC_IPE_ADDR_LSB]; |
| 197 | assign in_rcd_fdwbe = curr_rcd[`FIRE_DLC_IPE_FDWBE_MSB:`FIRE_DLC_IPE_FDWBE_LSB]; |
| 198 | assign in_rcd_ldwbe = curr_rcd[`FIRE_DLC_IPE_LDWBE_MSB:`FIRE_DLC_IPE_LDWBE_LSB]; |
| 199 | assign in_rcd_tag = curr_rcd[`FIRE_DLC_IPE_TAG_MSB:`FIRE_DLC_IPE_TAG_LSB]; |
| 200 | assign in_rcd_reqid = curr_rcd[`FIRE_DLC_IPE_REQID_MSB:`FIRE_DLC_IPE_REQID_LSB]; |
| 201 | assign in_rcd_len = curr_rcd[`FIRE_DLC_IPE_LEN_MSB:`FIRE_DLC_IPE_LEN_LSB]; |
| 202 | assign in_rcd_atr = curr_rcd[`FIRE_DLC_IPE_ATR_MSB:`FIRE_DLC_IPE_ATR_LSB]; |
| 203 | assign in_rcd_tc = curr_rcd[`FIRE_DLC_IPE_TC_MSB:`FIRE_DLC_IPE_TC_LSB]; |
| 204 | assign in_rcd_type = curr_rcd[`FIRE_DLC_IPE_F_MSB:`FIRE_DLC_IPE_TYPE_LSB]; |
| 205 | |
| 206 | //--------------------------------------------------------------------- |
| 207 | // type decoder |
| 208 | //--------------------------------------------------------------------- |
| 209 | assign potential_msi32 = in_rcd_addr[29:14] == im2tm_msi32_addr_reg; |
| 210 | //BP n2 12-12-05 |
| 211 | // assign potential_msi64 = in_rcd_addr[61:14] == im2tm_msi64_addr_reg; |
| 212 | assign potential_msi64 = (csr_sun4v_en & ~im2tm_eqs_adr_63) ? |
| 213 | (in_rcd_addr[60:14] == im2tm_msi64_addr_reg[46:0] ) : |
| 214 | (in_rcd_addr[61:14] == im2tm_msi64_addr_reg[47:0]) ; |
| 215 | |
| 216 | always @ (in_rcd_type or potential_msi32 or potential_msi64) |
| 217 | begin |
| 218 | rcd_is_msi = 1'b0; |
| 219 | rcd_is_msg = 1'b0; |
| 220 | rcd_is_dmawr = 1'b0; |
| 221 | rcd_is_cpld = 1'b0; |
| 222 | rcd_is_cpl = 1'b0; |
| 223 | out_rcd_type = in_rcd_type; |
| 224 | |
| 225 | // vlint fix: 3-3-03 pstabile - changed case to casez since DMA_MSG param = 7'b0110zzz |
| 226 | casez (in_rcd_type) // 0in < case -parallel -full -active ~rcd_empty |
| 227 | DMA_MWR32 : |
| 228 | if (potential_msi32) |
| 229 | begin |
| 230 | rcd_is_msi = 1'b1; |
| 231 | out_rcd_type = 7'b1011000; |
| 232 | end |
| 233 | else |
| 234 | begin |
| 235 | rcd_is_dmawr = 1'b1; |
| 236 | end |
| 237 | DMA_MWR64 : |
| 238 | if (potential_msi64) |
| 239 | begin |
| 240 | rcd_is_msi = 1'b1; |
| 241 | out_rcd_type = 7'b1111000; |
| 242 | end |
| 243 | else |
| 244 | begin |
| 245 | rcd_is_dmawr = 1'b1; |
| 246 | end |
| 247 | DMA_MSG : |
| 248 | begin |
| 249 | rcd_is_msg = 1'b1; |
| 250 | end |
| 251 | PIO_CPL : |
| 252 | begin |
| 253 | rcd_is_cpl = 1'b1; |
| 254 | end |
| 255 | PIO_CPLD : |
| 256 | begin |
| 257 | rcd_is_cpld = 1'b1; |
| 258 | end |
| 259 | DMA_MRD32, |
| 260 | DMA_MRD64, |
| 261 | DMA_MRDLK32, |
| 262 | DMA_MRDLK64, |
| 263 | DMA_UR : |
| 264 | begin // redudant - for 0in case checker |
| 265 | rcd_is_cpl = 1'b0; |
| 266 | end |
| 267 | |
| 268 | endcase // case(in_rcd_type) |
| 269 | end |
| 270 | |
| 271 | |
| 272 | //--------------------------------------------------------------------- |
| 273 | // Out record fields |
| 274 | //--------------------------------------------------------------------- |
| 275 | assign out_rcd_reqid = (rcd_is_cpl | rcd_is_cpld) ? |
| 276 | in_rcd_addr[29:14] : in_rcd_reqid; |
| 277 | assign out_rcd_tag = (rcd_is_cpl | rcd_is_cpld) ? |
| 278 | in_rcd_addr[13:6] : in_rcd_tag; |
| 279 | assign out_rcd_fdwbe = (rcd_is_cpl | rcd_is_cpld) ? |
| 280 | {in_rcd_fdwbe[0], in_rcd_tag[7:5]} : |
| 281 | in_rcd_fdwbe; |
| 282 | assign out_rcd_addr = (rcd_is_cpl | rcd_is_cpld) ? |
| 283 | {in_rcd_addr[45:0], in_rcd_reqid} : |
| 284 | in_rcd_addr; |
| 285 | assign out_rcd_tc = in_rcd_tc; |
| 286 | assign out_rcd_atr = in_rcd_atr; |
| 287 | assign out_rcd_len = in_rcd_len; |
| 288 | assign out_rcd_ldwbe = in_rcd_ldwbe; |
| 289 | |
| 290 | assign n_tm2rm_rcd = {out_rcd_type, out_rcd_tc, out_rcd_atr, out_rcd_len, |
| 291 | out_rcd_reqid, out_rcd_tag, out_rcd_ldwbe, |
| 292 | out_rcd_fdwbe, out_rcd_addr, d_ptr_out}; |
| 293 | |
| 294 | //--------------------------------------------------------------------- |
| 295 | // Outputs |
| 296 | //--------------------------------------------------------------------- |
| 297 | assign payld_len = in_rcd_len[7:0]; |
| 298 | assign align_addr = in_rcd_addr[3:0]; |
| 299 | assign first_dwbe = in_rcd_fdwbe; |
| 300 | assign last_dwbe = in_rcd_ldwbe; |
| 301 | |
| 302 | always @ (posedge clk) |
| 303 | if(~rst_l) begin |
| 304 | tm2rm_rcd <= {`FIRE_DLC_DIM_REC_WDTH{1'b0}}; |
| 305 | end |
| 306 | else begin |
| 307 | tm2rm_rcd <= n_tm2rm_rcd; |
| 308 | end |
| 309 | |
| 310 | // >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 311 | |
| 312 | // simple fifo |
| 313 | pcie_common_srq #(6, `FIRE_DLC_IPE_REC_WDTH) rcd_fifo |
| 314 | ( |
| 315 | .clk (clk), |
| 316 | .rst_l (rst_l), |
| 317 | .enq (y2k_rcd_enq), |
| 318 | .deq (rcd_deq), |
| 319 | .di (y2k_rcd), |
| 320 | .do (curr_rcd), |
| 321 | .empty (rcd_empty), |
| 322 | .full (), |
| 323 | .afull () |
| 324 | ); |
| 325 | |
| 326 | endmodule // dmu_tmu_dim_rcdbldr |
| 327 | |
| 328 | |
| 329 | |
| 330 | |