| 1 | # ========== Copyright Header Begin ========================================== |
| 2 | # |
| 3 | # OpenSPARC T2 Processor File: user_cfg.scr |
| 4 | # Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | # 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | # |
| 7 | # * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | # |
| 9 | # This program is free software; you can redistribute it and/or modify |
| 10 | # it under the terms of the GNU General Public License as published by |
| 11 | # the Free Software Foundation; version 2 of the License. |
| 12 | # |
| 13 | # This program is distributed in the hope that it will be useful, |
| 14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | # GNU General Public License for more details. |
| 17 | # |
| 18 | # You should have received a copy of the GNU General Public License |
| 19 | # along with this program; if not, write to the Free Software |
| 20 | # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | # |
| 22 | # For the avoidance of doubt, and except that if any non-GPL license |
| 23 | # choice is available it will apply instead, Sun elects to use only |
| 24 | # the General Public License version 2 (GPLv2) at this time for any |
| 25 | # software where a choice of GPL license versions is made |
| 26 | # available with the language indicating that GPLv2 or any later version |
| 27 | # may be used, or where a choice of which version of the GPL is applied is |
| 28 | # otherwise unspecified. |
| 29 | # |
| 30 | # Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | # CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | # have any questions. |
| 33 | # |
| 34 | # ========== Copyright Header End ============================================ |
| 35 | source -echo -verbose $dv_root/design/sys/synopsys/script/project_sparc_cfg.scr |
| 36 | |
| 37 | set rtl_files {\ |
| 38 | libs/cl/cl_rtl_ext.v |
| 39 | libs/cl/cl_a1/cl_a1.behV |
| 40 | libs/cl/cl_u1/cl_u1.behV |
| 41 | libs/cl/cl_dp1/cl_dp1.behV |
| 42 | libs/cl/cl_sc1/cl_sc1.behV |
| 43 | libs/cl/cl_u1lvt/cl_u1lvt.behV |
| 44 | libs/cl/cl_u1gb/cl_u1gb.behV |
| 45 | libs/cl/cl_dp1lvt/cl_dp1lvt.behV |
| 46 | libs/cl/cl_sc1lvt/cl_sc1lvt.behV |
| 47 | libs/cl/cl_sc1gb/cl_sc1gb.behV |
| 48 | libs/cl/cl_mc1/cl_mc1.v |
| 49 | |
| 50 | libs/clk/n2_flop_bank_cust_l/n2_flop_bank_cust/rtl/n2_flop_bank_cust.v |
| 51 | libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v |
| 52 | libs/clk/n2_clk_pgrid_cust_l/n2_clk_l2t_cmp_cust/rtl/n2_clk_l2t_cmp_cust.v |
| 53 | |
| 54 | libs/n2sram/cams/n2_com_cm_64x64_cust_l/n2_com_cm_64x64_cust/rtl/n2_com_cm_64x64_cust.v |
| 55 | libs/n2sram/cams/n2_com_cm_32x40_cust_l/n2_com_cm_32x40_cust/rtl/n2_com_cm_32x40_cust.v |
| 56 | libs/n2sram/cams/n2_com_cm_8x40_cust_l/n2_com_cm_8x40_cust/rtl/n2_com_cm_8x40_cust.v |
| 57 | libs/n2sram/dp/n2_l2t_dp_32x128_cust_l/n2_l2t_dp_32x128_cust/rtl/n2_l2t_dp_32x128_cust.v |
| 58 | libs/n2sram/dp/n2_l2t_dp_16x160_cust_l/n2_l2t_dp_16x160_cust/rtl/n2_l2t_dp_16x160_cust.v |
| 59 | libs/n2sram/dp/n2_l2t_dp_32x160_cust_l/n2_l2t_dp_32x160_cust/rtl/n2_l2t_dp_32x160_cust.v |
| 60 | libs/tisram/soc/n2_l2t_sp_28kb_cust_l/n2_l2t_sp_28kb_cust/rtl/n2_l2t_sp_28kb_cust.v |
| 61 | |
| 62 | libs/clk/rtl/clkgen_l2t_cmp.v |
| 63 | libs/rtl/n2_efuhdr1_ctl.v |
| 64 | |
| 65 | design/sys/iop/l2t/rtl/l2t_arb_ctl.v |
| 66 | design/sys/iop/l2t/rtl/l2t_arbadr_dp.v |
| 67 | design/sys/iop/l2t/rtl/l2t_arbdat_dp.v |
| 68 | design/sys/iop/l2t/rtl/l2t_arbdec_dp.v |
| 69 | design/sys/iop/l2t/rtl/l2t_csr_ctl.v |
| 70 | design/sys/iop/l2t/rtl/l2t_csreg_ctl.v |
| 71 | design/sys/iop/l2t/rtl/l2t_decc_dp.v |
| 72 | design/sys/iop/l2t/rtl/l2t_deccck_ctl.v |
| 73 | design/sys/iop/l2t/rtl/l2t_dir_ctl.v |
| 74 | design/sys/iop/l2t/rtl/l2t_dirbuf_ctl.v |
| 75 | design/sys/iop/l2t/rtl/l2t_dirout_dp.v |
| 76 | design/sys/iop/l2t/rtl/l2t_dirrep_ctl.v |
| 77 | design/sys/iop/l2t/rtl/l2t_dirtop_ctl.v |
| 78 | design/sys/iop/l2t/rtl/l2t_dirvec_ctl.v |
| 79 | design/sys/iop/l2t/rtl/l2t_dmo_dp.v |
| 80 | design/sys/iop/l2t/rtl/l2t_dmorpt_dp.v |
| 81 | design/sys/iop/l2t/rtl/l2t_ecc24b_dp.v |
| 82 | design/sys/iop/l2t/rtl/l2t_ecc30b_dp.v |
| 83 | design/sys/iop/l2t/rtl/l2t_ecc39_dp.v |
| 84 | design/sys/iop/l2t/rtl/l2t_ecc39a_dp.v |
| 85 | design/sys/iop/l2t/rtl/l2t_evctag_dp.v |
| 86 | design/sys/iop/l2t/rtl/l2t_ffrpt_dp.v |
| 87 | design/sys/iop/l2t/rtl/l2t_filbuf_ctl.v |
| 88 | design/sys/iop/l2t/rtl/l2t_iqu_ctl.v |
| 89 | design/sys/iop/l2t/rtl/l2t_ique_dp.v |
| 90 | design/sys/iop/l2t/rtl/l2t_l2drpt_dp.v |
| 91 | design/sys/iop/l2t/rtl/l2t_mb0_ctl.v |
| 92 | design/sys/iop/l2t/rtl/l2t_mb2_ctl.v |
| 93 | design/sys/iop/l2t/rtl/l2t_mbist_ctl.v |
| 94 | design/sys/iop/l2t/rtl/l2t_misbuf_ctl.v |
| 95 | design/sys/iop/l2t/rtl/l2t_mrep4x6_dp.v |
| 96 | design/sys/iop/l2t/rtl/l2t_mrep8x16_dp.v |
| 97 | design/sys/iop/l2t/rtl/l2t_mrep16x8_dp.v |
| 98 | design/sys/iop/l2t/rtl/l2t_mrep2x64_dp.v |
| 99 | design/sys/iop/l2t/rtl/l2t_mrep32x3_dp.v |
| 100 | design/sys/iop/l2t/rtl/l2t_oqu_ctl.v |
| 101 | design/sys/iop/l2t/rtl/l2t_oque_dp.v |
| 102 | design/sys/iop/l2t/rtl/l2t_pgen32b_dp.v |
| 103 | design/sys/iop/l2t/rtl/l2t_rdmarpt_dp.v |
| 104 | design/sys/iop/l2t/rtl/l2t_rdmat_ctl.v |
| 105 | design/sys/iop/l2t/rtl/l2t_rep_dp.v |
| 106 | design/sys/iop/l2t/rtl/l2t_shdwscn_dp.v |
| 107 | design/sys/iop/l2t/rtl/l2t_snp_ctl.v |
| 108 | design/sys/iop/l2t/rtl/l2t_snpd_dp.v |
| 109 | design/sys/iop/l2t/rtl/l2t_tag_ctl.v |
| 110 | design/sys/iop/l2t/rtl/l2t_tagd_dp.v |
| 111 | design/sys/iop/l2t/rtl/l2t_tagdp_ctl.v |
| 112 | design/sys/iop/l2t/rtl/l2t_taghdr_ctl.v |
| 113 | design/sys/iop/l2t/rtl/l2t_tagl_dp.v |
| 114 | design/sys/iop/l2t/rtl/l2t_usaloc_dp.v |
| 115 | design/sys/iop/l2t/rtl/l2t_vlddir_dp.v |
| 116 | design/sys/iop/l2t/rtl/l2t_vuad_ctl.v |
| 117 | design/sys/iop/l2t/rtl/l2t_vuadcl_dp.v |
| 118 | design/sys/iop/l2t/rtl/l2t_vuadio_dp.v |
| 119 | design/sys/iop/l2t/rtl/l2t_vuadpm_dp.v |
| 120 | design/sys/iop/l2t/rtl/l2t_wbuf_ctl.v |
| 121 | design/sys/iop/l2t/rtl/l2t_wbufrpt_dp.v |
| 122 | design/sys/iop/l2t/rtl/l2t.v |
| 123 | } |
| 124 | |
| 125 | set link_library [concat $link_library \ |
| 126 | dw_foundation.sldb \ |
| 127 | ] |
| 128 | |
| 129 | |
| 130 | set mix_files {} |
| 131 | set top_module l2t |
| 132 | |
| 133 | set include_paths {\ |
| 134 | } |
| 135 | |
| 136 | set black_box_libs {} |
| 137 | set black_box_designs {} |
| 138 | set mem_libs {} |
| 139 | |
| 140 | set dont_touch_modules {\ |
| 141 | n2_com_cm_32x40_cust \ |
| 142 | n2_com_cm_8x40_cust \ |
| 143 | n2_com_cm_8x40_cust_array \ |
| 144 | n2_com_cm_64x64_cust \ |
| 145 | n2_l2t_dp_32x128_cust \ |
| 146 | n2_l2t_dp_32x160_cust \ |
| 147 | n2_l2t_dp_16x160_cust \ |
| 148 | n2_l2t_sp_28kb_cust \ |
| 149 | n2_l2t_array \ |
| 150 | n2_l2t_sr_latch \ |
| 151 | } |
| 152 | |
| 153 | set compile_effort "medium" |
| 154 | |
| 155 | set compile_flatten_all 1 |
| 156 | |
| 157 | set compile_no_new_cells_at_top_level false |
| 158 | |
| 159 | set default_clk gclk |
| 160 | set default_clk_freq 1400 |
| 161 | set default_setup_skew 0.0 |
| 162 | set default_hold_skew 0.0 |
| 163 | set default_clk_transition 0.05 |
| 164 | set clk_list { \ |
| 165 | { gclk 1400.0 0.000 0.000 0.05} \ |
| 166 | } |
| 167 | |
| 168 | set ideal_net_list {} |
| 169 | set false_path_list {} |
| 170 | set enforce_input_fanout_one 0 |
| 171 | set allow_outport_drive_innodes 1 |
| 172 | set skip_scan 0 |
| 173 | set add_lockup_latch false |
| 174 | set chain_count 1 |
| 175 | set scanin_port_list {} |
| 176 | set scanout_port_list {} |
| 177 | set scanenable_port global_shift_enable |
| 178 | set has_test_stub 1 |
| 179 | set scanenable_pin test_stub_no_bist/se |
| 180 | set long_chain_so_0_net long_chain_so_0 |
| 181 | set short_chain_so_0_net short_chain_so_0 |
| 182 | set so_0_net so_0 |
| 183 | set insert_extra_lockup_latch 0 |
| 184 | set extra_lockup_latch_clk_list {} |