| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fflp_pio_if.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /**********************************************************************/ |
| 36 | /*project name: NIU */ |
| 37 | /*module name: fflp_pio_if */ |
| 38 | /*description: pio registers for hdr matching and pio interface */ |
| 39 | /* control logic and data mux */ |
| 40 | /* */ |
| 41 | /*parent module in: fflp_pio_if.v */ |
| 42 | /*child modules in: none */ |
| 43 | /*interface modules: */ |
| 44 | /*author name: Jeanne Cai */ |
| 45 | /*date created: 03-18-04 */ |
| 46 | /* */ |
| 47 | /* Copyright (c) 2004, Sun Microsystems, Inc. */ |
| 48 | /* Sun Proprietary and Confidential */ |
| 49 | /* */ |
| 50 | /*modifications: */ |
| 51 | /* */ |
| 52 | /**********************************************************************/ |
| 53 | module fflp_pio_if( |
| 54 | cclk, |
| 55 | reset_l, |
| 56 | pio_fflp_wdata, |
| 57 | pio_fflp_rd, |
| 58 | pio_fflp_sel, |
| 59 | pio_fflp_addr, |
| 60 | pio_client_32b, |
| 61 | cam_key_reg0_dout, |
| 62 | cam_key_reg1_dout, |
| 63 | cam_key_reg2_dout, |
| 64 | cam_key_reg3_dout, |
| 65 | cam_key_mask_reg0_dout, |
| 66 | cam_key_mask_reg1_dout, |
| 67 | cam_key_mask_reg2_dout, |
| 68 | cam_key_mask_reg3_dout, |
| 69 | cam_cmd_stat_reg_dout, |
| 70 | vlan_tbl_din_reg_dout, |
| 71 | vlan_parity_err_log_en, |
| 72 | vlan_tag_id, |
| 73 | cpu_vlan_gnt_3, |
| 74 | cpu_fc_req_done_sync, |
| 75 | fc_rd_data_reg_dout, |
| 76 | fc_rd_ecc_err, |
| 77 | fflp_zcp_wr_p, |
| 78 | fc_err_status, |
| 79 | ecc_parity_status, |
| 80 | cpu_fio_req_done_sync, |
| 81 | cpu_fio_rd_data, |
| 82 | fio_cal_rd_latency, |
| 83 | |
| 84 | reset_s, |
| 85 | pio_wen, |
| 86 | pio_addr, |
| 87 | pio_wr_data, |
| 88 | pio_32b_mode, |
| 89 | fflp_pio_rdata, |
| 90 | fflp_pio_ack, |
| 91 | fflp_pio_err, |
| 92 | fflp_pio_intr, |
| 93 | snap_en, |
| 94 | disable_chksum, |
| 95 | pio_disable_cam, |
| 96 | fflp_init_done, |
| 97 | fcram_driver_imp_ctrl, |
| 98 | fcram_qs_mode, |
| 99 | fcram_lookup_ratio, |
| 100 | pio_fio_latency, |
| 101 | cam_srch_ratio, |
| 102 | cam_srch_latency, |
| 103 | h1_init_value_reg_dout, |
| 104 | h2_init_value_reg_dout, |
| 105 | fcram_refresh_timer_reg_dout, |
| 106 | class2_hdr_byte_value, |
| 107 | class3_hdr_byte_value, |
| 108 | class4_hdr_byte_value, |
| 109 | class5_hdr_byte_value, |
| 110 | class6_hdr_byte_value, |
| 111 | class7_hdr_byte_value, |
| 112 | class_action_reg4_dout, |
| 113 | class_action_reg5_dout, |
| 114 | class_action_reg6_dout, |
| 115 | class_action_reg7_dout, |
| 116 | class_action_reg8_dout, |
| 117 | class_action_reg9_dout, |
| 118 | class_action_reg10_dout, |
| 119 | class_action_reg11_dout, |
| 120 | class_action_reg12_dout, |
| 121 | class_action_reg13_dout, |
| 122 | class_action_reg14_dout, |
| 123 | class_action_reg15_dout, |
| 124 | f_key_class_action_reg4_dout, |
| 125 | f_key_class_action_reg5_dout, |
| 126 | f_key_class_action_reg6_dout, |
| 127 | f_key_class_action_reg7_dout, |
| 128 | f_key_class_action_reg8_dout, |
| 129 | f_key_class_action_reg9_dout, |
| 130 | f_key_class_action_reg10_dout, |
| 131 | f_key_class_action_reg11_dout, |
| 132 | f_key_class_action_reg12_dout, |
| 133 | f_key_class_action_reg13_dout, |
| 134 | f_key_class_action_reg14_dout, |
| 135 | f_key_class_action_reg15_dout, |
| 136 | hdr_ctrl_bit_mask_reg_dout, |
| 137 | cpu_vlan_req, |
| 138 | cpu_vlan_rd, |
| 139 | cpu_vlan_wr, |
| 140 | cpu_vlan_addr, |
| 141 | vlan_tbl_wr_dout, |
| 142 | flow_part_sel_reg0_dout, |
| 143 | flow_part_sel_reg1_dout, |
| 144 | flow_part_sel_reg2_dout, |
| 145 | flow_part_sel_reg3_dout, |
| 146 | flow_part_sel_reg4_dout, |
| 147 | flow_part_sel_reg5_dout, |
| 148 | flow_part_sel_reg6_dout, |
| 149 | flow_part_sel_reg7_dout, |
| 150 | hash_tbl_addr_reg0_dout, |
| 151 | hash_tbl_addr_reg1_dout, |
| 152 | hash_tbl_addr_reg2_dout, |
| 153 | hash_tbl_addr_reg3_dout, |
| 154 | hash_tbl_addr_reg4_dout, |
| 155 | hash_tbl_addr_reg5_dout, |
| 156 | hash_tbl_addr_reg6_dout, |
| 157 | hash_tbl_addr_reg7_dout, |
| 158 | hash_tbl_data_reg0_dout, |
| 159 | hash_tbl_data_reg1_dout, |
| 160 | hash_tbl_data_reg2_dout, |
| 161 | hash_tbl_data_reg3_dout, |
| 162 | hash_tbl_data_reg4_dout, |
| 163 | hash_tbl_data_reg5_dout, |
| 164 | hash_tbl_data_reg6_dout, |
| 165 | hash_tbl_data_reg7_dout, |
| 166 | fcram_err_test_reg_dout, |
| 167 | cpu_req_part0_sel, |
| 168 | cpu_req_part1_sel, |
| 169 | cpu_req_part2_sel, |
| 170 | cpu_req_part3_sel, |
| 171 | cpu_req_part4_sel, |
| 172 | cpu_req_part5_sel, |
| 173 | cpu_req_part6_sel, |
| 174 | cpu_req_part7_sel, |
| 175 | pio_rd, |
| 176 | cpu_fcram_req, |
| 177 | cpu_fio_req, |
| 178 | pio_fio_cfg_reset, |
| 179 | fio_cfg_addr_reg_dout, |
| 180 | fflp_config_reg_wen_pulse, |
| 181 | debug_training_vector, |
| 182 | pio_debug_data_sel |
| 183 | |
| 184 | ); |
| 185 | |
| 186 | input cclk; |
| 187 | input reset_l; |
| 188 | input[63:0] pio_fflp_wdata; |
| 189 | input pio_fflp_rd; |
| 190 | input pio_fflp_sel; |
| 191 | input[19:0] pio_fflp_addr; |
| 192 | input pio_client_32b; |
| 193 | input[7:0] cam_key_reg0_dout; |
| 194 | input[63:0] cam_key_reg1_dout; |
| 195 | input[63:0] cam_key_reg2_dout; |
| 196 | input[63:0] cam_key_reg3_dout; |
| 197 | input[7:0] cam_key_mask_reg0_dout; |
| 198 | input[63:0] cam_key_mask_reg1_dout; |
| 199 | input[63:0] cam_key_mask_reg2_dout; |
| 200 | input[63:0] cam_key_mask_reg3_dout; |
| 201 | input[20:0] cam_cmd_stat_reg_dout; |
| 202 | input[17:0] vlan_tbl_din_reg_dout; |
| 203 | input vlan_parity_err_log_en; |
| 204 | input[11:0] vlan_tag_id; |
| 205 | input cpu_vlan_gnt_3; |
| 206 | input cpu_fc_req_done_sync; |
| 207 | input[71:0] fc_rd_data_reg_dout; |
| 208 | input fc_rd_ecc_err; |
| 209 | input fflp_zcp_wr_p; |
| 210 | input[33:0] fc_err_status; |
| 211 | input[25:0] ecc_parity_status; |
| 212 | input cpu_fio_req_done_sync; |
| 213 | input[31:0] cpu_fio_rd_data; |
| 214 | input[7:0] fio_cal_rd_latency; |
| 215 | |
| 216 | output reset_s; |
| 217 | output pio_wen; |
| 218 | output[19:0] pio_addr; |
| 219 | output[63:0] pio_wr_data; |
| 220 | output pio_32b_mode; |
| 221 | output[63:0] fflp_pio_rdata; |
| 222 | output fflp_pio_ack; |
| 223 | output fflp_pio_err; |
| 224 | output fflp_pio_intr; |
| 225 | output snap_en; |
| 226 | output disable_chksum; |
| 227 | output pio_disable_cam; |
| 228 | output fflp_init_done; |
| 229 | output[3:0] fcram_driver_imp_ctrl; |
| 230 | output fcram_qs_mode; |
| 231 | output[3:0] fcram_lookup_ratio; |
| 232 | output[1:0] pio_fio_latency; |
| 233 | output[3:0] cam_srch_ratio; |
| 234 | output[3:0] cam_srch_latency; |
| 235 | output[31:0] h1_init_value_reg_dout; |
| 236 | output[15:0] h2_init_value_reg_dout; |
| 237 | output[31:0] fcram_refresh_timer_reg_dout; |
| 238 | output[16:0] class2_hdr_byte_value; |
| 239 | output[16:0] class3_hdr_byte_value; |
| 240 | output[25:0] class4_hdr_byte_value; |
| 241 | output[25:0] class5_hdr_byte_value; |
| 242 | output[25:0] class6_hdr_byte_value; |
| 243 | output[25:0] class7_hdr_byte_value; |
| 244 | output[2:0] class_action_reg4_dout; |
| 245 | output[2:0] class_action_reg5_dout; |
| 246 | output[2:0] class_action_reg6_dout; |
| 247 | output[2:0] class_action_reg7_dout; |
| 248 | output[2:0] class_action_reg8_dout; |
| 249 | output[2:0] class_action_reg9_dout; |
| 250 | output[2:0] class_action_reg10_dout; |
| 251 | output[2:0] class_action_reg11_dout; |
| 252 | output[2:0] class_action_reg12_dout; |
| 253 | output[2:0] class_action_reg13_dout; |
| 254 | output[2:0] class_action_reg14_dout; |
| 255 | output[2:0] class_action_reg15_dout; |
| 256 | output[9:0] f_key_class_action_reg4_dout; |
| 257 | output[9:0] f_key_class_action_reg5_dout; |
| 258 | output[9:0] f_key_class_action_reg6_dout; |
| 259 | output[9:0] f_key_class_action_reg7_dout; |
| 260 | output[9:0] f_key_class_action_reg8_dout; |
| 261 | output[9:0] f_key_class_action_reg9_dout; |
| 262 | output[9:0] f_key_class_action_reg10_dout; |
| 263 | output[9:0] f_key_class_action_reg11_dout; |
| 264 | output[9:0] f_key_class_action_reg12_dout; |
| 265 | output[9:0] f_key_class_action_reg13_dout; |
| 266 | output[9:0] f_key_class_action_reg14_dout; |
| 267 | output[9:0] f_key_class_action_reg15_dout; |
| 268 | output[11:0] hdr_ctrl_bit_mask_reg_dout; |
| 269 | output cpu_vlan_req; |
| 270 | output cpu_vlan_rd; |
| 271 | output cpu_vlan_wr; |
| 272 | output[11:0] cpu_vlan_addr; |
| 273 | output[17:0] vlan_tbl_wr_dout; |
| 274 | output[10:0] flow_part_sel_reg0_dout; |
| 275 | output[10:0] flow_part_sel_reg1_dout; |
| 276 | output[10:0] flow_part_sel_reg2_dout; |
| 277 | output[10:0] flow_part_sel_reg3_dout; |
| 278 | output[10:0] flow_part_sel_reg4_dout; |
| 279 | output[10:0] flow_part_sel_reg5_dout; |
| 280 | output[10:0] flow_part_sel_reg6_dout; |
| 281 | output[10:0] flow_part_sel_reg7_dout; |
| 282 | output[23:0] hash_tbl_addr_reg0_dout; |
| 283 | output[23:0] hash_tbl_addr_reg1_dout; |
| 284 | output[23:0] hash_tbl_addr_reg2_dout; |
| 285 | output[23:0] hash_tbl_addr_reg3_dout; |
| 286 | output[23:0] hash_tbl_addr_reg4_dout; |
| 287 | output[23:0] hash_tbl_addr_reg5_dout; |
| 288 | output[23:0] hash_tbl_addr_reg6_dout; |
| 289 | output[23:0] hash_tbl_addr_reg7_dout; |
| 290 | output[63:0] hash_tbl_data_reg0_dout; |
| 291 | output[63:0] hash_tbl_data_reg1_dout; |
| 292 | output[63:0] hash_tbl_data_reg2_dout; |
| 293 | output[63:0] hash_tbl_data_reg3_dout; |
| 294 | output[63:0] hash_tbl_data_reg4_dout; |
| 295 | output[63:0] hash_tbl_data_reg5_dout; |
| 296 | output[63:0] hash_tbl_data_reg6_dout; |
| 297 | output[63:0] hash_tbl_data_reg7_dout; |
| 298 | output[71:0] fcram_err_test_reg_dout; |
| 299 | output cpu_req_part0_sel; |
| 300 | output cpu_req_part1_sel; |
| 301 | output cpu_req_part2_sel; |
| 302 | output cpu_req_part3_sel; |
| 303 | output cpu_req_part4_sel; |
| 304 | output cpu_req_part5_sel; |
| 305 | output cpu_req_part6_sel; |
| 306 | output cpu_req_part7_sel; |
| 307 | output pio_rd; |
| 308 | output cpu_fcram_req; |
| 309 | output cpu_fio_req; |
| 310 | output pio_fio_cfg_reset; |
| 311 | output[7:0] fio_cfg_addr_reg_dout; |
| 312 | output fflp_config_reg_wen_pulse; |
| 313 | output[31:0] debug_training_vector; |
| 314 | output[2:0] pio_debug_data_sel; |
| 315 | |
| 316 | |
| 317 | wire fflp_pio_sel; |
| 318 | wire pio_rd; |
| 319 | wire[19:0] pio_addr; |
| 320 | wire[63:0] pio_wr_data; |
| 321 | wire pio_32b_mode; |
| 322 | |
| 323 | wire pio_selected; |
| 324 | wire pio_sel_pulse_dly1; |
| 325 | wire fflp_pio_ack_en; |
| 326 | wire pio_addr_err_in; |
| 327 | wire fflp_pio_ack; |
| 328 | wire fflp_pio_err; |
| 329 | wire fflp_pio_rdata_en; |
| 330 | wire[63:0] fflp_pio_rdata_in; |
| 331 | wire[63:0] fflp_pio_rdata; |
| 332 | wire pio_wen_en; |
| 333 | wire pio_wen; |
| 334 | |
| 335 | reg[63:0] pio_rd_data_tmp; |
| 336 | reg pio_addr_err; |
| 337 | |
| 338 | wire cpu_vlan_req_en; |
| 339 | wire cpu_vlan_req_in; |
| 340 | wire cpu_vlan_req; |
| 341 | |
| 342 | wire[31:0] vlan_parity_err_log_tmp; |
| 343 | wire[31:0] vlan_parity_err_log_mux; |
| 344 | wire[31:0] vlan_parity_err_log_reg_dout; |
| 345 | wire vlan_parity_err_log_wen; |
| 346 | wire vlan_parity_err_log_pio_wen; |
| 347 | |
| 348 | wire cpu_vlan_rd; |
| 349 | wire cpu_vlan_wr; |
| 350 | wire is_vlan_addr; |
| 351 | wire[11:0] cpu_vlan_addr; |
| 352 | wire[17:0] vlan_tbl_wr_dout; |
| 353 | wire[17:0] vlan_tbl_rd_data; |
| 354 | |
| 355 | wire cpu_fc_req_done_sync_d; |
| 356 | wire cpu_fc_req_done_p; |
| 357 | wire cpu_fc_req_done_p1; |
| 358 | wire is_fcram_data_addr; |
| 359 | wire is_ext_fcram; |
| 360 | wire is_fcram_req; |
| 361 | wire cpu_fcram_req_en; |
| 362 | wire cpu_fcram_req_in; |
| 363 | wire cpu_fcram_req; |
| 364 | |
| 365 | wire cpu_fio_req_done_sync_d; |
| 366 | wire cpu_fio_req_done_p; |
| 367 | wire is_fio_data_addr; |
| 368 | wire is_ext_fio; |
| 369 | wire cpu_fio_req_en; |
| 370 | wire cpu_fio_req_in; |
| 371 | wire cpu_fio_req; |
| 372 | |
| 373 | wire[16:0] class2_hdr_byte_value; |
| 374 | wire[16:0] class3_hdr_byte_value; |
| 375 | wire[25:0] class4_hdr_byte_value; |
| 376 | wire[25:0] class5_hdr_byte_value; |
| 377 | wire[25:0] class6_hdr_byte_value; |
| 378 | wire[25:0] class7_hdr_byte_value; |
| 379 | |
| 380 | wire class2_hdr_byte_value_pio_wen; |
| 381 | wire class3_hdr_byte_value_pio_wen; |
| 382 | wire class4_hdr_byte_value_pio_wen; |
| 383 | wire class5_hdr_byte_value_pio_wen; |
| 384 | wire class6_hdr_byte_value_pio_wen; |
| 385 | wire class7_hdr_byte_value_pio_wen; |
| 386 | |
| 387 | wire[2:0] class_action_reg4_dout; |
| 388 | wire[2:0] class_action_reg5_dout; |
| 389 | wire[2:0] class_action_reg6_dout; |
| 390 | wire[2:0] class_action_reg7_dout; |
| 391 | wire[2:0] class_action_reg8_dout; |
| 392 | wire[2:0] class_action_reg9_dout; |
| 393 | wire[2:0] class_action_reg10_dout; |
| 394 | wire[2:0] class_action_reg11_dout; |
| 395 | wire[2:0] class_action_reg12_dout; |
| 396 | wire[2:0] class_action_reg13_dout; |
| 397 | wire[2:0] class_action_reg14_dout; |
| 398 | wire[2:0] class_action_reg15_dout; |
| 399 | |
| 400 | wire class_action_reg4_pio_wen; |
| 401 | wire class_action_reg5_pio_wen; |
| 402 | wire class_action_reg6_pio_wen; |
| 403 | wire class_action_reg7_pio_wen; |
| 404 | wire class_action_reg8_pio_wen; |
| 405 | wire class_action_reg9_pio_wen; |
| 406 | wire class_action_reg10_pio_wen; |
| 407 | wire class_action_reg11_pio_wen; |
| 408 | wire class_action_reg12_pio_wen; |
| 409 | wire class_action_reg13_pio_wen; |
| 410 | wire class_action_reg14_pio_wen; |
| 411 | wire class_action_reg15_pio_wen; |
| 412 | |
| 413 | wire[9:0] f_key_class_action_reg4_dout; |
| 414 | wire[9:0] f_key_class_action_reg5_dout; |
| 415 | wire[9:0] f_key_class_action_reg6_dout; |
| 416 | wire[9:0] f_key_class_action_reg7_dout; |
| 417 | wire[9:0] f_key_class_action_reg8_dout; |
| 418 | wire[9:0] f_key_class_action_reg9_dout; |
| 419 | wire[9:0] f_key_class_action_reg10_dout; |
| 420 | wire[9:0] f_key_class_action_reg11_dout; |
| 421 | wire[9:0] f_key_class_action_reg12_dout; |
| 422 | wire[9:0] f_key_class_action_reg13_dout; |
| 423 | wire[9:0] f_key_class_action_reg14_dout; |
| 424 | wire[9:0] f_key_class_action_reg15_dout; |
| 425 | |
| 426 | wire f_key_class_action_reg4_pio_wen; |
| 427 | wire f_key_class_action_reg5_pio_wen; |
| 428 | wire f_key_class_action_reg6_pio_wen; |
| 429 | wire f_key_class_action_reg7_pio_wen; |
| 430 | wire f_key_class_action_reg8_pio_wen; |
| 431 | wire f_key_class_action_reg9_pio_wen; |
| 432 | wire f_key_class_action_reg10_pio_wen; |
| 433 | wire f_key_class_action_reg11_pio_wen; |
| 434 | wire f_key_class_action_reg12_pio_wen; |
| 435 | wire f_key_class_action_reg13_pio_wen; |
| 436 | wire f_key_class_action_reg14_pio_wen; |
| 437 | wire f_key_class_action_reg15_pio_wen; |
| 438 | |
| 439 | wire h1_init_value_reg_pio_wen; |
| 440 | wire h2_init_value_reg_pio_wen; |
| 441 | wire flow_part_sel_reg0_pio_wen; |
| 442 | wire flow_part_sel_reg1_pio_wen; |
| 443 | wire flow_part_sel_reg2_pio_wen; |
| 444 | wire flow_part_sel_reg3_pio_wen; |
| 445 | wire flow_part_sel_reg4_pio_wen; |
| 446 | wire flow_part_sel_reg5_pio_wen; |
| 447 | wire flow_part_sel_reg6_pio_wen; |
| 448 | wire flow_part_sel_reg7_pio_wen; |
| 449 | |
| 450 | wire hash_tbl_addr_reg0_pio_wen; |
| 451 | wire hash_tbl_addr_reg1_pio_wen; |
| 452 | wire hash_tbl_addr_reg2_pio_wen; |
| 453 | wire hash_tbl_addr_reg3_pio_wen; |
| 454 | wire hash_tbl_addr_reg4_pio_wen; |
| 455 | wire hash_tbl_addr_reg5_pio_wen; |
| 456 | wire hash_tbl_addr_reg6_pio_wen; |
| 457 | wire hash_tbl_addr_reg7_pio_wen; |
| 458 | |
| 459 | wire hash_tbl_addr_inc_wen0; |
| 460 | wire hash_tbl_addr_inc_wen1; |
| 461 | wire hash_tbl_addr_inc_wen2; |
| 462 | wire hash_tbl_addr_inc_wen3; |
| 463 | wire hash_tbl_addr_inc_wen4; |
| 464 | wire hash_tbl_addr_inc_wen5; |
| 465 | wire hash_tbl_addr_inc_wen6; |
| 466 | wire hash_tbl_addr_inc_wen7; |
| 467 | |
| 468 | wire hash_tbl_addr_reg0_wen; |
| 469 | wire hash_tbl_addr_reg1_wen; |
| 470 | wire hash_tbl_addr_reg2_wen; |
| 471 | wire hash_tbl_addr_reg3_wen; |
| 472 | wire hash_tbl_addr_reg4_wen; |
| 473 | wire hash_tbl_addr_reg5_wen; |
| 474 | wire hash_tbl_addr_reg6_wen; |
| 475 | wire hash_tbl_addr_reg7_wen; |
| 476 | |
| 477 | wire cpu_req_part0_sel; |
| 478 | wire cpu_req_part1_sel; |
| 479 | wire cpu_req_part2_sel; |
| 480 | wire cpu_req_part3_sel; |
| 481 | wire cpu_req_part4_sel; |
| 482 | wire cpu_req_part5_sel; |
| 483 | wire cpu_req_part6_sel; |
| 484 | wire cpu_req_part7_sel; |
| 485 | |
| 486 | wire[22:0] curr_hash_tbl_addr; |
| 487 | wire[22:0] next_hash_tbl_addr; |
| 488 | wire[22:0] next_hash_tbl_addr_r; |
| 489 | |
| 490 | wire[23:0] hash_tbl_addr_reg0_mux; |
| 491 | wire[23:0] hash_tbl_addr_reg1_mux; |
| 492 | wire[23:0] hash_tbl_addr_reg2_mux; |
| 493 | wire[23:0] hash_tbl_addr_reg3_mux; |
| 494 | wire[23:0] hash_tbl_addr_reg4_mux; |
| 495 | wire[23:0] hash_tbl_addr_reg5_mux; |
| 496 | wire[23:0] hash_tbl_addr_reg6_mux; |
| 497 | wire[23:0] hash_tbl_addr_reg7_mux; |
| 498 | |
| 499 | wire hash_tbl_data_reg0_pio_wen; |
| 500 | wire hash_tbl_data_reg1_pio_wen; |
| 501 | wire hash_tbl_data_reg2_pio_wen; |
| 502 | wire hash_tbl_data_reg3_pio_wen; |
| 503 | wire hash_tbl_data_reg4_pio_wen; |
| 504 | wire hash_tbl_data_reg5_pio_wen; |
| 505 | wire hash_tbl_data_reg6_pio_wen; |
| 506 | wire hash_tbl_data_reg7_pio_wen; |
| 507 | |
| 508 | wire hash_tbl_data_reg0_h_pio_wen; |
| 509 | wire hash_tbl_data_reg1_h_pio_wen; |
| 510 | wire hash_tbl_data_reg2_h_pio_wen; |
| 511 | wire hash_tbl_data_reg3_h_pio_wen; |
| 512 | wire hash_tbl_data_reg4_h_pio_wen; |
| 513 | wire hash_tbl_data_reg5_h_pio_wen; |
| 514 | wire hash_tbl_data_reg6_h_pio_wen; |
| 515 | wire hash_tbl_data_reg7_h_pio_wen; |
| 516 | |
| 517 | wire hash_tbl_data_reg0_wen; |
| 518 | wire hash_tbl_data_reg1_wen; |
| 519 | wire hash_tbl_data_reg2_wen; |
| 520 | wire hash_tbl_data_reg3_wen; |
| 521 | wire hash_tbl_data_reg4_wen; |
| 522 | wire hash_tbl_data_reg5_wen; |
| 523 | wire hash_tbl_data_reg6_wen; |
| 524 | wire hash_tbl_data_reg7_wen; |
| 525 | |
| 526 | wire hash_tbl_data_reg0_h_wen; |
| 527 | wire hash_tbl_data_reg1_h_wen; |
| 528 | wire hash_tbl_data_reg2_h_wen; |
| 529 | wire hash_tbl_data_reg3_h_wen; |
| 530 | wire hash_tbl_data_reg4_h_wen; |
| 531 | wire hash_tbl_data_reg5_h_wen; |
| 532 | wire hash_tbl_data_reg6_h_wen; |
| 533 | wire hash_tbl_data_reg7_h_wen; |
| 534 | |
| 535 | wire hash_tbl_ecc_log_reg0_pio_wen; |
| 536 | wire hash_tbl_ecc_log_reg1_pio_wen; |
| 537 | wire hash_tbl_ecc_log_reg2_pio_wen; |
| 538 | wire hash_tbl_ecc_log_reg3_pio_wen; |
| 539 | wire hash_tbl_ecc_log_reg4_pio_wen; |
| 540 | wire hash_tbl_ecc_log_reg5_pio_wen; |
| 541 | wire hash_tbl_ecc_log_reg6_pio_wen; |
| 542 | wire hash_tbl_ecc_log_reg7_pio_wen; |
| 543 | |
| 544 | wire hash_tbl_ecc_log_reg0_wen; |
| 545 | wire hash_tbl_ecc_log_reg1_wen; |
| 546 | wire hash_tbl_ecc_log_reg2_wen; |
| 547 | wire hash_tbl_ecc_log_reg3_wen; |
| 548 | wire hash_tbl_ecc_log_reg4_wen; |
| 549 | wire hash_tbl_ecc_log_reg5_wen; |
| 550 | wire hash_tbl_ecc_log_reg6_wen; |
| 551 | wire hash_tbl_ecc_log_reg7_wen; |
| 552 | |
| 553 | wire fcram_err_test_reg0_pio_wen; |
| 554 | wire fcram_err_test_reg1_pio_wen; |
| 555 | wire fcram_err_test_reg2_pio_wen; |
| 556 | |
| 557 | wire[7:0] fcram_err_test_reg0_dout; |
| 558 | wire[31:0] fcram_err_test_reg1_dout; |
| 559 | wire[31:0] fcram_err_test_reg2_dout; |
| 560 | wire[71:0] fcram_err_test_reg_dout; |
| 561 | |
| 562 | wire[31:0] hash_tbl_data_reg_mux; |
| 563 | wire[31:0] hash_tbl_data_reg_h_mux; |
| 564 | wire[31:0] hash_tbl_ecc_log_reg_mux; |
| 565 | |
| 566 | wire[31:0] h1_init_value_reg_dout; |
| 567 | wire[15:0] h2_init_value_reg_dout; |
| 568 | |
| 569 | wire[10:0] flow_part_sel_reg0_dout; |
| 570 | wire[10:0] flow_part_sel_reg1_dout; |
| 571 | wire[10:0] flow_part_sel_reg2_dout; |
| 572 | wire[10:0] flow_part_sel_reg3_dout; |
| 573 | wire[10:0] flow_part_sel_reg4_dout; |
| 574 | wire[10:0] flow_part_sel_reg5_dout; |
| 575 | wire[10:0] flow_part_sel_reg6_dout; |
| 576 | wire[10:0] flow_part_sel_reg7_dout; |
| 577 | |
| 578 | wire[23:0] hash_tbl_addr_reg0_dout; |
| 579 | wire[23:0] hash_tbl_addr_reg1_dout; |
| 580 | wire[23:0] hash_tbl_addr_reg2_dout; |
| 581 | wire[23:0] hash_tbl_addr_reg3_dout; |
| 582 | wire[23:0] hash_tbl_addr_reg4_dout; |
| 583 | wire[23:0] hash_tbl_addr_reg5_dout; |
| 584 | wire[23:0] hash_tbl_addr_reg6_dout; |
| 585 | wire[23:0] hash_tbl_addr_reg7_dout; |
| 586 | |
| 587 | wire[63:0] hash_tbl_data_reg0_dout; |
| 588 | wire[63:0] hash_tbl_data_reg1_dout; |
| 589 | wire[63:0] hash_tbl_data_reg2_dout; |
| 590 | wire[63:0] hash_tbl_data_reg3_dout; |
| 591 | wire[63:0] hash_tbl_data_reg4_dout; |
| 592 | wire[63:0] hash_tbl_data_reg5_dout; |
| 593 | wire[63:0] hash_tbl_data_reg6_dout; |
| 594 | wire[63:0] hash_tbl_data_reg7_dout; |
| 595 | |
| 596 | wire[31:0] hash_tbl_ecc_log_reg0_dout; |
| 597 | wire[31:0] hash_tbl_ecc_log_reg1_dout; |
| 598 | wire[31:0] hash_tbl_ecc_log_reg2_dout; |
| 599 | wire[31:0] hash_tbl_ecc_log_reg3_dout; |
| 600 | wire[31:0] hash_tbl_ecc_log_reg4_dout; |
| 601 | wire[31:0] hash_tbl_ecc_log_reg5_dout; |
| 602 | wire[31:0] hash_tbl_ecc_log_reg6_dout; |
| 603 | wire[31:0] hash_tbl_ecc_log_reg7_dout; |
| 604 | |
| 605 | wire hash_lookup_log_reg0_pio_wen; |
| 606 | wire hash_lookup_log_reg1_pio_wen; |
| 607 | wire hash_lookup_log_reg0_en; |
| 608 | wire hash_lookup_log_reg1_en; |
| 609 | wire hash_lookup_log_reg0_wen; |
| 610 | wire hash_lookup_log_reg1_wen; |
| 611 | wire hash_lookup_log_reg0_din_bit1; |
| 612 | wire hash_lookup_log_reg0_din_bit0; |
| 613 | wire hash_lookup_log_reg0_din_bit2; |
| 614 | wire[3:0] hash_lookup_log_reg0_din; |
| 615 | wire[3:0] hash_lookup_log_reg0_mux; |
| 616 | wire[30:0] hash_lookup_log_reg1_mux; |
| 617 | wire[3:0] hash_lookup_log_reg0_dout; |
| 618 | wire[30:0] hash_lookup_log_reg1_dout; |
| 619 | |
| 620 | wire cam_ecc_log_reg_pio_wen; |
| 621 | wire cam_ecc_log_reg_wen; |
| 622 | wire[26:0] cam_ecc_log_reg_din; |
| 623 | wire[26:0] cam_ecc_log_reg_mux; |
| 624 | wire[26:0] cam_ecc_log_reg_dout; |
| 625 | |
| 626 | wire fflp_config_reg_pio_wen; |
| 627 | wire hdr_ctrl_bit_mask_reg_pio_wen; |
| 628 | wire fcram_refresh_timer_reg_pio_wen; |
| 629 | wire fio_cfg_addr_reg_pio_wen; |
| 630 | wire debug_training_vector_pio_wen; |
| 631 | |
| 632 | wire snap_en; |
| 633 | wire fflp_init_done; |
| 634 | wire disable_chksum; |
| 635 | wire pio_disable_cam; |
| 636 | wire[3:0] fcram_driver_imp_ctrl; |
| 637 | wire fcram_qs_mode; |
| 638 | wire[3:0] fcram_lookup_ratio_i; |
| 639 | wire[3:0] fcram_lookup_ratio; |
| 640 | wire[3:0] cam_srch_ratio_i; |
| 641 | wire[3:0] cam_srch_ratio; |
| 642 | wire[3:0] cam_srch_latency_i; |
| 643 | wire[3:0] cam_srch_latency; |
| 644 | wire[1:0] pio_fio_latency; |
| 645 | wire pio_fio_cfg_reset; |
| 646 | wire[2:0] pio_debug_data_sel; |
| 647 | wire[26:0] fflp_config_reg_dout; |
| 648 | wire[11:0] hdr_ctrl_bit_mask_reg_dout; |
| 649 | wire[31:0] fcram_refresh_timer_reg_dout; |
| 650 | wire[7:0] fio_cfg_addr_reg_dout; |
| 651 | wire[31:0] debug_training_vector; |
| 652 | wire pio_sel_pulse; |
| 653 | wire fflp_config_reg_wen_pulse_in; |
| 654 | wire fflp_config_reg_wen_pulse; |
| 655 | |
| 656 | wire fflp_err_intr_mask_wen; |
| 657 | wire[10:0] fflp_err_intr_bits; |
| 658 | wire fflp_pio_intr_in; |
| 659 | wire fflp_pio_intr; |
| 660 | reg[10:0] fflp_err_intr_mask_reg_dout; |
| 661 | |
| 662 | |
| 663 | wire reset_s; |
| 664 | wire reset_in = !reset_l; |
| 665 | |
| 666 | niu_dff #(1) reset_s_reg (cclk, reset_in, reset_s); |
| 667 | |
| 668 | |
| 669 | /**************************/ |
| 670 | //pio ack logic |
| 671 | /**************************/ |
| 672 | assign pio_sel_pulse = fflp_pio_sel & !pio_selected; |
| 673 | |
| 674 | dffr #(1) fflp_pio_sel_reg (cclk, reset_s, pio_fflp_sel, fflp_pio_sel); |
| 675 | dffr #(1) pio_rd_reg (cclk, reset_s, pio_fflp_rd, pio_rd); |
| 676 | dffr #(20) pio_addr_reg (cclk, reset_s, pio_fflp_addr, pio_addr); |
| 677 | dffr #(64) pio_wr_data_reg (cclk, reset_s, pio_fflp_wdata, pio_wr_data); |
| 678 | dffr #(1) pio_selected_reg (cclk, reset_s, fflp_pio_sel, pio_selected); |
| 679 | dffr #(1) pio_sel_pulse_dly1_reg (cclk, reset_s, pio_sel_pulse, pio_sel_pulse_dly1); |
| 680 | dffr #(1) pio_32b_mode_reg (cclk, reset_s, pio_client_32b, pio_32b_mode); |
| 681 | |
| 682 | assign fflp_pio_ack_en = pio_sel_pulse_dly1 & !(cpu_fcram_req | cpu_vlan_req | cpu_fio_req) | |
| 683 | cpu_vlan_req & cpu_vlan_gnt_3 | cpu_fcram_req & cpu_fc_req_done_p1 | |
| 684 | cpu_fio_req & cpu_fio_req_done_p; |
| 685 | assign pio_addr_err_in = pio_sel_pulse_dly1 & pio_addr_err & pio_rd; |
| 686 | |
| 687 | dffr #(1) fflp_pio_ack_reg (cclk, reset_s, fflp_pio_ack_en, fflp_pio_ack); |
| 688 | dffr #(1) fflp_pio_err_reg (cclk, reset_s, pio_addr_err_in, fflp_pio_err); |
| 689 | |
| 690 | assign fflp_pio_rdata_en = fflp_pio_ack_en & pio_rd; |
| 691 | assign fflp_pio_rdata_in = pio_addr_err_in ? 64'b0 : pio_rd_data_tmp; |
| 692 | |
| 693 | dffre #(64) fflp_pio_rdata_reg (cclk, reset_s, fflp_pio_rdata_en, fflp_pio_rdata_in, fflp_pio_rdata); |
| 694 | |
| 695 | /* |
| 696 | always @ (posedge cclk) |
| 697 | if (reset_s) |
| 698 | fflp_pio_rdata <= 64'b0; |
| 699 | else if (pio_sel_pulse_dly1 & pio_rd & pio_addr_err) |
| 700 | fflp_pio_rdata <= 64'b0; |
| 701 | else if ((pio_sel_pulse_dly1 & !cpu_vlan_req | cpu_vlan_req & cpu_vlan_gnt_3) & pio_rd) |
| 702 | fflp_pio_rdata <= pio_rd_data_tmp; |
| 703 | else |
| 704 | fflp_pio_rdata <= fflp_pio_rdata; |
| 705 | */ |
| 706 | |
| 707 | //pio read enable for ACR and write enable logic |
| 708 | //read pio data is 2 mult-cycles |
| 709 | |
| 710 | assign pio_wen_en = pio_sel_pulse & !pio_rd; |
| 711 | |
| 712 | dffr #(1) pio_wen_reg (cclk, reset_s, pio_wen_en, pio_wen); |
| 713 | dffr #(1) fflp_config_reg_wen_pulse_reg (cclk, reset_s, fflp_config_reg_wen_pulse_in, fflp_config_reg_wen_pulse); |
| 714 | |
| 715 | |
| 716 | assign fflp_config_reg_wen_pulse_in = (pio_sel_pulse | pio_sel_pulse_dly1) & !pio_rd & (pio_addr == 20'ha0100); |
| 717 | |
| 718 | assign fflp_config_reg_pio_wen = pio_wen & (pio_addr == 20'ha0100); |
| 719 | assign hdr_ctrl_bit_mask_reg_pio_wen = pio_wen & (pio_addr == 20'ha0108); |
| 720 | assign fcram_refresh_timer_reg_pio_wen = pio_wen & (pio_addr == 20'ha0110); |
| 721 | assign fio_cfg_addr_reg_pio_wen = pio_wen & (pio_addr == 20'ha0118); |
| 722 | |
| 723 | assign fcram_err_test_reg0_pio_wen = pio_wen & (pio_addr == 20'ha0128); |
| 724 | assign fcram_err_test_reg1_pio_wen = pio_wen & (pio_addr == 20'ha0130); |
| 725 | assign fcram_err_test_reg2_pio_wen = pio_wen & (pio_addr == 20'ha0138); |
| 726 | assign debug_training_vector_pio_wen = pio_wen & (pio_addr == 20'ha0148); |
| 727 | |
| 728 | assign class2_hdr_byte_value_pio_wen = pio_wen & (pio_addr == 20'ha0000); |
| 729 | assign class3_hdr_byte_value_pio_wen = pio_wen & (pio_addr == 20'ha0008); |
| 730 | assign class4_hdr_byte_value_pio_wen = pio_wen & (pio_addr == 20'ha0010); |
| 731 | assign class5_hdr_byte_value_pio_wen = pio_wen & (pio_addr == 20'ha0018); |
| 732 | assign class6_hdr_byte_value_pio_wen = pio_wen & (pio_addr == 20'ha0020); |
| 733 | assign class7_hdr_byte_value_pio_wen = pio_wen & (pio_addr == 20'ha0028); |
| 734 | |
| 735 | assign class_action_reg4_pio_wen = pio_wen & (pio_addr == 20'ha0030); |
| 736 | assign class_action_reg5_pio_wen = pio_wen & (pio_addr == 20'ha0038); |
| 737 | assign class_action_reg6_pio_wen = pio_wen & (pio_addr == 20'ha0040); |
| 738 | assign class_action_reg7_pio_wen = pio_wen & (pio_addr == 20'ha0048); |
| 739 | assign class_action_reg8_pio_wen = pio_wen & (pio_addr == 20'ha0050); |
| 740 | assign class_action_reg9_pio_wen = pio_wen & (pio_addr == 20'ha0058); |
| 741 | assign class_action_reg10_pio_wen = pio_wen & (pio_addr == 20'ha0060); |
| 742 | assign class_action_reg11_pio_wen = pio_wen & (pio_addr == 20'ha0068); |
| 743 | assign class_action_reg12_pio_wen = pio_wen & (pio_addr == 20'ha0070); |
| 744 | assign class_action_reg13_pio_wen = pio_wen & (pio_addr == 20'ha0078); |
| 745 | assign class_action_reg14_pio_wen = pio_wen & (pio_addr == 20'ha0080); |
| 746 | assign class_action_reg15_pio_wen = pio_wen & (pio_addr == 20'ha0088); |
| 747 | |
| 748 | assign f_key_class_action_reg4_pio_wen = pio_wen & (pio_addr == 20'hc0000); |
| 749 | assign f_key_class_action_reg5_pio_wen = pio_wen & (pio_addr == 20'hc0008); |
| 750 | assign f_key_class_action_reg6_pio_wen = pio_wen & (pio_addr == 20'hc0010); |
| 751 | assign f_key_class_action_reg7_pio_wen = pio_wen & (pio_addr == 20'hc0018); |
| 752 | assign f_key_class_action_reg8_pio_wen = pio_wen & (pio_addr == 20'hc0020); |
| 753 | assign f_key_class_action_reg9_pio_wen = pio_wen & (pio_addr == 20'hc0028); |
| 754 | assign f_key_class_action_reg10_pio_wen = pio_wen & (pio_addr == 20'hc0030); |
| 755 | assign f_key_class_action_reg11_pio_wen = pio_wen & (pio_addr == 20'hc0038); |
| 756 | assign f_key_class_action_reg12_pio_wen = pio_wen & (pio_addr == 20'hc0040); |
| 757 | assign f_key_class_action_reg13_pio_wen = pio_wen & (pio_addr == 20'hc0048); |
| 758 | assign f_key_class_action_reg14_pio_wen = pio_wen & (pio_addr == 20'hc0050); |
| 759 | assign f_key_class_action_reg15_pio_wen = pio_wen & (pio_addr == 20'hc0058); |
| 760 | |
| 761 | assign h1_init_value_reg_pio_wen = pio_wen & (pio_addr == 20'hc0060); |
| 762 | assign h2_init_value_reg_pio_wen = pio_wen & (pio_addr == 20'hc0068); |
| 763 | |
| 764 | assign flow_part_sel_reg0_pio_wen = pio_wen & (pio_addr == 20'hc0070); |
| 765 | assign flow_part_sel_reg1_pio_wen = pio_wen & (pio_addr == 20'hc0078); |
| 766 | assign flow_part_sel_reg2_pio_wen = pio_wen & (pio_addr == 20'hc0080); |
| 767 | assign flow_part_sel_reg3_pio_wen = pio_wen & (pio_addr == 20'hc0088); |
| 768 | assign flow_part_sel_reg4_pio_wen = pio_wen & (pio_addr == 20'hc0090); |
| 769 | assign flow_part_sel_reg5_pio_wen = pio_wen & (pio_addr == 20'hc0098); |
| 770 | assign flow_part_sel_reg6_pio_wen = pio_wen & (pio_addr == 20'hc00a0); |
| 771 | assign flow_part_sel_reg7_pio_wen = pio_wen & (pio_addr == 20'hc00a8); |
| 772 | |
| 773 | assign hash_tbl_addr_reg0_pio_wen = pio_wen & (pio_addr == 20'h00000); |
| 774 | assign hash_tbl_addr_reg1_pio_wen = pio_wen & (pio_addr == 20'h02000); |
| 775 | assign hash_tbl_addr_reg2_pio_wen = pio_wen & (pio_addr == 20'h04000); |
| 776 | assign hash_tbl_addr_reg3_pio_wen = pio_wen & (pio_addr == 20'h06000); |
| 777 | assign hash_tbl_addr_reg4_pio_wen = pio_wen & (pio_addr == 20'h08000); |
| 778 | assign hash_tbl_addr_reg5_pio_wen = pio_wen & (pio_addr == 20'h0a000); |
| 779 | assign hash_tbl_addr_reg6_pio_wen = pio_wen & (pio_addr == 20'h0c000); |
| 780 | assign hash_tbl_addr_reg7_pio_wen = pio_wen & (pio_addr == 20'h0e000); |
| 781 | |
| 782 | assign hash_tbl_addr_inc_wen0 = (pio_addr[15:13] == 3'd0) & hash_tbl_addr_reg0_dout[23] & cpu_fc_req_done_p; |
| 783 | assign hash_tbl_addr_inc_wen1 = (pio_addr[15:13] == 3'd1) & hash_tbl_addr_reg1_dout[23] & cpu_fc_req_done_p; |
| 784 | assign hash_tbl_addr_inc_wen2 = (pio_addr[15:13] == 3'd2) & hash_tbl_addr_reg2_dout[23] & cpu_fc_req_done_p; |
| 785 | assign hash_tbl_addr_inc_wen3 = (pio_addr[15:13] == 3'd3) & hash_tbl_addr_reg3_dout[23] & cpu_fc_req_done_p; |
| 786 | assign hash_tbl_addr_inc_wen4 = (pio_addr[15:13] == 3'd4) & hash_tbl_addr_reg4_dout[23] & cpu_fc_req_done_p; |
| 787 | assign hash_tbl_addr_inc_wen5 = (pio_addr[15:13] == 3'd5) & hash_tbl_addr_reg5_dout[23] & cpu_fc_req_done_p; |
| 788 | assign hash_tbl_addr_inc_wen6 = (pio_addr[15:13] == 3'd6) & hash_tbl_addr_reg6_dout[23] & cpu_fc_req_done_p; |
| 789 | assign hash_tbl_addr_inc_wen7 = (pio_addr[15:13] == 3'd7) & hash_tbl_addr_reg7_dout[23] & cpu_fc_req_done_p; |
| 790 | |
| 791 | assign hash_tbl_addr_reg0_wen = hash_tbl_addr_reg0_pio_wen | hash_tbl_addr_inc_wen0; |
| 792 | assign hash_tbl_addr_reg1_wen = hash_tbl_addr_reg1_pio_wen | hash_tbl_addr_inc_wen1; |
| 793 | assign hash_tbl_addr_reg2_wen = hash_tbl_addr_reg2_pio_wen | hash_tbl_addr_inc_wen2; |
| 794 | assign hash_tbl_addr_reg3_wen = hash_tbl_addr_reg3_pio_wen | hash_tbl_addr_inc_wen3; |
| 795 | assign hash_tbl_addr_reg4_wen = hash_tbl_addr_reg4_pio_wen | hash_tbl_addr_inc_wen4; |
| 796 | assign hash_tbl_addr_reg5_wen = hash_tbl_addr_reg5_pio_wen | hash_tbl_addr_inc_wen5; |
| 797 | assign hash_tbl_addr_reg6_wen = hash_tbl_addr_reg6_pio_wen | hash_tbl_addr_inc_wen6; |
| 798 | assign hash_tbl_addr_reg7_wen = hash_tbl_addr_reg7_pio_wen | hash_tbl_addr_inc_wen7; |
| 799 | |
| 800 | assign cpu_req_part0_sel = (pio_addr[15:13] == 3'd0); |
| 801 | assign cpu_req_part1_sel = (pio_addr[15:13] == 3'd1); |
| 802 | assign cpu_req_part2_sel = (pio_addr[15:13] == 3'd2); |
| 803 | assign cpu_req_part3_sel = (pio_addr[15:13] == 3'd3); |
| 804 | assign cpu_req_part4_sel = (pio_addr[15:13] == 3'd4); |
| 805 | assign cpu_req_part5_sel = (pio_addr[15:13] == 3'd5); |
| 806 | assign cpu_req_part6_sel = (pio_addr[15:13] == 3'd6); |
| 807 | assign cpu_req_part7_sel = (pio_addr[15:13] == 3'd7); |
| 808 | |
| 809 | |
| 810 | assign curr_hash_tbl_addr = {23{cpu_req_part0_sel}} & hash_tbl_addr_reg0_dout[22:0] | |
| 811 | {23{cpu_req_part1_sel}} & hash_tbl_addr_reg1_dout[22:0] | |
| 812 | {23{cpu_req_part2_sel}} & hash_tbl_addr_reg2_dout[22:0] | |
| 813 | {23{cpu_req_part3_sel}} & hash_tbl_addr_reg3_dout[22:0] | |
| 814 | {23{cpu_req_part4_sel}} & hash_tbl_addr_reg4_dout[22:0] | |
| 815 | {23{cpu_req_part5_sel}} & hash_tbl_addr_reg5_dout[22:0] | |
| 816 | {23{cpu_req_part6_sel}} & hash_tbl_addr_reg6_dout[22:0] | |
| 817 | {23{cpu_req_part7_sel}} & hash_tbl_addr_reg7_dout[22:0]; |
| 818 | |
| 819 | assign next_hash_tbl_addr = curr_hash_tbl_addr[22:0] + 23'd1; |
| 820 | |
| 821 | dffr #(23) next_hash_tbl_addr_reg (cclk, reset_s, next_hash_tbl_addr, next_hash_tbl_addr_r); |
| 822 | |
| 823 | assign hash_tbl_addr_reg0_mux = hash_tbl_addr_inc_wen0 ? {hash_tbl_addr_reg0_dout[23], next_hash_tbl_addr_r[22:0]} : pio_wr_data[23:0]; |
| 824 | assign hash_tbl_addr_reg1_mux = hash_tbl_addr_inc_wen1 ? {hash_tbl_addr_reg1_dout[23], next_hash_tbl_addr_r[22:0]} : pio_wr_data[23:0]; |
| 825 | assign hash_tbl_addr_reg2_mux = hash_tbl_addr_inc_wen2 ? {hash_tbl_addr_reg2_dout[23], next_hash_tbl_addr_r[22:0]} : pio_wr_data[23:0]; |
| 826 | assign hash_tbl_addr_reg3_mux = hash_tbl_addr_inc_wen3 ? {hash_tbl_addr_reg3_dout[23], next_hash_tbl_addr_r[22:0]} : pio_wr_data[23:0]; |
| 827 | assign hash_tbl_addr_reg4_mux = hash_tbl_addr_inc_wen4 ? {hash_tbl_addr_reg4_dout[23], next_hash_tbl_addr_r[22:0]} : pio_wr_data[23:0]; |
| 828 | assign hash_tbl_addr_reg5_mux = hash_tbl_addr_inc_wen5 ? {hash_tbl_addr_reg5_dout[23], next_hash_tbl_addr_r[22:0]} : pio_wr_data[23:0]; |
| 829 | assign hash_tbl_addr_reg6_mux = hash_tbl_addr_inc_wen6 ? {hash_tbl_addr_reg6_dout[23], next_hash_tbl_addr_r[22:0]} : pio_wr_data[23:0]; |
| 830 | assign hash_tbl_addr_reg7_mux = hash_tbl_addr_inc_wen7 ? {hash_tbl_addr_reg7_dout[23], next_hash_tbl_addr_r[22:0]} : pio_wr_data[23:0]; |
| 831 | |
| 832 | assign hash_tbl_data_reg0_pio_wen = pio_wen & (pio_addr == 20'h00008); |
| 833 | assign hash_tbl_data_reg1_pio_wen = pio_wen & (pio_addr == 20'h02008); |
| 834 | assign hash_tbl_data_reg2_pio_wen = pio_wen & (pio_addr == 20'h04008); |
| 835 | assign hash_tbl_data_reg3_pio_wen = pio_wen & (pio_addr == 20'h06008); |
| 836 | assign hash_tbl_data_reg4_pio_wen = pio_wen & (pio_addr == 20'h08008); |
| 837 | assign hash_tbl_data_reg5_pio_wen = pio_wen & (pio_addr == 20'h0a008); |
| 838 | assign hash_tbl_data_reg6_pio_wen = pio_wen & (pio_addr == 20'h0c008); |
| 839 | assign hash_tbl_data_reg7_pio_wen = pio_wen & (pio_addr == 20'h0e008); |
| 840 | |
| 841 | assign hash_tbl_data_reg0_h_pio_wen = pio_wen & ((pio_addr == 20'h00008) & !pio_32b_mode | (pio_addr == 20'h0000c) & pio_32b_mode); |
| 842 | assign hash_tbl_data_reg1_h_pio_wen = pio_wen & ((pio_addr == 20'h02008) & !pio_32b_mode | (pio_addr == 20'h0200c) & pio_32b_mode); |
| 843 | assign hash_tbl_data_reg2_h_pio_wen = pio_wen & ((pio_addr == 20'h04008) & !pio_32b_mode | (pio_addr == 20'h0400c) & pio_32b_mode); |
| 844 | assign hash_tbl_data_reg3_h_pio_wen = pio_wen & ((pio_addr == 20'h06008) & !pio_32b_mode | (pio_addr == 20'h0600c) & pio_32b_mode); |
| 845 | assign hash_tbl_data_reg4_h_pio_wen = pio_wen & ((pio_addr == 20'h08008) & !pio_32b_mode | (pio_addr == 20'h0800c) & pio_32b_mode); |
| 846 | assign hash_tbl_data_reg5_h_pio_wen = pio_wen & ((pio_addr == 20'h0a008) & !pio_32b_mode | (pio_addr == 20'h0a00c) & pio_32b_mode); |
| 847 | assign hash_tbl_data_reg6_h_pio_wen = pio_wen & ((pio_addr == 20'h0c008) & !pio_32b_mode | (pio_addr == 20'h0c00c) & pio_32b_mode); |
| 848 | assign hash_tbl_data_reg7_h_pio_wen = pio_wen & ((pio_addr == 20'h0e008) & !pio_32b_mode | (pio_addr == 20'h0e00c) & pio_32b_mode); |
| 849 | |
| 850 | assign hash_tbl_ecc_log_reg0_pio_wen = pio_wen & (pio_addr == 20'h00010); |
| 851 | assign hash_tbl_ecc_log_reg1_pio_wen = pio_wen & (pio_addr == 20'h02010); |
| 852 | assign hash_tbl_ecc_log_reg2_pio_wen = pio_wen & (pio_addr == 20'h04010); |
| 853 | assign hash_tbl_ecc_log_reg3_pio_wen = pio_wen & (pio_addr == 20'h06010); |
| 854 | assign hash_tbl_ecc_log_reg4_pio_wen = pio_wen & (pio_addr == 20'h08010); |
| 855 | assign hash_tbl_ecc_log_reg5_pio_wen = pio_wen & (pio_addr == 20'h0a010); |
| 856 | assign hash_tbl_ecc_log_reg6_pio_wen = pio_wen & (pio_addr == 20'h0c010); |
| 857 | assign hash_tbl_ecc_log_reg7_pio_wen = pio_wen & (pio_addr == 20'h0e010); |
| 858 | |
| 859 | assign hash_tbl_data_reg0_wen = hash_tbl_data_reg0_pio_wen | cpu_req_part0_sel & cpu_fc_req_done_p & pio_rd; |
| 860 | assign hash_tbl_data_reg1_wen = hash_tbl_data_reg1_pio_wen | cpu_req_part1_sel & cpu_fc_req_done_p & pio_rd; |
| 861 | assign hash_tbl_data_reg2_wen = hash_tbl_data_reg2_pio_wen | cpu_req_part2_sel & cpu_fc_req_done_p & pio_rd; |
| 862 | assign hash_tbl_data_reg3_wen = hash_tbl_data_reg3_pio_wen | cpu_req_part3_sel & cpu_fc_req_done_p & pio_rd; |
| 863 | assign hash_tbl_data_reg4_wen = hash_tbl_data_reg4_pio_wen | cpu_req_part4_sel & cpu_fc_req_done_p & pio_rd; |
| 864 | assign hash_tbl_data_reg5_wen = hash_tbl_data_reg5_pio_wen | cpu_req_part5_sel & cpu_fc_req_done_p & pio_rd; |
| 865 | assign hash_tbl_data_reg6_wen = hash_tbl_data_reg6_pio_wen | cpu_req_part6_sel & cpu_fc_req_done_p & pio_rd; |
| 866 | assign hash_tbl_data_reg7_wen = hash_tbl_data_reg7_pio_wen | cpu_req_part7_sel & cpu_fc_req_done_p & pio_rd; |
| 867 | |
| 868 | assign hash_tbl_data_reg0_h_wen = hash_tbl_data_reg0_h_pio_wen | cpu_req_part0_sel & cpu_fc_req_done_p & pio_rd; |
| 869 | assign hash_tbl_data_reg1_h_wen = hash_tbl_data_reg1_h_pio_wen | cpu_req_part1_sel & cpu_fc_req_done_p & pio_rd; |
| 870 | assign hash_tbl_data_reg2_h_wen = hash_tbl_data_reg2_h_pio_wen | cpu_req_part2_sel & cpu_fc_req_done_p & pio_rd; |
| 871 | assign hash_tbl_data_reg3_h_wen = hash_tbl_data_reg3_h_pio_wen | cpu_req_part3_sel & cpu_fc_req_done_p & pio_rd; |
| 872 | assign hash_tbl_data_reg4_h_wen = hash_tbl_data_reg4_h_pio_wen | cpu_req_part4_sel & cpu_fc_req_done_p & pio_rd; |
| 873 | assign hash_tbl_data_reg5_h_wen = hash_tbl_data_reg5_h_pio_wen | cpu_req_part5_sel & cpu_fc_req_done_p & pio_rd; |
| 874 | assign hash_tbl_data_reg6_h_wen = hash_tbl_data_reg6_h_pio_wen | cpu_req_part6_sel & cpu_fc_req_done_p & pio_rd; |
| 875 | assign hash_tbl_data_reg7_h_wen = hash_tbl_data_reg7_h_pio_wen | cpu_req_part7_sel & cpu_fc_req_done_p & pio_rd; |
| 876 | |
| 877 | assign hash_tbl_ecc_log_reg0_wen = hash_tbl_ecc_log_reg0_pio_wen | cpu_req_part0_sel & cpu_fc_req_done_p & pio_rd; |
| 878 | assign hash_tbl_ecc_log_reg1_wen = hash_tbl_ecc_log_reg1_pio_wen | cpu_req_part1_sel & cpu_fc_req_done_p & pio_rd; |
| 879 | assign hash_tbl_ecc_log_reg2_wen = hash_tbl_ecc_log_reg2_pio_wen | cpu_req_part2_sel & cpu_fc_req_done_p & pio_rd; |
| 880 | assign hash_tbl_ecc_log_reg3_wen = hash_tbl_ecc_log_reg3_pio_wen | cpu_req_part3_sel & cpu_fc_req_done_p & pio_rd; |
| 881 | assign hash_tbl_ecc_log_reg4_wen = hash_tbl_ecc_log_reg4_pio_wen | cpu_req_part4_sel & cpu_fc_req_done_p & pio_rd; |
| 882 | assign hash_tbl_ecc_log_reg5_wen = hash_tbl_ecc_log_reg5_pio_wen | cpu_req_part5_sel & cpu_fc_req_done_p & pio_rd; |
| 883 | assign hash_tbl_ecc_log_reg6_wen = hash_tbl_ecc_log_reg6_pio_wen | cpu_req_part6_sel & cpu_fc_req_done_p & pio_rd; |
| 884 | assign hash_tbl_ecc_log_reg7_wen = hash_tbl_ecc_log_reg7_pio_wen | cpu_req_part7_sel & cpu_fc_req_done_p & pio_rd; |
| 885 | |
| 886 | assign hash_tbl_data_reg_mux = cpu_fc_req_done_p ? fc_rd_data_reg_dout[31:0] : pio_wr_data[31:0]; |
| 887 | assign hash_tbl_data_reg_h_mux = cpu_fc_req_done_p ? fc_rd_data_reg_dout[63:32] : pio_wr_data[63:32]; |
| 888 | assign hash_tbl_ecc_log_reg_mux = cpu_fc_req_done_p ? {fc_rd_ecc_err, curr_hash_tbl_addr[22:0], fc_rd_data_reg_dout[71:64]} : |
| 889 | pio_wr_data[31:0]; |
| 890 | |
| 891 | assign cam_ecc_log_reg_pio_wen = pio_wen & (pio_addr == 20'ha00d8); |
| 892 | assign cam_ecc_log_reg_wen = cam_ecc_log_reg_pio_wen | ecc_parity_status[25]; |
| 893 | assign cam_ecc_log_reg_din = cam_ecc_log_reg_dout[26] ? {cam_ecc_log_reg_dout[26:25], 1'b1, cam_ecc_log_reg_dout[23:0]} : |
| 894 | {ecc_parity_status[25:24], 1'b0, ecc_parity_status[23:0]}; |
| 895 | assign cam_ecc_log_reg_mux = ecc_parity_status[25] ? cam_ecc_log_reg_din[26:0] : {pio_wr_data[31:29], pio_wr_data[23:0]}; |
| 896 | |
| 897 | assign hash_lookup_log_reg0_pio_wen = pio_wen & (pio_addr == 20'ha00e0); |
| 898 | assign hash_lookup_log_reg1_pio_wen = pio_wen & (pio_addr == 20'ha00e8); |
| 899 | |
| 900 | assign hash_lookup_log_reg0_en = fflp_zcp_wr_p & fc_err_status[33]; |
| 901 | assign hash_lookup_log_reg1_en = fflp_zcp_wr_p & fc_err_status[33] & !hash_lookup_log_reg0_dout[3]; |
| 902 | assign hash_lookup_log_reg0_wen = hash_lookup_log_reg0_pio_wen | hash_lookup_log_reg0_en; |
| 903 | assign hash_lookup_log_reg1_wen = hash_lookup_log_reg1_pio_wen | hash_lookup_log_reg1_en; |
| 904 | |
| 905 | assign hash_lookup_log_reg0_din_bit2 = hash_lookup_log_reg0_dout[3] ? 1'b1 : 1'b0; |
| 906 | assign hash_lookup_log_reg0_din_bit1 = hash_lookup_log_reg0_dout[3] ? hash_lookup_log_reg0_dout[1] : fc_err_status[32]; |
| 907 | assign hash_lookup_log_reg0_din_bit0 = hash_lookup_log_reg0_dout[3] ? hash_lookup_log_reg0_dout[0] : fc_err_status[31]; |
| 908 | assign hash_lookup_log_reg0_din = {fc_err_status[33], hash_lookup_log_reg0_din_bit2, hash_lookup_log_reg0_din_bit1, |
| 909 | hash_lookup_log_reg0_din_bit0}; |
| 910 | assign hash_lookup_log_reg0_mux = hash_lookup_log_reg0_en ? hash_lookup_log_reg0_din[3:0] : pio_wr_data[3:0]; |
| 911 | |
| 912 | assign hash_lookup_log_reg1_mux = hash_lookup_log_reg1_en ? fc_err_status[30:0] : pio_wr_data[30:0]; |
| 913 | |
| 914 | |
| 915 | dffre #(12) hdr_ctrl_bit_mask_reg (cclk, reset_s, hdr_ctrl_bit_mask_reg_pio_wen, pio_wr_data[11:0], hdr_ctrl_bit_mask_reg_dout[11:0]); |
| 916 | dffre #(27) fflp_config_reg (cclk, reset_s, fflp_config_reg_pio_wen, pio_wr_data[26:0], fflp_config_reg_dout[26:0]); |
| 917 | dffre #(32) fcram_refresh_timer_reg (cclk, reset_s, fcram_refresh_timer_reg_pio_wen, pio_wr_data[31:0], fcram_refresh_timer_reg_dout); |
| 918 | dffre #(8) fio_cfg_addr_reg (cclk, reset_s, fio_cfg_addr_reg_pio_wen, pio_wr_data[7:0], fio_cfg_addr_reg_dout); |
| 919 | |
| 920 | assign snap_en = fflp_config_reg_dout[0]; |
| 921 | assign fflp_init_done = fflp_config_reg_dout[1]; |
| 922 | assign disable_chksum = fflp_config_reg_dout[2]; |
| 923 | assign fcram_qs_mode = fflp_config_reg_dout[3]; // set 1 to free running QS mode |
| 924 | assign fcram_driver_imp_ctrl = fflp_config_reg_dout[7:4]; // 4'b0 for normal output drive |
| 925 | assign fcram_lookup_ratio_i = fflp_config_reg_dout[11:8]; |
| 926 | assign cam_srch_ratio_i = fflp_config_reg_dout[15:12]; |
| 927 | assign cam_srch_latency_i = fflp_config_reg_dout[19:16]; |
| 928 | assign pio_fio_latency = fflp_config_reg_dout[21:20]; |
| 929 | assign pio_fio_cfg_reset = fflp_config_reg_dout[22]; |
| 930 | assign pio_debug_data_sel = fflp_config_reg_dout[25:23]; |
| 931 | assign pio_disable_cam = fflp_config_reg_dout[26]; |
| 932 | |
| 933 | assign fcram_lookup_ratio = (fcram_lookup_ratio_i == 4'b0) ? 4'd1 : fcram_lookup_ratio_i; |
| 934 | assign cam_srch_ratio = (cam_srch_ratio_i == 4'b0) ? 4'd1 : cam_srch_ratio_i; |
| 935 | assign cam_srch_latency = (cam_srch_latency_i[3:2] == 2'b0) ? 4'd3 : cam_srch_latency_i; |
| 936 | |
| 937 | |
| 938 | dffre #(17) class2_hdr_byte_value_reg (cclk, reset_s, class2_hdr_byte_value_pio_wen, pio_wr_data[16:0], class2_hdr_byte_value[16:0]); |
| 939 | dffre #(17) class3_hdr_byte_value_reg (cclk, reset_s, class3_hdr_byte_value_pio_wen, pio_wr_data[16:0], class3_hdr_byte_value[16:0]); |
| 940 | dffre #(26) class4_hdr_byte_value_reg (cclk, reset_s, class4_hdr_byte_value_pio_wen, pio_wr_data[25:0], class4_hdr_byte_value[25:0]); |
| 941 | dffre #(26) class5_hdr_byte_value_reg (cclk, reset_s, class5_hdr_byte_value_pio_wen, pio_wr_data[25:0], class5_hdr_byte_value[25:0]); |
| 942 | dffre #(26) class6_hdr_byte_value_reg (cclk, reset_s, class6_hdr_byte_value_pio_wen, pio_wr_data[25:0], class6_hdr_byte_value[25:0]); |
| 943 | dffre #(26) class7_hdr_byte_value_reg (cclk, reset_s, class7_hdr_byte_value_pio_wen, pio_wr_data[25:0], class7_hdr_byte_value[25:0]); |
| 944 | |
| 945 | //def class action register per l3 class |
| 946 | dffre #(3) class_action_reg4 (cclk, reset_s, class_action_reg4_pio_wen, {pio_wr_data[3:2], pio_wr_data[0]}, class_action_reg4_dout[2:0]); |
| 947 | dffre #(3) class_action_reg5 (cclk, reset_s, class_action_reg5_pio_wen, {pio_wr_data[3:2], pio_wr_data[0]}, class_action_reg5_dout[2:0]); |
| 948 | dffre #(3) class_action_reg6 (cclk, reset_s, class_action_reg6_pio_wen, {pio_wr_data[3:2], pio_wr_data[0]}, class_action_reg6_dout[2:0]); |
| 949 | dffre #(3) class_action_reg7 (cclk, reset_s, class_action_reg7_pio_wen, {pio_wr_data[3:2], pio_wr_data[0]}, class_action_reg7_dout[2:0]); |
| 950 | dffre #(3) class_action_reg8 (cclk, reset_s, class_action_reg8_pio_wen, {pio_wr_data[3:2], pio_wr_data[0]}, class_action_reg8_dout[2:0]); |
| 951 | dffre #(3) class_action_reg9 (cclk, reset_s, class_action_reg9_pio_wen, {pio_wr_data[3:2], pio_wr_data[0]}, class_action_reg9_dout[2:0]); |
| 952 | dffre #(3) class_action_reg10 (cclk, reset_s, class_action_reg10_pio_wen, {pio_wr_data[3:2], pio_wr_data[0]}, class_action_reg10_dout[2:0]); |
| 953 | dffre #(3) class_action_reg11 (cclk, reset_s, class_action_reg11_pio_wen, {pio_wr_data[3:2], pio_wr_data[0]}, class_action_reg11_dout[2:0]); |
| 954 | dffre #(3) class_action_reg12 (cclk, reset_s, class_action_reg12_pio_wen, {pio_wr_data[3:2], pio_wr_data[0]}, class_action_reg12_dout[2:0]); |
| 955 | dffre #(3) class_action_reg13 (cclk, reset_s, class_action_reg13_pio_wen, {pio_wr_data[3:2], pio_wr_data[0]}, class_action_reg13_dout[2:0]); |
| 956 | dffre #(3) class_action_reg14 (cclk, reset_s, class_action_reg14_pio_wen, {pio_wr_data[3:2], pio_wr_data[0]}, class_action_reg14_dout[2:0]); |
| 957 | dffre #(3) class_action_reg15 (cclk, reset_s, class_action_reg15_pio_wen, {pio_wr_data[3:2], pio_wr_data[0]}, class_action_reg15_dout[2:0]); |
| 958 | |
| 959 | dffre #(10) f_key_class_action_reg4 (cclk, reset_s, f_key_class_action_reg4_pio_wen, pio_wr_data[9:0], f_key_class_action_reg4_dout[9:0]); |
| 960 | dffre #(10) f_key_class_action_reg5 (cclk, reset_s, f_key_class_action_reg5_pio_wen, pio_wr_data[9:0], f_key_class_action_reg5_dout[9:0]); |
| 961 | dffre #(10) f_key_class_action_reg6 (cclk, reset_s, f_key_class_action_reg6_pio_wen, pio_wr_data[9:0], f_key_class_action_reg6_dout[9:0]); |
| 962 | dffre #(10) f_key_class_action_reg7 (cclk, reset_s, f_key_class_action_reg7_pio_wen, pio_wr_data[9:0], f_key_class_action_reg7_dout[9:0]); |
| 963 | dffre #(10) f_key_class_action_reg8 (cclk, reset_s, f_key_class_action_reg8_pio_wen, pio_wr_data[9:0], f_key_class_action_reg8_dout[9:0]); |
| 964 | dffre #(10) f_key_class_action_reg9 (cclk, reset_s, f_key_class_action_reg9_pio_wen, pio_wr_data[9:0], f_key_class_action_reg9_dout[9:0]); |
| 965 | dffre #(10) f_key_class_action_reg10 (cclk, reset_s, f_key_class_action_reg10_pio_wen, pio_wr_data[9:0], f_key_class_action_reg10_dout[9:0]); |
| 966 | dffre #(10) f_key_class_action_reg11 (cclk, reset_s, f_key_class_action_reg11_pio_wen, pio_wr_data[9:0], f_key_class_action_reg11_dout[9:0]); |
| 967 | dffre #(10) f_key_class_action_reg12 (cclk, reset_s, f_key_class_action_reg12_pio_wen, pio_wr_data[9:0], f_key_class_action_reg12_dout[9:0]); |
| 968 | dffre #(10) f_key_class_action_reg13 (cclk, reset_s, f_key_class_action_reg13_pio_wen, pio_wr_data[9:0], f_key_class_action_reg13_dout[9:0]); |
| 969 | dffre #(10) f_key_class_action_reg14 (cclk, reset_s, f_key_class_action_reg14_pio_wen, pio_wr_data[9:0], f_key_class_action_reg14_dout[9:0]); |
| 970 | dffre #(10) f_key_class_action_reg15 (cclk, reset_s, f_key_class_action_reg15_pio_wen, pio_wr_data[9:0], f_key_class_action_reg15_dout[9:0]); |
| 971 | |
| 972 | dffre #(32) h1_poly_init_value_reg (cclk, reset_s, h1_init_value_reg_pio_wen, pio_wr_data[31:0], h1_init_value_reg_dout); |
| 973 | dffre #(16) h2_poly_init_value_reg (cclk, reset_s, h2_init_value_reg_pio_wen, pio_wr_data[15:0], h2_init_value_reg_dout); |
| 974 | |
| 975 | wire[10:0] flow_part_pio_wr_data = {pio_wr_data[16], pio_wr_data[12:8], pio_wr_data[4:0]}; |
| 976 | |
| 977 | dffre #(11) flow_part_sel_reg0 (cclk, reset_s, flow_part_sel_reg0_pio_wen, flow_part_pio_wr_data[10:0], flow_part_sel_reg0_dout); |
| 978 | dffre #(11) flow_part_sel_reg1 (cclk, reset_s, flow_part_sel_reg1_pio_wen, flow_part_pio_wr_data[10:0], flow_part_sel_reg1_dout); |
| 979 | dffre #(11) flow_part_sel_reg2 (cclk, reset_s, flow_part_sel_reg2_pio_wen, flow_part_pio_wr_data[10:0], flow_part_sel_reg2_dout); |
| 980 | dffre #(11) flow_part_sel_reg3 (cclk, reset_s, flow_part_sel_reg3_pio_wen, flow_part_pio_wr_data[10:0], flow_part_sel_reg3_dout); |
| 981 | dffre #(11) flow_part_sel_reg4 (cclk, reset_s, flow_part_sel_reg4_pio_wen, flow_part_pio_wr_data[10:0], flow_part_sel_reg4_dout); |
| 982 | dffre #(11) flow_part_sel_reg5 (cclk, reset_s, flow_part_sel_reg5_pio_wen, flow_part_pio_wr_data[10:0], flow_part_sel_reg5_dout); |
| 983 | dffre #(11) flow_part_sel_reg6 (cclk, reset_s, flow_part_sel_reg6_pio_wen, flow_part_pio_wr_data[10:0], flow_part_sel_reg6_dout); |
| 984 | dffre #(11) flow_part_sel_reg7 (cclk, reset_s, flow_part_sel_reg7_pio_wen, flow_part_pio_wr_data[10:0], flow_part_sel_reg7_dout); |
| 985 | |
| 986 | dffre #(24) hash_tbl_addr_reg0 (cclk, reset_s, hash_tbl_addr_reg0_wen, hash_tbl_addr_reg0_mux[23:0], hash_tbl_addr_reg0_dout); |
| 987 | dffre #(24) hash_tbl_addr_reg1 (cclk, reset_s, hash_tbl_addr_reg1_wen, hash_tbl_addr_reg1_mux[23:0], hash_tbl_addr_reg1_dout); |
| 988 | dffre #(24) hash_tbl_addr_reg2 (cclk, reset_s, hash_tbl_addr_reg2_wen, hash_tbl_addr_reg2_mux[23:0], hash_tbl_addr_reg2_dout); |
| 989 | dffre #(24) hash_tbl_addr_reg3 (cclk, reset_s, hash_tbl_addr_reg3_wen, hash_tbl_addr_reg3_mux[23:0], hash_tbl_addr_reg3_dout); |
| 990 | dffre #(24) hash_tbl_addr_reg4 (cclk, reset_s, hash_tbl_addr_reg4_wen, hash_tbl_addr_reg4_mux[23:0], hash_tbl_addr_reg4_dout); |
| 991 | dffre #(24) hash_tbl_addr_reg5 (cclk, reset_s, hash_tbl_addr_reg5_wen, hash_tbl_addr_reg5_mux[23:0], hash_tbl_addr_reg5_dout); |
| 992 | dffre #(24) hash_tbl_addr_reg6 (cclk, reset_s, hash_tbl_addr_reg6_wen, hash_tbl_addr_reg6_mux[23:0], hash_tbl_addr_reg6_dout); |
| 993 | dffre #(24) hash_tbl_addr_reg7 (cclk, reset_s, hash_tbl_addr_reg7_wen, hash_tbl_addr_reg7_mux[23:0], hash_tbl_addr_reg7_dout); |
| 994 | |
| 995 | dffre #(32) hash_tbl_data_reg0_l (cclk, reset_s, hash_tbl_data_reg0_wen, hash_tbl_data_reg_mux[31:0], hash_tbl_data_reg0_dout[31:0]); |
| 996 | dffre #(32) hash_tbl_data_reg1_l (cclk, reset_s, hash_tbl_data_reg1_wen, hash_tbl_data_reg_mux[31:0], hash_tbl_data_reg1_dout[31:0]); |
| 997 | dffre #(32) hash_tbl_data_reg2_l (cclk, reset_s, hash_tbl_data_reg2_wen, hash_tbl_data_reg_mux[31:0], hash_tbl_data_reg2_dout[31:0]); |
| 998 | dffre #(32) hash_tbl_data_reg3_l (cclk, reset_s, hash_tbl_data_reg3_wen, hash_tbl_data_reg_mux[31:0], hash_tbl_data_reg3_dout[31:0]); |
| 999 | dffre #(32) hash_tbl_data_reg4_l (cclk, reset_s, hash_tbl_data_reg4_wen, hash_tbl_data_reg_mux[31:0], hash_tbl_data_reg4_dout[31:0]); |
| 1000 | dffre #(32) hash_tbl_data_reg5_l (cclk, reset_s, hash_tbl_data_reg5_wen, hash_tbl_data_reg_mux[31:0], hash_tbl_data_reg5_dout[31:0]); |
| 1001 | dffre #(32) hash_tbl_data_reg6_l (cclk, reset_s, hash_tbl_data_reg6_wen, hash_tbl_data_reg_mux[31:0], hash_tbl_data_reg6_dout[31:0]); |
| 1002 | dffre #(32) hash_tbl_data_reg7_l (cclk, reset_s, hash_tbl_data_reg7_wen, hash_tbl_data_reg_mux[31:0], hash_tbl_data_reg7_dout[31:0]); |
| 1003 | |
| 1004 | dffre #(32) hash_tbl_data_reg0_h (cclk, reset_s, hash_tbl_data_reg0_h_wen, hash_tbl_data_reg_h_mux[31:0], hash_tbl_data_reg0_dout[63:32]); |
| 1005 | dffre #(32) hash_tbl_data_reg1_h (cclk, reset_s, hash_tbl_data_reg1_h_wen, hash_tbl_data_reg_h_mux[31:0], hash_tbl_data_reg1_dout[63:32]); |
| 1006 | dffre #(32) hash_tbl_data_reg2_h (cclk, reset_s, hash_tbl_data_reg2_h_wen, hash_tbl_data_reg_h_mux[31:0], hash_tbl_data_reg2_dout[63:32]); |
| 1007 | dffre #(32) hash_tbl_data_reg3_h (cclk, reset_s, hash_tbl_data_reg3_h_wen, hash_tbl_data_reg_h_mux[31:0], hash_tbl_data_reg3_dout[63:32]); |
| 1008 | dffre #(32) hash_tbl_data_reg4_h (cclk, reset_s, hash_tbl_data_reg4_h_wen, hash_tbl_data_reg_h_mux[31:0], hash_tbl_data_reg4_dout[63:32]); |
| 1009 | dffre #(32) hash_tbl_data_reg5_h (cclk, reset_s, hash_tbl_data_reg5_h_wen, hash_tbl_data_reg_h_mux[31:0], hash_tbl_data_reg5_dout[63:32]); |
| 1010 | dffre #(32) hash_tbl_data_reg6_h (cclk, reset_s, hash_tbl_data_reg6_h_wen, hash_tbl_data_reg_h_mux[31:0], hash_tbl_data_reg6_dout[63:32]); |
| 1011 | dffre #(32) hash_tbl_data_reg7_h (cclk, reset_s, hash_tbl_data_reg7_h_wen, hash_tbl_data_reg_h_mux[31:0], hash_tbl_data_reg7_dout[63:32]); |
| 1012 | |
| 1013 | dffre #(32) hash_tbl_ecc_log_reg0 (cclk, reset_s, hash_tbl_ecc_log_reg0_wen, hash_tbl_ecc_log_reg_mux, hash_tbl_ecc_log_reg0_dout); |
| 1014 | dffre #(32) hash_tbl_ecc_log_reg1 (cclk, reset_s, hash_tbl_ecc_log_reg1_wen, hash_tbl_ecc_log_reg_mux, hash_tbl_ecc_log_reg1_dout); |
| 1015 | dffre #(32) hash_tbl_ecc_log_reg2 (cclk, reset_s, hash_tbl_ecc_log_reg2_wen, hash_tbl_ecc_log_reg_mux, hash_tbl_ecc_log_reg2_dout); |
| 1016 | dffre #(32) hash_tbl_ecc_log_reg3 (cclk, reset_s, hash_tbl_ecc_log_reg3_wen, hash_tbl_ecc_log_reg_mux, hash_tbl_ecc_log_reg3_dout); |
| 1017 | dffre #(32) hash_tbl_ecc_log_reg4 (cclk, reset_s, hash_tbl_ecc_log_reg4_wen, hash_tbl_ecc_log_reg_mux, hash_tbl_ecc_log_reg4_dout); |
| 1018 | dffre #(32) hash_tbl_ecc_log_reg5 (cclk, reset_s, hash_tbl_ecc_log_reg5_wen, hash_tbl_ecc_log_reg_mux, hash_tbl_ecc_log_reg5_dout); |
| 1019 | dffre #(32) hash_tbl_ecc_log_reg6 (cclk, reset_s, hash_tbl_ecc_log_reg6_wen, hash_tbl_ecc_log_reg_mux, hash_tbl_ecc_log_reg6_dout); |
| 1020 | dffre #(32) hash_tbl_ecc_log_reg7 (cclk, reset_s, hash_tbl_ecc_log_reg7_wen, hash_tbl_ecc_log_reg_mux, hash_tbl_ecc_log_reg7_dout); |
| 1021 | |
| 1022 | dffre #(27) cam_ecc_log_reg (cclk, reset_s, cam_ecc_log_reg_wen, cam_ecc_log_reg_mux, cam_ecc_log_reg_dout); |
| 1023 | dffre #(4) hash_lookup_log_reg0 (cclk, reset_s, hash_lookup_log_reg0_wen, hash_lookup_log_reg0_mux, hash_lookup_log_reg0_dout); |
| 1024 | dffre #(31) hash_lookup_log_reg1 (cclk, reset_s, hash_lookup_log_reg1_wen, hash_lookup_log_reg1_mux, hash_lookup_log_reg1_dout); |
| 1025 | |
| 1026 | dffre #(8) fcram_err_test_reg0 (cclk, reset_s, fcram_err_test_reg0_pio_wen, pio_wr_data[7:0], fcram_err_test_reg0_dout); |
| 1027 | dffre #(32) fcram_err_test_reg1 (cclk, reset_s, fcram_err_test_reg1_pio_wen, pio_wr_data[31:0], fcram_err_test_reg1_dout); |
| 1028 | dffre #(32) fcram_err_test_reg2 (cclk, reset_s, fcram_err_test_reg2_pio_wen, pio_wr_data[31:0], fcram_err_test_reg2_dout); |
| 1029 | |
| 1030 | dffre #(32) debug_tran_vector_reg (cclk, reset_s, debug_training_vector_pio_wen, pio_wr_data[31:0], debug_training_vector); |
| 1031 | |
| 1032 | /************************/ |
| 1033 | //CPU Vlan table access |
| 1034 | /************************/ |
| 1035 | assign cpu_vlan_rd = pio_rd & (pio_addr[16:15] == 2'b00) & (!pio_32b_mode | pio_32b_mode & !pio_addr[2]); |
| 1036 | assign cpu_vlan_wr = !pio_rd & (pio_addr[16:15] == 2'b00) & (!pio_32b_mode | pio_32b_mode & !pio_addr[2]); |
| 1037 | |
| 1038 | assign is_vlan_addr = (pio_addr[19:17] == 3'b100); |
| 1039 | assign cpu_vlan_addr = pio_addr[14:3]; |
| 1040 | assign vlan_tbl_wr_dout = {pio_wr_data[17], pio_wr_data[15:8], pio_wr_data[16], pio_wr_data[7:0]}; |
| 1041 | assign vlan_tbl_rd_data = {18{cpu_vlan_gnt_3}} & vlan_tbl_din_reg_dout[17:0]; |
| 1042 | |
| 1043 | assign cpu_vlan_req_en = pio_sel_pulse & is_vlan_addr | cpu_vlan_gnt_3; |
| 1044 | assign cpu_vlan_req_in = pio_sel_pulse & is_vlan_addr ? 1'b1 : 1'b0; |
| 1045 | |
| 1046 | dffre #(1) cpu_vlan_req_reg (cclk, reset_s, cpu_vlan_req_en, cpu_vlan_req_in, cpu_vlan_req); |
| 1047 | |
| 1048 | assign vlan_parity_err_log_tmp = vlan_parity_err_log_reg_dout[31] ? {2'b11, vlan_parity_err_log_reg_dout[29:0]} : |
| 1049 | {2'b10, vlan_tag_id[11:0], vlan_tbl_din_reg_dout[17:0]}; |
| 1050 | assign vlan_parity_err_log_mux = vlan_parity_err_log_en ? vlan_parity_err_log_tmp[31:0] : pio_wr_data[31:0]; |
| 1051 | |
| 1052 | assign vlan_parity_err_log_pio_wen = pio_wen & (pio_addr == 20'h88000); |
| 1053 | assign vlan_parity_err_log_wen = vlan_parity_err_log_pio_wen | vlan_parity_err_log_en; |
| 1054 | |
| 1055 | dffre #(32) vlan_parity_err_log_reg (cclk, reset_s, vlan_parity_err_log_wen, vlan_parity_err_log_mux, vlan_parity_err_log_reg_dout); |
| 1056 | |
| 1057 | /************************/ |
| 1058 | //CPU access FCRAM |
| 1059 | /************************/ |
| 1060 | assign fcram_err_test_reg_dout = {fcram_err_test_reg0_dout, fcram_err_test_reg1_dout, fcram_err_test_reg2_dout}; |
| 1061 | assign cpu_fc_req_done_p = cpu_fc_req_done_sync & !cpu_fc_req_done_sync_d; |
| 1062 | assign is_fcram_data_addr = (pio_addr[12:0] == 13'd8) & (pio_addr[19:16] == 4'b0) & !pio_32b_mode | |
| 1063 | (pio_addr[12:0] == 13'd12) & (pio_addr[19:16] == 4'b0) & pio_32b_mode; |
| 1064 | assign is_ext_fcram = ((pio_addr[15:13] == 3'd0) & flow_part_sel_reg0_dout[10] | |
| 1065 | (pio_addr[15:13] == 3'd1) & flow_part_sel_reg1_dout[10] | |
| 1066 | (pio_addr[15:13] == 3'd2) & flow_part_sel_reg2_dout[10] | |
| 1067 | (pio_addr[15:13] == 3'd3) & flow_part_sel_reg3_dout[10] | |
| 1068 | (pio_addr[15:13] == 3'd4) & flow_part_sel_reg4_dout[10] | |
| 1069 | (pio_addr[15:13] == 3'd5) & flow_part_sel_reg5_dout[10] | |
| 1070 | (pio_addr[15:13] == 3'd6) & flow_part_sel_reg6_dout[10] | |
| 1071 | (pio_addr[15:13] == 3'd7) & flow_part_sel_reg7_dout[10]); |
| 1072 | assign is_fcram_req = pio_sel_pulse & is_fcram_data_addr & is_ext_fcram; |
| 1073 | assign cpu_fcram_req_en = is_fcram_req | cpu_fc_req_done_p1; |
| 1074 | assign cpu_fcram_req_in = is_fcram_req ? 1'b1 : 1'b0; |
| 1075 | |
| 1076 | dffr #(1) cpu_fc_req_done_d_reg (cclk, reset_s, cpu_fc_req_done_sync, cpu_fc_req_done_sync_d); |
| 1077 | dffr #(1) cpu_fc_req_done_p1_reg (cclk, reset_s, cpu_fc_req_done_p, cpu_fc_req_done_p1); |
| 1078 | |
| 1079 | dffre #(1) cpu_fcram_req_reg (cclk, reset_s, cpu_fcram_req_en, cpu_fcram_req_in, cpu_fcram_req); |
| 1080 | |
| 1081 | |
| 1082 | /************************/ |
| 1083 | //CPU access FIO |
| 1084 | /************************/ |
| 1085 | assign cpu_fio_req_done_p = cpu_fio_req_done_sync & !cpu_fio_req_done_sync_d; |
| 1086 | assign is_fio_data_addr = (pio_addr == 20'ha0120); |
| 1087 | assign is_ext_fio = flow_part_sel_reg0_dout[10] | flow_part_sel_reg1_dout[10] | |
| 1088 | flow_part_sel_reg2_dout[10] | flow_part_sel_reg3_dout[10] | |
| 1089 | flow_part_sel_reg4_dout[10] | flow_part_sel_reg5_dout[10] | |
| 1090 | flow_part_sel_reg6_dout[10] | flow_part_sel_reg7_dout[10]; |
| 1091 | assign cpu_fio_req_en = pio_sel_pulse & is_fio_data_addr & is_ext_fio | cpu_fio_req_done_p; |
| 1092 | assign cpu_fio_req_in = pio_sel_pulse & is_fio_data_addr & is_ext_fio ? 1'b1 : 1'b0; |
| 1093 | |
| 1094 | dffr #(1) cpu_fio_req_done_d_reg (cclk, reset_s, cpu_fio_req_done_sync, cpu_fio_req_done_sync_d); |
| 1095 | dffre #(1) cpu_fio_req_reg (cclk, reset_s, cpu_fio_req_en, cpu_fio_req_in, cpu_fio_req); |
| 1096 | |
| 1097 | /************************/ |
| 1098 | //Interrupt |
| 1099 | /************************/ |
| 1100 | assign fflp_err_intr_mask_wen = pio_wen & (pio_addr == 20'ha0140); |
| 1101 | assign fflp_err_intr_bits = { hash_tbl_ecc_log_reg7_dout[31], |
| 1102 | hash_tbl_ecc_log_reg6_dout[31], |
| 1103 | hash_tbl_ecc_log_reg5_dout[31], |
| 1104 | hash_tbl_ecc_log_reg4_dout[31], |
| 1105 | hash_tbl_ecc_log_reg3_dout[31], |
| 1106 | hash_tbl_ecc_log_reg2_dout[31], |
| 1107 | hash_tbl_ecc_log_reg1_dout[31], |
| 1108 | hash_tbl_ecc_log_reg0_dout[31], |
| 1109 | hash_lookup_log_reg0_dout[3], |
| 1110 | cam_ecc_log_reg_dout[26], |
| 1111 | vlan_parity_err_log_reg_dout[31] }; |
| 1112 | |
| 1113 | assign fflp_pio_intr_in = |(fflp_err_intr_bits[10:0] & (~fflp_err_intr_mask_reg_dout[10:0])); |
| 1114 | |
| 1115 | dffr #(1) fflp_err_intr_reg (cclk, reset_s, fflp_pio_intr_in, fflp_pio_intr); |
| 1116 | |
| 1117 | always @ (posedge cclk) |
| 1118 | if (reset_s) |
| 1119 | fflp_err_intr_mask_reg_dout <= 11'h7ff; |
| 1120 | else if (fflp_err_intr_mask_wen) |
| 1121 | fflp_err_intr_mask_reg_dout <= pio_wr_data[10:0]; |
| 1122 | else |
| 1123 | fflp_err_intr_mask_reg_dout <= fflp_err_intr_mask_reg_dout; |
| 1124 | |
| 1125 | |
| 1126 | |
| 1127 | always @ (pio_addr or pio_32b_mode or fflp_config_reg_dout or |
| 1128 | hdr_ctrl_bit_mask_reg_dout or fcram_refresh_timer_reg_dout or |
| 1129 | class2_hdr_byte_value or class3_hdr_byte_value or |
| 1130 | class4_hdr_byte_value or class5_hdr_byte_value or |
| 1131 | class6_hdr_byte_value or class7_hdr_byte_value or |
| 1132 | class_action_reg4_dout or class_action_reg5_dout or |
| 1133 | class_action_reg6_dout or class_action_reg7_dout or |
| 1134 | class_action_reg8_dout or class_action_reg9_dout or |
| 1135 | class_action_reg10_dout or class_action_reg11_dout or |
| 1136 | class_action_reg12_dout or class_action_reg13_dout or |
| 1137 | class_action_reg14_dout or class_action_reg15_dout or |
| 1138 | f_key_class_action_reg4_dout or f_key_class_action_reg5_dout or |
| 1139 | f_key_class_action_reg6_dout or f_key_class_action_reg7_dout or |
| 1140 | f_key_class_action_reg8_dout or f_key_class_action_reg9_dout or |
| 1141 | f_key_class_action_reg10_dout or f_key_class_action_reg11_dout or |
| 1142 | f_key_class_action_reg12_dout or f_key_class_action_reg13_dout or |
| 1143 | f_key_class_action_reg14_dout or f_key_class_action_reg15_dout or |
| 1144 | cam_key_reg0_dout or cam_key_reg1_dout or |
| 1145 | cam_key_reg2_dout or cam_key_reg3_dout or |
| 1146 | cam_key_mask_reg0_dout or cam_key_mask_reg1_dout or |
| 1147 | cam_key_mask_reg2_dout or cam_key_mask_reg3_dout or |
| 1148 | cam_cmd_stat_reg_dout or vlan_tbl_rd_data or |
| 1149 | vlan_parity_err_log_reg_dout or |
| 1150 | h1_init_value_reg_dout or h2_init_value_reg_dout or |
| 1151 | flow_part_sel_reg0_dout or flow_part_sel_reg1_dout or |
| 1152 | flow_part_sel_reg2_dout or flow_part_sel_reg3_dout or |
| 1153 | flow_part_sel_reg4_dout or flow_part_sel_reg5_dout or |
| 1154 | flow_part_sel_reg6_dout or flow_part_sel_reg7_dout or |
| 1155 | hash_tbl_addr_reg0_dout or hash_tbl_addr_reg1_dout or |
| 1156 | hash_tbl_addr_reg2_dout or hash_tbl_addr_reg3_dout or |
| 1157 | hash_tbl_addr_reg4_dout or hash_tbl_addr_reg5_dout or |
| 1158 | hash_tbl_addr_reg6_dout or hash_tbl_addr_reg7_dout or |
| 1159 | hash_tbl_data_reg0_dout or hash_tbl_data_reg1_dout or |
| 1160 | hash_tbl_data_reg2_dout or hash_tbl_data_reg3_dout or |
| 1161 | hash_tbl_data_reg4_dout or hash_tbl_data_reg5_dout or |
| 1162 | hash_tbl_data_reg6_dout or hash_tbl_data_reg7_dout or |
| 1163 | hash_tbl_ecc_log_reg0_dout or hash_tbl_ecc_log_reg1_dout or |
| 1164 | hash_tbl_ecc_log_reg2_dout or hash_tbl_ecc_log_reg3_dout or |
| 1165 | hash_tbl_ecc_log_reg4_dout or hash_tbl_ecc_log_reg5_dout or |
| 1166 | hash_tbl_ecc_log_reg6_dout or hash_tbl_ecc_log_reg7_dout or |
| 1167 | fcram_err_test_reg0_dout or fcram_err_test_reg1_dout or fcram_err_test_reg2_dout or |
| 1168 | hash_lookup_log_reg0_dout or hash_lookup_log_reg1_dout or |
| 1169 | cam_ecc_log_reg_dout or cpu_fio_rd_data or fio_cfg_addr_reg_dout or |
| 1170 | fflp_err_intr_mask_reg_dout or debug_training_vector or fio_cal_rd_latency) |
| 1171 | |
| 1172 | begin |
| 1173 | |
| 1174 | pio_addr_err = 1'b0; |
| 1175 | |
| 1176 | casex (pio_addr[19:2]) //synopsys parallel_case full_case |
| 1177 | // 0in < case -full -parallel -message "0in ERROR: case check in fflp_pio_if:pio_addr" |
| 1178 | |
| 1179 | 18'h00000: pio_rd_data_tmp = {40'b0, hash_tbl_addr_reg0_dout[23:0]}; |
| 1180 | 18'h00001: pio_rd_data_tmp = 64'b0; |
| 1181 | 18'h00800: pio_rd_data_tmp = {40'b0, hash_tbl_addr_reg1_dout[23:0]}; |
| 1182 | 18'h00801: pio_rd_data_tmp = 64'b0; |
| 1183 | 18'h01000: pio_rd_data_tmp = {40'b0, hash_tbl_addr_reg2_dout[23:0]}; |
| 1184 | 18'h01001: pio_rd_data_tmp = 64'b0; |
| 1185 | 18'h01800: pio_rd_data_tmp = {40'b0, hash_tbl_addr_reg3_dout[23:0]}; |
| 1186 | 18'h01801: pio_rd_data_tmp = 64'b0; |
| 1187 | 18'h02000: pio_rd_data_tmp = {40'b0, hash_tbl_addr_reg4_dout[23:0]}; |
| 1188 | 18'h02001: pio_rd_data_tmp = 64'b0; |
| 1189 | 18'h02800: pio_rd_data_tmp = {40'b0, hash_tbl_addr_reg5_dout[23:0]}; |
| 1190 | 18'h02801: pio_rd_data_tmp = 64'b0; |
| 1191 | 18'h03000: pio_rd_data_tmp = {40'b0, hash_tbl_addr_reg6_dout[23:0]}; |
| 1192 | 18'h03001: pio_rd_data_tmp = 64'b0; |
| 1193 | 18'h03800: pio_rd_data_tmp = {40'b0, hash_tbl_addr_reg7_dout[23:0]}; |
| 1194 | 18'h03801: pio_rd_data_tmp = 64'b0; |
| 1195 | |
| 1196 | 18'h00002, 18'h00802, 18'h01002, 18'h01802, 18'h02002, 18'h02802, 18'h03002, 18'h03802: |
| 1197 | begin |
| 1198 | if (pio_32b_mode) |
| 1199 | begin |
| 1200 | case (pio_addr[13:11]) |
| 1201 | // 0in < case -full -parallel -message "0in ERROR: case check in fflp_pio_if:pio_addr0" |
| 1202 | |
| 1203 | 3'h0: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg0_dout[31:0]}; |
| 1204 | 3'h1: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg1_dout[31:0]}; |
| 1205 | 3'h2: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg2_dout[31:0]}; |
| 1206 | 3'h3: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg3_dout[31:0]}; |
| 1207 | 3'h4: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg4_dout[31:0]}; |
| 1208 | 3'h5: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg5_dout[31:0]}; |
| 1209 | 3'h6: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg6_dout[31:0]}; |
| 1210 | 3'h7: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg7_dout[31:0]}; |
| 1211 | |
| 1212 | endcase |
| 1213 | end |
| 1214 | else |
| 1215 | begin |
| 1216 | case (pio_addr[15:13]) |
| 1217 | // 0in < case -full -parallel -message "0in ERROR: case check in fflp_pio_if:pio_addr1" |
| 1218 | |
| 1219 | 3'h0: pio_rd_data_tmp = hash_tbl_data_reg0_dout[63:0]; |
| 1220 | 3'h1: pio_rd_data_tmp = hash_tbl_data_reg1_dout[63:0]; |
| 1221 | 3'h2: pio_rd_data_tmp = hash_tbl_data_reg2_dout[63:0]; |
| 1222 | 3'h3: pio_rd_data_tmp = hash_tbl_data_reg3_dout[63:0]; |
| 1223 | 3'h4: pio_rd_data_tmp = hash_tbl_data_reg4_dout[63:0]; |
| 1224 | 3'h5: pio_rd_data_tmp = hash_tbl_data_reg5_dout[63:0]; |
| 1225 | 3'h6: pio_rd_data_tmp = hash_tbl_data_reg6_dout[63:0]; |
| 1226 | 3'h7: pio_rd_data_tmp = hash_tbl_data_reg7_dout[63:0]; |
| 1227 | |
| 1228 | endcase |
| 1229 | end |
| 1230 | end |
| 1231 | |
| 1232 | 18'h00003, 18'h00803, 18'h01003, 18'h01803, 18'h02003, 18'h02803, 18'h03003, 18'h03803: |
| 1233 | begin |
| 1234 | if (pio_32b_mode) |
| 1235 | begin |
| 1236 | case (pio_addr[15:13]) |
| 1237 | // 0in < case -full -parallel -message "0in ERROR: case check in fflp_pio_if:pio_addr2" |
| 1238 | |
| 1239 | 3'h0: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg0_dout[63:32]}; |
| 1240 | 3'h1: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg1_dout[63:32]}; |
| 1241 | 3'h2: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg2_dout[63:32]}; |
| 1242 | 3'h3: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg3_dout[63:32]}; |
| 1243 | 3'h4: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg4_dout[63:32]}; |
| 1244 | 3'h5: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg5_dout[63:32]}; |
| 1245 | 3'h6: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg6_dout[63:32]}; |
| 1246 | 3'h7: pio_rd_data_tmp = {32'b0, hash_tbl_data_reg7_dout[63:32]}; |
| 1247 | |
| 1248 | endcase |
| 1249 | end |
| 1250 | else |
| 1251 | begin |
| 1252 | pio_addr_err = 1'b0; |
| 1253 | pio_rd_data_tmp = 64'b0; |
| 1254 | end |
| 1255 | end |
| 1256 | |
| 1257 | 18'h00004: pio_rd_data_tmp = {32'b0, hash_tbl_ecc_log_reg0_dout[31:0]}; |
| 1258 | 18'h00005: pio_rd_data_tmp = 64'b0; |
| 1259 | 18'h00804: pio_rd_data_tmp = {32'b0, hash_tbl_ecc_log_reg1_dout[31:0]}; |
| 1260 | 18'h00805: pio_rd_data_tmp = 64'b0; |
| 1261 | 18'h01004: pio_rd_data_tmp = {32'b0, hash_tbl_ecc_log_reg2_dout[31:0]}; |
| 1262 | 18'h01005: pio_rd_data_tmp = 64'b0; |
| 1263 | 18'h01804: pio_rd_data_tmp = {32'b0, hash_tbl_ecc_log_reg3_dout[31:0]}; |
| 1264 | 18'h01805: pio_rd_data_tmp = 64'b0; |
| 1265 | 18'h02004: pio_rd_data_tmp = {32'b0, hash_tbl_ecc_log_reg4_dout[31:0]}; |
| 1266 | 18'h02005: pio_rd_data_tmp = 64'b0; |
| 1267 | 18'h02804: pio_rd_data_tmp = {32'b0, hash_tbl_ecc_log_reg5_dout[31:0]}; |
| 1268 | 18'h02805: pio_rd_data_tmp = 64'b0; |
| 1269 | 18'h03004: pio_rd_data_tmp = {32'b0, hash_tbl_ecc_log_reg6_dout[31:0]}; |
| 1270 | 18'h03005: pio_rd_data_tmp = 64'b0; |
| 1271 | 18'h03804: pio_rd_data_tmp = {32'b0, hash_tbl_ecc_log_reg7_dout[31:0]}; |
| 1272 | 18'h03805: pio_rd_data_tmp = 64'b0; |
| 1273 | |
| 1274 | 18'h20xxx, 18'h21xxx: |
| 1275 | begin |
| 1276 | if (pio_32b_mode & pio_addr[2]) |
| 1277 | pio_rd_data_tmp = 64'b0; |
| 1278 | else |
| 1279 | pio_rd_data_tmp = {46'b0, |
| 1280 | vlan_tbl_rd_data[17], vlan_tbl_rd_data[8], vlan_tbl_rd_data[16:9], vlan_tbl_rd_data[7:0]}; |
| 1281 | end |
| 1282 | |
| 1283 | 18'h22000: pio_rd_data_tmp = {32'b0, vlan_parity_err_log_reg_dout[31:0]}; |
| 1284 | 18'h22001: pio_rd_data_tmp = 64'b0; |
| 1285 | |
| 1286 | 18'h28000: pio_rd_data_tmp = {47'b0, class2_hdr_byte_value[16:0]}; |
| 1287 | 18'h28001: pio_rd_data_tmp = 64'b0; |
| 1288 | 18'h28002: pio_rd_data_tmp = {47'b0, class3_hdr_byte_value[16:0]}; |
| 1289 | 18'h28003: pio_rd_data_tmp = 64'b0; |
| 1290 | 18'h28004: pio_rd_data_tmp = {38'b0, class4_hdr_byte_value[25:0]}; |
| 1291 | 18'h28005: pio_rd_data_tmp = 64'b0; |
| 1292 | 18'h28006: pio_rd_data_tmp = {38'b0, class5_hdr_byte_value[25:0]}; |
| 1293 | 18'h28007: pio_rd_data_tmp = 64'b0; |
| 1294 | 18'h28008: pio_rd_data_tmp = {38'b0, class6_hdr_byte_value[25:0]}; |
| 1295 | 18'h28009: pio_rd_data_tmp = 64'b0; |
| 1296 | 18'h2800a: pio_rd_data_tmp = {38'b0, class7_hdr_byte_value[25:0]}; |
| 1297 | 18'h2800b: pio_rd_data_tmp = 64'b0; |
| 1298 | 18'h2800c: pio_rd_data_tmp = {60'b0, class_action_reg4_dout[2:1], 1'b0, class_action_reg4_dout[0]}; |
| 1299 | 18'h2800d: pio_rd_data_tmp = 64'b0; |
| 1300 | 18'h2800e: pio_rd_data_tmp = {60'b0, class_action_reg5_dout[2:1], 1'b0, class_action_reg5_dout[0]}; |
| 1301 | 18'h2800f: pio_rd_data_tmp = 64'b0; |
| 1302 | 18'h28010: pio_rd_data_tmp = {60'b0, class_action_reg6_dout[2:1], 1'b0, class_action_reg6_dout[0]}; |
| 1303 | 18'h28011: pio_rd_data_tmp = 64'b0; |
| 1304 | 18'h28012: pio_rd_data_tmp = {60'b0, class_action_reg7_dout[2:1], 1'b0, class_action_reg7_dout[0]}; |
| 1305 | 18'h28013: pio_rd_data_tmp = 64'b0; |
| 1306 | 18'h28014: pio_rd_data_tmp = {60'b0, class_action_reg8_dout[2:1], 1'b0, class_action_reg8_dout[0]}; |
| 1307 | 18'h28015: pio_rd_data_tmp = 64'b0; |
| 1308 | 18'h28016: pio_rd_data_tmp = {60'b0, class_action_reg9_dout[2:1], 1'b0, class_action_reg9_dout[0]}; |
| 1309 | 18'h28017: pio_rd_data_tmp = 64'b0; |
| 1310 | 18'h28018: pio_rd_data_tmp = {60'b0, class_action_reg10_dout[2:1], 1'b0, class_action_reg10_dout[0]}; |
| 1311 | 18'h28019: pio_rd_data_tmp = 64'b0; |
| 1312 | 18'h2801a: pio_rd_data_tmp = {60'b0, class_action_reg11_dout[2:1], 1'b0, class_action_reg11_dout[0]}; |
| 1313 | 18'h2801b: pio_rd_data_tmp = 64'b0; |
| 1314 | 18'h2801c: pio_rd_data_tmp = {60'b0, class_action_reg12_dout[2:1], 1'b0, class_action_reg12_dout[0]}; |
| 1315 | 18'h2801d: pio_rd_data_tmp = 64'b0; |
| 1316 | 18'h2801e: pio_rd_data_tmp = {60'b0, class_action_reg13_dout[2:1], 1'b0, class_action_reg13_dout[0]}; |
| 1317 | 18'h2801f: pio_rd_data_tmp = 64'b0; |
| 1318 | 18'h28020: pio_rd_data_tmp = {60'b0, class_action_reg14_dout[2:1], 1'b0, class_action_reg14_dout[0]}; |
| 1319 | 18'h28021: pio_rd_data_tmp = 64'b0; |
| 1320 | 18'h28022: pio_rd_data_tmp = {60'b0, class_action_reg15_dout[2:1], 1'b0, class_action_reg15_dout[0]}; |
| 1321 | 18'h28023: pio_rd_data_tmp = 64'b0; |
| 1322 | 18'h28024: pio_rd_data_tmp = {56'b0, cam_key_reg0_dout[7:0]}; |
| 1323 | 18'h28025: pio_rd_data_tmp = 64'b0; |
| 1324 | |
| 1325 | 18'h28026: begin |
| 1326 | if (pio_32b_mode) |
| 1327 | pio_rd_data_tmp = {32'b0, cam_key_reg1_dout[31:0]}; |
| 1328 | else |
| 1329 | pio_rd_data_tmp = cam_key_reg1_dout[63:0]; |
| 1330 | end |
| 1331 | |
| 1332 | 18'h28027: begin |
| 1333 | if (pio_32b_mode) |
| 1334 | pio_rd_data_tmp = {32'b0, cam_key_reg1_dout[63:32]}; |
| 1335 | else |
| 1336 | begin |
| 1337 | pio_addr_err = 1'b0; |
| 1338 | pio_rd_data_tmp = 64'b0; |
| 1339 | end |
| 1340 | end |
| 1341 | |
| 1342 | 18'h28028: begin |
| 1343 | if (pio_32b_mode) |
| 1344 | pio_rd_data_tmp = {32'b0, cam_key_reg2_dout[31:0]}; |
| 1345 | else |
| 1346 | pio_rd_data_tmp = cam_key_reg2_dout[63:0]; |
| 1347 | end |
| 1348 | |
| 1349 | 18'h28029: begin |
| 1350 | if (pio_32b_mode) |
| 1351 | pio_rd_data_tmp = {32'b0, cam_key_reg2_dout[63:32]}; |
| 1352 | else |
| 1353 | begin |
| 1354 | pio_addr_err = 1'b0; |
| 1355 | pio_rd_data_tmp = 64'b0; |
| 1356 | end |
| 1357 | end |
| 1358 | |
| 1359 | 18'h2802a: begin |
| 1360 | if (pio_32b_mode) |
| 1361 | pio_rd_data_tmp = {32'b0, cam_key_reg3_dout[31:0]}; |
| 1362 | else |
| 1363 | pio_rd_data_tmp = cam_key_reg3_dout[63:0]; |
| 1364 | end |
| 1365 | |
| 1366 | 18'h2802b: begin |
| 1367 | if (pio_32b_mode) |
| 1368 | pio_rd_data_tmp = {32'b0, cam_key_reg3_dout[63:32]}; |
| 1369 | else |
| 1370 | begin |
| 1371 | pio_addr_err = 1'b0; |
| 1372 | pio_rd_data_tmp = 64'b0; |
| 1373 | end |
| 1374 | end |
| 1375 | |
| 1376 | 18'h2802c: pio_rd_data_tmp = {56'b0, cam_key_mask_reg0_dout[7:0]}; |
| 1377 | |
| 1378 | 18'h2802d: pio_rd_data_tmp = 64'b0; |
| 1379 | |
| 1380 | 18'h2802e: begin |
| 1381 | if (pio_32b_mode) |
| 1382 | pio_rd_data_tmp = {32'b0, cam_key_mask_reg1_dout[31:0]}; |
| 1383 | else |
| 1384 | pio_rd_data_tmp = cam_key_mask_reg1_dout[63:0]; |
| 1385 | end |
| 1386 | |
| 1387 | 18'h2802f: begin |
| 1388 | if (pio_32b_mode) |
| 1389 | pio_rd_data_tmp = {32'b0, cam_key_mask_reg1_dout[63:32]}; |
| 1390 | else |
| 1391 | begin |
| 1392 | pio_addr_err = 1'b0; |
| 1393 | pio_rd_data_tmp = 64'b0; |
| 1394 | end |
| 1395 | end |
| 1396 | |
| 1397 | 18'h28030: begin |
| 1398 | if (pio_32b_mode) |
| 1399 | pio_rd_data_tmp = {32'b0, cam_key_mask_reg2_dout[31:0]}; |
| 1400 | else |
| 1401 | pio_rd_data_tmp = cam_key_mask_reg2_dout[63:0]; |
| 1402 | end |
| 1403 | |
| 1404 | 18'h28031: begin |
| 1405 | if (pio_32b_mode) |
| 1406 | pio_rd_data_tmp = {32'b0, cam_key_mask_reg2_dout[63:32]}; |
| 1407 | else |
| 1408 | begin |
| 1409 | pio_addr_err = 1'b0; |
| 1410 | pio_rd_data_tmp = 64'b0; |
| 1411 | end |
| 1412 | end |
| 1413 | |
| 1414 | 18'h28032: begin |
| 1415 | if (pio_32b_mode) |
| 1416 | pio_rd_data_tmp = {32'b0, cam_key_mask_reg3_dout[31:0]}; |
| 1417 | else |
| 1418 | pio_rd_data_tmp = cam_key_mask_reg3_dout[63:0]; |
| 1419 | end |
| 1420 | |
| 1421 | 18'h28033: begin |
| 1422 | if (pio_32b_mode) |
| 1423 | pio_rd_data_tmp = {32'b0, cam_key_mask_reg3_dout[63:32]}; |
| 1424 | else |
| 1425 | begin |
| 1426 | pio_addr_err = 1'b0; |
| 1427 | pio_rd_data_tmp = 64'b0; |
| 1428 | end |
| 1429 | end |
| 1430 | |
| 1431 | 18'h28034: pio_rd_data_tmp = {43'b0, cam_cmd_stat_reg_dout[20:0]}; |
| 1432 | 18'h28035: pio_rd_data_tmp = 64'b0; |
| 1433 | 18'h28036: pio_rd_data_tmp = {32'b0, cam_ecc_log_reg_dout[26:24], 5'b0, cam_ecc_log_reg_dout[23:0]}; |
| 1434 | 18'h28037: pio_rd_data_tmp = 64'b0; |
| 1435 | 18'h28038: pio_rd_data_tmp = {60'b0, hash_lookup_log_reg0_dout[3:0]}; |
| 1436 | 18'h28039: pio_rd_data_tmp = 64'b0; |
| 1437 | 18'h2803a: pio_rd_data_tmp = {33'b0, hash_lookup_log_reg1_dout[30:0]}; |
| 1438 | 18'h2803b: pio_rd_data_tmp = 64'b0; |
| 1439 | |
| 1440 | 18'h28040: pio_rd_data_tmp = {37'b0, fflp_config_reg_dout[26:0]}; |
| 1441 | 18'h28041: pio_rd_data_tmp = 64'b0; |
| 1442 | 18'h28042: pio_rd_data_tmp = {52'b0, hdr_ctrl_bit_mask_reg_dout[11:0]}; |
| 1443 | 18'h28043: pio_rd_data_tmp = 64'b0; |
| 1444 | 18'h28044: pio_rd_data_tmp = {32'b0, fcram_refresh_timer_reg_dout}; |
| 1445 | 18'h28045: pio_rd_data_tmp = 64'b0; |
| 1446 | 18'h28046: pio_rd_data_tmp = {56'b0, fio_cfg_addr_reg_dout[7:0]}; |
| 1447 | 18'h28047: pio_rd_data_tmp = 64'b0; |
| 1448 | 18'h28048: pio_rd_data_tmp = {32'b0, cpu_fio_rd_data[31:0]}; |
| 1449 | 18'h28049: pio_rd_data_tmp = 64'b0; |
| 1450 | 18'h2804a: pio_rd_data_tmp = {56'b0, fcram_err_test_reg0_dout[7:0]}; |
| 1451 | 18'h2804b: pio_rd_data_tmp = 64'b0; |
| 1452 | 18'h2804c: pio_rd_data_tmp = {32'b0, fcram_err_test_reg1_dout[31:0]}; |
| 1453 | 18'h2804d: pio_rd_data_tmp = 64'b0; |
| 1454 | 18'h2804e: pio_rd_data_tmp = {32'b0, fcram_err_test_reg2_dout[31:0]}; |
| 1455 | 18'h2804f: pio_rd_data_tmp = 64'b0; |
| 1456 | |
| 1457 | 18'h28050: pio_rd_data_tmp = {32'b0, 21'b0, fflp_err_intr_mask_reg_dout[10:0]}; |
| 1458 | 18'h28051: pio_rd_data_tmp = 64'b0; |
| 1459 | 18'h28052: pio_rd_data_tmp = {32'b0, debug_training_vector[31:0]}; |
| 1460 | 18'h28053: pio_rd_data_tmp = 64'b0; |
| 1461 | |
| 1462 | 18'h28054: pio_rd_data_tmp = {56'b0, fio_cal_rd_latency[7:0]}; |
| 1463 | 18'h28055: pio_rd_data_tmp = 64'b0; |
| 1464 | |
| 1465 | 18'h30000: pio_rd_data_tmp = {54'b0, f_key_class_action_reg4_dout[9:0]}; |
| 1466 | 18'h30001: pio_rd_data_tmp = 64'b0; |
| 1467 | 18'h30002: pio_rd_data_tmp = {54'b0, f_key_class_action_reg5_dout[9:0]}; |
| 1468 | 18'h30003: pio_rd_data_tmp = 64'b0; |
| 1469 | 18'h30004: pio_rd_data_tmp = {54'b0, f_key_class_action_reg6_dout[9:0]}; |
| 1470 | 18'h30005: pio_rd_data_tmp = 64'b0; |
| 1471 | 18'h30006: pio_rd_data_tmp = {54'b0, f_key_class_action_reg7_dout[9:0]}; |
| 1472 | 18'h30007: pio_rd_data_tmp = 64'b0; |
| 1473 | 18'h30008: pio_rd_data_tmp = {54'b0, f_key_class_action_reg8_dout[9:0]}; |
| 1474 | 18'h30009: pio_rd_data_tmp = 64'b0; |
| 1475 | 18'h3000a: pio_rd_data_tmp = {54'b0, f_key_class_action_reg9_dout[9:0]}; |
| 1476 | 18'h3000b: pio_rd_data_tmp = 64'b0; |
| 1477 | 18'h3000c: pio_rd_data_tmp = {54'b0, f_key_class_action_reg10_dout[9:0]}; |
| 1478 | 18'h3000d: pio_rd_data_tmp = 64'b0; |
| 1479 | 18'h3000e: pio_rd_data_tmp = {54'b0, f_key_class_action_reg11_dout[9:0]}; |
| 1480 | 18'h3000f: pio_rd_data_tmp = 64'b0; |
| 1481 | 18'h30010: pio_rd_data_tmp = {54'b0, f_key_class_action_reg12_dout[9:0]}; |
| 1482 | 18'h30011: pio_rd_data_tmp = 64'b0; |
| 1483 | 18'h30012: pio_rd_data_tmp = {54'b0, f_key_class_action_reg13_dout[9:0]}; |
| 1484 | 18'h30013: pio_rd_data_tmp = 64'b0; |
| 1485 | 18'h30014: pio_rd_data_tmp = {54'b0, f_key_class_action_reg14_dout[9:0]}; |
| 1486 | 18'h30015: pio_rd_data_tmp = 64'b0; |
| 1487 | 18'h30016: pio_rd_data_tmp = {54'b0, f_key_class_action_reg15_dout[9:0]}; |
| 1488 | 18'h30017: pio_rd_data_tmp = 64'b0; |
| 1489 | 18'h30018: pio_rd_data_tmp = {32'b0, h1_init_value_reg_dout[31:0]}; |
| 1490 | 18'h30019: pio_rd_data_tmp = 64'b0; |
| 1491 | 18'h3001a: pio_rd_data_tmp = {48'b0, h2_init_value_reg_dout[15:0]}; |
| 1492 | 18'h3001b: pio_rd_data_tmp = 64'b0; |
| 1493 | 18'h3001c: pio_rd_data_tmp = {47'b0, flow_part_sel_reg0_dout[10], 3'b0, flow_part_sel_reg0_dout[9:5], 3'b0, flow_part_sel_reg0_dout[4:0]}; |
| 1494 | 18'h3001d: pio_rd_data_tmp = 64'b0; |
| 1495 | 18'h3001e: pio_rd_data_tmp = {47'b0, flow_part_sel_reg1_dout[10], 3'b0, flow_part_sel_reg1_dout[9:5], 3'b0, flow_part_sel_reg1_dout[4:0]}; |
| 1496 | 18'h3001f: pio_rd_data_tmp = 64'b0; |
| 1497 | 18'h30020: pio_rd_data_tmp = {47'b0, flow_part_sel_reg2_dout[10], 3'b0, flow_part_sel_reg2_dout[9:5], 3'b0, flow_part_sel_reg2_dout[4:0]}; |
| 1498 | 18'h30021: pio_rd_data_tmp = 64'b0; |
| 1499 | 18'h30022: pio_rd_data_tmp = {47'b0, flow_part_sel_reg3_dout[10], 3'b0, flow_part_sel_reg3_dout[9:5], 3'b0, flow_part_sel_reg3_dout[4:0]}; |
| 1500 | 18'h30023: pio_rd_data_tmp = 64'b0; |
| 1501 | 18'h30024: pio_rd_data_tmp = {47'b0, flow_part_sel_reg4_dout[10], 3'b0, flow_part_sel_reg4_dout[9:5], 3'b0, flow_part_sel_reg4_dout[4:0]}; |
| 1502 | 18'h30025: pio_rd_data_tmp = 64'b0; |
| 1503 | 18'h30026: pio_rd_data_tmp = {47'b0, flow_part_sel_reg5_dout[10], 3'b0, flow_part_sel_reg5_dout[9:5], 3'b0, flow_part_sel_reg5_dout[4:0]}; |
| 1504 | 18'h30027: pio_rd_data_tmp = 64'b0; |
| 1505 | 18'h30028: pio_rd_data_tmp = {47'b0, flow_part_sel_reg6_dout[10], 3'b0, flow_part_sel_reg6_dout[9:5], 3'b0, flow_part_sel_reg6_dout[4:0]}; |
| 1506 | 18'h30029: pio_rd_data_tmp = 64'b0; |
| 1507 | 18'h3002a: pio_rd_data_tmp = {47'b0, flow_part_sel_reg7_dout[10], 3'b0, flow_part_sel_reg7_dout[9:5], 3'b0, flow_part_sel_reg7_dout[4:0]}; |
| 1508 | 18'h3002b: pio_rd_data_tmp = 64'b0; |
| 1509 | |
| 1510 | default: begin |
| 1511 | pio_rd_data_tmp = 64'hdeadbeefdeadbeef; |
| 1512 | pio_addr_err = 1'b1; |
| 1513 | end |
| 1514 | endcase |
| 1515 | |
| 1516 | end |
| 1517 | |
| 1518 | |
| 1519 | endmodule |