| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_dmc_txcif.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | |
| 36 | /********************************************************************* |
| 37 | * |
| 38 | * |
| 39 | * Orignal Author(s): Arvind Srinivasan |
| 40 | * Modifier(s): |
| 41 | * Project(s): Neptune |
| 42 | * |
| 43 | * Copyright (c) 2004 Sun Microsystems, Inc. |
| 44 | * |
| 45 | * All Rights Reserved. |
| 46 | * |
| 47 | * This verilog model is the confidential and proprietary property of |
| 48 | * Sun Microsystems, Inc., and the possession or use of this model |
| 49 | * requires a written license from Sun Microsystems, Inc. |
| 50 | * |
| 51 | **********************************************************************/ |
| 52 | |
| 53 | |
| 54 | |
| 55 | module niu_dmc_txcif ( /*AUTOARG*/ |
| 56 | // Outputs |
| 57 | inc_head_shadow, incr_read_ptr, gotnxtdesc, read_req, |
| 58 | dmc_txc_dma_descriptor, dmc_txc_dma_partial, cache_ready, |
| 59 | reset_cache_pointers, dma_reset_done_hold, |
| 60 | dmc_txc_dma_reset_scheduled, |
| 61 | set_pref_buf_par_err_dma, set_pkt_part_err_dma, |
| 62 | pkt_part_error_address_dma, |
| 63 | // Inputs |
| 64 | SysClk, Reset_L, read_gnt, getnxtdesc, empty, dma_cache_readdata, |
| 65 | dma_cache_tags, cache_filled_size, cache_entry_valid, |
| 66 | page0_mask_dma, page0_value_dma, page0_reloc_dma, page0_valid_dma, |
| 67 | page1_mask_dma, page1_value_dma, page1_reloc_dma, page1_valid_dma, |
| 68 | dma_reset_scheduled, txc_dmc_dma_reset_done, cache_parity_status,tx_dma_cfg_dma_stop |
| 69 | ); |
| 70 | input SysClk; |
| 71 | input Reset_L; |
| 72 | input read_gnt; |
| 73 | input getnxtdesc; |
| 74 | input empty; |
| 75 | input [127:0] dma_cache_readdata; |
| 76 | |
| 77 | input [3:0] dma_cache_tags; |
| 78 | input [4:0] cache_filled_size; |
| 79 | |
| 80 | output inc_head_shadow; |
| 81 | input cache_entry_valid; |
| 82 | input tx_dma_cfg_dma_stop; |
| 83 | |
| 84 | output incr_read_ptr; |
| 85 | output gotnxtdesc; |
| 86 | output read_req; |
| 87 | output [63:0] dmc_txc_dma_descriptor; |
| 88 | output dmc_txc_dma_partial; |
| 89 | output cache_ready; |
| 90 | output reset_cache_pointers; |
| 91 | |
| 92 | input [31:0] page0_mask_dma; |
| 93 | input [31:0] page0_value_dma; |
| 94 | input [31:0] page0_reloc_dma; |
| 95 | input page0_valid_dma; |
| 96 | input [31:0] page1_mask_dma; |
| 97 | input [31:0] page1_value_dma; |
| 98 | input [31:0] page1_reloc_dma; |
| 99 | input page1_valid_dma; |
| 100 | |
| 101 | input dma_reset_scheduled; |
| 102 | output dma_reset_done_hold; |
| 103 | input txc_dmc_dma_reset_done; |
| 104 | output dmc_txc_dma_reset_scheduled; |
| 105 | input cache_parity_status; |
| 106 | |
| 107 | |
| 108 | output set_pref_buf_par_err_dma; |
| 109 | output set_pkt_part_err_dma; |
| 110 | output [43:0] pkt_part_error_address_dma; |
| 111 | |
| 112 | |
| 113 | reg latch_descriptor; |
| 114 | reg [63:0] dmc_txc_dma_descriptor_e; |
| 115 | reg [63:0] dmc_txc_dma_descriptor_o; |
| 116 | reg incr_read_ptr; |
| 117 | reg gotnxtdesc; |
| 118 | reg read_req; |
| 119 | reg [63:0] dmc_txc_dma_descriptor; |
| 120 | reg cache_ready; |
| 121 | reg inc_head_shadow; |
| 122 | // reg dmc_txc_dma_error; |
| 123 | |
| 124 | reg [3:0] TxIfState; |
| 125 | reg reset_cache_pointers; |
| 126 | reg [3:0] dma_cache_tags_d; |
| 127 | reg cache_read_status; |
| 128 | reg [4:0] odd_num_ptr; |
| 129 | reg odd_sop_set; |
| 130 | reg [4:0] even_num_ptr; |
| 131 | reg even_sop_set; |
| 132 | reg partial_descriptor; |
| 133 | |
| 134 | reg [63:0] dma_descriptor_toxlate; |
| 135 | reg xlate_addr; |
| 136 | reg even_valid; |
| 137 | reg odd_valid; |
| 138 | reg [63:0] dma_descriptor_xlate; |
| 139 | reg xlate_done; |
| 140 | reg [3:0] page_xlate_state; |
| 141 | reg page0_match; |
| 142 | reg page1_match; |
| 143 | reg page_xlate_error_dma; |
| 144 | reg [31:0] page0_reloc_addr; |
| 145 | reg [31:0] page1_reloc_addr; |
| 146 | reg [43:0] pkt_part_error_address_dma; |
| 147 | reg txc_dmc_dma_reset_done_d; |
| 148 | |
| 149 | reg set_pref_buf_par_err_dma; |
| 150 | reg set_pkt_part_err_dma; |
| 151 | reg go_back_to_even; |
| 152 | reg go_back_to_odd; |
| 153 | reg read_done; |
| 154 | parameter IDLE = 4'h0, |
| 155 | REQ_FOR_CACHE_READ = 4'h1, |
| 156 | WAIT_FOR_DATA = 4'h2, |
| 157 | PARSE_DESCRIPTOR = 4'h3, |
| 158 | XLATE_ADDR = 4'h4, |
| 159 | SEND_EVEN_DESC = 4'h5, |
| 160 | CHECK_ODD_VALID = 4'h6, |
| 161 | SEND_ODD_DESC = 4'h7, |
| 162 | CHECK_NEXT_ENTRY = 4'h8, |
| 163 | RESET_CACHE_POINTERS = 4'h9, |
| 164 | CHECK_ODD_VALID_INC = 4'hA, |
| 165 | CHECK_NEXT_ENTRY_INC = 4'hB , |
| 166 | STOP_STATE = 4'hC , |
| 167 | ERROR = 4'hD ; |
| 168 | |
| 169 | //VCS coverage off |
| 170 | // synopsys translate_off |
| 171 | reg [192:1] TX_IFSTATE; |
| 172 | always@(TxIfState) begin |
| 173 | case(TxIfState) |
| 174 | IDLE:TX_IFSTATE = "IDLE" ; |
| 175 | REQ_FOR_CACHE_READ: TX_IFSTATE = "REQ_FOR_CACHE_READ"; |
| 176 | WAIT_FOR_DATA: TX_IFSTATE = "WAIT_FOR_DATA"; |
| 177 | PARSE_DESCRIPTOR: TX_IFSTATE = "PARSE_DESCRIPTOR"; |
| 178 | XLATE_ADDR: TX_IFSTATE = "XLATE_ADDR"; |
| 179 | SEND_EVEN_DESC: TX_IFSTATE = "SEND_EVEN_DESC"; |
| 180 | CHECK_ODD_VALID: TX_IFSTATE = "CHECK_ODD_VALID"; |
| 181 | SEND_ODD_DESC: TX_IFSTATE = "SEND_ODD_DESC"; |
| 182 | CHECK_NEXT_ENTRY: TX_IFSTATE = "CHECK_NEXT_ENTRY"; |
| 183 | RESET_CACHE_POINTERS: TX_IFSTATE = "RESET_CACHE_POINTERS"; |
| 184 | CHECK_ODD_VALID_INC: TX_IFSTATE = "CHECK_ODD_VALID_INC"; |
| 185 | CHECK_NEXT_ENTRY_INC: TX_IFSTATE = "CHECK_NEXT_ENTRY_INC"; |
| 186 | STOP_STATE: TX_IFSTATE = "STOP_STATE"; |
| 187 | ERROR: TX_IFSTATE = "ERROR"; |
| 188 | |
| 189 | default: TX_IFSTATE = "UNKNOWN"; |
| 190 | endcase // case(TxIfState) |
| 191 | end // always@ (TxIfState) |
| 192 | |
| 193 | always@(posedge gotnxtdesc ) begin |
| 194 | $display(" DEBUG- %m Sending Descriptor - %x Time - %t ",dmc_txc_dma_descriptor,$time); |
| 195 | end |
| 196 | // synopsys translate_on |
| 197 | // VCS coverage on |
| 198 | |
| 199 | |
| 200 | // Interface signals/logic related to reset - scheduling and done |
| 201 | |
| 202 | reg dmc_txc_dma_reset_scheduled; |
| 203 | reg dma_reset_done_hold; |
| 204 | reg dma_reset_scheduled_d; |
| 205 | reg reset_sm; |
| 206 | reg sm_reset_done; |
| 207 | reg stop_txif_sm; |
| 208 | reg tx_dma_cfg_dma_stop_d ; |
| 209 | |
| 210 | always@(posedge SysClk) begin |
| 211 | if(!Reset_L) begin |
| 212 | dmc_txc_dma_reset_scheduled <= 1'b0; |
| 213 | dma_reset_done_hold <= 1'b0; |
| 214 | dma_reset_scheduled_d <= 1'b0; |
| 215 | txc_dmc_dma_reset_done_d <= 1'b0; |
| 216 | reset_sm <= 1'b0; |
| 217 | stop_txif_sm <= 1'b0; |
| 218 | tx_dma_cfg_dma_stop_d <= 1'b0; |
| 219 | end else begin // if (!Reset_L) |
| 220 | dma_reset_scheduled_d <= dma_reset_scheduled ; |
| 221 | tx_dma_cfg_dma_stop_d <= tx_dma_cfg_dma_stop; |
| 222 | txc_dmc_dma_reset_done_d <= txc_dmc_dma_reset_done; |
| 223 | dmc_txc_dma_reset_scheduled <= (dma_reset_scheduled & !dma_reset_scheduled_d) |
| 224 | |( dmc_txc_dma_reset_scheduled & ~txc_dmc_dma_reset_done_d); |
| 225 | // hold signal for the reset state machine |
| 226 | dma_reset_done_hold <= (sm_reset_done ) | ( dma_reset_done_hold & dma_reset_scheduled); |
| 227 | reset_sm <= (txc_dmc_dma_reset_done & ~txc_dmc_dma_reset_done_d) | (reset_sm & dma_reset_scheduled) ; |
| 228 | stop_txif_sm <= ( !dma_reset_scheduled & dma_reset_scheduled_d & tx_dma_cfg_dma_stop) | |
| 229 | ( stop_txif_sm & ~( ~tx_dma_cfg_dma_stop & tx_dma_cfg_dma_stop_d ) ); |
| 230 | end // else: !if(!Reset_L) |
| 231 | end // always@ (posedge SysClk) |
| 232 | |
| 233 | // TOADS -- until dma_reset_done_hold is true there should not be more gots/gets |
| 234 | |
| 235 | |
| 236 | always@(posedge SysClk ) |
| 237 | begin |
| 238 | if(!Reset_L) begin |
| 239 | dmc_txc_dma_descriptor_o <= 64'h0; |
| 240 | dmc_txc_dma_descriptor_e <= 64'h0; |
| 241 | dma_cache_tags_d <= 4'h0; |
| 242 | odd_sop_set <= 1'b0; |
| 243 | even_sop_set <= 1'b0; |
| 244 | odd_num_ptr <= 5'h0; |
| 245 | even_num_ptr <= 5'h0; |
| 246 | cache_read_status <= 1'b0; |
| 247 | end else if(latch_descriptor) begin |
| 248 | dmc_txc_dma_descriptor_o <= dma_cache_readdata[127:64]; |
| 249 | dmc_txc_dma_descriptor_e <= dma_cache_readdata[63:0]; |
| 250 | dma_cache_tags_d <= dma_cache_tags; |
| 251 | odd_sop_set <= dma_cache_readdata[127]; |
| 252 | even_sop_set <= dma_cache_readdata[63]; |
| 253 | odd_num_ptr <= {1'b0,dma_cache_readdata[125:122] } ; |
| 254 | even_num_ptr <= {1'b0,dma_cache_readdata[61:58] } ; |
| 255 | cache_read_status <= cache_parity_status; |
| 256 | end |
| 257 | end // always@ (posedge SysClk ) |
| 258 | |
| 259 | // To Add as part of error -- |
| 260 | // if(cache_read_status) -- > Parity Error detected in reads |
| 261 | // drive dma_error signals appropriately |
| 262 | |
| 263 | |
| 264 | // Main State Machine for interfacing with TXC |
| 265 | |
| 266 | always@(posedge SysClk ) |
| 267 | if (!Reset_L) begin |
| 268 | TxIfState <= IDLE; |
| 269 | read_done <= 1'b0; |
| 270 | latch_descriptor <= 1'b0; |
| 271 | cache_ready <= 1'b0; |
| 272 | read_req <= 1'b0; |
| 273 | gotnxtdesc <= 1'b0; |
| 274 | xlate_addr <= 1'b0; |
| 275 | even_valid <= 1'b0; |
| 276 | odd_valid <= 1'b0; |
| 277 | // dmc_txc_dma_error <= 1'b0; |
| 278 | reset_cache_pointers <= 1'b0; |
| 279 | incr_read_ptr <= 1'b0; |
| 280 | partial_descriptor <= 1'b0; |
| 281 | set_pref_buf_par_err_dma <= 1'b0; |
| 282 | set_pkt_part_err_dma <= 1'b0; |
| 283 | sm_reset_done <= 1'b0; |
| 284 | go_back_to_even <= 1'b0; |
| 285 | go_back_to_odd <= 1'b0; |
| 286 | end else begin |
| 287 | case(TxIfState) // synopsys full_case parallel_case |
| 288 | IDLE: begin |
| 289 | set_pref_buf_par_err_dma <= 1'b0; |
| 290 | // dmc_txc_dma_error <= 1'b0; |
| 291 | sm_reset_done <= 1'b0; |
| 292 | go_back_to_even <= 1'b0; |
| 293 | go_back_to_odd <= 1'b0; |
| 294 | |
| 295 | // TOADD- |
| 296 | // Take this DMA off line whenever an error occurs and keep it offline untill a reset is |
| 297 | // done |
| 298 | if(reset_sm) begin |
| 299 | TxIfState <= IDLE; |
| 300 | sm_reset_done <= 1'b1; |
| 301 | cache_ready <= 1'b0; |
| 302 | gotnxtdesc <= 1'b0; |
| 303 | end else if(!empty & cache_entry_valid & ~stop_txif_sm) begin |
| 304 | TxIfState <= REQ_FOR_CACHE_READ; |
| 305 | read_req <= 1'b1; |
| 306 | partial_descriptor <= 1'b0; |
| 307 | end else begin |
| 308 | TxIfState <= IDLE; |
| 309 | cache_ready <= 1'b0; |
| 310 | partial_descriptor <= 1'b0; |
| 311 | end // else: !if(!empty) |
| 312 | end // case: IDLE |
| 313 | REQ_FOR_CACHE_READ: begin |
| 314 | if(read_gnt) begin |
| 315 | incr_read_ptr <= 1'b1; |
| 316 | latch_descriptor <= 1'b0; |
| 317 | read_done <= 1'b0; |
| 318 | read_req <= 1'b0; |
| 319 | TxIfState <= WAIT_FOR_DATA; |
| 320 | end else begin // if (read_gnt) |
| 321 | TxIfState <= REQ_FOR_CACHE_READ; |
| 322 | end // else: !if(read_gnt) |
| 323 | end // case: REQ_FOR_CACHE_READ |
| 324 | WAIT_FOR_DATA: begin |
| 325 | if(read_done) begin |
| 326 | incr_read_ptr <= 1'b0; |
| 327 | latch_descriptor <= 1'b0; |
| 328 | TxIfState <= PARSE_DESCRIPTOR; |
| 329 | end else begin |
| 330 | incr_read_ptr <= 1'b0; |
| 331 | TxIfState <= WAIT_FOR_DATA; |
| 332 | latch_descriptor <= 1'b1; |
| 333 | read_done <= 1'b1; |
| 334 | end |
| 335 | end |
| 336 | PARSE_DESCRIPTOR: begin |
| 337 | latch_descriptor <= 1'b0; |
| 338 | read_done <= 1'b0; |
| 339 | // dmc_txc_dma_error <= cache_read_status; |
| 340 | // Need to go to an error state here--- |
| 341 | if(cache_read_status) begin |
| 342 | set_pref_buf_par_err_dma <= 1'b1; |
| 343 | TxIfState <= ERROR; |
| 344 | end else begin |
| 345 | if(dma_cache_tags_d[0]) begin |
| 346 | // Drive signals like partials etc |
| 347 | // Check num_ptr against no of entries valid |
| 348 | // based upon that just wait here until enough entries are available |
| 349 | |
| 350 | if(even_sop_set & ( cache_filled_size < even_num_ptr)) begin |
| 351 | TxIfState <=PARSE_DESCRIPTOR; |
| 352 | partial_descriptor <= 1'b1; |
| 353 | // Just wait here |
| 354 | end else begin |
| 355 | TxIfState <= XLATE_ADDR; |
| 356 | partial_descriptor <= 1'b0; |
| 357 | dma_descriptor_toxlate <=dmc_txc_dma_descriptor_e; |
| 358 | xlate_addr <= 1'b1; |
| 359 | even_valid <= 1'b1; |
| 360 | odd_valid <= 1'b0; |
| 361 | end // else: !if(even_sop_set & (cache_filled_size < even_num_ptr)) |
| 362 | |
| 363 | end else if(dma_cache_tags_d[1]) begin |
| 364 | if(odd_sop_set & ( cache_filled_size < odd_num_ptr)) begin |
| 365 | TxIfState <=PARSE_DESCRIPTOR; |
| 366 | partial_descriptor <= 1'b1; |
| 367 | // Just wait here |
| 368 | end else begin |
| 369 | TxIfState <= XLATE_ADDR; |
| 370 | partial_descriptor <= 1'b0; |
| 371 | dma_descriptor_toxlate <=dmc_txc_dma_descriptor_o; |
| 372 | xlate_addr <= 1'b1; |
| 373 | even_valid <= 1'b0; |
| 374 | odd_valid <= 1'b1; |
| 375 | end // else: !if(odd_sop_set & (cache_filled_size < odd_num_ptr)) |
| 376 | |
| 377 | end else begin |
| 378 | TxIfState <= IDLE; |
| 379 | // synopsys translate_off |
| 380 | $display("%m CacheTags Invalid -- ERROR Time=%t",$time); |
| 381 | // synopsys translate_on |
| 382 | end |
| 383 | end // else: !if(cache_read_status) |
| 384 | |
| 385 | end // case: PARSE_DESCRIPTOR |
| 386 | XLATE_ADDR: begin |
| 387 | xlate_addr <= 1'b0; |
| 388 | if(page_xlate_error_dma ) begin |
| 389 | set_pkt_part_err_dma <= 1'b1; |
| 390 | // dmc_txc_dma_error <= 1'b1; |
| 391 | TxIfState <= ERROR; |
| 392 | end else if(!xlate_done) begin |
| 393 | TxIfState <= XLATE_ADDR; |
| 394 | end else begin // if (!xlate_done) |
| 395 | if(reset_sm) begin |
| 396 | gotnxtdesc <= 1'b0; |
| 397 | cache_ready <= 1'b0; |
| 398 | end else begin |
| 399 | gotnxtdesc <= 1'b1; |
| 400 | cache_ready <= 1'b1; |
| 401 | end |
| 402 | dmc_txc_dma_descriptor <= dma_descriptor_xlate; |
| 403 | if(even_valid & ~odd_valid) begin |
| 404 | TxIfState <= SEND_EVEN_DESC; |
| 405 | end else if( odd_valid & ~even_valid) begin |
| 406 | TxIfState <= SEND_ODD_DESC; |
| 407 | end |
| 408 | end // else: !if(!xlate_done) |
| 409 | end |
| 410 | SEND_EVEN_DESC: begin |
| 411 | go_back_to_even <= 1'b0; |
| 412 | go_back_to_odd <= 1'b0; |
| 413 | if(reset_sm & tx_dma_cfg_dma_stop) begin |
| 414 | go_back_to_even <= 1'b1; |
| 415 | go_back_to_odd <= 1'b0; |
| 416 | cache_ready <= 1'b0; |
| 417 | sm_reset_done <= 1'b1; |
| 418 | gotnxtdesc <= 1'b0; |
| 419 | TxIfState <= STOP_STATE; |
| 420 | end else if(reset_sm) begin |
| 421 | sm_reset_done <= 1'b1; |
| 422 | TxIfState <= IDLE; |
| 423 | cache_ready <= 1'b0; |
| 424 | gotnxtdesc <= 1'b0; |
| 425 | end else if(getnxtdesc) begin |
| 426 | gotnxtdesc <= 1'b0; |
| 427 | //inc_head_shadow <= 1'b1; |
| 428 | TxIfState <= CHECK_ODD_VALID_INC; |
| 429 | end else begin |
| 430 | TxIfState <= SEND_EVEN_DESC; |
| 431 | end // else: !if(getnxtdesc) |
| 432 | end // case: SEND_EVEN_DESC |
| 433 | CHECK_ODD_VALID_INC: begin |
| 434 | //inc_head_shadow <= 1'b0; |
| 435 | gotnxtdesc <= 1'b0; |
| 436 | TxIfState <= CHECK_ODD_VALID; |
| 437 | end // case: CHECK_ODD_VALID_INC |
| 438 | CHECK_ODD_VALID: begin |
| 439 | //inc_head_shadow <= 1'b0; |
| 440 | // Check for partials also |
| 441 | if(!dma_cache_tags_d[1]) begin |
| 442 | TxIfState <= IDLE; |
| 443 | end else begin |
| 444 | if(cache_entry_valid) begin |
| 445 | if(odd_sop_set & (cache_filled_size < odd_num_ptr)) begin |
| 446 | TxIfState <=CHECK_ODD_VALID; |
| 447 | partial_descriptor <= 1'b1; |
| 448 | // Just wait here |
| 449 | end else begin // if (odd_sop_set & (cache_filled_size < odd_num_ptr)) |
| 450 | TxIfState <= XLATE_ADDR; |
| 451 | partial_descriptor <= 1'b0; |
| 452 | dma_descriptor_toxlate <= dmc_txc_dma_descriptor_o; |
| 453 | xlate_addr <= 1'b1; |
| 454 | even_valid <= 1'b0; |
| 455 | odd_valid <= 1'b1; |
| 456 | end // else: !if(odd_sop_set & (cache_filled_size < odd_num_ptr)) |
| 457 | end else begin // if (cache_entry_valid) |
| 458 | TxIfState <= RESET_CACHE_POINTERS; |
| 459 | reset_cache_pointers <= 1'b1; |
| 460 | end // else: !if(cache_entry_valid) |
| 461 | end // else: !if(!dma_cache_tags_d[1]) |
| 462 | end // case: CHECK_ODD_VALID |
| 463 | SEND_ODD_DESC: begin |
| 464 | go_back_to_even <= 1'b0; |
| 465 | go_back_to_odd <= 1'b0; |
| 466 | if(reset_sm & tx_dma_cfg_dma_stop) begin |
| 467 | go_back_to_even <= 1'b0; |
| 468 | go_back_to_odd <= 1'b1; |
| 469 | sm_reset_done <= 1'b1; |
| 470 | cache_ready <= 1'b0; |
| 471 | gotnxtdesc <= 1'b0; |
| 472 | TxIfState <= STOP_STATE; |
| 473 | end else if(reset_sm) begin |
| 474 | sm_reset_done <= 1'b1; |
| 475 | TxIfState <= IDLE; |
| 476 | cache_ready <= 1'b0; |
| 477 | gotnxtdesc <= 1'b0; |
| 478 | end else if(getnxtdesc) begin |
| 479 | gotnxtdesc <= 1'b0; |
| 480 | //inc_head_shadow <= 1'b1; |
| 481 | TxIfState <= CHECK_NEXT_ENTRY_INC; |
| 482 | end else begin // if (getnxtdesc) |
| 483 | TxIfState <= SEND_ODD_DESC; |
| 484 | end // else: !if(getnxtdesc) |
| 485 | end // case: SEND_ODD_DESC |
| 486 | CHECK_NEXT_ENTRY_INC: begin |
| 487 | //inc_head_shadow <= 1'b0; |
| 488 | gotnxtdesc <= 1'b0; |
| 489 | TxIfState <= CHECK_NEXT_ENTRY; |
| 490 | end // case: CHECK_NEXT_ENTRY_INC |
| 491 | CHECK_NEXT_ENTRY: begin |
| 492 | //inc_head_shadow <= 1'b0; |
| 493 | gotnxtdesc <= 1'b0; |
| 494 | if(cache_entry_valid) begin |
| 495 | TxIfState <= IDLE; |
| 496 | end else begin // if (cache_entry_valid) |
| 497 | TxIfState <= RESET_CACHE_POINTERS; |
| 498 | reset_cache_pointers <= 1'b1; |
| 499 | end // else: !if(cache_entry_valid) |
| 500 | end // case: CHECK_NEXT_ENTRY |
| 501 | RESET_CACHE_POINTERS: begin |
| 502 | cache_ready <= 1'b0; |
| 503 | reset_cache_pointers <= 1'b0; |
| 504 | TxIfState <= IDLE; |
| 505 | end // case: RESET_CACHE_POINTERS |
| 506 | |
| 507 | STOP_STATE: begin |
| 508 | sm_reset_done <= 1'b0; |
| 509 | if(tx_dma_cfg_dma_stop) begin |
| 510 | cache_ready <= 1'b0; |
| 511 | gotnxtdesc <= 1'b0; |
| 512 | TxIfState <= STOP_STATE; |
| 513 | end else begin |
| 514 | cache_ready <= 1'b1; |
| 515 | gotnxtdesc <= 1'b1; |
| 516 | if(go_back_to_even) |
| 517 | TxIfState <= SEND_EVEN_DESC; |
| 518 | else if(go_back_to_odd) |
| 519 | TxIfState <= SEND_ODD_DESC; |
| 520 | end |
| 521 | end |
| 522 | ERROR: begin |
| 523 | set_pkt_part_err_dma <= 1'b0; |
| 524 | cache_ready <= 1'b0; |
| 525 | set_pref_buf_par_err_dma <= 1'b0; |
| 526 | if(reset_sm) begin // stay here untill reset is asserted from s/w |
| 527 | TxIfState <= IDLE; // go back to idle for now!! |
| 528 | sm_reset_done <= 1'b1; |
| 529 | end |
| 530 | end // case: ERROR |
| 531 | default: TxIfState <= IDLE; |
| 532 | endcase // case(TxIfState) |
| 533 | end // else: !if(!Reset_L) |
| 534 | |
| 535 | |
| 536 | |
| 537 | always@(/*AUTOSENSE*/TxIfState or getnxtdesc) begin |
| 538 | inc_head_shadow = ((TxIfState==SEND_ODD_DESC) | (TxIfState==SEND_EVEN_DESC )) & getnxtdesc; |
| 539 | end |
| 540 | |
| 541 | |
| 542 | |
| 543 | parameter PAGE_XLATE_IDLE = 4'h0, |
| 544 | CHECK_PAGE_STATUS = 4'h1, |
| 545 | PAGE_XLATE_ERROR = 4'h2; |
| 546 | |
| 547 | //VCS coverage off |
| 548 | // synopsys translate_off |
| 549 | reg [192:1] PAGE_XLATE_STATE; |
| 550 | |
| 551 | always @(page_xlate_state) |
| 552 | begin |
| 553 | case(page_xlate_state) |
| 554 | PAGE_XLATE_IDLE : PAGE_XLATE_STATE = "PAGE_XLATE_IDLE"; |
| 555 | CHECK_PAGE_STATUS: PAGE_XLATE_STATE = "CHECK_PAGE_STATUS"; |
| 556 | PAGE_XLATE_ERROR : PAGE_XLATE_STATE = "PAGE_XLATE_ERROR"; |
| 557 | default : PAGE_XLATE_STATE = "UNKNOWN"; |
| 558 | endcase |
| 559 | end |
| 560 | // synopsys translate_on |
| 561 | //VCS coverage on |
| 562 | |
| 563 | |
| 564 | |
| 565 | always@(posedge SysClk) begin |
| 566 | if (!Reset_L) begin |
| 567 | page_xlate_state <= PAGE_XLATE_IDLE; |
| 568 | xlate_done <= 1'b0; |
| 569 | page0_match <= 1'b0; |
| 570 | page1_match <= 1'b0; |
| 571 | dma_descriptor_xlate <= 64'h0; |
| 572 | page_xlate_error_dma <= 1'b0; |
| 573 | pkt_part_error_address_dma <= 44'h0; |
| 574 | end else begin |
| 575 | case(page_xlate_state) // synopsys parallel_case |
| 576 | |
| 577 | PAGE_XLATE_IDLE: begin |
| 578 | xlate_done <= 1'b0; |
| 579 | page_xlate_error_dma <= 1'b0; |
| 580 | page0_match <= 1'b0; |
| 581 | page1_match <= 1'b0; |
| 582 | |
| 583 | if(xlate_addr ) begin |
| 584 | dma_descriptor_xlate <= dma_descriptor_toxlate; |
| 585 | if( ~page0_valid_dma & ~page1_valid_dma ) begin |
| 586 | // Set ERROR Flags? |
| 587 | pkt_part_error_address_dma <= dma_descriptor_toxlate[43:0]; |
| 588 | page_xlate_state <= PAGE_XLATE_ERROR; |
| 589 | page_xlate_error_dma <= 1'b1; |
| 590 | end else begin |
| 591 | page_xlate_state <= CHECK_PAGE_STATUS; |
| 592 | page0_reloc_addr <= ((dma_descriptor_toxlate[43:12] & ~page0_mask_dma) | |
| 593 | ( page0_reloc_dma & page0_mask_dma)) ; |
| 594 | page0_match <= page0_valid_dma & |
| 595 | ((page0_mask_dma & dma_descriptor_toxlate [43:12] ) == page0_value_dma ); |
| 596 | |
| 597 | page1_reloc_addr <= ((dma_descriptor_toxlate[43:12] & ~page1_mask_dma) | |
| 598 | ( page1_reloc_dma & page1_mask_dma)) ; |
| 599 | |
| 600 | page1_match <= page1_valid_dma & |
| 601 | ((page1_mask_dma & dma_descriptor_toxlate [43:12] ) == page1_value_dma ); |
| 602 | end // else: !if( ~page0_valid_dma & ~page1_valid_dma ) |
| 603 | end |
| 604 | end // case: PAGE_XLATE_IDLE |
| 605 | |
| 606 | CHECK_PAGE_STATUS: begin |
| 607 | if(page0_match) begin |
| 608 | xlate_done <= 1'b1; |
| 609 | dma_descriptor_xlate <= {dma_descriptor_toxlate[63:44],page0_reloc_addr,dma_descriptor_toxlate[11:0]}; |
| 610 | page_xlate_state <= PAGE_XLATE_IDLE; |
| 611 | end else if(page1_match) begin |
| 612 | xlate_done <= 1'b1; |
| 613 | dma_descriptor_xlate <= {dma_descriptor_toxlate[63:44],page1_reloc_addr,dma_descriptor_toxlate[11:0]}; |
| 614 | page_xlate_state <= PAGE_XLATE_IDLE; |
| 615 | end else begin |
| 616 | page_xlate_error_dma <= 1'b1; |
| 617 | pkt_part_error_address_dma <= dma_descriptor_toxlate[43:0]; |
| 618 | page_xlate_state <= PAGE_XLATE_ERROR; |
| 619 | end |
| 620 | end // case: CHECK_PAGE_STATUS |
| 621 | |
| 622 | PAGE_XLATE_ERROR: begin |
| 623 | // Go back to IDLE -- for now |
| 624 | // xlate_done <= 1'b1; |
| 625 | page_xlate_error_dma <= 1'b0; |
| 626 | dma_descriptor_xlate <= dma_descriptor_toxlate; |
| 627 | page_xlate_state <= PAGE_XLATE_IDLE; |
| 628 | // synopsys translate_off |
| 629 | $display(" %m: Warning-- Page translation failure Time - %t",$time); |
| 630 | // synopsys translate_on |
| 631 | end |
| 632 | // default: begin |
| 633 | // page_xlate_state <= 4'hx; |
| 634 | // dma_descriptor_xlate <= 64'hx; |
| 635 | // end |
| 636 | endcase // case(page_xlate_state) |
| 637 | end // else: !if(!Reset_L) |
| 638 | end // always@ (posedge SysClk) |
| 639 | |
| 640 | assign dmc_txc_dma_partial = partial_descriptor; |
| 641 | |
| 642 | endmodule // niu_dmc_txcif |
| 643 | |
| 644 | |
| 645 | |