| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_txc_tdmc_context.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /********************************************************************* |
| 36 | * |
| 37 | * niu_txc_tdmc_context.v |
| 38 | * |
| 39 | * TXC TDMC DMA Context |
| 40 | * |
| 41 | * Orignal Author(s): Rahoul Puri |
| 42 | * Modifier(s): |
| 43 | * Project(s): Neptune/Niagara 2 |
| 44 | * |
| 45 | * Copyright (c) 2004 Sun Microsystems, Inc. |
| 46 | * |
| 47 | * All Rights Reserved. |
| 48 | * |
| 49 | * This verilog model is the confidential and proprietary property of |
| 50 | * Sun Microsystems, Inc., and the possession or use of this model |
| 51 | * requires a written license from Sun Microsystems, Inc. |
| 52 | * |
| 53 | **********************************************************************/ |
| 54 | |
| 55 | `include "timescale.v" |
| 56 | |
| 57 | module niu_txc_tdmc_context ( |
| 58 | SysClk, |
| 59 | Reset_L, |
| 60 | |
| 61 | Port0_DMA_inc_head, |
| 62 | Port0_DMA_reset_done, |
| 63 | Port0_DMA_mark_bit, |
| 64 | Port0_DMA_inc_pkt_cnt, |
| 65 | Port0_SetGetNextDescDMA, |
| 66 | |
| 67 | Port1_DMA_inc_head, |
| 68 | Port1_DMA_reset_done, |
| 69 | Port1_DMA_mark_bit, |
| 70 | Port1_DMA_inc_pkt_cnt, |
| 71 | Port1_SetGetNextDescDMA, |
| 72 | |
| 73 | Port2_DMA_inc_head, |
| 74 | Port2_DMA_reset_done, |
| 75 | Port2_DMA_mark_bit, |
| 76 | Port2_DMA_inc_pkt_cnt, |
| 77 | Port2_SetGetNextDescDMA, |
| 78 | |
| 79 | Port3_DMA_inc_head, |
| 80 | Port3_DMA_reset_done, |
| 81 | Port3_DMA_mark_bit, |
| 82 | Port3_DMA_inc_pkt_cnt, |
| 83 | Port3_SetGetNextDescDMA, |
| 84 | |
| 85 | DMC_TXC_DMA_GotNxtDesc, |
| 86 | TXC_DMC_DMA_GetNxtDesc, |
| 87 | TXC_DMC_DMA_inc_head, |
| 88 | TXC_DMC_DMA_reset_done, |
| 89 | TXC_DMC_DMA_mark_bit, |
| 90 | TXC_DMC_DMA_inc_pkt_cnt |
| 91 | ); |
| 92 | |
| 93 | `include "txc_defines.h" |
| 94 | |
| 95 | // Global Signals |
| 96 | input SysClk; |
| 97 | input Reset_L; |
| 98 | |
| 99 | // Port Interfaces |
| 100 | input Port0_DMA_inc_head; |
| 101 | input Port0_DMA_reset_done; |
| 102 | input Port0_DMA_mark_bit; |
| 103 | input Port0_DMA_inc_pkt_cnt; |
| 104 | input Port0_SetGetNextDescDMA; |
| 105 | |
| 106 | input Port1_DMA_inc_head; |
| 107 | input Port1_DMA_reset_done; |
| 108 | input Port1_DMA_mark_bit; |
| 109 | input Port1_DMA_inc_pkt_cnt; |
| 110 | input Port1_SetGetNextDescDMA; |
| 111 | |
| 112 | input Port2_DMA_inc_head; |
| 113 | input Port2_DMA_reset_done; |
| 114 | input Port2_DMA_mark_bit; |
| 115 | input Port2_DMA_inc_pkt_cnt; |
| 116 | input Port2_SetGetNextDescDMA; |
| 117 | |
| 118 | input Port3_DMA_inc_head; |
| 119 | input Port3_DMA_reset_done; |
| 120 | input Port3_DMA_mark_bit; |
| 121 | input Port3_DMA_inc_pkt_cnt; |
| 122 | input Port3_SetGetNextDescDMA; |
| 123 | |
| 124 | // TDMC Interface |
| 125 | input DMC_TXC_DMA_GotNxtDesc; |
| 126 | |
| 127 | output TXC_DMC_DMA_GetNxtDesc; |
| 128 | output TXC_DMC_DMA_inc_head; |
| 129 | output TXC_DMC_DMA_reset_done; |
| 130 | output TXC_DMC_DMA_mark_bit; |
| 131 | output TXC_DMC_DMA_inc_pkt_cnt; |
| 132 | |
| 133 | reg TXC_DMC_DMA_GetNxtDesc; |
| 134 | reg TXC_DMC_DMA_inc_head; |
| 135 | reg TXC_DMC_DMA_reset_done; |
| 136 | reg TXC_DMC_DMA_mark_bit; |
| 137 | reg TXC_DMC_DMA_inc_pkt_cnt; |
| 138 | |
| 139 | /*--------------------------------------------------------------*/ |
| 140 | // Wires & Registers |
| 141 | /*--------------------------------------------------------------*/ |
| 142 | wire dma_inc_head; |
| 143 | wire dma_reset_done; |
| 144 | wire dma_mark_bit; |
| 145 | wire dma_inc_pkt_cnt; |
| 146 | wire setGetNextDescDMA; |
| 147 | |
| 148 | /*--------------------------------------------------------------*/ |
| 149 | // Assigns |
| 150 | /*--------------------------------------------------------------*/ |
| 151 | assign dma_inc_head = (Port0_DMA_inc_head | Port1_DMA_inc_head |
| 152 | | |
| 153 | Port2_DMA_inc_head | Port3_DMA_inc_head |
| 154 | ); |
| 155 | |
| 156 | assign dma_reset_done = (Port0_DMA_reset_done | Port1_DMA_reset_done |
| 157 | | |
| 158 | Port2_DMA_reset_done | Port3_DMA_reset_done |
| 159 | ); |
| 160 | |
| 161 | assign dma_mark_bit = (Port0_DMA_mark_bit | Port1_DMA_mark_bit |
| 162 | | |
| 163 | Port2_DMA_mark_bit | Port3_DMA_mark_bit |
| 164 | ); |
| 165 | |
| 166 | assign dma_inc_pkt_cnt = (Port0_DMA_inc_pkt_cnt | Port1_DMA_inc_pkt_cnt |
| 167 | | |
| 168 | Port2_DMA_inc_pkt_cnt | Port3_DMA_inc_pkt_cnt |
| 169 | ); |
| 170 | |
| 171 | assign setGetNextDescDMA = (Port3_SetGetNextDescDMA | Port2_SetGetNextDescDMA |
| 172 | | |
| 173 | Port1_SetGetNextDescDMA | Port0_SetGetNextDescDMA); |
| 174 | |
| 175 | /*--------------------------------------------------------------*/ |
| 176 | // Logic |
| 177 | /*--------------------------------------------------------------*/ |
| 178 | always @(posedge SysClk) |
| 179 | if (!Reset_L) TXC_DMC_DMA_inc_head <= #`SD 1'b0; |
| 180 | else TXC_DMC_DMA_inc_head <= #`SD dma_inc_head; |
| 181 | |
| 182 | always @(posedge SysClk) |
| 183 | if (!Reset_L) TXC_DMC_DMA_reset_done <= #`SD 1'b0; |
| 184 | else TXC_DMC_DMA_reset_done <= #`SD dma_reset_done; |
| 185 | |
| 186 | always @(posedge SysClk) |
| 187 | if (!Reset_L) TXC_DMC_DMA_mark_bit <= #`SD 1'b0; |
| 188 | else TXC_DMC_DMA_mark_bit <= #`SD dma_mark_bit; |
| 189 | |
| 190 | always @(posedge SysClk) |
| 191 | if (!Reset_L) TXC_DMC_DMA_inc_pkt_cnt <= #`SD 1'b0; |
| 192 | else TXC_DMC_DMA_inc_pkt_cnt <= #`SD dma_inc_pkt_cnt; |
| 193 | |
| 194 | always @(posedge SysClk) |
| 195 | if (!Reset_L) TXC_DMC_DMA_GetNxtDesc <= #`SD 1'b0; |
| 196 | else if (setGetNextDescDMA) TXC_DMC_DMA_GetNxtDesc <= #`SD 1'b1; |
| 197 | else if (DMC_TXC_DMA_GotNxtDesc) TXC_DMC_DMA_GetNxtDesc <= #`SD 1'b0; |
| 198 | |
| 199 | endmodule |