| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: sio_opcc_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module sio_opcc_ctl ( |
| 36 | l2clk, |
| 37 | olc0_opcc_req, |
| 38 | olc1_opcc_req, |
| 39 | olc2_opcc_req, |
| 40 | olc3_opcc_req, |
| 41 | olc4_opcc_req, |
| 42 | olc5_opcc_req, |
| 43 | olc6_opcc_req, |
| 44 | olc7_opcc_req, |
| 45 | olc0_opcc_dmureq, |
| 46 | olc1_opcc_dmureq, |
| 47 | olc2_opcc_dmureq, |
| 48 | olc3_opcc_dmureq, |
| 49 | olc4_opcc_dmureq, |
| 50 | olc5_opcc_dmureq, |
| 51 | olc6_opcc_dmureq, |
| 52 | olc7_opcc_dmureq, |
| 53 | olc0_opcc_datareq, |
| 54 | olc1_opcc_datareq, |
| 55 | olc2_opcc_datareq, |
| 56 | olc3_opcc_datareq, |
| 57 | olc4_opcc_datareq, |
| 58 | olc5_opcc_datareq, |
| 59 | olc6_opcc_datareq, |
| 60 | olc7_opcc_datareq, |
| 61 | l2sio_v_bits, |
| 62 | l2sio_j_bits, |
| 63 | l2sio_r_bits, |
| 64 | l2sio_o_bits, |
| 65 | l2sio_s_bits, |
| 66 | ojc0_opcc_sync, |
| 67 | ojc1_opcc_sync, |
| 68 | ojc2_opcc_sync, |
| 69 | ojc3_opcc_sync, |
| 70 | ojc4_opcc_sync, |
| 71 | ojc5_opcc_sync, |
| 72 | ojc6_opcc_sync, |
| 73 | ojc7_opcc_sync, |
| 74 | ojc0_opcc_ack, |
| 75 | ojc1_opcc_ack, |
| 76 | ojc2_opcc_ack, |
| 77 | ojc3_opcc_ack, |
| 78 | ojc4_opcc_ack, |
| 79 | ojc5_opcc_ack, |
| 80 | ojc6_opcc_ack, |
| 81 | ojc7_opcc_ack, |
| 82 | old0_opcc_jtag, |
| 83 | old1_opcc_jtag, |
| 84 | old2_opcc_jtag, |
| 85 | old3_opcc_jtag, |
| 86 | old4_opcc_jtag, |
| 87 | old5_opcc_jtag, |
| 88 | old6_opcc_jtag, |
| 89 | old7_opcc_jtag, |
| 90 | sio_tcu_vld, |
| 91 | sio_tcu_data, |
| 92 | sio_sii_opcc_ipcc_niu_by_deq, |
| 93 | sio_sii_opcc_ipcc_niu_by_cnt, |
| 94 | sio_sii_opcc_ipcc_niu_or_deq, |
| 95 | sio_sii_opcc_ipcc_dmu_by_deq, |
| 96 | sio_sii_opcc_ipcc_dmu_by_cnt, |
| 97 | sio_sii_opcc_ipcc_dmu_or_deq, |
| 98 | array_wr_inhibit_cmp, |
| 99 | array_wr_inhibit_io, |
| 100 | array_wr_inhibit, |
| 101 | opcc_olc0_gnt, |
| 102 | opcc_olc1_gnt, |
| 103 | opcc_olc2_gnt, |
| 104 | opcc_olc3_gnt, |
| 105 | opcc_olc4_gnt, |
| 106 | opcc_olc5_gnt, |
| 107 | opcc_olc6_gnt, |
| 108 | opcc_olc7_gnt, |
| 109 | opcc_opdc_gnt0_opc0, |
| 110 | opcc_opdc_gnt2_opc0, |
| 111 | opcc_opdc_gnt4_opc0, |
| 112 | opcc_opdc_gnt6_opc0, |
| 113 | opcc_opdc_gnt01_opc1, |
| 114 | opcc_opdc_gnt45_opc1, |
| 115 | opcc_opdc_gnt0123_opc1, |
| 116 | opcc_opddq00_wr_addr, |
| 117 | opcc_opddq10_wr_addr, |
| 118 | opcc_opddq01_wr_addr, |
| 119 | opcc_opddq11_wr_addr, |
| 120 | opcc_opdhq0_wr_addr, |
| 121 | opcc_opdhq1_wr_addr, |
| 122 | opcc_opddq00_wr_en, |
| 123 | opcc_opddq10_wr_en, |
| 124 | opcc_opddq01_wr_en, |
| 125 | opcc_opddq11_wr_en, |
| 126 | opcc_opdhq0_wr_en, |
| 127 | opcc_opdhq1_wr_en, |
| 128 | cmp_io_sync_en_in, |
| 129 | io_cmp_sync_en_in, |
| 130 | opcc_opcs_opddq00_wr_addr, |
| 131 | opcc_opcs_opddq10_wr_addr, |
| 132 | opcc_opcs_opddq01_wr_addr, |
| 133 | opcc_opcs_opddq11_wr_addr, |
| 134 | opcc_opcs_opdhq0_wr_addr, |
| 135 | opcc_opcs_opdhq1_wr_addr, |
| 136 | opcs_opcc_opdhq0_rd_addr, |
| 137 | opcs_opcc_opdhq1_rd_addr, |
| 138 | tcu_scan_en, |
| 139 | scan_in, |
| 140 | tcu_aclk, |
| 141 | tcu_bclk, |
| 142 | tcu_pce_ov, |
| 143 | tcu_clk_stop, |
| 144 | scan_out); |
| 145 | wire se; |
| 146 | wire siclk; |
| 147 | wire soclk; |
| 148 | wire pce_ov; |
| 149 | wire stop; |
| 150 | wire l1clk; |
| 151 | wire spares_scanin; |
| 152 | wire spares_scanout; |
| 153 | wire tcu_vld; |
| 154 | wire tcu_data; |
| 155 | wire ff_tcu_jtag_scanin; |
| 156 | wire ff_tcu_jtag_scanout; |
| 157 | wire [7:0] sio_sii_opcc_ipcc_niu_by_cnt_mask; |
| 158 | wire [1:0] niubysum10; |
| 159 | wire [1:0] niubysum32; |
| 160 | wire [1:0] niubysum54; |
| 161 | wire [1:0] niubysum76; |
| 162 | wire [3:0] niubysum; |
| 163 | wire [3:0] sio_sii_opcc_ipcc_niu_by_cnt_next; |
| 164 | wire sio_sii_opcc_ipcc_niu_by_deq_next; |
| 165 | wire sio_sii_opcc_ipcc_niu_or_deq_next; |
| 166 | wire [7:0] sio_sii_opcc_ipcc_dmu_by_cnt_mask; |
| 167 | wire [1:0] dmubysum10; |
| 168 | wire [1:0] dmubysum32; |
| 169 | wire [1:0] dmubysum54; |
| 170 | wire [1:0] dmubysum76; |
| 171 | wire [3:0] dmubysum; |
| 172 | wire [3:0] sio_sii_opcc_ipcc_dmu_by_cnt_next; |
| 173 | wire sio_sii_opcc_ipcc_dmu_by_deq_next; |
| 174 | wire sio_sii_opcc_ipcc_dmu_or_deq_next; |
| 175 | wire ff_dqcnt_scanin; |
| 176 | wire ff_dqcnt_scanout; |
| 177 | wire [4:0] sync_in_opdhq0_rd_addr; |
| 178 | wire io_cmp_sync_en; |
| 179 | wire [4:0] sync_out_opdhq0_rd_addr; |
| 180 | wire ff_syn_opdhq0_rd_addr_scanin; |
| 181 | wire ff_syn_opdhq0_rd_addr_scanout; |
| 182 | wire ff_opdhq0_rd_addr_scanin; |
| 183 | wire ff_opdhq0_rd_addr_scanout; |
| 184 | wire [4:0] opdhq0_rd_addr; |
| 185 | wire [4:0] sync_in_opdhq1_rd_addr; |
| 186 | wire [4:0] sync_out_opdhq1_rd_addr; |
| 187 | wire ff_syn_opdhq1_rd_addr_scanin; |
| 188 | wire ff_syn_opdhq1_rd_addr_scanout; |
| 189 | wire ff_opdhq1_rd_addr_scanin; |
| 190 | wire ff_opdhq1_rd_addr_scanout; |
| 191 | wire [4:0] opdhq1_rd_addr; |
| 192 | wire ff_opdhq0sub_scanin; |
| 193 | wire ff_opdhq0sub_scanout; |
| 194 | wire [4:0] opdhq0sub_l; |
| 195 | wire [4:0] opdhq0sub; |
| 196 | wire ff_opdhq1sub_scanin; |
| 197 | wire ff_opdhq1sub_scanout; |
| 198 | wire [4:0] opdhq1sub_l; |
| 199 | wire [4:0] opdhq1sub; |
| 200 | wire [4:0] opdhq0_rd_addr_early; |
| 201 | wire [4:0] opdhq1_rd_addr_early; |
| 202 | wire [4:0] opdhq0_wr_addr_early; |
| 203 | wire opdhq0_wr_addrinc; |
| 204 | wire [4:0] opdhq0_wr_addr; |
| 205 | wire [4:0] opdhq1_wr_addr_early; |
| 206 | wire opdhq1_wr_addrinc; |
| 207 | wire [4:0] opdhq1_wr_addr; |
| 208 | wire [1:0] opdhq0sub_unused; |
| 209 | wire [1:0] opdhq1sub_unused; |
| 210 | wire dmureqfull; |
| 211 | wire entreqfull; |
| 212 | wire [7:0] gnt_d1; |
| 213 | wire [5:0] gnt_d2; |
| 214 | wire [7:0] queuecredit; |
| 215 | wire [7:0] nextreq; |
| 216 | wire [7:0] gnt; |
| 217 | wire [7:0] newwinner; |
| 218 | wire [7:0] gnt_hist; |
| 219 | wire busbusy; |
| 220 | wire read_slph; |
| 221 | wire [7:0] nextwinner; |
| 222 | wire [2:0] buscnt; |
| 223 | wire nextread_slph; |
| 224 | wire [7:0] winner; |
| 225 | wire [7:0] nextgnt; |
| 226 | wire [7:0] gnt_hist_l; |
| 227 | wire ff_slpstates_scanin; |
| 228 | wire ff_slpstates_scanout; |
| 229 | wire [7:0] nextgntd1; |
| 230 | wire nextcycleis_slph; |
| 231 | wire nextdmuread_slph; |
| 232 | wire nextentread_slph; |
| 233 | wire cycle_slph; |
| 234 | wire dmuread_slph; |
| 235 | wire entread_slph; |
| 236 | wire [7:0] dmuwinner; |
| 237 | wire [7:0] dmureq; |
| 238 | wire [7:0] entwinner; |
| 239 | wire [7:0] entreq; |
| 240 | wire [7:0] dmureadreq; |
| 241 | wire [7:0] readreq; |
| 242 | wire [7:0] entreadreq; |
| 243 | wire [2:0] buscnt_plus1; |
| 244 | wire buscnt_inc; |
| 245 | wire [2:0] buscnt_next; |
| 246 | wire ff_buscnt_scanin; |
| 247 | wire ff_buscnt_scanout; |
| 248 | wire opdhq0won; |
| 249 | wire opdhq1won; |
| 250 | wire opdhq0won_slph; |
| 251 | wire opdhq0won_d1; |
| 252 | wire opdhq1won_slph; |
| 253 | wire opdhq1won_d1; |
| 254 | wire opdhq0won_opc1; |
| 255 | wire opdhq1won_opc1; |
| 256 | wire [4:0] opdhq0_wr_addr_next; |
| 257 | wire [4:0] opdhq1_wr_addr_next; |
| 258 | wire opddq0x_wr_addrinc4_next; |
| 259 | wire opddq1x_wr_addrinc4_next; |
| 260 | wire opddq00_wr_addrinc_next; |
| 261 | wire dmuread_opc1; |
| 262 | wire dmuread_opc3; |
| 263 | wire dmuread_opc5; |
| 264 | wire dmuread_opc7; |
| 265 | wire opddq10_wr_addrinc_next; |
| 266 | wire entread_opc1; |
| 267 | wire entread_opc3; |
| 268 | wire entread_opc5; |
| 269 | wire entread_opc7; |
| 270 | wire opddq01_wr_addrinc_next; |
| 271 | wire dmuread_opc2; |
| 272 | wire dmuread_opc4; |
| 273 | wire dmuread_opc6; |
| 274 | wire dmuread_opc8; |
| 275 | wire opddq11_wr_addrinc_next; |
| 276 | wire entread_opc2; |
| 277 | wire entread_opc4; |
| 278 | wire entread_opc6; |
| 279 | wire entread_opc8; |
| 280 | wire [6:0] opddq00_wr_addr_next; |
| 281 | wire [6:0] opddq00_wr_addr; |
| 282 | wire opddq00_wr_addrinc; |
| 283 | wire [6:0] opddq10_wr_addr_next; |
| 284 | wire [6:0] opddq10_wr_addr; |
| 285 | wire opddq10_wr_addrinc; |
| 286 | wire [6:0] opddq01_wr_addr_next; |
| 287 | wire [6:0] opddq01_wr_addr; |
| 288 | wire opddq01_wr_addrinc; |
| 289 | wire [6:0] opddq11_wr_addr_next; |
| 290 | wire [6:0] opddq11_wr_addr; |
| 291 | wire opddq11_wr_addrinc; |
| 292 | wire ff_hqxwonstage_scanin; |
| 293 | wire ff_hqxwonstage_scanout; |
| 294 | wire ff_qxdatastage_scanin; |
| 295 | wire ff_qxdatastage_scanout; |
| 296 | wire ff_opdhq0_wr_addr_scanin; |
| 297 | wire ff_opdhq0_wr_addr_scanout; |
| 298 | wire ff_opdhq1_wr_addr_scanin; |
| 299 | wire ff_opdhq1_wr_addr_scanout; |
| 300 | wire ff_opddq00_wr_addr_scanin; |
| 301 | wire ff_opddq00_wr_addr_scanout; |
| 302 | wire ff_opddq10_wr_addr_scanin; |
| 303 | wire ff_opddq10_wr_addr_scanout; |
| 304 | wire ff_opddq01_wr_addr_scanin; |
| 305 | wire ff_opddq01_wr_addr_scanout; |
| 306 | wire ff_opddq11_wr_addr_scanin; |
| 307 | wire ff_opddq11_wr_addr_scanout; |
| 308 | wire ff_opddq00_wr_addrinc_scanin; |
| 309 | wire ff_opddq00_wr_addrinc_scanout; |
| 310 | wire ff_opddq01_wr_addrinc_scanin; |
| 311 | wire ff_opddq01_wr_addrinc_scanout; |
| 312 | wire ff_opddq10_wr_addrinc_scanin; |
| 313 | wire ff_opddq10_wr_addrinc_scanout; |
| 314 | wire ff_opddq11_wr_addrinc_scanin; |
| 315 | wire ff_opddq11_wr_addrinc_scanout; |
| 316 | wire ff_opddq00_wr_addr_d1_scanin; |
| 317 | wire ff_opddq00_wr_addr_d1_scanout; |
| 318 | wire [6:0] opddq00_wr_addr_d1; |
| 319 | wire [6:0] sync_in_opddq00_wr_addr; |
| 320 | wire cmp_io_sync_en; |
| 321 | wire [6:0] sync_out_opddq00_wr_addr; |
| 322 | wire ff_syn_opddq00_wr_addr_scanin; |
| 323 | wire ff_syn_opddq00_wr_addr_scanout; |
| 324 | wire ff_opddq01_wr_addr_d1_scanin; |
| 325 | wire ff_opddq01_wr_addr_d1_scanout; |
| 326 | wire [6:0] opddq01_wr_addr_d1; |
| 327 | wire [6:0] sync_in_opddq01_wr_addr; |
| 328 | wire [6:0] sync_out_opddq01_wr_addr; |
| 329 | wire ff_syn_opddq01_wr_addr_scanin; |
| 330 | wire ff_syn_opddq01_wr_addr_scanout; |
| 331 | wire ff_opddq10_wr_addr_d1_scanin; |
| 332 | wire ff_opddq10_wr_addr_d1_scanout; |
| 333 | wire [6:0] opddq10_wr_addr_d1; |
| 334 | wire [6:0] sync_in_opddq10_wr_addr; |
| 335 | wire [6:0] sync_out_opddq10_wr_addr; |
| 336 | wire ff_syn_opddq10_wr_addr_scanin; |
| 337 | wire ff_syn_opddq10_wr_addr_scanout; |
| 338 | wire ff_opddq11_wr_addr_d1_scanin; |
| 339 | wire ff_opddq11_wr_addr_d1_scanout; |
| 340 | wire [6:0] opddq11_wr_addr_d1; |
| 341 | wire [6:0] sync_in_opddq11_wr_addr; |
| 342 | wire [6:0] sync_out_opddq11_wr_addr; |
| 343 | wire ff_syn_opddq11_wr_addr_scanin; |
| 344 | wire ff_syn_opddq11_wr_addr_scanout; |
| 345 | wire ff_opdhq0_wr_addr_d1_scanin; |
| 346 | wire ff_opdhq0_wr_addr_d1_scanout; |
| 347 | wire [4:0] opdhq0_wr_addr_d1; |
| 348 | wire [4:0] sync_in_opdhq0_wr_addr; |
| 349 | wire [4:0] sync_out_opdhq0_wr_addr; |
| 350 | wire ff_syn_opdhq0_wr_addr_scanin; |
| 351 | wire ff_syn_opdhq0_wr_addr_scanout; |
| 352 | wire ff_opdhq1_wr_addr_d1_scanin; |
| 353 | wire ff_opdhq1_wr_addr_d1_scanout; |
| 354 | wire [4:0] opdhq1_wr_addr_d1; |
| 355 | wire [4:0] sync_in_opdhq1_wr_addr; |
| 356 | wire [4:0] sync_out_opdhq1_wr_addr; |
| 357 | wire ff_syn_opdhq1_wr_addr_scanin; |
| 358 | wire ff_syn_opdhq1_wr_addr_scanout; |
| 359 | wire sync_in_opdhq0_wr_en; |
| 360 | wire sync_out_opdhq0_wr_en_d1; |
| 361 | wire opdhq0_wr_en_tmp; |
| 362 | wire sync_out_opdhq0_wr_en; |
| 363 | wire sync_out_opdhq0_wr_en_d2; |
| 364 | wire ff_syn_opdhq0_wr_en_d1_scanin; |
| 365 | wire ff_syn_opdhq0_wr_en_d1_scanout; |
| 366 | wire ff_syn_opdhq0_wr_en_d2_scanin; |
| 367 | wire ff_syn_opdhq0_wr_en_d2_scanout; |
| 368 | wire sync_in_opdhq1_wr_en; |
| 369 | wire sync_out_opdhq1_wr_en_d1; |
| 370 | wire opdhq1_wr_en_tmp; |
| 371 | wire sync_out_opdhq1_wr_en; |
| 372 | wire sync_out_opdhq1_wr_en_d2; |
| 373 | wire ff_syn_opdhq1_wr_en_d1_scanin; |
| 374 | wire ff_syn_opdhq1_wr_en_d1_scanout; |
| 375 | wire ff_syn_opdhq1_wr_en_d2_scanin; |
| 376 | wire ff_syn_opdhq1_wr_en_d2_scanout; |
| 377 | wire reg_cmp_io_sync_en_scanin; |
| 378 | wire reg_cmp_io_sync_en_scanout; |
| 379 | wire reg_io_cmp_sync_en_scanin; |
| 380 | wire reg_io_cmp_sync_en_scanout; |
| 381 | |
| 382 | |
| 383 | input l2clk; |
| 384 | |
| 385 | input olc0_opcc_req; |
| 386 | input olc1_opcc_req; |
| 387 | input olc2_opcc_req; |
| 388 | input olc3_opcc_req; |
| 389 | input olc4_opcc_req; |
| 390 | input olc5_opcc_req; |
| 391 | input olc6_opcc_req; |
| 392 | input olc7_opcc_req; |
| 393 | |
| 394 | input olc0_opcc_dmureq; |
| 395 | input olc1_opcc_dmureq; |
| 396 | input olc2_opcc_dmureq; |
| 397 | input olc3_opcc_dmureq; |
| 398 | input olc4_opcc_dmureq; |
| 399 | input olc5_opcc_dmureq; |
| 400 | input olc6_opcc_dmureq; |
| 401 | input olc7_opcc_dmureq; |
| 402 | |
| 403 | input olc0_opcc_datareq; |
| 404 | input olc1_opcc_datareq; |
| 405 | input olc2_opcc_datareq; |
| 406 | input olc3_opcc_datareq; |
| 407 | input olc4_opcc_datareq; |
| 408 | input olc5_opcc_datareq; |
| 409 | input olc6_opcc_datareq; |
| 410 | input olc7_opcc_datareq; |
| 411 | |
| 412 | |
| 413 | input [7:0] l2sio_v_bits; // valid bit |
| 414 | input [7:0] l2sio_j_bits; // jtag bit |
| 415 | input [7:0] l2sio_r_bits; // read bit |
| 416 | input [7:0] l2sio_o_bits; // ordered bit |
| 417 | input [7:0] l2sio_s_bits; // source-bit (1=dmu, 0=ent) |
| 418 | |
| 419 | input ojc0_opcc_sync; |
| 420 | input ojc1_opcc_sync; |
| 421 | input ojc2_opcc_sync; |
| 422 | input ojc3_opcc_sync; |
| 423 | input ojc4_opcc_sync; |
| 424 | input ojc5_opcc_sync; |
| 425 | input ojc6_opcc_sync; |
| 426 | input ojc7_opcc_sync; |
| 427 | |
| 428 | input ojc0_opcc_ack; |
| 429 | input ojc1_opcc_ack; |
| 430 | input ojc2_opcc_ack; |
| 431 | input ojc3_opcc_ack; |
| 432 | input ojc4_opcc_ack; |
| 433 | input ojc5_opcc_ack; |
| 434 | input ojc6_opcc_ack; |
| 435 | input ojc7_opcc_ack; |
| 436 | |
| 437 | input old0_opcc_jtag; |
| 438 | input old1_opcc_jtag; |
| 439 | input old2_opcc_jtag; |
| 440 | input old3_opcc_jtag; |
| 441 | input old4_opcc_jtag; |
| 442 | input old5_opcc_jtag; |
| 443 | input old6_opcc_jtag; |
| 444 | input old7_opcc_jtag; |
| 445 | |
| 446 | |
| 447 | |
| 448 | // ================== JTAG_RAS ============= |
| 449 | output sio_tcu_vld; // assert for jtag read return valid |
| 450 | output sio_tcu_data; // bit 0 is transfered on first cycle...63 on last cycle |
| 451 | // ================== JTAG_RAS ============= |
| 452 | |
| 453 | |
| 454 | output sio_sii_opcc_ipcc_niu_by_deq; |
| 455 | output [3:0] sio_sii_opcc_ipcc_niu_by_cnt; |
| 456 | output sio_sii_opcc_ipcc_niu_or_deq; |
| 457 | |
| 458 | output sio_sii_opcc_ipcc_dmu_by_deq; |
| 459 | output [3:0] sio_sii_opcc_ipcc_dmu_by_cnt; |
| 460 | output sio_sii_opcc_ipcc_dmu_or_deq; |
| 461 | |
| 462 | input array_wr_inhibit_cmp; |
| 463 | input array_wr_inhibit_io; |
| 464 | output array_wr_inhibit; |
| 465 | |
| 466 | output opcc_olc0_gnt; |
| 467 | output opcc_olc1_gnt; |
| 468 | output opcc_olc2_gnt; |
| 469 | output opcc_olc3_gnt; |
| 470 | output opcc_olc4_gnt; |
| 471 | output opcc_olc5_gnt; |
| 472 | output opcc_olc6_gnt; |
| 473 | output opcc_olc7_gnt; |
| 474 | |
| 475 | output opcc_opdc_gnt0_opc0; |
| 476 | output opcc_opdc_gnt2_opc0; |
| 477 | output opcc_opdc_gnt4_opc0; |
| 478 | output opcc_opdc_gnt6_opc0; |
| 479 | output opcc_opdc_gnt01_opc1; |
| 480 | output opcc_opdc_gnt45_opc1; |
| 481 | output opcc_opdc_gnt0123_opc1; |
| 482 | |
| 483 | output [5:0] opcc_opddq00_wr_addr; // DMU dataq -- valid on opc1 |
| 484 | output [5:0] opcc_opddq10_wr_addr; // ENT dataq -- valid on opc1 |
| 485 | output [5:0] opcc_opddq01_wr_addr; // DMU dataq -- valid on opc1 |
| 486 | output [5:0] opcc_opddq11_wr_addr; // ENT dataq -- valid on opc1 |
| 487 | |
| 488 | output [3:0] opcc_opdhq0_wr_addr; // DMU hdrq -- valid on opc1 |
| 489 | output [3:0] opcc_opdhq1_wr_addr; // ENT hdrq -- valid on opc1 |
| 490 | |
| 491 | output opcc_opddq00_wr_en; // DMU dataq -- valid on opc1 |
| 492 | output opcc_opddq10_wr_en; // ENT dataq -- valid on opc1 |
| 493 | output opcc_opddq01_wr_en; // DMU dataq -- valid on opc1 |
| 494 | output opcc_opddq11_wr_en; // ENT dataq -- valid on opc1 |
| 495 | output opcc_opdhq0_wr_en; // DMU hdrq -- valid on opc1 |
| 496 | output opcc_opdhq1_wr_en; // ENT hdrq -- valid on opc1 |
| 497 | |
| 498 | input cmp_io_sync_en_in; // active high - ok to cross from CMP to IO clock domain |
| 499 | input io_cmp_sync_en_in; // active high - ok to cross from IO to CMP clock domain |
| 500 | output [6:0] opcc_opcs_opddq00_wr_addr; // DMU dataq -- cmp domain synced, gray-coded + 1 bit, valid on |
| 501 | output [6:0] opcc_opcs_opddq10_wr_addr; // ENT dataq -- cmp domain synced, gray-coded + 1 bit, valid on |
| 502 | output [6:0] opcc_opcs_opddq01_wr_addr; // DMU dataq -- cmp domain synced, gray-coded + 1 bit, valid on |
| 503 | output [6:0] opcc_opcs_opddq11_wr_addr; // ENT dataq -- cmp domain synced, gray-coded + 1 bit, valid on |
| 504 | |
| 505 | output [4:0] opcc_opcs_opdhq0_wr_addr; // DMU hdrq -- cmp domain synced, gray-coded + 1 bit, valid on |
| 506 | output [4:0] opcc_opcs_opdhq1_wr_addr; // ENT hdrq -- cmp domain synced, gray-coded + 1 bit, valid on |
| 507 | |
| 508 | |
| 509 | |
| 510 | input [4:0] opcs_opcc_opdhq0_rd_addr; // DMU hdrq -- io domain unsync, gray-coded + 1 bit, valid on |
| 511 | input [4:0] opcs_opcc_opdhq1_rd_addr; // ENT hdrq -- io domain unsync, gray-coded + 1 bit, valid on |
| 512 | |
| 513 | |
| 514 | input tcu_scan_en; |
| 515 | input scan_in; |
| 516 | input tcu_aclk; |
| 517 | input tcu_bclk; |
| 518 | input tcu_pce_ov; |
| 519 | input tcu_clk_stop; |
| 520 | output scan_out; |
| 521 | |
| 522 | /////////////////////////////////////// |
| 523 | // Scan chain connections |
| 524 | /////////////////////////////////////// |
| 525 | // scan renames |
| 526 | assign se = tcu_scan_en; |
| 527 | assign siclk = tcu_aclk; |
| 528 | assign soclk = tcu_bclk; |
| 529 | assign pce_ov = tcu_pce_ov; |
| 530 | assign stop = tcu_clk_stop; |
| 531 | assign array_wr_inhibit = array_wr_inhibit_cmp & array_wr_inhibit_io; |
| 532 | // end scan |
| 533 | |
| 534 | sio_opcc_ctl_l1clkhdr_ctl_macro clkgen ( |
| 535 | .l2clk (l2clk ), |
| 536 | .l1en (1'b1 ), |
| 537 | .l1clk (l1clk), |
| 538 | .pce_ov(pce_ov), |
| 539 | .stop(stop), |
| 540 | .se(se) |
| 541 | ); |
| 542 | //Spare gates |
| 543 | sio_opcc_ctl_spare_ctl_macro__num_3 spares ( |
| 544 | .scan_in(spares_scanin), |
| 545 | .scan_out(spares_scanout), |
| 546 | .l1clk (l1clk), |
| 547 | .siclk(siclk), |
| 548 | .soclk(soclk) |
| 549 | ); |
| 550 | |
| 551 | |
| 552 | |
| 553 | assign tcu_vld = |{ojc0_opcc_sync, |
| 554 | ojc1_opcc_sync, |
| 555 | ojc2_opcc_sync, |
| 556 | ojc3_opcc_sync, |
| 557 | ojc4_opcc_sync, |
| 558 | ojc5_opcc_sync, |
| 559 | ojc6_opcc_sync, |
| 560 | ojc7_opcc_sync}; |
| 561 | |
| 562 | assign tcu_data = |{old0_opcc_jtag , |
| 563 | old1_opcc_jtag , |
| 564 | old2_opcc_jtag , |
| 565 | old3_opcc_jtag , |
| 566 | old4_opcc_jtag , |
| 567 | old5_opcc_jtag , |
| 568 | old6_opcc_jtag , |
| 569 | old7_opcc_jtag}; |
| 570 | |
| 571 | sio_opcc_ctl_msff_ctl_macro__width_2 ff_tcu_jtag ( |
| 572 | .scan_in(ff_tcu_jtag_scanin), |
| 573 | .scan_out(ff_tcu_jtag_scanout), |
| 574 | .din ({tcu_vld, tcu_data}), |
| 575 | .dout ({sio_tcu_vld, sio_tcu_data}), |
| 576 | .l1clk(l1clk), |
| 577 | .siclk(siclk), |
| 578 | .soclk(soclk) |
| 579 | ); |
| 580 | |
| 581 | |
| 582 | assign sio_sii_opcc_ipcc_niu_by_cnt_mask[7:0] = (l2sio_v_bits[7:0] & ~l2sio_j_bits[7:0] & ~l2sio_o_bits[7:0] & ~l2sio_s_bits[7:0] & ~l2sio_r_bits[7:0]); |
| 583 | // implement summing of all 8 bits in the mask |
| 584 | assign niubysum10[1:0] = {&sio_sii_opcc_ipcc_niu_by_cnt_mask[1:0], ^sio_sii_opcc_ipcc_niu_by_cnt_mask[1:0]}; |
| 585 | assign niubysum32[1:0] = {&sio_sii_opcc_ipcc_niu_by_cnt_mask[3:2], ^sio_sii_opcc_ipcc_niu_by_cnt_mask[3:2]}; |
| 586 | assign niubysum54[1:0] = {&sio_sii_opcc_ipcc_niu_by_cnt_mask[5:4], ^sio_sii_opcc_ipcc_niu_by_cnt_mask[5:4]}; |
| 587 | assign niubysum76[1:0] = {&sio_sii_opcc_ipcc_niu_by_cnt_mask[7:6], ^sio_sii_opcc_ipcc_niu_by_cnt_mask[7:6]}; |
| 588 | assign niubysum[3:0] = {2'b00, niubysum32[1:0]} + {2'b00, niubysum10[1:0]} + {2'b00, niubysum76[1:0]} + {2'b00, niubysum54[1:0]}; |
| 589 | assign sio_sii_opcc_ipcc_niu_by_cnt_next[3:0] = niubysum[3:0]; |
| 590 | assign sio_sii_opcc_ipcc_niu_by_deq_next = |sio_sii_opcc_ipcc_niu_by_cnt_mask[7:0]; |
| 591 | assign sio_sii_opcc_ipcc_niu_or_deq_next = |(l2sio_v_bits[7:0] & ~l2sio_j_bits[7:0] & l2sio_o_bits[7:0] & ~l2sio_s_bits[7:0] & ~l2sio_r_bits[7:0]); |
| 592 | |
| 593 | |
| 594 | |
| 595 | |
| 596 | |
| 597 | assign sio_sii_opcc_ipcc_dmu_by_cnt_mask[7:0] = (l2sio_v_bits[7:0] & ~l2sio_j_bits[7:0] & ~l2sio_o_bits[7:0] & l2sio_s_bits[7:0] & ~l2sio_r_bits[7:0]); |
| 598 | // implement summing of all 8 bits in the mask |
| 599 | assign dmubysum10[1:0] = {&sio_sii_opcc_ipcc_dmu_by_cnt_mask[1:0], ^sio_sii_opcc_ipcc_dmu_by_cnt_mask[1:0]}; |
| 600 | assign dmubysum32[1:0] = {&sio_sii_opcc_ipcc_dmu_by_cnt_mask[3:2], ^sio_sii_opcc_ipcc_dmu_by_cnt_mask[3:2]}; |
| 601 | assign dmubysum54[1:0] = {&sio_sii_opcc_ipcc_dmu_by_cnt_mask[5:4], ^sio_sii_opcc_ipcc_dmu_by_cnt_mask[5:4]}; |
| 602 | assign dmubysum76[1:0] = {&sio_sii_opcc_ipcc_dmu_by_cnt_mask[7:6], ^sio_sii_opcc_ipcc_dmu_by_cnt_mask[7:6]}; |
| 603 | assign dmubysum[3:0] = {2'b00, dmubysum32[1:0]} + {2'b00, dmubysum10[1:0]} + {2'b00, dmubysum76[1:0]} + {2'b00, dmubysum54[1:0]}; |
| 604 | assign sio_sii_opcc_ipcc_dmu_by_cnt_next[3:0] = dmubysum[3:0]; |
| 605 | assign sio_sii_opcc_ipcc_dmu_by_deq_next = |sio_sii_opcc_ipcc_dmu_by_cnt_mask[7:0]; |
| 606 | assign sio_sii_opcc_ipcc_dmu_or_deq_next = |(l2sio_v_bits[7:0] & ~l2sio_j_bits[7:0] & l2sio_o_bits[7:0] & l2sio_s_bits[7:0] & ~l2sio_r_bits[7:0]); |
| 607 | |
| 608 | sio_opcc_ctl_msff_ctl_macro__width_12 ff_dqcnt ( |
| 609 | .scan_in(ff_dqcnt_scanin), |
| 610 | .scan_out(ff_dqcnt_scanout), |
| 611 | .din ({sio_sii_opcc_ipcc_niu_or_deq_next, sio_sii_opcc_ipcc_niu_by_deq_next, sio_sii_opcc_ipcc_niu_by_cnt_next[3:0], |
| 612 | sio_sii_opcc_ipcc_dmu_or_deq_next, sio_sii_opcc_ipcc_dmu_by_deq_next, sio_sii_opcc_ipcc_dmu_by_cnt_next[3:0]}), |
| 613 | |
| 614 | .dout ({sio_sii_opcc_ipcc_niu_or_deq, sio_sii_opcc_ipcc_niu_by_deq, sio_sii_opcc_ipcc_niu_by_cnt[3:0], |
| 615 | sio_sii_opcc_ipcc_dmu_or_deq, sio_sii_opcc_ipcc_dmu_by_deq, sio_sii_opcc_ipcc_dmu_by_cnt[3:0]}), |
| 616 | .l1clk(l1clk), |
| 617 | .siclk(siclk), |
| 618 | .soclk(soclk) |
| 619 | ); |
| 620 | |
| 621 | |
| 622 | |
| 623 | // Synchronize the gray coded read pointers from sio_opcs_ctl and compare with write pointer |
| 624 | // to generate full signals |
| 625 | |
| 626 | // until we have a sync macro cell, i'm using 2 msff_ctl_macros |
| 627 | assign sync_in_opdhq0_rd_addr[4:0] = io_cmp_sync_en ? opcs_opcc_opdhq0_rd_addr[4:0] : sync_out_opdhq0_rd_addr[4:0]; |
| 628 | |
| 629 | sio_opcc_ctl_msff_ctl_macro__width_5 ff_syn_opdhq0_rd_addr ( |
| 630 | .scan_in(ff_syn_opdhq0_rd_addr_scanin), |
| 631 | .scan_out(ff_syn_opdhq0_rd_addr_scanout), |
| 632 | .din (sync_in_opdhq0_rd_addr[4:0]), |
| 633 | .dout (sync_out_opdhq0_rd_addr[4:0]), |
| 634 | .l1clk(l1clk), |
| 635 | .siclk(siclk), |
| 636 | .soclk(soclk) |
| 637 | ); |
| 638 | sio_opcc_ctl_msff_ctl_macro__width_5 ff_opdhq0_rd_addr ( |
| 639 | .scan_in(ff_opdhq0_rd_addr_scanin), |
| 640 | .scan_out(ff_opdhq0_rd_addr_scanout), |
| 641 | .din (sync_out_opdhq0_rd_addr[4:0]), |
| 642 | .dout (opdhq0_rd_addr[4:0]), |
| 643 | .l1clk(l1clk), |
| 644 | .siclk(siclk), |
| 645 | .soclk(soclk) |
| 646 | ); |
| 647 | |
| 648 | assign sync_in_opdhq1_rd_addr[4:0] = io_cmp_sync_en ? opcs_opcc_opdhq1_rd_addr[4:0] : sync_out_opdhq1_rd_addr[4:0]; |
| 649 | |
| 650 | sio_opcc_ctl_msff_ctl_macro__width_5 ff_syn_opdhq1_rd_addr ( |
| 651 | .scan_in(ff_syn_opdhq1_rd_addr_scanin), |
| 652 | .scan_out(ff_syn_opdhq1_rd_addr_scanout), |
| 653 | .din (sync_in_opdhq1_rd_addr[4:0]), |
| 654 | .dout (sync_out_opdhq1_rd_addr[4:0]), |
| 655 | .l1clk(l1clk), |
| 656 | .siclk(siclk), |
| 657 | .soclk(soclk) |
| 658 | ); |
| 659 | sio_opcc_ctl_msff_ctl_macro__width_5 ff_opdhq1_rd_addr ( |
| 660 | .scan_in(ff_opdhq1_rd_addr_scanin), |
| 661 | .scan_out(ff_opdhq1_rd_addr_scanout), |
| 662 | .din (sync_out_opdhq1_rd_addr[4:0]), |
| 663 | .dout (opdhq1_rd_addr[4:0]), |
| 664 | .l1clk(l1clk), |
| 665 | .siclk(siclk), |
| 666 | .soclk(soclk) |
| 667 | ); |
| 668 | |
| 669 | |
| 670 | sio_opcc_ctl_msff_ctl_macro__width_5 ff_opdhq0sub ( |
| 671 | .scan_in(ff_opdhq0sub_scanin), |
| 672 | .scan_out(ff_opdhq0sub_scanout), |
| 673 | .din (opdhq0sub_l[4:0]), |
| 674 | .dout (opdhq0sub[4:0]), |
| 675 | .l1clk(l1clk), |
| 676 | .siclk(siclk), |
| 677 | .soclk(soclk) |
| 678 | ); |
| 679 | sio_opcc_ctl_msff_ctl_macro__width_5 ff_opdhq1sub ( |
| 680 | .scan_in(ff_opdhq1sub_scanin), |
| 681 | .scan_out(ff_opdhq1sub_scanout), |
| 682 | .din (opdhq1sub_l[4:0]), |
| 683 | .dout (opdhq1sub[4:0]), |
| 684 | .l1clk(l1clk), |
| 685 | .siclk(siclk), |
| 686 | .soclk(soclk) |
| 687 | ); |
| 688 | |
| 689 | assign opdhq0_rd_addr_early[4:0] = sync_out_opdhq0_rd_addr[4:0]; |
| 690 | assign opdhq1_rd_addr_early[4:0] = sync_out_opdhq1_rd_addr[4:0]; |
| 691 | assign opdhq0_wr_addr_early[4:0] = opdhq0_wr_addrinc ? opdhq0_wr_addr[4:0] + 5'b00001 : opdhq0_wr_addr[4:0]; |
| 692 | assign opdhq1_wr_addr_early[4:0] = opdhq1_wr_addrinc ? opdhq1_wr_addr[4:0] + 5'b00001 : opdhq1_wr_addr[4:0]; |
| 693 | |
| 694 | assign opdhq0sub_l[4:0] = (opdhq0_wr_addr_early[4:0] - opdhq0_rd_addr_early[4:0]) ; |
| 695 | assign opdhq1sub_l[4:0] = (opdhq1_wr_addr_early[4:0] - opdhq1_rd_addr_early[4:0]) ; |
| 696 | assign opdhq0sub_unused[1:0] = opdhq0sub[1:0]; |
| 697 | assign opdhq1sub_unused[1:0] = opdhq1sub[1:0]; |
| 698 | |
| 699 | |
| 700 | assign dmureqfull = (opdhq0sub[4]) | |
| 701 | (~opdhq0sub[4] & (&opdhq0sub[3:2])) |
| 702 | ; |
| 703 | |
| 704 | assign entreqfull = (opdhq1sub[4]) | |
| 705 | (~opdhq1sub[4] & (&opdhq1sub[3:2])) |
| 706 | ; |
| 707 | |
| 708 | |
| 709 | // REQUEST - GRANT LOGIC |
| 710 | assign opcc_opdc_gnt0_opc0 = gnt_d1[0] ; |
| 711 | assign opcc_opdc_gnt2_opc0 = gnt_d1[2] ; |
| 712 | assign opcc_opdc_gnt4_opc0 = gnt_d1[4] ; |
| 713 | assign opcc_opdc_gnt6_opc0 = gnt_d1[6] ; |
| 714 | assign opcc_opdc_gnt01_opc1 = gnt_d2[0] | gnt_d2[1]; |
| 715 | assign opcc_opdc_gnt45_opc1 = gnt_d2[4] | gnt_d2[5]; |
| 716 | assign opcc_opdc_gnt0123_opc1 = gnt_d2[0] | gnt_d2[1] | gnt_d2[2] | gnt_d2[3] ; |
| 717 | |
| 718 | assign queuecredit[0] = (olc0_opcc_dmureq & ~dmureqfull) | (~olc0_opcc_dmureq & ~entreqfull); |
| 719 | assign queuecredit[1] = (olc1_opcc_dmureq & ~dmureqfull) | (~olc1_opcc_dmureq & ~entreqfull); |
| 720 | assign queuecredit[2] = (olc2_opcc_dmureq & ~dmureqfull) | (~olc2_opcc_dmureq & ~entreqfull); |
| 721 | assign queuecredit[3] = (olc3_opcc_dmureq & ~dmureqfull) | (~olc3_opcc_dmureq & ~entreqfull); |
| 722 | assign queuecredit[4] = (olc4_opcc_dmureq & ~dmureqfull) | (~olc4_opcc_dmureq & ~entreqfull); |
| 723 | assign queuecredit[5] = (olc5_opcc_dmureq & ~dmureqfull) | (~olc5_opcc_dmureq & ~entreqfull); |
| 724 | assign queuecredit[6] = (olc6_opcc_dmureq & ~dmureqfull) | (~olc6_opcc_dmureq & ~entreqfull); |
| 725 | assign queuecredit[7] = (olc7_opcc_dmureq & ~dmureqfull) | (~olc7_opcc_dmureq & ~entreqfull); |
| 726 | |
| 727 | assign nextreq[0] = olc0_opcc_req & queuecredit[0] & ~gnt[0]; |
| 728 | assign nextreq[1] = olc1_opcc_req & queuecredit[1] & ~gnt[1]; |
| 729 | assign nextreq[2] = olc2_opcc_req & queuecredit[2] & ~gnt[2]; |
| 730 | assign nextreq[3] = olc3_opcc_req & queuecredit[3] & ~gnt[3]; |
| 731 | assign nextreq[4] = olc4_opcc_req & queuecredit[4] & ~gnt[4]; |
| 732 | assign nextreq[5] = olc5_opcc_req & queuecredit[5] & ~gnt[5]; |
| 733 | assign nextreq[6] = olc6_opcc_req & queuecredit[6] & ~gnt[6]; |
| 734 | assign nextreq[7] = olc7_opcc_req & queuecredit[7] & ~gnt[7]; |
| 735 | |
| 736 | |
| 737 | assign newwinner[0] = (nextreq[0] & (gnt_hist[7] | (~|gnt_hist[6:0]))) | |
| 738 | (nextreq[0] & ~nextreq[7 ] & gnt_hist[6]) | |
| 739 | (nextreq[0] & ~|nextreq[7:6] & gnt_hist[5]) | |
| 740 | (nextreq[0] & ~|nextreq[7:5] & gnt_hist[4]) | |
| 741 | (nextreq[0] & ~|nextreq[7:4] & gnt_hist[3]) | |
| 742 | (nextreq[0] & ~|nextreq[7:3] & gnt_hist[2]) | |
| 743 | (nextreq[0] & ~|nextreq[7:2] & gnt_hist[1]) | |
| 744 | (nextreq[0] & ~|nextreq[7:1]); |
| 745 | |
| 746 | |
| 747 | assign newwinner[1] = (nextreq[1] & gnt_hist[0]) | |
| 748 | (nextreq[1] & ~nextreq[0] & (gnt_hist[7] || (~|gnt_hist[6:0]))) | |
| 749 | (nextreq[1] & ~|{nextreq[7 ], nextreq[0]} & gnt_hist[6]) | |
| 750 | (nextreq[1] & ~|{nextreq[7:6], nextreq[0]} & gnt_hist[5]) | |
| 751 | (nextreq[1] & ~|{nextreq[7:5], nextreq[0]} & gnt_hist[4]) | |
| 752 | (nextreq[1] & ~|{nextreq[7:4], nextreq[0]} & gnt_hist[3]) | |
| 753 | (nextreq[1] & ~|{nextreq[7:3], nextreq[0]} & gnt_hist[2]) | |
| 754 | (nextreq[1] & ~|{nextreq[7:2], nextreq[0]}); |
| 755 | |
| 756 | assign newwinner[2] = (nextreq[2] & gnt_hist[1]) | |
| 757 | (nextreq[2] & ~nextreq[1] & gnt_hist[0]) | |
| 758 | (nextreq[2] & ~|{nextreq[1:0]} & (gnt_hist[7] || (~|gnt_hist[6:0]))) | |
| 759 | (nextreq[2] & ~|{nextreq[7 ], nextreq[1:0]} & gnt_hist[6]) | |
| 760 | (nextreq[2] & ~|{nextreq[7:6], nextreq[1:0]} & gnt_hist[5]) | |
| 761 | (nextreq[2] & ~|{nextreq[7:5], nextreq[1:0]} & gnt_hist[4]) | |
| 762 | (nextreq[2] & ~|{nextreq[7:4], nextreq[1:0]} & gnt_hist[3]) | |
| 763 | (nextreq[2] & ~|{nextreq[7:3], nextreq[1:0]}); |
| 764 | |
| 765 | assign newwinner[3] = (nextreq[3] & gnt_hist[2]) | |
| 766 | (nextreq[3] & ~nextreq[2] & gnt_hist[1]) | |
| 767 | (nextreq[3] & ~|{ nextreq[2:1]} & gnt_hist[0]) | |
| 768 | (nextreq[3] & ~|{nextreq[2:0]} & (gnt_hist[7] || (~|gnt_hist[6:0]))) | |
| 769 | (nextreq[3] & ~|{nextreq[7 ], nextreq[2:0]} & gnt_hist[6]) | |
| 770 | (nextreq[3] & ~|{nextreq[7:6], nextreq[2:0]} & gnt_hist[5]) | |
| 771 | (nextreq[3] & ~|{nextreq[7:5], nextreq[2:0]} & gnt_hist[4]) | |
| 772 | (nextreq[3] & ~|{nextreq[7:4], nextreq[2:0]}); |
| 773 | |
| 774 | assign newwinner[4] = (nextreq[4] & gnt_hist[3]) | |
| 775 | (nextreq[4] & ~nextreq[3] & gnt_hist[2]) | |
| 776 | (nextreq[4] & ~|{ nextreq[3:2]} & gnt_hist[1]) | |
| 777 | (nextreq[4] & ~|{ nextreq[3:1]} & gnt_hist[0]) | |
| 778 | (nextreq[4] & ~|{nextreq[3:0]} & (gnt_hist[7] || (~|gnt_hist[6:0]))) | |
| 779 | (nextreq[4] & ~|{nextreq[7 ], nextreq[3:0]} & gnt_hist[6]) | |
| 780 | (nextreq[4] & ~|{nextreq[7:6], nextreq[3:0]} & gnt_hist[5]) | |
| 781 | (nextreq[4] & ~|{nextreq[7:5], nextreq[3:0]}); |
| 782 | |
| 783 | assign newwinner[5] = (nextreq[5] & gnt_hist[4]) | |
| 784 | (nextreq[5] & ~nextreq[4] & gnt_hist[3]) | |
| 785 | (nextreq[5] & ~|{ nextreq[4:3]} & gnt_hist[2]) | |
| 786 | (nextreq[5] & ~|{ nextreq[4:2]} & gnt_hist[1]) | |
| 787 | (nextreq[5] & ~|{ nextreq[4:1]} & gnt_hist[0]) | |
| 788 | (nextreq[5] & ~|{nextreq[4:0]} & (gnt_hist[7] || (~|gnt_hist[6:0]))) | |
| 789 | (nextreq[5] & ~|{nextreq[7 ], nextreq[4:0]} & gnt_hist[6]) | |
| 790 | (nextreq[5] & ~|{nextreq[7:6], nextreq[4:0]}); |
| 791 | |
| 792 | assign newwinner[6] = (nextreq[6] & gnt_hist[5]) | |
| 793 | (nextreq[6] & ~nextreq[5] & gnt_hist[4]) | |
| 794 | (nextreq[6] & ~|{ nextreq[5:4]} & gnt_hist[3]) | |
| 795 | (nextreq[6] & ~|{ nextreq[5:3]} & gnt_hist[2]) | |
| 796 | (nextreq[6] & ~|{ nextreq[5:2]} & gnt_hist[1]) | |
| 797 | (nextreq[6] & ~|{ nextreq[5:1]} & gnt_hist[0]) | |
| 798 | (nextreq[6] & ~|{nextreq[5:0]} & (gnt_hist[7] || (~|gnt_hist[6:0]))) | |
| 799 | (nextreq[6] & ~|{nextreq[7 ], nextreq[5:0]}); |
| 800 | |
| 801 | assign newwinner[7] = (nextreq[7] & gnt_hist[6]) | |
| 802 | (nextreq[7] & ~nextreq[6] & gnt_hist[5]) | |
| 803 | (nextreq[7] & ~|{ nextreq[6:5]} & gnt_hist[4]) | |
| 804 | (nextreq[7] & ~|{ nextreq[6:4]} & gnt_hist[3]) | |
| 805 | (nextreq[7] & ~|{ nextreq[6:3]} & gnt_hist[2]) | |
| 806 | (nextreq[7] & ~|{ nextreq[6:2]} & gnt_hist[1]) | |
| 807 | (nextreq[7] & ~|{ nextreq[6:1]} & gnt_hist[0]) | |
| 808 | (nextreq[7] & ~|{ nextreq[6:0]}); |
| 809 | |
| 810 | assign opcc_olc0_gnt = ~busbusy & ~read_slph & gnt[0] ; |
| 811 | assign opcc_olc1_gnt = ~busbusy & ~read_slph & gnt[1] ; |
| 812 | assign opcc_olc2_gnt = ~busbusy & ~read_slph & gnt[2] ; |
| 813 | assign opcc_olc3_gnt = ~busbusy & ~read_slph & gnt[3] ; |
| 814 | assign opcc_olc4_gnt = ~busbusy & ~read_slph & gnt[4] ; |
| 815 | assign opcc_olc5_gnt = ~busbusy & ~read_slph & gnt[5] ; |
| 816 | assign opcc_olc6_gnt = ~busbusy & ~read_slph & gnt[6] ; |
| 817 | assign opcc_olc7_gnt = ~busbusy & ~read_slph & gnt[7] ; |
| 818 | |
| 819 | assign nextwinner[7:0] = (~busbusy | &buscnt[2:0]) & ~nextread_slph & ~read_slph ? newwinner[7:0] : winner[7:0]; |
| 820 | // assign nextgnt[7:0] = (~busbusy | &buscnt[2:0] ) & ~nextread_slph & ~read_slph ? nextwinner[7:0] :gnt[7:0] ; |
| 821 | |
| 822 | assign nextgnt[7:0] = (~busbusy | &buscnt[2:0] ) & ~nextread_slph & ~read_slph ? newwinner[7:0] :gnt[7:0] ; |
| 823 | assign gnt_hist_l[7:0] = | nextgnt[7:0] ? nextgnt[7:0] : gnt_hist[7:0] ; |
| 824 | |
| 825 | |
| 826 | |
| 827 | sio_opcc_ctl_msff_ctl_macro__width_42 ff_slpstates ( |
| 828 | .scan_in(ff_slpstates_scanin), |
| 829 | .scan_out(ff_slpstates_scanout), |
| 830 | .din ({gnt_d1[5:0], nextgntd1[7:0], nextgnt[7:0], nextwinner[7:0], |
| 831 | nextread_slph, nextcycleis_slph, |
| 832 | nextdmuread_slph, |
| 833 | nextentread_slph, |
| 834 | gnt_hist_l[7:0]}), |
| 835 | .dout ({gnt_d2[5:0], gnt_d1[7:0], gnt[7:0], winner[7:0], |
| 836 | read_slph, cycle_slph, |
| 837 | dmuread_slph, |
| 838 | entread_slph, |
| 839 | gnt_hist[7:0]}), |
| 840 | .l1clk(l1clk), |
| 841 | .siclk(siclk), |
| 842 | .soclk(soclk) |
| 843 | ); |
| 844 | |
| 845 | |
| 846 | assign dmuwinner[7:0] = gnt[7:0] & dmureq[7:0]; |
| 847 | |
| 848 | assign entwinner[7:0] = gnt[7:0] & entreq[7:0]; |
| 849 | |
| 850 | // the follow signals are not qualified by the request valid signal nor grant |
| 851 | |
| 852 | assign dmureadreq[7:0] = dmureq[7:0] & readreq[7:0]; |
| 853 | assign entreadreq[7:0] = entreq[7:0] & readreq[7:0]; |
| 854 | |
| 855 | |
| 856 | assign readreq[7:0] = {olc7_opcc_datareq, |
| 857 | olc6_opcc_datareq, |
| 858 | olc5_opcc_datareq, |
| 859 | olc4_opcc_datareq, |
| 860 | olc3_opcc_datareq, |
| 861 | olc2_opcc_datareq, |
| 862 | olc1_opcc_datareq, |
| 863 | olc0_opcc_datareq}; |
| 864 | |
| 865 | assign dmureq[7:0] = {olc7_opcc_dmureq, |
| 866 | olc6_opcc_dmureq, |
| 867 | olc5_opcc_dmureq, |
| 868 | olc4_opcc_dmureq, |
| 869 | olc3_opcc_dmureq, |
| 870 | olc2_opcc_dmureq, |
| 871 | olc1_opcc_dmureq, |
| 872 | olc0_opcc_dmureq}; |
| 873 | |
| 874 | assign entreq[7:0] = {~olc7_opcc_dmureq, |
| 875 | ~olc6_opcc_dmureq, |
| 876 | ~olc5_opcc_dmureq, |
| 877 | ~olc4_opcc_dmureq, |
| 878 | ~olc3_opcc_dmureq, |
| 879 | ~olc2_opcc_dmureq, |
| 880 | ~olc1_opcc_dmureq, |
| 881 | ~olc0_opcc_dmureq}; |
| 882 | |
| 883 | assign nextcycleis_slph = ~busbusy & ~read_slph & (|gnt[7:0]); |
| 884 | assign nextread_slph = ~busbusy & ~read_slph & |(gnt[7:0] & readreq[7:0]); |
| 885 | assign nextdmuread_slph = ~busbusy & ~read_slph & |(gnt[7:0] & dmureadreq[7:0]); |
| 886 | assign nextentread_slph = ~busbusy & ~read_slph & |(gnt[7:0] & entreadreq[7:0]); |
| 887 | |
| 888 | assign busbusy = (|buscnt[2:0]); // | nextread_slph; |
| 889 | |
| 890 | assign buscnt_plus1[2:0] = buscnt[2:0] + 3'b001; |
| 891 | assign buscnt_inc = (|buscnt[2:0]) | (read_slph); |
| 892 | assign buscnt_next[2:0] = buscnt_inc ? buscnt_plus1[2:0] : buscnt[2:0]; |
| 893 | assign nextgntd1[7:0] = (nextcycleis_slph) ? gnt[7:0] : gnt_d1[7:0]; |
| 894 | |
| 895 | |
| 896 | |
| 897 | sio_opcc_ctl_msff_ctl_macro__width_3 ff_buscnt ( |
| 898 | .scan_in(ff_buscnt_scanin), |
| 899 | .scan_out(ff_buscnt_scanout), |
| 900 | .din (buscnt_next[2:0]), |
| 901 | .dout (buscnt[2:0]), |
| 902 | .l1clk(l1clk), |
| 903 | .siclk(siclk), |
| 904 | .soclk(soclk) |
| 905 | ); |
| 906 | |
| 907 | |
| 908 | // CREATE FIFO WRITE POINTER LOGIC |
| 909 | |
| 910 | assign opdhq0won = |dmuwinner[7:0]; |
| 911 | assign opdhq1won = |entwinner[7:0]; |
| 912 | assign opdhq0won_slph = cycle_slph & opdhq0won_d1; |
| 913 | assign opdhq1won_slph = cycle_slph & opdhq1won_d1; |
| 914 | |
| 915 | assign opcc_opdhq0_wr_en = opdhq0won_opc1; // DMU hdrq -- valid on opc1 |
| 916 | assign opcc_opdhq1_wr_en = opdhq1won_opc1; // ENT hdrq -- valid on opc1 |
| 917 | |
| 918 | assign opdhq0_wr_addrinc = opdhq0won_opc1; |
| 919 | assign opdhq1_wr_addrinc = opdhq1won_opc1; |
| 920 | assign opdhq0_wr_addr_next[4:0] = opdhq0_wr_addrinc ? opdhq0_wr_addr[4:0] + 5'b00001 : opdhq0_wr_addr[4:0]; |
| 921 | assign opdhq1_wr_addr_next[4:0] = opdhq1_wr_addrinc ? opdhq1_wr_addr[4:0] + 5'b00001 : opdhq1_wr_addr[4:0]; |
| 922 | |
| 923 | assign opcc_opdhq0_wr_addr[3:0] = opdhq0_wr_addr[3:0]; // DMU hdrq -- valid on opc1 |
| 924 | assign opcc_opdhq1_wr_addr[3:0] = opdhq1_wr_addr[3:0]; // ENT hdrq -- valid on opc1 |
| 925 | |
| 926 | |
| 927 | // assign opddq0x_wr_addrinc4_next = opdhq0won_opc1 & ~dmuread_opc1; |
| 928 | // assign opddq1x_wr_addrinc4_next = opdhq1won_opc1 & ~entread_opc1; |
| 929 | assign opddq0x_wr_addrinc4_next = 1'b0; |
| 930 | assign opddq1x_wr_addrinc4_next = 1'b0; //do not skip 4 location when no data |
| 931 | |
| 932 | assign opddq00_wr_addrinc_next = |{dmuread_opc1, dmuread_opc3, |
| 933 | dmuread_opc5, dmuread_opc7}; |
| 934 | |
| 935 | assign opddq10_wr_addrinc_next = |{entread_opc1, entread_opc3, |
| 936 | entread_opc5, entread_opc7}; |
| 937 | |
| 938 | assign opddq01_wr_addrinc_next = |{dmuread_opc2, dmuread_opc4, |
| 939 | dmuread_opc6, dmuread_opc8}; |
| 940 | |
| 941 | assign opddq11_wr_addrinc_next = |{entread_opc2, entread_opc4, |
| 942 | entread_opc6, entread_opc8}; |
| 943 | |
| 944 | assign opddq00_wr_addr_next[6:0] = opddq0x_wr_addrinc4_next ? (opddq00_wr_addr[6:0] + 7'b0000100) : |
| 945 | (opddq00_wr_addrinc ? opddq00_wr_addr[6:0] + 7'b0000001 : opddq00_wr_addr[6:0]); |
| 946 | assign opddq10_wr_addr_next[6:0] = opddq1x_wr_addrinc4_next ? (opddq10_wr_addr[6:0] + 7'b0000100) : |
| 947 | (opddq10_wr_addrinc ? opddq10_wr_addr[6:0] + 7'b0000001 : opddq10_wr_addr[6:0]); |
| 948 | |
| 949 | assign opcc_opddq00_wr_addr[5:0] = opddq00_wr_addr[5:0]; // DMU dataq -- valid on opc2,4,6,8 |
| 950 | assign opcc_opddq10_wr_addr[5:0] = opddq10_wr_addr[5:0]; // ENT dataq -- valid on opc2,4,6,8 |
| 951 | |
| 952 | assign opddq01_wr_addr_next[6:0] = opddq0x_wr_addrinc4_next ? (opddq01_wr_addr[6:0] + 7'b0000100) : |
| 953 | (opddq01_wr_addrinc ? opddq01_wr_addr[6:0] + 7'b0000001 : opddq01_wr_addr[6:0]); |
| 954 | assign opddq11_wr_addr_next[6:0] = opddq1x_wr_addrinc4_next ? (opddq11_wr_addr[6:0] + 7'b0000100) : |
| 955 | (opddq11_wr_addrinc ? opddq11_wr_addr[6:0] + 7'b0000001 : opddq11_wr_addr[6:0]); |
| 956 | |
| 957 | assign opcc_opddq01_wr_addr[5:0] = opddq01_wr_addr[5:0]; // DMU dataq -- valid on opc3,5,7,9 |
| 958 | assign opcc_opddq11_wr_addr[5:0] = opddq11_wr_addr[5:0]; // ENT dataq -- valid on opc3,5,7,9 |
| 959 | |
| 960 | assign opcc_opddq00_wr_en = opddq00_wr_addrinc; // DMU dataq -- valid on opc1 |
| 961 | assign opcc_opddq10_wr_en = opddq10_wr_addrinc; // ENT dataq -- valid on opc1 |
| 962 | assign opcc_opddq01_wr_en = opddq01_wr_addrinc; // DMU dataq -- valid on opc1 |
| 963 | assign opcc_opddq11_wr_en = opddq11_wr_addrinc; // ENT dataq -- valid on opc1 |
| 964 | |
| 965 | |
| 966 | |
| 967 | sio_opcc_ctl_msff_ctl_macro__width_4 ff_hqxwonstage ( |
| 968 | .scan_in(ff_hqxwonstage_scanin), |
| 969 | .scan_out(ff_hqxwonstage_scanout), |
| 970 | .din ({opdhq0won, opdhq0won_slph, |
| 971 | opdhq1won, opdhq1won_slph} |
| 972 | ), |
| 973 | .dout ({opdhq0won_d1, opdhq0won_opc1, |
| 974 | opdhq1won_d1, opdhq1won_opc1} |
| 975 | ), |
| 976 | .l1clk(l1clk), |
| 977 | .siclk(siclk), |
| 978 | .soclk(soclk) |
| 979 | ); |
| 980 | |
| 981 | sio_opcc_ctl_msff_ctl_macro__width_16 ff_qxdatastage ( |
| 982 | .scan_in(ff_qxdatastage_scanin), |
| 983 | .scan_out(ff_qxdatastage_scanout), |
| 984 | .din ({dmuread_slph, dmuread_opc1, dmuread_opc2, dmuread_opc3, |
| 985 | dmuread_opc4, dmuread_opc5, dmuread_opc6, dmuread_opc7, |
| 986 | entread_slph, entread_opc1, entread_opc2, entread_opc3, |
| 987 | entread_opc4, entread_opc5, entread_opc6, entread_opc7} |
| 988 | ), |
| 989 | .dout ({dmuread_opc1, dmuread_opc2, dmuread_opc3, dmuread_opc4, |
| 990 | dmuread_opc5, dmuread_opc6, dmuread_opc7, dmuread_opc8, |
| 991 | entread_opc1, entread_opc2, entread_opc3, entread_opc4, |
| 992 | entread_opc5, entread_opc6, entread_opc7, entread_opc8} |
| 993 | ), |
| 994 | .l1clk(l1clk), |
| 995 | .siclk(siclk), |
| 996 | .soclk(soclk) |
| 997 | ); |
| 998 | |
| 999 | // INTERNAL DMU hdrq -- valid on opc1 |
| 1000 | |
| 1001 | sio_opcc_ctl_msff_ctl_macro__width_5 ff_opdhq0_wr_addr ( |
| 1002 | .scan_in(ff_opdhq0_wr_addr_scanin), |
| 1003 | .scan_out(ff_opdhq0_wr_addr_scanout), |
| 1004 | .din (opdhq0_wr_addr_next[4:0]), |
| 1005 | .dout (opdhq0_wr_addr[4:0]), |
| 1006 | .l1clk(l1clk), |
| 1007 | .siclk(siclk), |
| 1008 | .soclk(soclk) |
| 1009 | ); |
| 1010 | |
| 1011 | // INTERNAL ENT hdrq -- valid on opc1 |
| 1012 | |
| 1013 | sio_opcc_ctl_msff_ctl_macro__width_5 ff_opdhq1_wr_addr ( |
| 1014 | .scan_in(ff_opdhq1_wr_addr_scanin), |
| 1015 | .scan_out(ff_opdhq1_wr_addr_scanout), |
| 1016 | .din (opdhq1_wr_addr_next[4:0]), |
| 1017 | .dout (opdhq1_wr_addr[4:0]), |
| 1018 | .l1clk(l1clk), |
| 1019 | .siclk(siclk), |
| 1020 | .soclk(soclk) |
| 1021 | ); |
| 1022 | |
| 1023 | // INTERNAL DMU dataq0 -- valid on opc2,4,6,8 |
| 1024 | sio_opcc_ctl_msff_ctl_macro__width_7 ff_opddq00_wr_addr ( |
| 1025 | .scan_in(ff_opddq00_wr_addr_scanin), |
| 1026 | .scan_out(ff_opddq00_wr_addr_scanout), |
| 1027 | .din (opddq00_wr_addr_next[6:0]), |
| 1028 | .dout (opddq00_wr_addr[6:0]), |
| 1029 | .l1clk(l1clk), |
| 1030 | .siclk(siclk), |
| 1031 | .soclk(soclk) |
| 1032 | ); |
| 1033 | |
| 1034 | // INTERNAL ENT dataq0 -- valid on opc2,4,6,8 |
| 1035 | sio_opcc_ctl_msff_ctl_macro__width_7 ff_opddq10_wr_addr ( |
| 1036 | .scan_in(ff_opddq10_wr_addr_scanin), |
| 1037 | .scan_out(ff_opddq10_wr_addr_scanout), |
| 1038 | .din (opddq10_wr_addr_next[6:0]), |
| 1039 | .dout (opddq10_wr_addr[6:0]), |
| 1040 | .l1clk(l1clk), |
| 1041 | .siclk(siclk), |
| 1042 | .soclk(soclk) |
| 1043 | ); |
| 1044 | |
| 1045 | // INTERNAL DMU dataq1 -- valid on opc3,5,7,9 |
| 1046 | sio_opcc_ctl_msff_ctl_macro__width_7 ff_opddq01_wr_addr ( |
| 1047 | .scan_in(ff_opddq01_wr_addr_scanin), |
| 1048 | .scan_out(ff_opddq01_wr_addr_scanout), |
| 1049 | .din (opddq01_wr_addr_next[6:0]), |
| 1050 | .dout (opddq01_wr_addr[6:0]), |
| 1051 | .l1clk(l1clk), |
| 1052 | .siclk(siclk), |
| 1053 | .soclk(soclk) |
| 1054 | ); |
| 1055 | |
| 1056 | // INTERNAL ENT dataq1-- valid on opc3,5,7,9 |
| 1057 | sio_opcc_ctl_msff_ctl_macro__width_7 ff_opddq11_wr_addr ( |
| 1058 | .scan_in(ff_opddq11_wr_addr_scanin), |
| 1059 | .scan_out(ff_opddq11_wr_addr_scanout), |
| 1060 | .din (opddq11_wr_addr_next[6:0]), |
| 1061 | .dout (opddq11_wr_addr[6:0]), |
| 1062 | .l1clk(l1clk), |
| 1063 | .siclk(siclk), |
| 1064 | .soclk(soclk) |
| 1065 | ); |
| 1066 | |
| 1067 | // INTERNAL dataq write pointer increment |
| 1068 | |
| 1069 | sio_opcc_ctl_msff_ctl_macro__width_1 ff_opddq00_wr_addrinc ( |
| 1070 | .scan_in(ff_opddq00_wr_addrinc_scanin), |
| 1071 | .scan_out(ff_opddq00_wr_addrinc_scanout), |
| 1072 | .din (opddq00_wr_addrinc_next), |
| 1073 | .dout (opddq00_wr_addrinc), |
| 1074 | .l1clk(l1clk), |
| 1075 | .siclk(siclk), |
| 1076 | .soclk(soclk) |
| 1077 | ); |
| 1078 | |
| 1079 | sio_opcc_ctl_msff_ctl_macro__width_1 ff_opddq01_wr_addrinc ( |
| 1080 | .scan_in(ff_opddq01_wr_addrinc_scanin), |
| 1081 | .scan_out(ff_opddq01_wr_addrinc_scanout), |
| 1082 | .din (opddq01_wr_addrinc_next), |
| 1083 | .dout (opddq01_wr_addrinc), |
| 1084 | .l1clk(l1clk), |
| 1085 | .siclk(siclk), |
| 1086 | .soclk(soclk) |
| 1087 | ); |
| 1088 | |
| 1089 | sio_opcc_ctl_msff_ctl_macro__width_1 ff_opddq10_wr_addrinc ( |
| 1090 | .scan_in(ff_opddq10_wr_addrinc_scanin), |
| 1091 | .scan_out(ff_opddq10_wr_addrinc_scanout), |
| 1092 | .din (opddq10_wr_addrinc_next), |
| 1093 | .dout (opddq10_wr_addrinc), |
| 1094 | .l1clk(l1clk), |
| 1095 | .siclk(siclk), |
| 1096 | .soclk(soclk) |
| 1097 | ); |
| 1098 | |
| 1099 | sio_opcc_ctl_msff_ctl_macro__width_1 ff_opddq11_wr_addrinc ( |
| 1100 | .scan_in(ff_opddq11_wr_addrinc_scanin), |
| 1101 | .scan_out(ff_opddq11_wr_addrinc_scanout), |
| 1102 | .din (opddq11_wr_addrinc_next), |
| 1103 | .dout (opddq11_wr_addrinc), |
| 1104 | .l1clk(l1clk), |
| 1105 | .siclk(siclk), |
| 1106 | .soclk(soclk) |
| 1107 | ); |
| 1108 | |
| 1109 | |
| 1110 | // Synchronize the gray coded write pointers TO sio_opcs_ctl |
| 1111 | |
| 1112 | // until we have a sync macro cell, i'm using 2 msff_ctl_macros |
| 1113 | sio_opcc_ctl_msff_ctl_macro__width_7 ff_opddq00_wr_addr_d1 ( |
| 1114 | .scan_in(ff_opddq00_wr_addr_d1_scanin), |
| 1115 | .scan_out(ff_opddq00_wr_addr_d1_scanout), |
| 1116 | .din (opddq00_wr_addr[6:0]), |
| 1117 | .dout (opddq00_wr_addr_d1[6:0]), |
| 1118 | .l1clk(l1clk), |
| 1119 | .siclk(siclk), |
| 1120 | .soclk(soclk) |
| 1121 | ); |
| 1122 | |
| 1123 | assign sync_in_opddq00_wr_addr[6:0] = cmp_io_sync_en ? opddq00_wr_addr_d1[6:0] : sync_out_opddq00_wr_addr[6:0]; |
| 1124 | sio_opcc_ctl_msff_ctl_macro__width_7 ff_syn_opddq00_wr_addr ( |
| 1125 | .scan_in(ff_syn_opddq00_wr_addr_scanin), |
| 1126 | .scan_out(ff_syn_opddq00_wr_addr_scanout), |
| 1127 | .din (sync_in_opddq00_wr_addr[6:0]), |
| 1128 | .dout (sync_out_opddq00_wr_addr[6:0]), |
| 1129 | .l1clk(l1clk), |
| 1130 | .siclk(siclk), |
| 1131 | .soclk(soclk) |
| 1132 | ); |
| 1133 | |
| 1134 | |
| 1135 | |
| 1136 | sio_opcc_ctl_msff_ctl_macro__width_7 ff_opddq01_wr_addr_d1 ( |
| 1137 | .scan_in(ff_opddq01_wr_addr_d1_scanin), |
| 1138 | .scan_out(ff_opddq01_wr_addr_d1_scanout), |
| 1139 | .din (opddq01_wr_addr[6:0]), |
| 1140 | .dout (opddq01_wr_addr_d1[6:0]), |
| 1141 | .l1clk(l1clk), |
| 1142 | .siclk(siclk), |
| 1143 | .soclk(soclk) |
| 1144 | ); |
| 1145 | assign sync_in_opddq01_wr_addr[6:0] = cmp_io_sync_en ? opddq01_wr_addr_d1[6:0] : sync_out_opddq01_wr_addr[6:0]; |
| 1146 | sio_opcc_ctl_msff_ctl_macro__width_7 ff_syn_opddq01_wr_addr ( |
| 1147 | .scan_in(ff_syn_opddq01_wr_addr_scanin), |
| 1148 | .scan_out(ff_syn_opddq01_wr_addr_scanout), |
| 1149 | .din (sync_in_opddq01_wr_addr[6:0]), |
| 1150 | .dout (sync_out_opddq01_wr_addr[6:0]), |
| 1151 | .l1clk(l1clk), |
| 1152 | .siclk(siclk), |
| 1153 | .soclk(soclk) |
| 1154 | ); |
| 1155 | |
| 1156 | |
| 1157 | |
| 1158 | sio_opcc_ctl_msff_ctl_macro__width_7 ff_opddq10_wr_addr_d1 ( |
| 1159 | .scan_in(ff_opddq10_wr_addr_d1_scanin), |
| 1160 | .scan_out(ff_opddq10_wr_addr_d1_scanout), |
| 1161 | .din (opddq10_wr_addr[6:0]), |
| 1162 | .dout (opddq10_wr_addr_d1[6:0]), |
| 1163 | .l1clk(l1clk), |
| 1164 | .siclk(siclk), |
| 1165 | .soclk(soclk) |
| 1166 | ); |
| 1167 | assign sync_in_opddq10_wr_addr[6:0] = cmp_io_sync_en ? opddq10_wr_addr_d1[6:0] : sync_out_opddq10_wr_addr[6:0]; |
| 1168 | |
| 1169 | |
| 1170 | sio_opcc_ctl_msff_ctl_macro__width_7 ff_syn_opddq10_wr_addr ( |
| 1171 | .scan_in(ff_syn_opddq10_wr_addr_scanin), |
| 1172 | .scan_out(ff_syn_opddq10_wr_addr_scanout), |
| 1173 | .din (sync_in_opddq10_wr_addr[6:0]), |
| 1174 | .dout (sync_out_opddq10_wr_addr[6:0]), |
| 1175 | .l1clk(l1clk), |
| 1176 | .siclk(siclk), |
| 1177 | .soclk(soclk) |
| 1178 | ); |
| 1179 | |
| 1180 | |
| 1181 | |
| 1182 | sio_opcc_ctl_msff_ctl_macro__width_7 ff_opddq11_wr_addr_d1 ( |
| 1183 | .scan_in(ff_opddq11_wr_addr_d1_scanin), |
| 1184 | .scan_out(ff_opddq11_wr_addr_d1_scanout), |
| 1185 | .din (opddq11_wr_addr[6:0]), |
| 1186 | .dout (opddq11_wr_addr_d1[6:0]), |
| 1187 | .l1clk(l1clk), |
| 1188 | .siclk(siclk), |
| 1189 | .soclk(soclk) |
| 1190 | ); |
| 1191 | assign sync_in_opddq11_wr_addr[6:0] = cmp_io_sync_en ? opddq11_wr_addr_d1[6:0] : sync_out_opddq11_wr_addr[6:0]; |
| 1192 | sio_opcc_ctl_msff_ctl_macro__width_7 ff_syn_opddq11_wr_addr ( |
| 1193 | .scan_in(ff_syn_opddq11_wr_addr_scanin), |
| 1194 | .scan_out(ff_syn_opddq11_wr_addr_scanout), |
| 1195 | .din (sync_in_opddq11_wr_addr[6:0]), |
| 1196 | .dout (sync_out_opddq11_wr_addr[6:0]), |
| 1197 | .l1clk(l1clk), |
| 1198 | .siclk(siclk), |
| 1199 | .soclk(soclk) |
| 1200 | ); |
| 1201 | |
| 1202 | sio_opcc_ctl_msff_ctl_macro__width_5 ff_opdhq0_wr_addr_d1 ( |
| 1203 | .scan_in(ff_opdhq0_wr_addr_d1_scanin), |
| 1204 | .scan_out(ff_opdhq0_wr_addr_d1_scanout), |
| 1205 | .din (opdhq0_wr_addr[4:0]), |
| 1206 | .dout (opdhq0_wr_addr_d1[4:0]), |
| 1207 | .l1clk(l1clk), |
| 1208 | .siclk(siclk), |
| 1209 | .soclk(soclk) |
| 1210 | ); |
| 1211 | assign sync_in_opdhq0_wr_addr[4:0] = cmp_io_sync_en ? opdhq0_wr_addr_d1[4:0] : sync_out_opdhq0_wr_addr[4:0]; |
| 1212 | sio_opcc_ctl_msff_ctl_macro__width_5 ff_syn_opdhq0_wr_addr ( |
| 1213 | .scan_in(ff_syn_opdhq0_wr_addr_scanin), |
| 1214 | .scan_out(ff_syn_opdhq0_wr_addr_scanout), |
| 1215 | .din (sync_in_opdhq0_wr_addr[4:0]), |
| 1216 | .dout (sync_out_opdhq0_wr_addr[4:0]), |
| 1217 | .l1clk(l1clk), |
| 1218 | .siclk(siclk), |
| 1219 | .soclk(soclk) |
| 1220 | ); |
| 1221 | |
| 1222 | sio_opcc_ctl_msff_ctl_macro__width_5 ff_opdhq1_wr_addr_d1 ( |
| 1223 | .scan_in(ff_opdhq1_wr_addr_d1_scanin), |
| 1224 | .scan_out(ff_opdhq1_wr_addr_d1_scanout), |
| 1225 | .din (opdhq1_wr_addr[4:0]), |
| 1226 | .dout (opdhq1_wr_addr_d1[4:0]), |
| 1227 | .l1clk(l1clk), |
| 1228 | .siclk(siclk), |
| 1229 | .soclk(soclk) |
| 1230 | ); |
| 1231 | assign sync_in_opdhq1_wr_addr[4:0] = cmp_io_sync_en ? opdhq1_wr_addr_d1[4:0] : sync_out_opdhq1_wr_addr[4:0]; |
| 1232 | sio_opcc_ctl_msff_ctl_macro__width_5 ff_syn_opdhq1_wr_addr ( |
| 1233 | .scan_in(ff_syn_opdhq1_wr_addr_scanin), |
| 1234 | .scan_out(ff_syn_opdhq1_wr_addr_scanout), |
| 1235 | .din (sync_in_opdhq1_wr_addr[4:0]), |
| 1236 | .dout (sync_out_opdhq1_wr_addr[4:0]), |
| 1237 | .l1clk(l1clk), |
| 1238 | .siclk(siclk), |
| 1239 | .soclk(soclk) |
| 1240 | ); |
| 1241 | |
| 1242 | //--- |
| 1243 | |
| 1244 | assign sync_in_opdhq0_wr_en = opcc_opdhq0_wr_en ? 1'b1 : cmp_io_sync_en ? 1'b0 : sync_out_opdhq0_wr_en_d1; |
| 1245 | assign opdhq0_wr_en_tmp = sync_out_opdhq0_wr_en_d1 || sync_in_opdhq0_wr_en; |
| 1246 | assign sync_out_opdhq0_wr_en = sync_out_opdhq0_wr_en_d2 || sync_in_opdhq0_wr_en; |
| 1247 | |
| 1248 | sio_opcc_ctl_msff_ctl_macro__width_1 ff_syn_opdhq0_wr_en_d1 ( |
| 1249 | .scan_in(ff_syn_opdhq0_wr_en_d1_scanin), |
| 1250 | .scan_out(ff_syn_opdhq0_wr_en_d1_scanout), |
| 1251 | .din (sync_in_opdhq0_wr_en), |
| 1252 | .dout (sync_out_opdhq0_wr_en_d1), |
| 1253 | .l1clk(l1clk), |
| 1254 | .siclk(siclk), |
| 1255 | .soclk(soclk) |
| 1256 | ); |
| 1257 | |
| 1258 | sio_opcc_ctl_msff_ctl_macro__en_1__width_1 ff_syn_opdhq0_wr_en_d2 ( |
| 1259 | .scan_in(ff_syn_opdhq0_wr_en_d2_scanin), |
| 1260 | .scan_out(ff_syn_opdhq0_wr_en_d2_scanout), |
| 1261 | .en (cmp_io_sync_en), |
| 1262 | .din (opdhq0_wr_en_tmp), |
| 1263 | .dout (sync_out_opdhq0_wr_en_d2), |
| 1264 | .l1clk(l1clk), |
| 1265 | .siclk(siclk), |
| 1266 | .soclk(soclk) |
| 1267 | ); |
| 1268 | |
| 1269 | assign sync_in_opdhq1_wr_en = opcc_opdhq1_wr_en ? 1'b1 : cmp_io_sync_en ? 1'b0 : sync_out_opdhq1_wr_en_d1; |
| 1270 | assign opdhq1_wr_en_tmp = sync_out_opdhq1_wr_en_d1 || sync_in_opdhq1_wr_en; |
| 1271 | assign sync_out_opdhq1_wr_en = sync_out_opdhq1_wr_en_d2 || sync_in_opdhq1_wr_en; |
| 1272 | |
| 1273 | sio_opcc_ctl_msff_ctl_macro__width_1 ff_syn_opdhq1_wr_en_d1 ( |
| 1274 | .scan_in(ff_syn_opdhq1_wr_en_d1_scanin), |
| 1275 | .scan_out(ff_syn_opdhq1_wr_en_d1_scanout), |
| 1276 | .din (sync_in_opdhq1_wr_en), |
| 1277 | .dout (sync_out_opdhq1_wr_en_d1), |
| 1278 | .l1clk(l1clk), |
| 1279 | .siclk(siclk), |
| 1280 | .soclk(soclk) |
| 1281 | ); |
| 1282 | |
| 1283 | sio_opcc_ctl_msff_ctl_macro__width_1 ff_syn_opdhq1_wr_en_d2 ( |
| 1284 | // .en(cmp_io_sync_en), |
| 1285 | .scan_in(ff_syn_opdhq1_wr_en_d2_scanin), |
| 1286 | .scan_out(ff_syn_opdhq1_wr_en_d2_scanout), |
| 1287 | .din (opdhq1_wr_en_tmp), |
| 1288 | .dout (sync_out_opdhq1_wr_en_d2), |
| 1289 | .l1clk(l1clk), |
| 1290 | .siclk(siclk), |
| 1291 | .soclk(soclk) |
| 1292 | ); |
| 1293 | |
| 1294 | |
| 1295 | |
| 1296 | |
| 1297 | assign opcc_opcs_opddq00_wr_addr[6:0] = sync_out_opddq00_wr_addr[6:0]; // DMU dataq -- cmp domain synced, gray-coded + 1 bit |
| 1298 | assign opcc_opcs_opddq10_wr_addr[6:0] = sync_out_opddq10_wr_addr[6:0]; // ENT dataq -- cmp domain synced, gray-coded + 1 bit |
| 1299 | assign opcc_opcs_opddq01_wr_addr[6:0] = sync_out_opddq01_wr_addr[6:0]; // DMU dataq -- cmp domain synced, gray-coded + 1 bit |
| 1300 | assign opcc_opcs_opddq11_wr_addr[6:0] = sync_out_opddq11_wr_addr[6:0]; // ENT dataq -- cmp domain synced, gray-coded + 1 bit |
| 1301 | assign opcc_opcs_opdhq0_wr_addr[4:0] = sync_out_opdhq0_wr_addr[4:0]; // DMU hdrq -- cmp domain synced, gray-coded + 1 bit |
| 1302 | assign opcc_opcs_opdhq1_wr_addr[4:0] = sync_out_opdhq1_wr_addr[4:0]; // ENT hdrq -- cmp domain synced, gray-coded + 1 bit |
| 1303 | |
| 1304 | sio_opcc_ctl_msff_ctl_macro__width_1 reg_cmp_io_sync_en // ASYNC reset active low |
| 1305 | ( |
| 1306 | .scan_in(reg_cmp_io_sync_en_scanin), |
| 1307 | .scan_out(reg_cmp_io_sync_en_scanout), |
| 1308 | .dout(cmp_io_sync_en), |
| 1309 | .l1clk(l1clk), |
| 1310 | .din(cmp_io_sync_en_in), |
| 1311 | .siclk(siclk), |
| 1312 | .soclk(soclk) |
| 1313 | ); |
| 1314 | |
| 1315 | sio_opcc_ctl_msff_ctl_macro__width_1 reg_io_cmp_sync_en // ASYNC reset active low |
| 1316 | ( |
| 1317 | .scan_in(reg_io_cmp_sync_en_scanin), |
| 1318 | .scan_out(reg_io_cmp_sync_en_scanout), |
| 1319 | .dout(io_cmp_sync_en), |
| 1320 | .l1clk(l1clk), |
| 1321 | .din(io_cmp_sync_en_in), |
| 1322 | .siclk(siclk), |
| 1323 | .soclk(soclk) |
| 1324 | ); |
| 1325 | |
| 1326 | // fixscan start: |
| 1327 | assign spares_scanin = scan_in ; |
| 1328 | assign ff_tcu_jtag_scanin = spares_scanout ; |
| 1329 | assign ff_dqcnt_scanin = ff_tcu_jtag_scanout ; |
| 1330 | assign ff_syn_opdhq0_rd_addr_scanin = ff_dqcnt_scanout ; |
| 1331 | assign ff_opdhq0_rd_addr_scanin = ff_syn_opdhq0_rd_addr_scanout; |
| 1332 | assign ff_syn_opdhq1_rd_addr_scanin = ff_opdhq0_rd_addr_scanout; |
| 1333 | assign ff_opdhq1_rd_addr_scanin = ff_syn_opdhq1_rd_addr_scanout; |
| 1334 | assign ff_opdhq0sub_scanin = ff_opdhq1_rd_addr_scanout; |
| 1335 | assign ff_opdhq1sub_scanin = ff_opdhq0sub_scanout ; |
| 1336 | assign ff_slpstates_scanin = ff_opdhq1sub_scanout ; |
| 1337 | assign ff_buscnt_scanin = ff_slpstates_scanout ; |
| 1338 | assign ff_hqxwonstage_scanin = ff_buscnt_scanout ; |
| 1339 | assign ff_qxdatastage_scanin = ff_hqxwonstage_scanout ; |
| 1340 | assign ff_opdhq0_wr_addr_scanin = ff_qxdatastage_scanout ; |
| 1341 | assign ff_opdhq1_wr_addr_scanin = ff_opdhq0_wr_addr_scanout; |
| 1342 | assign ff_opddq00_wr_addr_scanin = ff_opdhq1_wr_addr_scanout; |
| 1343 | assign ff_opddq10_wr_addr_scanin = ff_opddq00_wr_addr_scanout; |
| 1344 | assign ff_opddq01_wr_addr_scanin = ff_opddq10_wr_addr_scanout; |
| 1345 | assign ff_opddq11_wr_addr_scanin = ff_opddq01_wr_addr_scanout; |
| 1346 | assign ff_opddq00_wr_addrinc_scanin = ff_opddq11_wr_addr_scanout; |
| 1347 | assign ff_opddq01_wr_addrinc_scanin = ff_opddq00_wr_addrinc_scanout; |
| 1348 | assign ff_opddq10_wr_addrinc_scanin = ff_opddq01_wr_addrinc_scanout; |
| 1349 | assign ff_opddq11_wr_addrinc_scanin = ff_opddq10_wr_addrinc_scanout; |
| 1350 | assign ff_opddq00_wr_addr_d1_scanin = ff_opddq11_wr_addrinc_scanout; |
| 1351 | assign ff_syn_opddq00_wr_addr_scanin = ff_opddq00_wr_addr_d1_scanout; |
| 1352 | assign ff_opddq01_wr_addr_d1_scanin = ff_syn_opddq00_wr_addr_scanout; |
| 1353 | assign ff_syn_opddq01_wr_addr_scanin = ff_opddq01_wr_addr_d1_scanout; |
| 1354 | assign ff_opddq10_wr_addr_d1_scanin = ff_syn_opddq01_wr_addr_scanout; |
| 1355 | assign ff_syn_opddq10_wr_addr_scanin = ff_opddq10_wr_addr_d1_scanout; |
| 1356 | assign ff_opddq11_wr_addr_d1_scanin = ff_syn_opddq10_wr_addr_scanout; |
| 1357 | assign ff_syn_opddq11_wr_addr_scanin = ff_opddq11_wr_addr_d1_scanout; |
| 1358 | assign ff_opdhq0_wr_addr_d1_scanin = ff_syn_opddq11_wr_addr_scanout; |
| 1359 | assign ff_syn_opdhq0_wr_addr_scanin = ff_opdhq0_wr_addr_d1_scanout; |
| 1360 | assign ff_opdhq1_wr_addr_d1_scanin = ff_syn_opdhq0_wr_addr_scanout; |
| 1361 | assign ff_syn_opdhq1_wr_addr_scanin = ff_opdhq1_wr_addr_d1_scanout; |
| 1362 | assign ff_syn_opdhq0_wr_en_d1_scanin = ff_syn_opdhq1_wr_addr_scanout; |
| 1363 | assign ff_syn_opdhq0_wr_en_d2_scanin = ff_syn_opdhq0_wr_en_d1_scanout; |
| 1364 | assign ff_syn_opdhq1_wr_en_d1_scanin = ff_syn_opdhq0_wr_en_d2_scanout; |
| 1365 | assign ff_syn_opdhq1_wr_en_d2_scanin = ff_syn_opdhq1_wr_en_d1_scanout; |
| 1366 | assign reg_cmp_io_sync_en_scanin = ff_syn_opdhq1_wr_en_d2_scanout; |
| 1367 | assign reg_io_cmp_sync_en_scanin = reg_cmp_io_sync_en_scanout; |
| 1368 | assign scan_out = reg_io_cmp_sync_en_scanout; |
| 1369 | // fixscan end: |
| 1370 | endmodule // sio_opcc_ctl |
| 1371 | |
| 1372 | |
| 1373 | |
| 1374 | |
| 1375 | |
| 1376 | |
| 1377 | // any PARAMS parms go into naming of macro |
| 1378 | |
| 1379 | module sio_opcc_ctl_l1clkhdr_ctl_macro ( |
| 1380 | l2clk, |
| 1381 | l1en, |
| 1382 | pce_ov, |
| 1383 | stop, |
| 1384 | se, |
| 1385 | l1clk); |
| 1386 | |
| 1387 | |
| 1388 | input l2clk; |
| 1389 | input l1en; |
| 1390 | input pce_ov; |
| 1391 | input stop; |
| 1392 | input se; |
| 1393 | output l1clk; |
| 1394 | |
| 1395 | |
| 1396 | |
| 1397 | |
| 1398 | |
| 1399 | cl_sc1_l1hdr_8x c_0 ( |
| 1400 | |
| 1401 | |
| 1402 | .l2clk(l2clk), |
| 1403 | .pce(l1en), |
| 1404 | .l1clk(l1clk), |
| 1405 | .se(se), |
| 1406 | .pce_ov(pce_ov), |
| 1407 | .stop(stop) |
| 1408 | ); |
| 1409 | |
| 1410 | |
| 1411 | |
| 1412 | endmodule |
| 1413 | |
| 1414 | |
| 1415 | |
| 1416 | |
| 1417 | |
| 1418 | |
| 1419 | |
| 1420 | |
| 1421 | |
| 1422 | // Description: Spare gate macro for control blocks |
| 1423 | // |
| 1424 | // Param num controls the number of times the macro is added |
| 1425 | // flops=0 can be used to use only combination spare logic |
| 1426 | |
| 1427 | |
| 1428 | module sio_opcc_ctl_spare_ctl_macro__num_3 ( |
| 1429 | l1clk, |
| 1430 | scan_in, |
| 1431 | siclk, |
| 1432 | soclk, |
| 1433 | scan_out); |
| 1434 | wire si_0; |
| 1435 | wire so_0; |
| 1436 | wire spare0_flop_unused; |
| 1437 | wire spare0_buf_32x_unused; |
| 1438 | wire spare0_nand3_8x_unused; |
| 1439 | wire spare0_inv_8x_unused; |
| 1440 | wire spare0_aoi22_4x_unused; |
| 1441 | wire spare0_buf_8x_unused; |
| 1442 | wire spare0_oai22_4x_unused; |
| 1443 | wire spare0_inv_16x_unused; |
| 1444 | wire spare0_nand2_16x_unused; |
| 1445 | wire spare0_nor3_4x_unused; |
| 1446 | wire spare0_nand2_8x_unused; |
| 1447 | wire spare0_buf_16x_unused; |
| 1448 | wire spare0_nor2_16x_unused; |
| 1449 | wire spare0_inv_32x_unused; |
| 1450 | wire si_1; |
| 1451 | wire so_1; |
| 1452 | wire spare1_flop_unused; |
| 1453 | wire spare1_buf_32x_unused; |
| 1454 | wire spare1_nand3_8x_unused; |
| 1455 | wire spare1_inv_8x_unused; |
| 1456 | wire spare1_aoi22_4x_unused; |
| 1457 | wire spare1_buf_8x_unused; |
| 1458 | wire spare1_oai22_4x_unused; |
| 1459 | wire spare1_inv_16x_unused; |
| 1460 | wire spare1_nand2_16x_unused; |
| 1461 | wire spare1_nor3_4x_unused; |
| 1462 | wire spare1_nand2_8x_unused; |
| 1463 | wire spare1_buf_16x_unused; |
| 1464 | wire spare1_nor2_16x_unused; |
| 1465 | wire spare1_inv_32x_unused; |
| 1466 | wire si_2; |
| 1467 | wire so_2; |
| 1468 | wire spare2_flop_unused; |
| 1469 | wire spare2_buf_32x_unused; |
| 1470 | wire spare2_nand3_8x_unused; |
| 1471 | wire spare2_inv_8x_unused; |
| 1472 | wire spare2_aoi22_4x_unused; |
| 1473 | wire spare2_buf_8x_unused; |
| 1474 | wire spare2_oai22_4x_unused; |
| 1475 | wire spare2_inv_16x_unused; |
| 1476 | wire spare2_nand2_16x_unused; |
| 1477 | wire spare2_nor3_4x_unused; |
| 1478 | wire spare2_nand2_8x_unused; |
| 1479 | wire spare2_buf_16x_unused; |
| 1480 | wire spare2_nor2_16x_unused; |
| 1481 | wire spare2_inv_32x_unused; |
| 1482 | |
| 1483 | |
| 1484 | input l1clk; |
| 1485 | input scan_in; |
| 1486 | input siclk; |
| 1487 | input soclk; |
| 1488 | output scan_out; |
| 1489 | |
| 1490 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 1491 | .siclk(siclk), |
| 1492 | .soclk(soclk), |
| 1493 | .si(si_0), |
| 1494 | .so(so_0), |
| 1495 | .d(1'b0), |
| 1496 | .q(spare0_flop_unused)); |
| 1497 | assign si_0 = scan_in; |
| 1498 | |
| 1499 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 1500 | .out(spare0_buf_32x_unused)); |
| 1501 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 1502 | .in1(1'b1), |
| 1503 | .in2(1'b1), |
| 1504 | .out(spare0_nand3_8x_unused)); |
| 1505 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 1506 | .out(spare0_inv_8x_unused)); |
| 1507 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 1508 | .in01(1'b1), |
| 1509 | .in10(1'b1), |
| 1510 | .in11(1'b1), |
| 1511 | .out(spare0_aoi22_4x_unused)); |
| 1512 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 1513 | .out(spare0_buf_8x_unused)); |
| 1514 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 1515 | .in01(1'b1), |
| 1516 | .in10(1'b1), |
| 1517 | .in11(1'b1), |
| 1518 | .out(spare0_oai22_4x_unused)); |
| 1519 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 1520 | .out(spare0_inv_16x_unused)); |
| 1521 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 1522 | .in1(1'b1), |
| 1523 | .out(spare0_nand2_16x_unused)); |
| 1524 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 1525 | .in1(1'b0), |
| 1526 | .in2(1'b0), |
| 1527 | .out(spare0_nor3_4x_unused)); |
| 1528 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 1529 | .in1(1'b1), |
| 1530 | .out(spare0_nand2_8x_unused)); |
| 1531 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 1532 | .out(spare0_buf_16x_unused)); |
| 1533 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 1534 | .in1(1'b0), |
| 1535 | .out(spare0_nor2_16x_unused)); |
| 1536 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 1537 | .out(spare0_inv_32x_unused)); |
| 1538 | |
| 1539 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 1540 | .siclk(siclk), |
| 1541 | .soclk(soclk), |
| 1542 | .si(si_1), |
| 1543 | .so(so_1), |
| 1544 | .d(1'b0), |
| 1545 | .q(spare1_flop_unused)); |
| 1546 | assign si_1 = so_0; |
| 1547 | |
| 1548 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 1549 | .out(spare1_buf_32x_unused)); |
| 1550 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 1551 | .in1(1'b1), |
| 1552 | .in2(1'b1), |
| 1553 | .out(spare1_nand3_8x_unused)); |
| 1554 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 1555 | .out(spare1_inv_8x_unused)); |
| 1556 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 1557 | .in01(1'b1), |
| 1558 | .in10(1'b1), |
| 1559 | .in11(1'b1), |
| 1560 | .out(spare1_aoi22_4x_unused)); |
| 1561 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 1562 | .out(spare1_buf_8x_unused)); |
| 1563 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 1564 | .in01(1'b1), |
| 1565 | .in10(1'b1), |
| 1566 | .in11(1'b1), |
| 1567 | .out(spare1_oai22_4x_unused)); |
| 1568 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 1569 | .out(spare1_inv_16x_unused)); |
| 1570 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 1571 | .in1(1'b1), |
| 1572 | .out(spare1_nand2_16x_unused)); |
| 1573 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 1574 | .in1(1'b0), |
| 1575 | .in2(1'b0), |
| 1576 | .out(spare1_nor3_4x_unused)); |
| 1577 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 1578 | .in1(1'b1), |
| 1579 | .out(spare1_nand2_8x_unused)); |
| 1580 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 1581 | .out(spare1_buf_16x_unused)); |
| 1582 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 1583 | .in1(1'b0), |
| 1584 | .out(spare1_nor2_16x_unused)); |
| 1585 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 1586 | .out(spare1_inv_32x_unused)); |
| 1587 | |
| 1588 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), |
| 1589 | .siclk(siclk), |
| 1590 | .soclk(soclk), |
| 1591 | .si(si_2), |
| 1592 | .so(so_2), |
| 1593 | .d(1'b0), |
| 1594 | .q(spare2_flop_unused)); |
| 1595 | assign si_2 = so_1; |
| 1596 | |
| 1597 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), |
| 1598 | .out(spare2_buf_32x_unused)); |
| 1599 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), |
| 1600 | .in1(1'b1), |
| 1601 | .in2(1'b1), |
| 1602 | .out(spare2_nand3_8x_unused)); |
| 1603 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), |
| 1604 | .out(spare2_inv_8x_unused)); |
| 1605 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), |
| 1606 | .in01(1'b1), |
| 1607 | .in10(1'b1), |
| 1608 | .in11(1'b1), |
| 1609 | .out(spare2_aoi22_4x_unused)); |
| 1610 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), |
| 1611 | .out(spare2_buf_8x_unused)); |
| 1612 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), |
| 1613 | .in01(1'b1), |
| 1614 | .in10(1'b1), |
| 1615 | .in11(1'b1), |
| 1616 | .out(spare2_oai22_4x_unused)); |
| 1617 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), |
| 1618 | .out(spare2_inv_16x_unused)); |
| 1619 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), |
| 1620 | .in1(1'b1), |
| 1621 | .out(spare2_nand2_16x_unused)); |
| 1622 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), |
| 1623 | .in1(1'b0), |
| 1624 | .in2(1'b0), |
| 1625 | .out(spare2_nor3_4x_unused)); |
| 1626 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), |
| 1627 | .in1(1'b1), |
| 1628 | .out(spare2_nand2_8x_unused)); |
| 1629 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), |
| 1630 | .out(spare2_buf_16x_unused)); |
| 1631 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), |
| 1632 | .in1(1'b0), |
| 1633 | .out(spare2_nor2_16x_unused)); |
| 1634 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), |
| 1635 | .out(spare2_inv_32x_unused)); |
| 1636 | assign scan_out = so_2; |
| 1637 | |
| 1638 | |
| 1639 | |
| 1640 | endmodule |
| 1641 | |
| 1642 | |
| 1643 | |
| 1644 | |
| 1645 | |
| 1646 | |
| 1647 | // any PARAMS parms go into naming of macro |
| 1648 | |
| 1649 | module sio_opcc_ctl_msff_ctl_macro__width_2 ( |
| 1650 | din, |
| 1651 | l1clk, |
| 1652 | scan_in, |
| 1653 | siclk, |
| 1654 | soclk, |
| 1655 | dout, |
| 1656 | scan_out); |
| 1657 | wire [1:0] fdin; |
| 1658 | wire [0:0] so; |
| 1659 | |
| 1660 | input [1:0] din; |
| 1661 | input l1clk; |
| 1662 | input scan_in; |
| 1663 | |
| 1664 | |
| 1665 | input siclk; |
| 1666 | input soclk; |
| 1667 | |
| 1668 | output [1:0] dout; |
| 1669 | output scan_out; |
| 1670 | assign fdin[1:0] = din[1:0]; |
| 1671 | |
| 1672 | |
| 1673 | |
| 1674 | |
| 1675 | |
| 1676 | |
| 1677 | dff #(2) d0_0 ( |
| 1678 | .l1clk(l1clk), |
| 1679 | .siclk(siclk), |
| 1680 | .soclk(soclk), |
| 1681 | .d(fdin[1:0]), |
| 1682 | .si({scan_in,so[0:0]}), |
| 1683 | .so({so[0:0],scan_out}), |
| 1684 | .q(dout[1:0]) |
| 1685 | ); |
| 1686 | |
| 1687 | |
| 1688 | |
| 1689 | |
| 1690 | |
| 1691 | |
| 1692 | |
| 1693 | |
| 1694 | |
| 1695 | |
| 1696 | |
| 1697 | |
| 1698 | endmodule |
| 1699 | |
| 1700 | |
| 1701 | |
| 1702 | |
| 1703 | |
| 1704 | |
| 1705 | |
| 1706 | |
| 1707 | |
| 1708 | |
| 1709 | |
| 1710 | |
| 1711 | |
| 1712 | // any PARAMS parms go into naming of macro |
| 1713 | |
| 1714 | module sio_opcc_ctl_msff_ctl_macro__width_12 ( |
| 1715 | din, |
| 1716 | l1clk, |
| 1717 | scan_in, |
| 1718 | siclk, |
| 1719 | soclk, |
| 1720 | dout, |
| 1721 | scan_out); |
| 1722 | wire [11:0] fdin; |
| 1723 | wire [10:0] so; |
| 1724 | |
| 1725 | input [11:0] din; |
| 1726 | input l1clk; |
| 1727 | input scan_in; |
| 1728 | |
| 1729 | |
| 1730 | input siclk; |
| 1731 | input soclk; |
| 1732 | |
| 1733 | output [11:0] dout; |
| 1734 | output scan_out; |
| 1735 | assign fdin[11:0] = din[11:0]; |
| 1736 | |
| 1737 | |
| 1738 | |
| 1739 | |
| 1740 | |
| 1741 | |
| 1742 | dff #(12) d0_0 ( |
| 1743 | .l1clk(l1clk), |
| 1744 | .siclk(siclk), |
| 1745 | .soclk(soclk), |
| 1746 | .d(fdin[11:0]), |
| 1747 | .si({scan_in,so[10:0]}), |
| 1748 | .so({so[10:0],scan_out}), |
| 1749 | .q(dout[11:0]) |
| 1750 | ); |
| 1751 | |
| 1752 | |
| 1753 | |
| 1754 | |
| 1755 | |
| 1756 | |
| 1757 | |
| 1758 | |
| 1759 | |
| 1760 | |
| 1761 | |
| 1762 | |
| 1763 | endmodule |
| 1764 | |
| 1765 | |
| 1766 | |
| 1767 | |
| 1768 | |
| 1769 | |
| 1770 | |
| 1771 | |
| 1772 | |
| 1773 | |
| 1774 | |
| 1775 | |
| 1776 | |
| 1777 | // any PARAMS parms go into naming of macro |
| 1778 | |
| 1779 | module sio_opcc_ctl_msff_ctl_macro__width_5 ( |
| 1780 | din, |
| 1781 | l1clk, |
| 1782 | scan_in, |
| 1783 | siclk, |
| 1784 | soclk, |
| 1785 | dout, |
| 1786 | scan_out); |
| 1787 | wire [4:0] fdin; |
| 1788 | wire [3:0] so; |
| 1789 | |
| 1790 | input [4:0] din; |
| 1791 | input l1clk; |
| 1792 | input scan_in; |
| 1793 | |
| 1794 | |
| 1795 | input siclk; |
| 1796 | input soclk; |
| 1797 | |
| 1798 | output [4:0] dout; |
| 1799 | output scan_out; |
| 1800 | assign fdin[4:0] = din[4:0]; |
| 1801 | |
| 1802 | |
| 1803 | |
| 1804 | |
| 1805 | |
| 1806 | |
| 1807 | dff #(5) d0_0 ( |
| 1808 | .l1clk(l1clk), |
| 1809 | .siclk(siclk), |
| 1810 | .soclk(soclk), |
| 1811 | .d(fdin[4:0]), |
| 1812 | .si({scan_in,so[3:0]}), |
| 1813 | .so({so[3:0],scan_out}), |
| 1814 | .q(dout[4:0]) |
| 1815 | ); |
| 1816 | |
| 1817 | |
| 1818 | |
| 1819 | |
| 1820 | |
| 1821 | |
| 1822 | |
| 1823 | |
| 1824 | |
| 1825 | |
| 1826 | |
| 1827 | |
| 1828 | endmodule |
| 1829 | |
| 1830 | |
| 1831 | |
| 1832 | |
| 1833 | |
| 1834 | |
| 1835 | |
| 1836 | |
| 1837 | |
| 1838 | |
| 1839 | |
| 1840 | |
| 1841 | |
| 1842 | // any PARAMS parms go into naming of macro |
| 1843 | |
| 1844 | module sio_opcc_ctl_msff_ctl_macro__width_42 ( |
| 1845 | din, |
| 1846 | l1clk, |
| 1847 | scan_in, |
| 1848 | siclk, |
| 1849 | soclk, |
| 1850 | dout, |
| 1851 | scan_out); |
| 1852 | wire [41:0] fdin; |
| 1853 | wire [40:0] so; |
| 1854 | |
| 1855 | input [41:0] din; |
| 1856 | input l1clk; |
| 1857 | input scan_in; |
| 1858 | |
| 1859 | |
| 1860 | input siclk; |
| 1861 | input soclk; |
| 1862 | |
| 1863 | output [41:0] dout; |
| 1864 | output scan_out; |
| 1865 | assign fdin[41:0] = din[41:0]; |
| 1866 | |
| 1867 | |
| 1868 | |
| 1869 | |
| 1870 | |
| 1871 | |
| 1872 | dff #(42) d0_0 ( |
| 1873 | .l1clk(l1clk), |
| 1874 | .siclk(siclk), |
| 1875 | .soclk(soclk), |
| 1876 | .d(fdin[41:0]), |
| 1877 | .si({scan_in,so[40:0]}), |
| 1878 | .so({so[40:0],scan_out}), |
| 1879 | .q(dout[41:0]) |
| 1880 | ); |
| 1881 | |
| 1882 | |
| 1883 | |
| 1884 | |
| 1885 | |
| 1886 | |
| 1887 | |
| 1888 | |
| 1889 | |
| 1890 | |
| 1891 | |
| 1892 | |
| 1893 | endmodule |
| 1894 | |
| 1895 | |
| 1896 | |
| 1897 | |
| 1898 | |
| 1899 | |
| 1900 | |
| 1901 | |
| 1902 | |
| 1903 | |
| 1904 | |
| 1905 | |
| 1906 | |
| 1907 | // any PARAMS parms go into naming of macro |
| 1908 | |
| 1909 | module sio_opcc_ctl_msff_ctl_macro__width_3 ( |
| 1910 | din, |
| 1911 | l1clk, |
| 1912 | scan_in, |
| 1913 | siclk, |
| 1914 | soclk, |
| 1915 | dout, |
| 1916 | scan_out); |
| 1917 | wire [2:0] fdin; |
| 1918 | wire [1:0] so; |
| 1919 | |
| 1920 | input [2:0] din; |
| 1921 | input l1clk; |
| 1922 | input scan_in; |
| 1923 | |
| 1924 | |
| 1925 | input siclk; |
| 1926 | input soclk; |
| 1927 | |
| 1928 | output [2:0] dout; |
| 1929 | output scan_out; |
| 1930 | assign fdin[2:0] = din[2:0]; |
| 1931 | |
| 1932 | |
| 1933 | |
| 1934 | |
| 1935 | |
| 1936 | |
| 1937 | dff #(3) d0_0 ( |
| 1938 | .l1clk(l1clk), |
| 1939 | .siclk(siclk), |
| 1940 | .soclk(soclk), |
| 1941 | .d(fdin[2:0]), |
| 1942 | .si({scan_in,so[1:0]}), |
| 1943 | .so({so[1:0],scan_out}), |
| 1944 | .q(dout[2:0]) |
| 1945 | ); |
| 1946 | |
| 1947 | |
| 1948 | |
| 1949 | |
| 1950 | |
| 1951 | |
| 1952 | |
| 1953 | |
| 1954 | |
| 1955 | |
| 1956 | |
| 1957 | |
| 1958 | endmodule |
| 1959 | |
| 1960 | |
| 1961 | |
| 1962 | |
| 1963 | |
| 1964 | |
| 1965 | |
| 1966 | |
| 1967 | |
| 1968 | |
| 1969 | |
| 1970 | |
| 1971 | |
| 1972 | // any PARAMS parms go into naming of macro |
| 1973 | |
| 1974 | module sio_opcc_ctl_msff_ctl_macro__width_4 ( |
| 1975 | din, |
| 1976 | l1clk, |
| 1977 | scan_in, |
| 1978 | siclk, |
| 1979 | soclk, |
| 1980 | dout, |
| 1981 | scan_out); |
| 1982 | wire [3:0] fdin; |
| 1983 | wire [2:0] so; |
| 1984 | |
| 1985 | input [3:0] din; |
| 1986 | input l1clk; |
| 1987 | input scan_in; |
| 1988 | |
| 1989 | |
| 1990 | input siclk; |
| 1991 | input soclk; |
| 1992 | |
| 1993 | output [3:0] dout; |
| 1994 | output scan_out; |
| 1995 | assign fdin[3:0] = din[3:0]; |
| 1996 | |
| 1997 | |
| 1998 | |
| 1999 | |
| 2000 | |
| 2001 | |
| 2002 | dff #(4) d0_0 ( |
| 2003 | .l1clk(l1clk), |
| 2004 | .siclk(siclk), |
| 2005 | .soclk(soclk), |
| 2006 | .d(fdin[3:0]), |
| 2007 | .si({scan_in,so[2:0]}), |
| 2008 | .so({so[2:0],scan_out}), |
| 2009 | .q(dout[3:0]) |
| 2010 | ); |
| 2011 | |
| 2012 | |
| 2013 | |
| 2014 | |
| 2015 | |
| 2016 | |
| 2017 | |
| 2018 | |
| 2019 | |
| 2020 | |
| 2021 | |
| 2022 | |
| 2023 | endmodule |
| 2024 | |
| 2025 | |
| 2026 | |
| 2027 | |
| 2028 | |
| 2029 | |
| 2030 | |
| 2031 | |
| 2032 | |
| 2033 | |
| 2034 | |
| 2035 | |
| 2036 | |
| 2037 | // any PARAMS parms go into naming of macro |
| 2038 | |
| 2039 | module sio_opcc_ctl_msff_ctl_macro__width_16 ( |
| 2040 | din, |
| 2041 | l1clk, |
| 2042 | scan_in, |
| 2043 | siclk, |
| 2044 | soclk, |
| 2045 | dout, |
| 2046 | scan_out); |
| 2047 | wire [15:0] fdin; |
| 2048 | wire [14:0] so; |
| 2049 | |
| 2050 | input [15:0] din; |
| 2051 | input l1clk; |
| 2052 | input scan_in; |
| 2053 | |
| 2054 | |
| 2055 | input siclk; |
| 2056 | input soclk; |
| 2057 | |
| 2058 | output [15:0] dout; |
| 2059 | output scan_out; |
| 2060 | assign fdin[15:0] = din[15:0]; |
| 2061 | |
| 2062 | |
| 2063 | |
| 2064 | |
| 2065 | |
| 2066 | |
| 2067 | dff #(16) d0_0 ( |
| 2068 | .l1clk(l1clk), |
| 2069 | .siclk(siclk), |
| 2070 | .soclk(soclk), |
| 2071 | .d(fdin[15:0]), |
| 2072 | .si({scan_in,so[14:0]}), |
| 2073 | .so({so[14:0],scan_out}), |
| 2074 | .q(dout[15:0]) |
| 2075 | ); |
| 2076 | |
| 2077 | |
| 2078 | |
| 2079 | |
| 2080 | |
| 2081 | |
| 2082 | |
| 2083 | |
| 2084 | |
| 2085 | |
| 2086 | |
| 2087 | |
| 2088 | endmodule |
| 2089 | |
| 2090 | |
| 2091 | |
| 2092 | |
| 2093 | |
| 2094 | |
| 2095 | |
| 2096 | |
| 2097 | |
| 2098 | |
| 2099 | |
| 2100 | |
| 2101 | |
| 2102 | // any PARAMS parms go into naming of macro |
| 2103 | |
| 2104 | module sio_opcc_ctl_msff_ctl_macro__width_7 ( |
| 2105 | din, |
| 2106 | l1clk, |
| 2107 | scan_in, |
| 2108 | siclk, |
| 2109 | soclk, |
| 2110 | dout, |
| 2111 | scan_out); |
| 2112 | wire [6:0] fdin; |
| 2113 | wire [5:0] so; |
| 2114 | |
| 2115 | input [6:0] din; |
| 2116 | input l1clk; |
| 2117 | input scan_in; |
| 2118 | |
| 2119 | |
| 2120 | input siclk; |
| 2121 | input soclk; |
| 2122 | |
| 2123 | output [6:0] dout; |
| 2124 | output scan_out; |
| 2125 | assign fdin[6:0] = din[6:0]; |
| 2126 | |
| 2127 | |
| 2128 | |
| 2129 | |
| 2130 | |
| 2131 | |
| 2132 | dff #(7) d0_0 ( |
| 2133 | .l1clk(l1clk), |
| 2134 | .siclk(siclk), |
| 2135 | .soclk(soclk), |
| 2136 | .d(fdin[6:0]), |
| 2137 | .si({scan_in,so[5:0]}), |
| 2138 | .so({so[5:0],scan_out}), |
| 2139 | .q(dout[6:0]) |
| 2140 | ); |
| 2141 | |
| 2142 | |
| 2143 | |
| 2144 | |
| 2145 | |
| 2146 | |
| 2147 | |
| 2148 | |
| 2149 | |
| 2150 | |
| 2151 | |
| 2152 | |
| 2153 | endmodule |
| 2154 | |
| 2155 | |
| 2156 | |
| 2157 | |
| 2158 | |
| 2159 | |
| 2160 | |
| 2161 | |
| 2162 | |
| 2163 | |
| 2164 | |
| 2165 | |
| 2166 | |
| 2167 | // any PARAMS parms go into naming of macro |
| 2168 | |
| 2169 | module sio_opcc_ctl_msff_ctl_macro__width_1 ( |
| 2170 | din, |
| 2171 | l1clk, |
| 2172 | scan_in, |
| 2173 | siclk, |
| 2174 | soclk, |
| 2175 | dout, |
| 2176 | scan_out); |
| 2177 | wire [0:0] fdin; |
| 2178 | |
| 2179 | input [0:0] din; |
| 2180 | input l1clk; |
| 2181 | input scan_in; |
| 2182 | |
| 2183 | |
| 2184 | input siclk; |
| 2185 | input soclk; |
| 2186 | |
| 2187 | output [0:0] dout; |
| 2188 | output scan_out; |
| 2189 | assign fdin[0:0] = din[0:0]; |
| 2190 | |
| 2191 | |
| 2192 | |
| 2193 | |
| 2194 | |
| 2195 | |
| 2196 | dff #(1) d0_0 ( |
| 2197 | .l1clk(l1clk), |
| 2198 | .siclk(siclk), |
| 2199 | .soclk(soclk), |
| 2200 | .d(fdin[0:0]), |
| 2201 | .si(scan_in), |
| 2202 | .so(scan_out), |
| 2203 | .q(dout[0:0]) |
| 2204 | ); |
| 2205 | |
| 2206 | |
| 2207 | |
| 2208 | |
| 2209 | |
| 2210 | |
| 2211 | |
| 2212 | |
| 2213 | |
| 2214 | |
| 2215 | |
| 2216 | |
| 2217 | endmodule |
| 2218 | |
| 2219 | |
| 2220 | |
| 2221 | |
| 2222 | |
| 2223 | |
| 2224 | |
| 2225 | |
| 2226 | |
| 2227 | |
| 2228 | |
| 2229 | |
| 2230 | |
| 2231 | // any PARAMS parms go into naming of macro |
| 2232 | |
| 2233 | module sio_opcc_ctl_msff_ctl_macro__en_1__width_1 ( |
| 2234 | din, |
| 2235 | en, |
| 2236 | l1clk, |
| 2237 | scan_in, |
| 2238 | siclk, |
| 2239 | soclk, |
| 2240 | dout, |
| 2241 | scan_out); |
| 2242 | wire [0:0] fdin; |
| 2243 | |
| 2244 | input [0:0] din; |
| 2245 | input en; |
| 2246 | input l1clk; |
| 2247 | input scan_in; |
| 2248 | |
| 2249 | |
| 2250 | input siclk; |
| 2251 | input soclk; |
| 2252 | |
| 2253 | output [0:0] dout; |
| 2254 | output scan_out; |
| 2255 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); |
| 2256 | |
| 2257 | |
| 2258 | |
| 2259 | |
| 2260 | |
| 2261 | |
| 2262 | dff #(1) d0_0 ( |
| 2263 | .l1clk(l1clk), |
| 2264 | .siclk(siclk), |
| 2265 | .soclk(soclk), |
| 2266 | .d(fdin[0:0]), |
| 2267 | .si(scan_in), |
| 2268 | .so(scan_out), |
| 2269 | .q(dout[0:0]) |
| 2270 | ); |
| 2271 | |
| 2272 | |
| 2273 | |
| 2274 | |
| 2275 | |
| 2276 | |
| 2277 | |
| 2278 | |
| 2279 | |
| 2280 | |
| 2281 | |
| 2282 | |
| 2283 | endmodule |
| 2284 | |
| 2285 | |
| 2286 | |
| 2287 | |
| 2288 | |
| 2289 | |
| 2290 | |
| 2291 | |