| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fgu_fdc_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module fgu_fdc_ctl ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | tcu_pce_ov, |
| 39 | spc_aclk, |
| 40 | spc_bclk, |
| 41 | tcu_scan_en, |
| 42 | scan_out, |
| 43 | fac_div_flush_fx3, |
| 44 | fpe_rs2_fmt_fx1_b0, |
| 45 | fpf_hi_bof_fx1, |
| 46 | fpf_lo_bof_fx1, |
| 47 | fpf_sa_xor_sb_fx1, |
| 48 | fac_div_valid_fx1, |
| 49 | fac_divq_valid_fx1, |
| 50 | fac_div_control_fx1, |
| 51 | fpc_rd_mode_fx3, |
| 52 | fpc_emin_fx3, |
| 53 | div_clken, |
| 54 | fdd_pe_clth, |
| 55 | fdd_cla_zero32_, |
| 56 | fdd_cla_zero64_, |
| 57 | fdd_result, |
| 58 | fdd_fdx_din0, |
| 59 | fdd_fdx_din1, |
| 60 | fdd_fdx_cin64, |
| 61 | fdd_fdq00_10_sum, |
| 62 | fdd_fdq00_10_carry, |
| 63 | fdd_fdq1p_sum, |
| 64 | fdd_fdq1p_carry, |
| 65 | fdd_fdq1n_sum, |
| 66 | fdd_fdq1n_carry, |
| 67 | fgu_fdiv_stall, |
| 68 | fgu_idiv_stall, |
| 69 | fdc_dec_exp_early, |
| 70 | fdc_icc_v_early, |
| 71 | fdc_xicc_z_early, |
| 72 | fdc_finish_int_early, |
| 73 | fdc_finish_fltd_early, |
| 74 | fdc_finish_flts_early, |
| 75 | fdc_flt_inexact, |
| 76 | fdc_asign_lth, |
| 77 | fdc_bsign_lth, |
| 78 | fdc_bsign_lth_, |
| 79 | fdc_pe_cycle3, |
| 80 | fdc_pe_cmux_sel, |
| 81 | fdc_pe_smux_sel, |
| 82 | fdc_pe_xsht_ctl, |
| 83 | fdc_ie_fsqrt_valid_even, |
| 84 | fdc_ie_fsqrt_valid_even_, |
| 85 | fdc_ie_fsqrt_valid_odd, |
| 86 | fdc_ie_fsqrt_valid_odd_, |
| 87 | fdc_ie_rmux_sel, |
| 88 | fdc_ie_dmux_sel, |
| 89 | fdc_flt_increment, |
| 90 | fdc_pte_clasel, |
| 91 | fdc_pte_csa_cin, |
| 92 | fdc_pte_cycle2, |
| 93 | fdc_emin_lth, |
| 94 | fdc_pte_qsel, |
| 95 | fdc_pte_stall_, |
| 96 | fdc_flt_round, |
| 97 | fdc_idiv_ctl, |
| 98 | fdc_fdx_cin_in, |
| 99 | fdc_qsel00, |
| 100 | fdc_qsel1, |
| 101 | fdc_q_in, |
| 102 | fdc_qm1_in); |
| 103 | wire pce_ov; |
| 104 | wire stop; |
| 105 | wire siclk; |
| 106 | wire soclk; |
| 107 | wire se; |
| 108 | wire l1clk_pm1; |
| 109 | wire spares_scanin; |
| 110 | wire spares_scanout; |
| 111 | wire incoming_sign_fx1; |
| 112 | wire [7:0] qcontrol_in; |
| 113 | wire fsqrt_fract_all_ones; |
| 114 | wire [7:0] qcontrol_fx1; |
| 115 | wire qdata_lth_scanin; |
| 116 | wire qdata_lth_scanout; |
| 117 | wire valid_in; |
| 118 | wire valid_lth; |
| 119 | wire [3:0] fdc_pte_cycle; |
| 120 | wire div_flush_lth; |
| 121 | wire [3:1] pe_cycle_in; |
| 122 | wire [3:1] fdc_pe_cycle; |
| 123 | wire engine_running_in; |
| 124 | wire engine_stop; |
| 125 | wire engine_running_lth; |
| 126 | wire engine_on; |
| 127 | wire [7:0] pe_ndq; |
| 128 | wire [3:0] pte_cycle_in; |
| 129 | wire [4:0] control_lth; |
| 130 | wire cntl_lth_scanin; |
| 131 | wire cntl_lth_scanout; |
| 132 | wire [2:0] pe_hmux_sel; |
| 133 | wire b_neg_one; |
| 134 | wire [7:0] pe_xsht_amt; |
| 135 | wire a_neg_max; |
| 136 | wire ovfl_64_in; |
| 137 | wire b_neg_one_lth; |
| 138 | wire finish_raw; |
| 139 | wire ovfl_64_lth; |
| 140 | wire flt_shift_sel_; |
| 141 | wire ovlf_lth_scanin; |
| 142 | wire ovlf_lth_scanout; |
| 143 | wire cla_zero64_lth_; |
| 144 | wire cla_zero32_lth_; |
| 145 | wire fdiv_stall_in; |
| 146 | wire stall_hold; |
| 147 | wire idiv_stall_in; |
| 148 | wire stall_hold_in; |
| 149 | wire [3:0] stall_cnt_raw; |
| 150 | wire [3:0] stall_cnt_in; |
| 151 | wire finish_lth; |
| 152 | wire [3:0] stall_cnt; |
| 153 | wire stall_lth_scanin; |
| 154 | wire stall_lth_scanout; |
| 155 | wire finish_lth_in; |
| 156 | wire idiv_stall_lth; |
| 157 | wire [4:0] control_in; |
| 158 | wire asign_in; |
| 159 | wire bsign_in; |
| 160 | wire ndq_odd_in; |
| 161 | wire data_lth_scanin; |
| 162 | wire data_lth_scanout; |
| 163 | wire ndq_odd_lth; |
| 164 | wire ndq_odd_2lth; |
| 165 | wire [63:0] clth; |
| 166 | wire b0_nor_76; |
| 167 | wire b0_nor_54; |
| 168 | wire b0_nor_32; |
| 169 | wire b0_nor_10; |
| 170 | wire b0_zeroh_; |
| 171 | wire b0_zerol_; |
| 172 | wire b0_zero_; |
| 173 | wire [1:0] b0_cnth; |
| 174 | wire [1:0] b0_cntl; |
| 175 | wire [2:0] b0_cnt; |
| 176 | wire b1_nor_76; |
| 177 | wire b1_nor_54; |
| 178 | wire b1_nor_32; |
| 179 | wire b1_nor_10; |
| 180 | wire b1_zeroh_; |
| 181 | wire b1_zerol_; |
| 182 | wire b1_zero_; |
| 183 | wire [1:0] b1_cnth; |
| 184 | wire [1:0] b1_cntl; |
| 185 | wire [2:0] b1_cnt; |
| 186 | wire b2_nor_76; |
| 187 | wire b2_nor_54; |
| 188 | wire b2_nor_32; |
| 189 | wire b2_nor_10; |
| 190 | wire b2_zeroh_; |
| 191 | wire b2_zerol_; |
| 192 | wire b2_zero_; |
| 193 | wire [1:0] b2_cnth; |
| 194 | wire [1:0] b2_cntl; |
| 195 | wire [2:0] b2_cnt; |
| 196 | wire b3_nor_76; |
| 197 | wire b3_nor_54; |
| 198 | wire b3_nor_32; |
| 199 | wire b3_nor_10; |
| 200 | wire b3_zeroh_; |
| 201 | wire b3_zerol_; |
| 202 | wire b3_zero_; |
| 203 | wire [1:0] b3_cnth; |
| 204 | wire [1:0] b3_cntl; |
| 205 | wire [2:0] b3_cnt; |
| 206 | wire b4_nor_76; |
| 207 | wire b4_nor_54; |
| 208 | wire b4_nor_32; |
| 209 | wire b4_nor_10; |
| 210 | wire b4_zeroh_; |
| 211 | wire b4_zerol_; |
| 212 | wire b4_zero_; |
| 213 | wire [1:0] b4_cnth; |
| 214 | wire [1:0] b4_cntl; |
| 215 | wire [2:0] b4_cnt; |
| 216 | wire b5_nor_76; |
| 217 | wire b5_nor_54; |
| 218 | wire b5_nor_32; |
| 219 | wire b5_nor_10; |
| 220 | wire b5_zeroh_; |
| 221 | wire b5_zerol_; |
| 222 | wire b5_zero_; |
| 223 | wire [1:0] b5_cnth; |
| 224 | wire [1:0] b5_cntl; |
| 225 | wire [2:0] b5_cnt; |
| 226 | wire b6_nor_76; |
| 227 | wire b6_nor_54; |
| 228 | wire b6_nor_32; |
| 229 | wire b6_nor_10; |
| 230 | wire b6_zeroh_; |
| 231 | wire b6_zerol_; |
| 232 | wire b6_zero_; |
| 233 | wire [1:0] b6_cnth; |
| 234 | wire [1:0] b6_cntl; |
| 235 | wire [2:0] b6_cnt; |
| 236 | wire b7_nor_76; |
| 237 | wire b7_nor_54; |
| 238 | wire b7_nor_32; |
| 239 | wire b7_nor_10; |
| 240 | wire b7_zeroh_; |
| 241 | wire b7_zerol_; |
| 242 | wire b7_zero_; |
| 243 | wire [1:0] b7_cnth; |
| 244 | wire [1:0] b7_cntl; |
| 245 | wire [2:0] b7_cnt; |
| 246 | wire b3_0sel; |
| 247 | wire b2_0sel; |
| 248 | wire b1_0sel; |
| 249 | wire b0_0sel; |
| 250 | wire [4:0] cntl0l; |
| 251 | wire b7_0sel; |
| 252 | wire b6_0sel; |
| 253 | wire b5_0sel; |
| 254 | wire b4_0sel; |
| 255 | wire [4:0] cntl0h; |
| 256 | wire cntl0_selh; |
| 257 | wire cntl0_sell; |
| 258 | wire [6:0] cntl0; |
| 259 | wire b7_nand_74; |
| 260 | wire b7_nand_30; |
| 261 | wire b7_ones; |
| 262 | wire b7_ones_; |
| 263 | wire [1:0] b7_cnt1h; |
| 264 | wire [1:0] b7_cnt1l; |
| 265 | wire [2:0] b7_cnt1; |
| 266 | wire b6_nand_74; |
| 267 | wire b6_nand_30; |
| 268 | wire b6_ones; |
| 269 | wire b6_ones_; |
| 270 | wire [1:0] b6_cnt1h; |
| 271 | wire [1:0] b6_cnt1l; |
| 272 | wire [2:0] b6_cnt1; |
| 273 | wire b5_nand_74; |
| 274 | wire b5_nand_30; |
| 275 | wire b5_ones; |
| 276 | wire b5_ones_; |
| 277 | wire [1:0] b5_cnt1h; |
| 278 | wire [1:0] b5_cnt1l; |
| 279 | wire [2:0] b5_cnt1; |
| 280 | wire b4_nand_74; |
| 281 | wire b4_nand_30; |
| 282 | wire b4_ones; |
| 283 | wire b4_ones_; |
| 284 | wire [1:0] b4_cnt1h; |
| 285 | wire [1:0] b4_cnt1l; |
| 286 | wire [2:0] b4_cnt1; |
| 287 | wire b3_nand_74; |
| 288 | wire b3_nand_30; |
| 289 | wire b3_ones; |
| 290 | wire b3_ones_; |
| 291 | wire [1:0] b3_cnt1h; |
| 292 | wire [1:0] b3_cnt1l; |
| 293 | wire [2:0] b3_cnt1; |
| 294 | wire b2_nand_74; |
| 295 | wire b2_nand_30; |
| 296 | wire b2_ones; |
| 297 | wire b2_ones_; |
| 298 | wire [1:0] b2_cnt1h; |
| 299 | wire [1:0] b2_cnt1l; |
| 300 | wire [2:0] b2_cnt1; |
| 301 | wire b1_nand_74; |
| 302 | wire b1_nand_30; |
| 303 | wire b1_ones; |
| 304 | wire b1_ones_; |
| 305 | wire [1:0] b1_cnt1h; |
| 306 | wire [1:0] b1_cnt1l; |
| 307 | wire [2:0] b1_cnt1; |
| 308 | wire b0_nand_74; |
| 309 | wire [1:0] b0_cnt1h; |
| 310 | wire [1:0] b0_cnt1l; |
| 311 | wire [2:0] b0_cnt1; |
| 312 | wire b3_1sel; |
| 313 | wire b2_1sel; |
| 314 | wire b1_1sel; |
| 315 | wire b0_1sel; |
| 316 | wire [4:0] cntl1l; |
| 317 | wire b7_1sel; |
| 318 | wire b6_1sel; |
| 319 | wire b5_1sel; |
| 320 | wire b4_1sel; |
| 321 | wire [4:0] cntl1h; |
| 322 | wire cntl1_selh; |
| 323 | wire [5:0] cntl1; |
| 324 | wire xsht_amt_sel10; |
| 325 | wire xsht_amt_sel11; |
| 326 | wire xsht_amt_sel20; |
| 327 | wire xsht_amt_sel21; |
| 328 | wire [7:0] xsht_amt_in; |
| 329 | wire [7:0] pe_hamt_lth; |
| 330 | wire [7:0] pe_hamt_in; |
| 331 | wire xsht_lth_scanin; |
| 332 | wire xsht_lth_scanout; |
| 333 | wire hamt_lth_scanin; |
| 334 | wire hamt_lth_scanout; |
| 335 | wire [5:0] xsht_ctl_in; |
| 336 | wire xcntl_lth_scanin; |
| 337 | wire xcntl_lth_scanout; |
| 338 | wire engine_valid_fx1; |
| 339 | wire engine_valid_fx2; |
| 340 | wire queue_valid_lth_fx2; |
| 341 | wire engine_valid_lth_fx2; |
| 342 | wire engine_valid_fx3; |
| 343 | wire queue_valid_lth_fx3; |
| 344 | wire engine_valid_lth_fx3; |
| 345 | wire queue_valid_fx1; |
| 346 | wire queue_valid_fx2; |
| 347 | wire q2e_fx3p; |
| 348 | wire xrnd_vld_lth_scanin; |
| 349 | wire xrnd_vld_lth_scanout; |
| 350 | wire [1:0] eround_mode_in; |
| 351 | wire [1:0] qround_mode_lth; |
| 352 | wire [1:0] eround_mode_lth; |
| 353 | wire e_emin_in; |
| 354 | wire q_emin_lth; |
| 355 | wire [1:0] qround_mode_in; |
| 356 | wire q_emin_in; |
| 357 | wire float_sign_in; |
| 358 | wire float_sign_lth; |
| 359 | wire flt_sqrte_kill_dec; |
| 360 | wire inexact_in; |
| 361 | wire final_sticky; |
| 362 | wire final_guard; |
| 363 | wire xrnd_lth_scanin; |
| 364 | wire xrnd_lth_scanout; |
| 365 | wire sticky_pte1; |
| 366 | wire sticky_pte0; |
| 367 | wire final_lsb; |
| 368 | wire flt_rnd00_en; |
| 369 | wire flt_rnd1x_en; |
| 370 | wire fsqrt_special_in; |
| 371 | wire fsqrt_special_lth; |
| 372 | wire spec_sqrt_lth_scanin; |
| 373 | wire spec_sqrt_lth_scanout; |
| 374 | wire cla_64; |
| 375 | wire cin_in_raw; |
| 376 | wire [3:0] fdq00_sum; |
| 377 | wire [3:0] fdq00_carry; |
| 378 | wire [3:0] pr00; |
| 379 | wire [3:0] pr1p; |
| 380 | wire [2:0] qsel1p; |
| 381 | wire [3:0] fdq10_sum; |
| 382 | wire [3:0] fdq10_carry; |
| 383 | wire [3:0] pr10; |
| 384 | wire [2:0] qsel10; |
| 385 | wire [3:0] pr1n; |
| 386 | wire [2:0] qsel1n; |
| 387 | wire engine_start; |
| 388 | |
| 389 | |
| 390 | // Timing constraints definition : |
| 391 | // For Inputs : Required setup to the end of the cycle |
| 392 | // For Outputs : Actual time the signal leaves block measured from L1CLK rise |
| 393 | // For pin location : I am assuming dataflow direction is vertical |
| 394 | |
| 395 | |
| 396 | // *** globals *** |
| 397 | input l2clk; |
| 398 | input scan_in; |
| 399 | input tcu_pce_ov; // scan signals |
| 400 | input spc_aclk; |
| 401 | input spc_bclk; |
| 402 | input tcu_scan_en; |
| 403 | output scan_out; |
| 404 | |
| 405 | input fac_div_flush_fx3; |
| 406 | input fpe_rs2_fmt_fx1_b0; |
| 407 | input fpf_hi_bof_fx1; |
| 408 | input fpf_lo_bof_fx1; |
| 409 | input fpf_sa_xor_sb_fx1; |
| 410 | |
| 411 | input fac_div_valid_fx1; // div_valid divq_valid | action |
| 412 | input fac_divq_valid_fx1; // --------- ---------- | --------------------------------------- |
| 413 | // 1 0 | start divide from FX1 RS1/RS2/control |
| 414 | // 0 1 | load queue from FX1 RS1/RS2/control |
| 415 | // 1 1 | start divide from queue RS1/RS2/control |
| 416 | |
| 417 | input [4:0] fac_div_control_fx1; // 0in value -var fac_div_control_fx1[3:0] -val 4'b0000 4'b0010 4'b0100 4'b0101 4'b0110 4'b0111 4'b1000 4'b1010 -active (fac_div_valid_fx1 ^ fac_divq_valid_fx1) |
| 418 | // [3:0] : [4] : Thread Group |
| 419 | // 0000 : Float Divide Single |
| 420 | // 0010 : Float Divide Double |
| 421 | // 0100 : Integer Unsigned - 32 bit |
| 422 | // 0101 : Integer Signed - 32 bit |
| 423 | // 0110 : Integer Unsigned - 64 bit |
| 424 | // 0111 : Integer Signed - 64 bit |
| 425 | // 1000 : Float SQRT Single |
| 426 | // 1010 : Float SQRT Double |
| 427 | |
| 428 | input [1:0] fpc_rd_mode_fx3; |
| 429 | input fpc_emin_fx3; |
| 430 | |
| 431 | input div_clken; // div clken |
| 432 | |
| 433 | |
| 434 | // *** locals *** |
| 435 | input [63:0] fdd_pe_clth; |
| 436 | input fdd_cla_zero32_; |
| 437 | input fdd_cla_zero64_; |
| 438 | input [63:9] fdd_result; |
| 439 | |
| 440 | input fdd_fdx_din0; |
| 441 | input fdd_fdx_din1; |
| 442 | input fdd_fdx_cin64; |
| 443 | |
| 444 | input [4:0] fdd_fdq00_10_sum; |
| 445 | input [4:0] fdd_fdq00_10_carry; |
| 446 | input [3:0] fdd_fdq1p_sum; |
| 447 | input [3:0] fdd_fdq1p_carry; |
| 448 | input [3:0] fdd_fdq1n_sum; |
| 449 | input [3:0] fdd_fdq1n_carry; |
| 450 | |
| 451 | |
| 452 | // *** globals *** |
| 453 | output fgu_fdiv_stall; |
| 454 | output [1:0] fgu_idiv_stall; // Stall by Thread Group |
| 455 | output fdc_dec_exp_early; |
| 456 | output fdc_icc_v_early; |
| 457 | output [1:0] fdc_xicc_z_early; |
| 458 | output fdc_finish_int_early; |
| 459 | output fdc_finish_fltd_early; |
| 460 | output fdc_finish_flts_early; |
| 461 | output fdc_flt_inexact; |
| 462 | |
| 463 | |
| 464 | // *** locals *** |
| 465 | output fdc_asign_lth; |
| 466 | output fdc_bsign_lth; |
| 467 | output fdc_bsign_lth_; |
| 468 | output fdc_pe_cycle3; |
| 469 | output fdc_pe_cmux_sel; |
| 470 | output [2:0] fdc_pe_smux_sel; |
| 471 | output [5:0] fdc_pe_xsht_ctl; |
| 472 | output fdc_ie_fsqrt_valid_even; |
| 473 | output fdc_ie_fsqrt_valid_even_; |
| 474 | output fdc_ie_fsqrt_valid_odd; |
| 475 | output fdc_ie_fsqrt_valid_odd_; |
| 476 | output [4:0] fdc_ie_rmux_sel; |
| 477 | output [2:0] fdc_ie_dmux_sel; |
| 478 | output fdc_flt_increment; |
| 479 | output [1:0] fdc_pte_clasel; |
| 480 | output fdc_pte_csa_cin; |
| 481 | output fdc_pte_cycle2; |
| 482 | output fdc_emin_lth; |
| 483 | output [2:0] fdc_pte_qsel; |
| 484 | output fdc_pte_stall_; |
| 485 | |
| 486 | output [1:0] fdc_flt_round; |
| 487 | output [4:0] fdc_idiv_ctl; // 0in bits_on -max 1 -var fdc_idiv_ctl[3:0] |
| 488 | // 3210 [4] = integer |
| 489 | // ---- |
| 490 | // 0001 : 8000 0000 0000 0000 |
| 491 | // 0010 : FFFF FFFF 8000 0000 |
| 492 | // 0100 : 0000 0000 7FFF FFFF |
| 493 | // 1000 : 0000 0000 FFFF FFFF |
| 494 | |
| 495 | output fdc_fdx_cin_in; |
| 496 | output [2:0] fdc_qsel00; |
| 497 | output [2:0] fdc_qsel1; |
| 498 | |
| 499 | output [1:0] fdc_q_in; |
| 500 | output [1:0] fdc_qm1_in; |
| 501 | |
| 502 | // scan renames |
| 503 | assign pce_ov = tcu_pce_ov; |
| 504 | assign stop = 1'b0; |
| 505 | assign siclk = spc_aclk; |
| 506 | assign soclk = spc_bclk; |
| 507 | assign se = tcu_scan_en; |
| 508 | // end scan |
| 509 | |
| 510 | |
| 511 | fgu_fdc_ctl_l1clkhdr_ctl_macro clkgen_pm1 ( |
| 512 | .l2clk(l2clk), |
| 513 | .l1en (div_clken), |
| 514 | .l1clk(l1clk_pm1), |
| 515 | .pce_ov(pce_ov), |
| 516 | .stop(stop), |
| 517 | .se(se) |
| 518 | ); |
| 519 | |
| 520 | fgu_fdc_ctl_spare_ctl_macro__num_3 spares ( // spares: 13 gates + 1 flop for each "num" |
| 521 | .scan_in(spares_scanin), |
| 522 | .scan_out(spares_scanout), |
| 523 | .l1clk(l1clk_pm1), |
| 524 | .siclk(siclk), |
| 525 | .soclk(soclk) |
| 526 | ); |
| 527 | |
| 528 | |
| 529 | assign incoming_sign_fx1= fpf_sa_xor_sb_fx1 & ~fac_div_control_fx1[3]; // Turn off for Square Root |
| 530 | |
| 531 | assign qcontrol_in[7:0] = ({8{ fac_divq_valid_fx1}} & {fsqrt_fract_all_ones,incoming_sign_fx1,fpe_rs2_fmt_fx1_b0,fac_div_control_fx1[4:0]}) | |
| 532 | ({8{~fac_divq_valid_fx1}} & qcontrol_fx1[7:0] ); |
| 533 | |
| 534 | fgu_fdc_ctl_msff_ctl_macro__width_8 qdata_lth ( |
| 535 | .scan_in(qdata_lth_scanin), |
| 536 | .scan_out(qdata_lth_scanout), |
| 537 | .l1clk( l1clk_pm1 ), |
| 538 | .din ({qcontrol_in[7:0] }), |
| 539 | .dout ({qcontrol_fx1[7:0]}), |
| 540 | .siclk(siclk), |
| 541 | .soclk(soclk)); |
| 542 | |
| 543 | |
| 544 | |
| 545 | // * * * * * * * * * * * * Main Controller * * * * * * * * * * * * |
| 546 | |
| 547 | |
| 548 | // *** State control *** |
| 549 | |
| 550 | //* * * * * * * * * * * * "pre-engine" (integer only)* * * * * |
| 551 | // |
| 552 | // cycle 0 : fac_div_valid_fx1 A&B are transmitted to divide hardware |
| 553 | // A loaded into Slth |
| 554 | // B loaded into Clth; |
| 555 | // |
| 556 | // cycle 1 : pe_cycle[1] B into CNTL0 and CNTL1 -> compute "lsb"; |
| 557 | // A loaded into Clth; |
| 558 | // B loaded into Slth; |
| 559 | // |
| 560 | // cycle 2 : pe_cycle[2] A into CNTL0 and CNTL1 -> compute "lsa"; |
| 561 | // B shifts by "lsb" amount |
| 562 | // A loaded into Slth; |
| 563 | // Xsht loaded into Clth; (this is Bsh) |
| 564 | // |
| 565 | // cycle 3 : pe_cycle[3] A shifts by "lsa" amount; |
| 566 | // engine_start Bsh is XORed to produce positive divisor |
| 567 | // compute ndq = lsb - lsa + 1; |
| 568 | // finished if ndq <= 0; (ie B > A) |
| 569 | // |
| 570 | //* * * * * * * * * * * * * "engine" * * * * * * * * * * * * * |
| 571 | // |
| 572 | // See Integer "engine" run-time below for how ndq is computed. |
| 573 | // |
| 574 | // if (even ndq) |
| 575 | // then X = ndq / 2 |
| 576 | // else X = (ndq - 1) / 2 |
| 577 | // |
| 578 | // for X cycles |
| 579 | // perform loop |
| 580 | // |
| 581 | // cycle X+3 : engine_stop last loop |
| 582 | // |
| 583 | //* * * * * * * * * * * * "post-engine" * * * * * * * * * * * * |
| 584 | // |
| 585 | // cycle X+4 : pte_cycle[3] load "S0" and "C0" latches into adder latches |
| 586 | // For an odd ndq, we actually compute the last Q and Qm1 |
| 587 | // and then load "C1" and "S1" into the adder latches. |
| 588 | // |
| 589 | // cycle X+5 : pte_cycle[2] compute Sign of Remainder |
| 590 | // compute zero remainder (used as Sticky and in correction) |
| 591 | // load Q and Qm1 into adder latches |
| 592 | // make correction if necessary |
| 593 | // turn off valid_lth (new divide will NOT affect result) |
| 594 | // |
| 595 | // cycle X+6 : pte_cycle[1] compute Qf = Q - Qm1 + correction; |
| 596 | // 64-bit Integer - load into Result latch |
| 597 | // |
| 598 | // cycle X+7 pte_cycle[0] 32-bit Integer - Overflow detection and correction |
| 599 | // Floating Point - Round |
| 600 | // |
| 601 | // cycle X+7/8 fdc_finish transmit Result |
| 602 | // |
| 603 | // |
| 604 | //* * * * * * * * * * * * Integer "engine" run-time * * * * * * * * * * |
| 605 | // |
| 606 | // |
| 607 | // Define : lsa : number of Leading Sign bits in A (n-1 for negative) |
| 608 | // lsb : number of Leading Sign bits in B (n for negative) |
| 609 | // nda : number of digits in A (nda=64-lsa) |
| 610 | // ndb : number of digits in B (ndb=64-lsb) |
| 611 | // ndq : number of digits in the Quotient Q (MAX) |
| 612 | // |
| 613 | // Then ndq = nda - (ndb - 1); |
| 614 | // |
| 615 | // The minus one comes from the fact that dividing by '1' does not reduce |
| 616 | // the number of significant bits in the dividend (A operand). |
| 617 | // |
| 618 | // By substitution : |
| 619 | // |
| 620 | // ndq = [64 - lsa] - ([64 - lsb] - 1); |
| 621 | // = lsb - lsa + 1; |
| 622 | // |
| 623 | // |
| 624 | // Example : A = 0000 1111 (+15) lsa = 4 |
| 625 | // (8-bit) B = 0000 0010 (+2) lsb = 6 |
| 626 | // ------------------ |
| 627 | // R = 0000 0111 (+7) notice ndq=3 |
| 628 | // |
| 629 | // compute ndq = lsb - lsa + 1 |
| 630 | // = 6 - 4 + 1 |
| 631 | // = 3 (this is a MAX ndq computation) |
| 632 | // |
| 633 | // |
| 634 | // Example : A = 0000 1000 (+8) lsa = 4 |
| 635 | // (8-bit) B = 0000 0011 (+3) lsb = 6 |
| 636 | // ------------------ |
| 637 | // R = 0000 0010 (+2) notice ndq=2 |
| 638 | // |
| 639 | // compute ndq = lsb - lsa + 1 |
| 640 | // = 6 - 4 + 1 |
| 641 | // = 3 (this is a MAX ndq computation) |
| 642 | // |
| 643 | // |
| 644 | // Example : A = 1111 0000 (-16) lsa = 3 (n-1 for negative) |
| 645 | // (8-bit) B = 0000 0010 (+2) lsb = 6 |
| 646 | // ------------------ |
| 647 | // R = 1111 1000 (-8) notice ndq=4 |
| 648 | // |
| 649 | // compute ndq = lsb - lsa + 1 |
| 650 | // = 6 - 3 + 1 |
| 651 | // = 4 (this is a MAX ndq computation) |
| 652 | // |
| 653 | // |
| 654 | // |
| 655 | // |
| 656 | // |
| 657 | //* * * * * * * * * * * * * Total cycle count * * * * * * * * * * * * |
| 658 | // |
| 659 | // *** 32-bit Integer Division*** |
| 660 | // |
| 661 | // FX1 transmit of RS1 and RS2 |
| 662 | // 3 "pre-engine" |
| 663 | // X "engine" where X = (lsb-lsa)// 2; {0 to 32 cycles} |
| 664 | // 4 "post-engine" where 4th cycle is Overflow detection and correction |
| 665 | // S "engine-stall" where S = 4 - X; {0 to 4 cycles} (needed to sync up with bubble) |
| 666 | // FX5 transmit to EXU |
| 667 | // W |
| 668 | // --- |
| 669 | // 10+X+S {14 to 42 cycles} |
| 670 | // |
| 671 | // |
| 672 | // *** 64-bit Integer Division*** |
| 673 | // |
| 674 | // FX1 transmit of RS1 and RS2 |
| 675 | // 3 "pre-engine" |
| 676 | // X "engine" where X = (lsb-lsa)// 2; {0 to 32 cycles} |
| 677 | // 3 "post-engine" |
| 678 | // S "engine-stall" where S = 4 - X; {0 to 4 cycles} (needed to sync up with bubble) |
| 679 | // FX5 transmit to EXU |
| 680 | // W |
| 681 | // --- |
| 682 | // 9+X+S {13 to 41 cycles} |
| 683 | // |
| 684 | // |
| 685 | // *** Float Double Precision divide and square root*** |
| 686 | // |
| 687 | // FX1 transmit of RS1 and RS2 |
| 688 | // 27 "engine" need 53 mantissa + 1 guard + 1 for 0.1 = 55 |
| 689 | // 27 cycles compute 54 quotient digits. The last bit is computed during pte_cycle[3]. |
| 690 | // 4 "post-engine" |
| 691 | // FB |
| 692 | // FW |
| 693 | // FW1 |
| 694 | // --- |
| 695 | // 35 cycles |
| 696 | // |
| 697 | // |
| 698 | // *** Float Single Precision divide and square root *** |
| 699 | // |
| 700 | // FX1 transmit of RS1 and RS2 |
| 701 | // 13 "engine" need 24 mantissa + 1 guard + 1 for 0.1 = 26 |
| 702 | // 4 "post-engine" |
| 703 | // FB |
| 704 | // FW |
| 705 | // FW1 |
| 706 | // --- |
| 707 | // 21 cycles |
| 708 | |
| 709 | |
| 710 | assign valid_in = (fac_div_valid_fx1 ) | |
| 711 | (valid_lth & ~fdc_pte_cycle[2] & ~div_flush_lth); |
| 712 | |
| 713 | assign pe_cycle_in[1] = (fac_div_valid_fx1 & fac_div_control_fx1[2] & ~fac_divq_valid_fx1) | |
| 714 | (fac_div_valid_fx1 & qcontrol_fx1[2] & fac_divq_valid_fx1); |
| 715 | |
| 716 | assign pe_cycle_in[3:2] = fdc_pe_cycle[2:1] & {2{~div_flush_lth}}; |
| 717 | |
| 718 | assign engine_running_in = (fac_div_valid_fx1 & ~fac_div_control_fx1[2] & ~fac_divq_valid_fx1) | // start FLT |
| 719 | (fac_div_valid_fx1 & ~qcontrol_fx1[2] & fac_divq_valid_fx1) | // start FLT |
| 720 | (fdc_pe_cycle[3] & ~engine_stop & ~div_flush_lth ) | // start INT |
| 721 | (engine_running_lth & ~engine_stop & ~div_flush_lth ); |
| 722 | |
| 723 | assign engine_on = fdc_pe_cycle[3] | engine_running_lth; |
| 724 | |
| 725 | // 0in assert_timer -var (engine_running_lth & (control_lth[2:0] == 3'b000)) -max 13 -message "FDIV/FSQRT engine running > 13 cycles for SP" |
| 726 | // 0in assert_timer -var (engine_running_lth & (control_lth[2:0] == 3'b010)) -max 27 -message "FDIV/FSQRT engine running > 27 cycles for DP" |
| 727 | // 0in assert_timer -var (engine_running_lth & (control_lth[3:2] == 2'b01 )) -max 32 -message "IDIV engine running > 32 cycles" |
| 728 | |
| 729 | assign engine_stop = ((pe_ndq[6:1] == 6'b000000) & engine_on) | |
| 730 | ( pe_ndq[7] & engine_on); |
| 731 | |
| 732 | assign pte_cycle_in[3:1] = {engine_stop,fdc_pte_cycle[3:2]} & {3{~div_flush_lth}}; |
| 733 | assign pte_cycle_in[0] = fdc_pte_cycle[1] & ~(control_lth[2] & control_lth[1]) & ~div_flush_lth; |
| 734 | |
| 735 | fgu_fdc_ctl_msff_ctl_macro__width_10 cntl_lth ( |
| 736 | .scan_in(cntl_lth_scanin), |
| 737 | .scan_out(cntl_lth_scanout), |
| 738 | .l1clk( l1clk_pm1 ), |
| 739 | .din ({valid_in , pe_cycle_in[3:1] , engine_running_in , pte_cycle_in[3:0] , fac_div_flush_fx3}), |
| 740 | .dout ({valid_lth , fdc_pe_cycle[3:1] , engine_running_lth , fdc_pte_cycle[3:0] , div_flush_lth }), |
| 741 | .siclk(siclk), |
| 742 | .soclk(soclk)); |
| 743 | |
| 744 | // 0in bits_on -max 1 -var {fdc_pe_cycle[3:1], engine_running_lth, fdc_pte_cycle[3:0], finish_lth} |
| 745 | |
| 746 | // 0in state_transition -var {fac_div_valid_fx1, pe_cycle_in[3:1], engine_running_in} -val {1'b1, 3'b000, 1'b0} -next {1'b0, 3'b001, 1'b0} {1'b0, 3'b000, 1'b1} {1'b0, 3'b000, 1'b0} -match_by_cycle |
| 747 | // 0in state_transition -var pe_cycle_in[3:1] -val 3'b000 -next 3'b001 3'b000 |
| 748 | // 0in state_transition -var pe_cycle_in[3:1] -val 3'b001 -next 3'b010 3'b000 -match_by_cycle |
| 749 | // 0in state_transition -var pe_cycle_in[3:1] -val 3'b010 -next 3'b100 3'b000 -match_by_cycle |
| 750 | // 0in state_transition -var {engine_running_in, pe_cycle_in[3:1]} -val {1'b0, 3'b100} -next {1'b1, 3'b000} {1'b0, 3'b000} -match_by_cycle |
| 751 | // 0in state_transition -var {pte_cycle_in[3:0], engine_running_in} -val {4'b0000, 1'b1} -next {4'b1000, 1'b0} {4'b0000, 1'b0} |
| 752 | // 0in state_transition -var pte_cycle_in[3:0] -val 4'b0000 -next 4'b1000 |
| 753 | // 0in state_transition -var pte_cycle_in[3:0] -val 4'b1000 -next 4'b0100 -match_by_cycle |
| 754 | // 0in state_transition -var pte_cycle_in[3:0] -val 4'b0100 -next 4'b0010 -match_by_cycle |
| 755 | // 0in state_transition -var {pte_cycle_in[3:0], finish_lth_in} -val {4'b0010, 1'b0} -next {4'b0001, 1'b0} {4'b0000, 1'b1} |
| 756 | // 0in state_transition -var {pte_cycle_in[3:0], finish_lth_in} -val {4'b0001, 1'b0} -next {4'b0000, 1'b1} |
| 757 | |
| 758 | assign fdc_pe_cycle3 = fdc_pe_cycle[3]; // Tools issues with single bit buses downstream |
| 759 | assign fdc_pte_cycle2 = fdc_pte_cycle[2]; // Tools issues with single bit buses downstream |
| 760 | |
| 761 | assign fdc_pe_cmux_sel = fdc_pe_cycle[1] | fdc_pe_cycle[2]; |
| 762 | |
| 763 | // For neg B, left shift by 1 to compensate for 'n-1' shift amount |
| 764 | assign fdc_pe_smux_sel[0] = fdc_pe_cycle[1] & fdd_pe_clth[63] & control_lth[0]; |
| 765 | assign fdc_pe_smux_sel[1] = fdc_pe_cycle[1] | fdc_pe_cycle[2]; |
| 766 | assign fdc_pe_smux_sel[2] = fac_div_valid_fx1 & ~fac_divq_valid_fx1; |
| 767 | |
| 768 | assign pe_hmux_sel[0] = ( fac_div_valid_fx1 & ~fac_div_control_fx1[2] & fac_div_control_fx1[1] & ~fac_divq_valid_fx1) | |
| 769 | ( fac_div_valid_fx1 & ~qcontrol_fx1[2] & qcontrol_fx1[1] & fac_divq_valid_fx1); |
| 770 | assign pe_hmux_sel[1] = ( fac_div_valid_fx1 & ~fac_div_control_fx1[2] & ~fac_div_control_fx1[1] & ~fac_divq_valid_fx1) | |
| 771 | ( fac_div_valid_fx1 & ~qcontrol_fx1[2] & ~qcontrol_fx1[1] & fac_divq_valid_fx1); |
| 772 | assign pe_hmux_sel[2] = ~fdc_pe_cycle[1] & valid_lth; |
| 773 | |
| 774 | |
| 775 | // *** Integer Overflow Detection *** |
| 776 | |
| 777 | // fdc_idiv_ctl |
| 778 | // 3210 |
| 779 | // ---- |
| 780 | // 0001 : 8000 0000 0000 0000 ovfl_64x |
| 781 | // 0010 : FFFF FFFF 8000 0000 ovfl_32n |
| 782 | // 0100 : 0000 0000 7FFF FFFF ovfl_32p |
| 783 | // 1000 : 0000 0000 FFFF FFFF ovfl_32u |
| 784 | |
| 785 | |
| 786 | // For 64-bit divide, the only OVFL condition exits is : neg max / -1 |
| 787 | // This results in a constant of "8000 0000 0000 0000" defined on pg 196. |
| 788 | |
| 789 | assign b_neg_one = fdc_pe_cycle[2] & fdc_bsign_lth & |
| 790 | (pe_xsht_amt[6:0] == 7'b0111111); |
| 791 | |
| 792 | assign a_neg_max = fdc_pe_cycle[3] & fdc_asign_lth & |
| 793 | (pe_xsht_amt[6:0] == 7'b1111111); // xsht_amt is inverted by cycle[3] |
| 794 | |
| 795 | assign ovfl_64_in = ( a_neg_max & b_neg_one_lth & ~div_flush_lth) | // 64-bit divide |
| 796 | (~finish_raw & ovfl_64_lth & ~div_flush_lth); |
| 797 | |
| 798 | assign fdc_idiv_ctl[0] = fdc_pte_cycle[0] & ovfl_64_lth & control_lth[1]; |
| 799 | |
| 800 | // For 64-bit/32-bit, three OVFL constants are possible. (see pages 152-154) |
| 801 | // For - signed : if quotient <= (-2^31 - 1) then result = FFFF FFFF 8000 0000 (-2^31 ) |
| 802 | // For + signed : if quotient >= ( 2^31 ) then result = 0000 0000 7FFF FFFF ( 2^31 - 1) |
| 803 | // For unsigned : if quotient >= ( 2^32 ) then result = 0000 0000 FFFF FFFF ( 2^32 - 1) |
| 804 | |
| 805 | assign fdc_idiv_ctl[1] = fdc_pte_cycle[0] & (control_lth[2:0] == 3'b101) & |
| 806 | fdd_result[63] & (fdd_result[62:31] != 32'hFFFFFFFF) & ~ovfl_64_lth; |
| 807 | |
| 808 | assign fdc_idiv_ctl[2] = fdc_pte_cycle[0] & (control_lth[2:0] == 3'b101) & |
| 809 | ((~fdd_result[63] & (fdd_result[62:31] != 32'h00000000)) | ovfl_64_lth); |
| 810 | |
| 811 | assign fdc_idiv_ctl[3] = fdc_pte_cycle[0] & (control_lth[2:0] == 3'b100) & |
| 812 | (fdd_result[63:32] != 32'h00000000); |
| 813 | |
| 814 | assign fdc_idiv_ctl[4] = fdc_pte_cycle[0] & ~control_lth[2] & ~flt_shift_sel_ & ~fdc_flt_increment; |
| 815 | |
| 816 | assign fdc_icc_v_early = | fdc_idiv_ctl[3:0]; |
| 817 | |
| 818 | |
| 819 | fgu_fdc_ctl_msff_ctl_macro__width_4 ovlf_lth ( |
| 820 | .scan_in(ovlf_lth_scanin), |
| 821 | .scan_out(ovlf_lth_scanout), |
| 822 | .l1clk( l1clk_pm1 ), |
| 823 | .din ({ovfl_64_in , b_neg_one , fdd_cla_zero64_ , fdd_cla_zero32_}), |
| 824 | .dout ({ovfl_64_lth , b_neg_one_lth , cla_zero64_lth_ , cla_zero32_lth_}), |
| 825 | .siclk(siclk), |
| 826 | .soclk(soclk)); |
| 827 | |
| 828 | |
| 829 | assign fdc_xicc_z_early[1] = ~cla_zero64_lth_; |
| 830 | assign fdc_xicc_z_early[0] = ~cla_zero32_lth_ & ~fdc_icc_v_early; |
| 831 | |
| 832 | |
| 833 | // *** Engine stall *** |
| 834 | |
| 835 | // The INTEGER divide has a variable timing dependent on the operand data. |
| 836 | // The divide must provide a STALL signal to the issue logic to ensure no |
| 837 | // collision on the shared FGU to EXU bus. The timing of the IDIV_STALL |
| 838 | // is given below. |
| 839 | // |
| 840 | // t-1 t t+1 t+2 t+3 t+4 t+5 t+6 t+7 |
| 841 | // -----|------|------|------|------|------|------|------|------| |
| 842 | // idiv | idiv | D | E | fx1 | fx2 | fx3 | fx4 | fx5 | |
| 843 | // stall | stall| | | | | | | | |
| 844 | // in | | | |engine|pte[3]|pte[2]|pte[1]|finish| |
| 845 | // | | | | stop | | | | | |
| 846 | // | | | | | | | | | |
| 847 | // 8/9 | 6/7 | 4/5 | 2/3 | 0/1 | | | | | |
| 848 | // | | | | | | | | | |
| 849 | // +0 | +1 | +2 | +3 | +4 | | | | | |
| 850 | // |
| 851 | // |
| 852 | // The Floating Point Divide and Square Root has a fixed latency. |
| 853 | // The divide must provide a STALL signal to the issue logic to ensure no |
| 854 | // collision at the W2 port to the FRF. |
| 855 | // |
| 856 | // t-1 t t+1 t+2 t+3 t+4 |
| 857 | // -----|------|------|------|------|------| |
| 858 | // fdiv | fdiv | D | E | M | fb/B | |
| 859 | // stall | stall| | | | | |
| 860 | // in | | | | | | |
| 861 | // | | | | | | |
| 862 | // |pte[3]|pte[2]|pte[1]|pte[0]|finish| |
| 863 | // | | | | | | |
| 864 | // | | | | | | |
| 865 | // 8/9 | 6/7 | | | | | |
| 866 | // | | | | | | |
| 867 | // +0 | +1 | | | | | |
| 868 | // |
| 869 | // |
| 870 | // at engine_start : |
| 871 | // stall_cnt |
| 872 | // 3 2 1 0 |
| 873 | // ------- |
| 874 | // ndq = neg -> 1 1 1 1 |
| 875 | // ndq = 0/1 -> 1 1 1 1 [6:1] = 000 000 |
| 876 | // ndq = 2/3 -> 0 1 1 1 = 000 001 |
| 877 | // ndq = 4/5 -> 0 0 1 1 = 000 010 |
| 878 | // ndq = 6/7 -> 0 0 0 1 = 000 011 |
| 879 | // ndq >=8/9 -> 0 0 0 0 = 000 100 idiv_stall_in |
| 880 | |
| 881 | |
| 882 | assign fdiv_stall_in = ((pe_ndq[6:1] == 6'b000000) & engine_on & ~control_lth[2] & ~stall_hold); |
| 883 | |
| 884 | assign idiv_stall_in = ((pe_ndq[6:1] == 6'b000100) & engine_on & control_lth[2] & control_lth[1] & ~stall_hold & ~div_flush_lth) | |
| 885 | ((pe_ndq[6:3] == 4'b0000 ) & engine_on & control_lth[2] & ~stall_hold & ~div_flush_lth) | |
| 886 | ( pe_ndq[7] & engine_on & control_lth[2] & ~stall_hold & ~div_flush_lth); |
| 887 | |
| 888 | |
| 889 | assign stall_hold_in = (fdiv_stall_in & ~div_flush_lth ) | |
| 890 | (idiv_stall_in & ~div_flush_lth ) | |
| 891 | (stall_hold & ~div_flush_lth & ~finish_raw); |
| 892 | |
| 893 | |
| 894 | assign stall_cnt_raw[3] = (pe_ndq[6:1] == 6'b000000) | |
| 895 | (pe_ndq[7] ); |
| 896 | |
| 897 | assign stall_cnt_raw[2] = (pe_ndq[6:2] == 5'b00000 ) | |
| 898 | (pe_ndq[7] ); |
| 899 | |
| 900 | assign stall_cnt_raw[1] = (pe_ndq[6:1] == 6'b000010) | |
| 901 | (pe_ndq[6:2] == 5'b00000 ) | |
| 902 | (pe_ndq[7] ); |
| 903 | |
| 904 | assign stall_cnt_raw[0] = (pe_ndq[6:3] == 4'b0000 ) | |
| 905 | (pe_ndq[7] ); |
| 906 | |
| 907 | assign stall_cnt_in[3:0] = ({4{ fdc_pe_cycle[3] & control_lth[1] & ~div_flush_lth}} & stall_cnt_raw[3:0] ) | // INT64 engine_start |
| 908 | ({4{ fdc_pe_cycle[3] & ~control_lth[1] & ~div_flush_lth}} & {1'b0,stall_cnt_raw[3:1]}) | // INT32 engine_start |
| 909 | ({4{~fdc_pe_cycle[3] & ~finish_lth & ~div_flush_lth}} & stall_cnt[3:0] ) | |
| 910 | ({4{ finish_lth & ~div_flush_lth}} & {1'b0,stall_cnt[3:1] }); |
| 911 | |
| 912 | fgu_fdc_ctl_msff_ctl_macro__width_8 stall_lth ( |
| 913 | .scan_in(stall_lth_scanin), |
| 914 | .scan_out(stall_lth_scanout), |
| 915 | .l1clk( l1clk_pm1 ), |
| 916 | .din ({finish_lth_in , fdiv_stall_in , idiv_stall_in , stall_hold_in , stall_cnt_in[3:0]}), |
| 917 | .dout ({finish_lth , fgu_fdiv_stall , idiv_stall_lth , stall_hold , stall_cnt[3:0] }), |
| 918 | .siclk(siclk), |
| 919 | .soclk(soclk)); |
| 920 | |
| 921 | |
| 922 | assign fgu_idiv_stall[1] = control_lth[4] & idiv_stall_lth; // Threads 4-7 |
| 923 | assign fgu_idiv_stall[0] = ~control_lth[4] & idiv_stall_lth; // Threads 0-3 |
| 924 | |
| 925 | |
| 926 | assign finish_lth_in = (fdc_pte_cycle[0] & ~div_flush_lth) | |
| 927 | (fdc_pte_cycle[1] & control_lth[2] & control_lth[1] & ~div_flush_lth) | |
| 928 | (finish_lth & stall_cnt[0] & ~div_flush_lth); |
| 929 | |
| 930 | |
| 931 | assign finish_raw = finish_lth & ~stall_cnt[0]; |
| 932 | |
| 933 | assign fdc_finish_int_early = (fdc_pte_cycle[0] & ~stall_cnt[0] & control_lth[2] ) | |
| 934 | (fdc_pte_cycle[1] & ~stall_cnt[0] & control_lth[2] & control_lth[1]) | |
| 935 | (finish_lth & stall_cnt[0] & ~stall_cnt[1] & control_lth[2] ); |
| 936 | |
| 937 | assign fdc_finish_fltd_early = fdc_pte_cycle[0] & ~control_lth[2] & control_lth[1]; |
| 938 | assign fdc_finish_flts_early = fdc_pte_cycle[0] & ~control_lth[2] & ~control_lth[1]; |
| 939 | |
| 940 | |
| 941 | |
| 942 | assign fdc_pte_stall_ = fdc_pte_cycle[1] | |
| 943 | fdc_idiv_ctl[0] | fdc_idiv_ctl[1] | fdc_idiv_ctl[2] | fdc_idiv_ctl[3] | |
| 944 | (fdc_pte_cycle[0] & ~flt_shift_sel_ & ~control_lth[2]) | |
| 945 | (fdc_pte_cycle[0] & fdc_flt_increment ); |
| 946 | |
| 947 | |
| 948 | |
| 949 | // *** State data *** |
| 950 | |
| 951 | assign control_in[4:0] = ({5{ fac_div_valid_fx1 & ~fac_divq_valid_fx1}} & fac_div_control_fx1[4:0]) | |
| 952 | ({5{ fac_div_valid_fx1 & fac_divq_valid_fx1}} & qcontrol_fx1[4:0]) | |
| 953 | ({5{~fac_div_valid_fx1 }} & control_lth[4:0]); |
| 954 | |
| 955 | assign asign_in = ( fdc_pe_cycle[2] & fdd_pe_clth[63] & control_lth[0] ) | |
| 956 | (~fdc_pe_cycle[2] & fdc_asign_lth & ~fac_div_valid_fx1); |
| 957 | |
| 958 | assign bsign_in = ( fdc_pe_cycle[1] & fdd_pe_clth[63] & control_lth[0] ) | |
| 959 | (~fdc_pe_cycle[1] & fdc_bsign_lth & ~fac_div_valid_fx1); |
| 960 | |
| 961 | assign ndq_odd_in = ~pe_ndq[7] & pe_ndq[0]; |
| 962 | |
| 963 | fgu_fdc_ctl_msff_ctl_macro__width_9 data_lth ( |
| 964 | .scan_in(data_lth_scanin), |
| 965 | .scan_out(data_lth_scanout), |
| 966 | .l1clk( l1clk_pm1 ), |
| 967 | .din ({control_in[4:0] ,asign_in ,bsign_in ,ndq_odd_in ,ndq_odd_lth }), |
| 968 | .dout ({control_lth[4:0],fdc_asign_lth,fdc_bsign_lth,ndq_odd_lth,ndq_odd_2lth }), |
| 969 | .siclk(siclk), |
| 970 | .soclk(soclk)); |
| 971 | |
| 972 | assign fdc_pte_clasel[0] = fdc_pte_cycle[3] & ~ndq_odd_lth; |
| 973 | assign fdc_pte_clasel[1] = fdc_pte_cycle[3] & ndq_odd_lth; |
| 974 | |
| 975 | assign fdc_pte_qsel[0] = control_lth[2] & ~ndq_odd_2lth; // INT even |
| 976 | assign fdc_pte_qsel[1] = control_lth[2] & ndq_odd_2lth; // INT odd |
| 977 | assign fdc_pte_qsel[2] = ~control_lth[2] & control_lth[1]; // FLT DP |
| 978 | |
| 979 | |
| 980 | assign fdc_bsign_lth_ = ~fdc_bsign_lth; |
| 981 | assign fdc_pte_csa_cin = fdc_asign_lth ^ fdc_bsign_lth; |
| 982 | |
| 983 | |
| 984 | |
| 985 | // * * * * * * * * * * * Interface to engine * * * * * * * * * * * |
| 986 | |
| 987 | // integer select by "fdc_pe_cycle[3]" |
| 988 | |
| 989 | // fac_div_control_fx1[3:0] == |
| 990 | // [3:0] : |
| 991 | // 0000 : Float Divide Single |
| 992 | // 0010 : Float Divide Double |
| 993 | // 0100 : Integer Unsigned - 32 bit |
| 994 | // 0101 : Integer Signed - 32 bit |
| 995 | // 0110 : Integer Unsigned - 64 bit |
| 996 | // 0111 : Integer Signed - 64 bit |
| 997 | // 1000 : Float SQRT Single |
| 998 | // 1010 : Float SQRT Double |
| 999 | |
| 1000 | |
| 1001 | assign fdc_ie_rmux_sel[0] = ~fac_div_valid_fx1; // integer |
| 1002 | assign fdc_ie_rmux_sel[1] = fac_div_valid_fx1 & fac_div_control_fx1[3] & ~fac_divq_valid_fx1; // float sqrt |
| 1003 | assign fdc_ie_rmux_sel[2] = fac_div_valid_fx1 & ~fac_div_control_fx1[3] & ~fac_divq_valid_fx1; // float div |
| 1004 | assign fdc_ie_rmux_sel[3] = fac_div_valid_fx1 & qcontrol_fx1[3] & fac_divq_valid_fx1; // float sqrt |
| 1005 | assign fdc_ie_rmux_sel[4] = fac_div_valid_fx1 & ~qcontrol_fx1[3] & fac_divq_valid_fx1; // float div |
| 1006 | |
| 1007 | assign fdc_ie_dmux_sel[0] = ~fac_div_valid_fx1; // integer |
| 1008 | assign fdc_ie_dmux_sel[1] = fac_div_valid_fx1 & ~fac_div_control_fx1[3] & ~fac_divq_valid_fx1; // float div |
| 1009 | assign fdc_ie_dmux_sel[2] = fac_div_valid_fx1 & ~qcontrol_fx1[3] & fac_divq_valid_fx1; // float div |
| 1010 | |
| 1011 | |
| 1012 | // must be qualified w/ valid so INT is not corrupted by garbage on bus during pe_cycle[3] |
| 1013 | assign fdc_ie_fsqrt_valid_even = (fac_div_valid_fx1 & fac_div_control_fx1[3] & fpe_rs2_fmt_fx1_b0 & ~fac_divq_valid_fx1) | |
| 1014 | (fac_div_valid_fx1 & qcontrol_fx1[3] & qcontrol_fx1[5] & fac_divq_valid_fx1); |
| 1015 | |
| 1016 | assign fdc_ie_fsqrt_valid_odd = (fac_div_valid_fx1 & fac_div_control_fx1[3] & ~fpe_rs2_fmt_fx1_b0 & ~fac_divq_valid_fx1) | |
| 1017 | (fac_div_valid_fx1 & qcontrol_fx1[3] & ~qcontrol_fx1[5] & fac_divq_valid_fx1); |
| 1018 | |
| 1019 | assign fdc_ie_fsqrt_valid_even_ = ~fdc_ie_fsqrt_valid_even; |
| 1020 | assign fdc_ie_fsqrt_valid_odd_ = ~fdc_ie_fsqrt_valid_odd; |
| 1021 | |
| 1022 | |
| 1023 | // * * * * * * * * * * * * start : Integer CNTL0 * * * * * * * * * * * * * |
| 1024 | |
| 1025 | //reg [6:0] cntl0; |
| 1026 | // |
| 1027 | //always @ (fdd_pe_clth[63:0]) |
| 1028 | // |
| 1029 | // begin |
| 1030 | // |
| 1031 | // casex (fdd_pe_clth[63:0]) |
| 1032 | // 64'b1???????????????????????????????????????????????????????????????: cntl0[6:0] = 7'b0000000; |
| 1033 | // 64'b01??????????????????????????????????????????????????????????????: cntl0[6:0] = 7'b0000001; |
| 1034 | // 64'b001?????????????????????????????????????????????????????????????: cntl0[6:0] = 7'b0000010; |
| 1035 | // 64'b0001????????????????????????????????????????????????????????????: cntl0[6:0] = 7'b0000011; |
| 1036 | // 64'b00001???????????????????????????????????????????????????????????: cntl0[6:0] = 7'b0000100; |
| 1037 | // 64'b000001??????????????????????????????????????????????????????????: cntl0[6:0] = 7'b0000101; |
| 1038 | // 64'b0000001?????????????????????????????????????????????????????????: cntl0[6:0] = 7'b0000110; |
| 1039 | // 64'b00000001????????????????????????????????????????????????????????: cntl0[6:0] = 7'b0000111; |
| 1040 | // |
| 1041 | // 64'b000000001???????????????????????????????????????????????????????: cntl0[6:0] = 7'b0001000; |
| 1042 | // 64'b0000000001??????????????????????????????????????????????????????: cntl0[6:0] = 7'b0001001; |
| 1043 | // 64'b00000000001?????????????????????????????????????????????????????: cntl0[6:0] = 7'b0001010; |
| 1044 | // 64'b000000000001????????????????????????????????????????????????????: cntl0[6:0] = 7'b0001011; |
| 1045 | // 64'b0000000000001???????????????????????????????????????????????????: cntl0[6:0] = 7'b0001100; |
| 1046 | // 64'b00000000000001??????????????????????????????????????????????????: cntl0[6:0] = 7'b0001101; |
| 1047 | // 64'b000000000000001?????????????????????????????????????????????????: cntl0[6:0] = 7'b0001110; |
| 1048 | // 64'b0000000000000001????????????????????????????????????????????????: cntl0[6:0] = 7'b0001111; |
| 1049 | // |
| 1050 | // 64'b00000000000000001???????????????????????????????????????????????: cntl0[6:0] = 7'b0010000; |
| 1051 | // 64'b000000000000000001??????????????????????????????????????????????: cntl0[6:0] = 7'b0010001; |
| 1052 | // 64'b0000000000000000001?????????????????????????????????????????????: cntl0[6:0] = 7'b0010010; |
| 1053 | // 64'b00000000000000000001????????????????????????????????????????????: cntl0[6:0] = 7'b0010011; |
| 1054 | // 64'b000000000000000000001???????????????????????????????????????????: cntl0[6:0] = 7'b0010100; |
| 1055 | // 64'b0000000000000000000001??????????????????????????????????????????: cntl0[6:0] = 7'b0010101; |
| 1056 | // 64'b00000000000000000000001?????????????????????????????????????????: cntl0[6:0] = 7'b0010110; |
| 1057 | // 64'b000000000000000000000001????????????????????????????????????????: cntl0[6:0] = 7'b0010111; |
| 1058 | // |
| 1059 | // 64'b0000000000000000000000001???????????????????????????????????????: cntl0[6:0] = 7'b0011000; |
| 1060 | // 64'b00000000000000000000000001??????????????????????????????????????: cntl0[6:0] = 7'b0011001; |
| 1061 | // 64'b000000000000000000000000001?????????????????????????????????????: cntl0[6:0] = 7'b0011010; |
| 1062 | // 64'b0000000000000000000000000001????????????????????????????????????: cntl0[6:0] = 7'b0011011; |
| 1063 | // 64'b00000000000000000000000000001???????????????????????????????????: cntl0[6:0] = 7'b0011100; |
| 1064 | // 64'b000000000000000000000000000001??????????????????????????????????: cntl0[6:0] = 7'b0011101; |
| 1065 | // 64'b0000000000000000000000000000001?????????????????????????????????: cntl0[6:0] = 7'b0011110; |
| 1066 | // 64'b00000000000000000000000000000001????????????????????????????????: cntl0[6:0] = 7'b0011111; |
| 1067 | // |
| 1068 | // 64'b000000000000000000000000000000001???????????????????????????????: cntl0[6:0] = 7'b0100000; |
| 1069 | // 64'b0000000000000000000000000000000001??????????????????????????????: cntl0[6:0] = 7'b0100001; |
| 1070 | // 64'b00000000000000000000000000000000001?????????????????????????????: cntl0[6:0] = 7'b0100010; |
| 1071 | // 64'b000000000000000000000000000000000001????????????????????????????: cntl0[6:0] = 7'b0100011; |
| 1072 | // 64'b0000000000000000000000000000000000001???????????????????????????: cntl0[6:0] = 7'b0100100; |
| 1073 | // 64'b00000000000000000000000000000000000001??????????????????????????: cntl0[6:0] = 7'b0100101; |
| 1074 | // 64'b000000000000000000000000000000000000001?????????????????????????: cntl0[6:0] = 7'b0100110; |
| 1075 | // 64'b0000000000000000000000000000000000000001????????????????????????: cntl0[6:0] = 7'b0100111; |
| 1076 | // |
| 1077 | // 64'b00000000000000000000000000000000000000001???????????????????????: cntl0[6:0] = 7'b0101000; |
| 1078 | // 64'b000000000000000000000000000000000000000001??????????????????????: cntl0[6:0] = 7'b0101001; |
| 1079 | // 64'b0000000000000000000000000000000000000000001?????????????????????: cntl0[6:0] = 7'b0101010; |
| 1080 | // 64'b00000000000000000000000000000000000000000001????????????????????: cntl0[6:0] = 7'b0101011; |
| 1081 | // 64'b000000000000000000000000000000000000000000001???????????????????: cntl0[6:0] = 7'b0101100; |
| 1082 | // 64'b0000000000000000000000000000000000000000000001??????????????????: cntl0[6:0] = 7'b0101101; |
| 1083 | // 64'b00000000000000000000000000000000000000000000001?????????????????: cntl0[6:0] = 7'b0101110; |
| 1084 | // 64'b000000000000000000000000000000000000000000000001????????????????: cntl0[6:0] = 7'b0101111; |
| 1085 | // |
| 1086 | // 64'b0000000000000000000000000000000000000000000000001???????????????: cntl0[6:0] = 7'b0110000; |
| 1087 | // 64'b00000000000000000000000000000000000000000000000001??????????????: cntl0[6:0] = 7'b0110001; |
| 1088 | // 64'b000000000000000000000000000000000000000000000000001?????????????: cntl0[6:0] = 7'b0110010; |
| 1089 | // 64'b0000000000000000000000000000000000000000000000000001????????????: cntl0[6:0] = 7'b0110011; |
| 1090 | // 64'b00000000000000000000000000000000000000000000000000001???????????: cntl0[6:0] = 7'b0110100; |
| 1091 | // 64'b000000000000000000000000000000000000000000000000000001??????????: cntl0[6:0] = 7'b0110101; |
| 1092 | // 64'b0000000000000000000000000000000000000000000000000000001?????????: cntl0[6:0] = 7'b0110110; |
| 1093 | // 64'b00000000000000000000000000000000000000000000000000000001????????: cntl0[6:0] = 7'b0110111; |
| 1094 | // |
| 1095 | // 64'b000000000000000000000000000000000000000000000000000000001???????: cntl0[6:0] = 7'b0111000; |
| 1096 | // 64'b0000000000000000000000000000000000000000000000000000000001??????: cntl0[6:0] = 7'b0111001; |
| 1097 | // 64'b00000000000000000000000000000000000000000000000000000000001?????: cntl0[6:0] = 7'b0111010; |
| 1098 | // 64'b000000000000000000000000000000000000000000000000000000000001????: cntl0[6:0] = 7'b0111011; |
| 1099 | // 64'b0000000000000000000000000000000000000000000000000000000000001???: cntl0[6:0] = 7'b0111100; |
| 1100 | // 64'b00000000000000000000000000000000000000000000000000000000000001??: cntl0[6:0] = 7'b0111101; |
| 1101 | // 64'b000000000000000000000000000000000000000000000000000000000000001?: cntl0[6:0] = 7'b0111110; |
| 1102 | // 64'b0000000000000000000000000000000000000000000000000000000000000001: cntl0[6:0] = 7'b0111111; |
| 1103 | // |
| 1104 | // 64'b0000000000000000000000000000000000000000000000000000000000000000: cntl0[6:0] = 7'b1000000; |
| 1105 | // |
| 1106 | // default: cntl0[6:0] = 7'bxxxxxxx; |
| 1107 | // |
| 1108 | // endcase |
| 1109 | // |
| 1110 | //end |
| 1111 | |
| 1112 | |
| 1113 | // The real count leading zero (CNTL0) circuit must be coded at the gate level. |
| 1114 | // For each 8-bit byte, a 3-bit count and an "all zero" will be computed. The |
| 1115 | // "all zero" will then be used to find which byte contains the leading 1. |
| 1116 | // The 3-bit count from each byte will be muxed using those "all zero" controls |
| 1117 | // to form the 3 LSB's of the CNTL0. The upper 4 bits of the CNTL0 are |
| 1118 | // computed directly from the byte "all zero" controls. See the truth tables |
| 1119 | // below for more details. |
| 1120 | // |
| 1121 | // byte |
| 1122 | // clth[7:0] | cnt[2:0] zero |
| 1123 | // -----------------|----------------- |
| 1124 | // 1 x x x x x x x | 0 0 0 0 |
| 1125 | // 0 1 x x x x x x | 0 0 1 0 |
| 1126 | // 0 0 1 x x x x x | 0 1 0 0 |
| 1127 | // 0 0 0 1 x x x x | 0 1 1 0 |
| 1128 | // 0 0 0 0 1 x x x | 1 0 0 0 |
| 1129 | // 0 0 0 0 0 1 x x | 1 0 1 0 |
| 1130 | // 0 0 0 0 0 0 1 x | 1 1 0 0 |
| 1131 | // 0 0 0 0 0 0 0 1 | 1 1 1 0 |
| 1132 | // 0 0 0 0 0 0 0 0 | 0 0 0 1 |
| 1133 | // |
| 1134 | // |
| 1135 | // Byte Zero_ |
| 1136 | // z7 z6 z5 z4 z3 z2 z1 z0 | cnt[6:3] |
| 1137 | // -------------------------|------------- |
| 1138 | // 1 x x x x x x x | 0 0 0 0 |
| 1139 | // 0 1 x x x x x x | 0 0 0 1 |
| 1140 | // 0 0 1 x x x x x | 0 0 1 0 |
| 1141 | // 0 0 0 1 x x x x | 0 0 1 1 |
| 1142 | // 0 0 0 0 1 x x x | 0 1 0 0 |
| 1143 | // 0 0 0 0 0 1 x x | 0 1 0 1 |
| 1144 | // 0 0 0 0 0 0 1 x | 0 1 1 0 |
| 1145 | // 0 0 0 0 0 0 0 1 | 0 1 1 1 |
| 1146 | // 0 0 0 0 0 0 0 0 | 1 x x x (divide ENDS!) |
| 1147 | // |
| 1148 | // |
| 1149 | // Byte Zero_ is an 8-way OR of all bits in that byte. |
| 1150 | // This can be accomplished by 4 * Nor2 + Nand4 |
| 1151 | // |
| 1152 | // In order to compute the 3-bit count, we must further |
| 1153 | // divide the byte down into an upper and lower half. |
| 1154 | // |
| 1155 | // Estimated critical path : |
| 1156 | // NOR2 + NAND4 + PE(3->4) + MUX4 + MUX2 + MUX3(merge CNTL0 + CNTL1) |
| 1157 | |
| 1158 | |
| 1159 | assign clth[63:0] = fdd_pe_clth[63:0]; |
| 1160 | |
| 1161 | |
| 1162 | // ************************ BYTE 0 => 07:00 ************************** |
| 1163 | |
| 1164 | assign b0_nor_76 = ~(clth[7] | clth[6]); |
| 1165 | assign b0_nor_54 = ~(clth[5] | clth[4]); |
| 1166 | assign b0_nor_32 = ~(clth[3] | clth[2]); |
| 1167 | assign b0_nor_10 = ~(clth[1] | clth[0]); |
| 1168 | |
| 1169 | assign b0_zeroh_ = ~(b0_nor_76 & b0_nor_54); |
| 1170 | assign b0_zerol_ = ~(b0_nor_32 & b0_nor_10); |
| 1171 | assign b0_zero_ = ~(b0_nor_76 & b0_nor_54 & b0_nor_32 & b0_nor_10); |
| 1172 | |
| 1173 | assign b0_cnth[0] = (~clth[7] & clth[6] ) | |
| 1174 | (~clth[7] & ~clth[5] & clth[4]); |
| 1175 | |
| 1176 | assign b0_cnth[1] = (~clth[7] & ~clth[6] & clth[5] ) | |
| 1177 | (~clth[7] & ~clth[6] & clth[4]); |
| 1178 | |
| 1179 | assign b0_cntl[0] = (~clth[3] & clth[2] ) | |
| 1180 | (~clth[3] & ~clth[1] & clth[0]); |
| 1181 | |
| 1182 | assign b0_cntl[1] = (~clth[3] & ~clth[2] & clth[1] ) | |
| 1183 | (~clth[3] & ~clth[2] & clth[0]); |
| 1184 | |
| 1185 | assign b0_cnt[0] = ( b0_zeroh_ & b0_cnth[0]) | |
| 1186 | (~b0_zeroh_ & b0_cntl[0]); |
| 1187 | |
| 1188 | assign b0_cnt[1] = ( b0_zeroh_ & b0_cnth[1]) | |
| 1189 | (~b0_zeroh_ & b0_cntl[1]); |
| 1190 | |
| 1191 | assign b0_cnt[2] = (~b0_zeroh_ & b0_zerol_); |
| 1192 | |
| 1193 | |
| 1194 | // ************************ BYTE 1 => 15:08 ************************** |
| 1195 | |
| 1196 | assign b1_nor_76 = ~(clth[15] | clth[14]); |
| 1197 | assign b1_nor_54 = ~(clth[13] | clth[12]); |
| 1198 | assign b1_nor_32 = ~(clth[11] | clth[10]); |
| 1199 | assign b1_nor_10 = ~(clth[9] | clth[8]); |
| 1200 | |
| 1201 | assign b1_zeroh_ = ~(b1_nor_76 & b1_nor_54); |
| 1202 | assign b1_zerol_ = ~(b1_nor_32 & b1_nor_10); |
| 1203 | assign b1_zero_ = ~(b1_nor_76 & b1_nor_54 & b1_nor_32 & b1_nor_10); |
| 1204 | |
| 1205 | assign b1_cnth[0] = (~clth[15] & clth[14] ) | |
| 1206 | (~clth[15] & ~clth[13] & clth[12]); |
| 1207 | |
| 1208 | assign b1_cnth[1] = (~clth[15] & ~clth[14] & clth[13] ) | |
| 1209 | (~clth[15] & ~clth[14] & clth[12]); |
| 1210 | |
| 1211 | assign b1_cntl[0] = (~clth[11] & clth[10] ) | |
| 1212 | (~clth[11] & ~clth[9] & clth[8]); |
| 1213 | |
| 1214 | assign b1_cntl[1] = (~clth[11] & ~clth[10] & clth[9] ) | |
| 1215 | (~clth[11] & ~clth[10] & clth[8]); |
| 1216 | |
| 1217 | assign b1_cnt[0] = ( b1_zeroh_ & b1_cnth[0]) | |
| 1218 | (~b1_zeroh_ & b1_cntl[0]); |
| 1219 | |
| 1220 | assign b1_cnt[1] = ( b1_zeroh_ & b1_cnth[1]) | |
| 1221 | (~b1_zeroh_ & b1_cntl[1]); |
| 1222 | |
| 1223 | assign b1_cnt[2] = (~b1_zeroh_ & b1_zerol_); |
| 1224 | |
| 1225 | |
| 1226 | // ************************ BYTE 2 => 23:16 ************************** |
| 1227 | |
| 1228 | assign b2_nor_76 = ~(clth[23] | clth[22]); |
| 1229 | assign b2_nor_54 = ~(clth[21] | clth[20]); |
| 1230 | assign b2_nor_32 = ~(clth[19] | clth[18]); |
| 1231 | assign b2_nor_10 = ~(clth[17] | clth[16]); |
| 1232 | |
| 1233 | assign b2_zeroh_ = ~(b2_nor_76 & b2_nor_54); |
| 1234 | assign b2_zerol_ = ~(b2_nor_32 & b2_nor_10); |
| 1235 | assign b2_zero_ = ~(b2_nor_76 & b2_nor_54 & b2_nor_32 & b2_nor_10); |
| 1236 | |
| 1237 | assign b2_cnth[0] = (~clth[23] & clth[22] ) | |
| 1238 | (~clth[23] & ~clth[21] & clth[20]); |
| 1239 | |
| 1240 | assign b2_cnth[1] = (~clth[23] & ~clth[22] & clth[21] ) | |
| 1241 | (~clth[23] & ~clth[22] & clth[20]); |
| 1242 | |
| 1243 | assign b2_cntl[0] = (~clth[19] & clth[18] ) | |
| 1244 | (~clth[19] & ~clth[17] & clth[16]); |
| 1245 | |
| 1246 | assign b2_cntl[1] = (~clth[19] & ~clth[18] & clth[17] ) | |
| 1247 | (~clth[19] & ~clth[18] & clth[16]); |
| 1248 | |
| 1249 | assign b2_cnt[0] = ( b2_zeroh_ & b2_cnth[0]) | |
| 1250 | (~b2_zeroh_ & b2_cntl[0]); |
| 1251 | |
| 1252 | assign b2_cnt[1] = ( b2_zeroh_ & b2_cnth[1]) | |
| 1253 | (~b2_zeroh_ & b2_cntl[1]); |
| 1254 | |
| 1255 | assign b2_cnt[2] = (~b2_zeroh_ & b2_zerol_); |
| 1256 | |
| 1257 | |
| 1258 | // ************************ BYTE 3 => 31:24 ************************** |
| 1259 | |
| 1260 | assign b3_nor_76 = ~(clth[31] | clth[30]); |
| 1261 | assign b3_nor_54 = ~(clth[29] | clth[28]); |
| 1262 | assign b3_nor_32 = ~(clth[27] | clth[26]); |
| 1263 | assign b3_nor_10 = ~(clth[25] | clth[24]); |
| 1264 | |
| 1265 | assign b3_zeroh_ = ~(b3_nor_76 & b3_nor_54); |
| 1266 | assign b3_zerol_ = ~(b3_nor_32 & b3_nor_10); |
| 1267 | assign b3_zero_ = ~(b3_nor_76 & b3_nor_54 & b3_nor_32 & b3_nor_10); |
| 1268 | |
| 1269 | assign b3_cnth[0] = (~clth[31] & clth[30] ) | |
| 1270 | (~clth[31] & ~clth[29] & clth[28]); |
| 1271 | |
| 1272 | assign b3_cnth[1] = (~clth[31] & ~clth[30] & clth[29] ) | |
| 1273 | (~clth[31] & ~clth[30] & clth[28]); |
| 1274 | |
| 1275 | assign b3_cntl[0] = (~clth[27] & clth[26] ) | |
| 1276 | (~clth[27] & ~clth[25] & clth[24]); |
| 1277 | |
| 1278 | assign b3_cntl[1] = (~clth[27] & ~clth[26] & clth[25] ) | |
| 1279 | (~clth[27] & ~clth[26] & clth[24]); |
| 1280 | |
| 1281 | assign b3_cnt[0] = ( b3_zeroh_ & b3_cnth[0]) | |
| 1282 | (~b3_zeroh_ & b3_cntl[0]); |
| 1283 | |
| 1284 | assign b3_cnt[1] = ( b3_zeroh_ & b3_cnth[1]) | |
| 1285 | (~b3_zeroh_ & b3_cntl[1]); |
| 1286 | |
| 1287 | assign b3_cnt[2] = (~b3_zeroh_ & b3_zerol_); |
| 1288 | |
| 1289 | |
| 1290 | // ************************ BYTE 4 => 39:32 ************************** |
| 1291 | |
| 1292 | assign b4_nor_76 = ~(clth[39] | clth[38]); |
| 1293 | assign b4_nor_54 = ~(clth[37] | clth[36]); |
| 1294 | assign b4_nor_32 = ~(clth[35] | clth[34]); |
| 1295 | assign b4_nor_10 = ~(clth[33] | clth[32]); |
| 1296 | |
| 1297 | assign b4_zeroh_ = ~(b4_nor_76 & b4_nor_54); |
| 1298 | assign b4_zerol_ = ~(b4_nor_32 & b4_nor_10); |
| 1299 | assign b4_zero_ = ~(b4_nor_76 & b4_nor_54 & b4_nor_32 & b4_nor_10); |
| 1300 | |
| 1301 | assign b4_cnth[0] = (~clth[39] & clth[38] ) | |
| 1302 | (~clth[39] & ~clth[37] & clth[36]); |
| 1303 | |
| 1304 | assign b4_cnth[1] = (~clth[39] & ~clth[38] & clth[37] ) | |
| 1305 | (~clth[39] & ~clth[38] & clth[36]); |
| 1306 | |
| 1307 | assign b4_cntl[0] = (~clth[35] & clth[34] ) | |
| 1308 | (~clth[35] & ~clth[33] & clth[32]); |
| 1309 | |
| 1310 | assign b4_cntl[1] = (~clth[35] & ~clth[34] & clth[33] ) | |
| 1311 | (~clth[35] & ~clth[34] & clth[32]); |
| 1312 | |
| 1313 | assign b4_cnt[0] = ( b4_zeroh_ & b4_cnth[0]) | |
| 1314 | (~b4_zeroh_ & b4_cntl[0]); |
| 1315 | |
| 1316 | assign b4_cnt[1] = ( b4_zeroh_ & b4_cnth[1]) | |
| 1317 | (~b4_zeroh_ & b4_cntl[1]); |
| 1318 | |
| 1319 | assign b4_cnt[2] = (~b4_zeroh_ & b4_zerol_); |
| 1320 | |
| 1321 | |
| 1322 | // ************************ BYTE 5 => 47:40 ************************** |
| 1323 | |
| 1324 | assign b5_nor_76 = ~(clth[47] | clth[46]); |
| 1325 | assign b5_nor_54 = ~(clth[45] | clth[44]); |
| 1326 | assign b5_nor_32 = ~(clth[43] | clth[42]); |
| 1327 | assign b5_nor_10 = ~(clth[41] | clth[40]); |
| 1328 | |
| 1329 | assign b5_zeroh_ = ~(b5_nor_76 & b5_nor_54); |
| 1330 | assign b5_zerol_ = ~(b5_nor_32 & b5_nor_10); |
| 1331 | assign b5_zero_ = ~(b5_nor_76 & b5_nor_54 & b5_nor_32 & b5_nor_10); |
| 1332 | |
| 1333 | assign b5_cnth[0] = (~clth[47] & clth[46] ) | |
| 1334 | (~clth[47] & ~clth[45] & clth[44]); |
| 1335 | |
| 1336 | assign b5_cnth[1] = (~clth[47] & ~clth[46] & clth[45] ) | |
| 1337 | (~clth[47] & ~clth[46] & clth[44]); |
| 1338 | |
| 1339 | assign b5_cntl[0] = (~clth[43] & clth[42] ) | |
| 1340 | (~clth[43] & ~clth[41] & clth[40]); |
| 1341 | |
| 1342 | assign b5_cntl[1] = (~clth[43] & ~clth[42] & clth[41] ) | |
| 1343 | (~clth[43] & ~clth[42] & clth[40]); |
| 1344 | |
| 1345 | assign b5_cnt[0] = ( b5_zeroh_ & b5_cnth[0]) | |
| 1346 | (~b5_zeroh_ & b5_cntl[0]); |
| 1347 | |
| 1348 | assign b5_cnt[1] = ( b5_zeroh_ & b5_cnth[1]) | |
| 1349 | (~b5_zeroh_ & b5_cntl[1]); |
| 1350 | |
| 1351 | assign b5_cnt[2] = (~b5_zeroh_ & b5_zerol_); |
| 1352 | |
| 1353 | |
| 1354 | // ************************ BYTE 6 => 55:48 ************************** |
| 1355 | |
| 1356 | assign b6_nor_76 = ~(clth[55] | clth[54]); |
| 1357 | assign b6_nor_54 = ~(clth[53] | clth[52]); |
| 1358 | assign b6_nor_32 = ~(clth[51] | clth[50]); |
| 1359 | assign b6_nor_10 = ~(clth[49] | clth[48]); |
| 1360 | |
| 1361 | assign b6_zeroh_ = ~(b6_nor_76 & b6_nor_54); |
| 1362 | assign b6_zerol_ = ~(b6_nor_32 & b6_nor_10); |
| 1363 | assign b6_zero_ = ~(b6_nor_76 & b6_nor_54 & b6_nor_32 & b6_nor_10); |
| 1364 | |
| 1365 | assign b6_cnth[0] = (~clth[55] & clth[54] ) | |
| 1366 | (~clth[55] & ~clth[53] & clth[52]); |
| 1367 | |
| 1368 | assign b6_cnth[1] = (~clth[55] & ~clth[54] & clth[53] ) | |
| 1369 | (~clth[55] & ~clth[54] & clth[52]); |
| 1370 | |
| 1371 | assign b6_cntl[0] = (~clth[51] & clth[50] ) | |
| 1372 | (~clth[51] & ~clth[49] & clth[48]); |
| 1373 | |
| 1374 | assign b6_cntl[1] = (~clth[51] & ~clth[50] & clth[49] ) | |
| 1375 | (~clth[51] & ~clth[50] & clth[48]); |
| 1376 | |
| 1377 | assign b6_cnt[0] = ( b6_zeroh_ & b6_cnth[0]) | |
| 1378 | (~b6_zeroh_ & b6_cntl[0]); |
| 1379 | |
| 1380 | assign b6_cnt[1] = ( b6_zeroh_ & b6_cnth[1]) | |
| 1381 | (~b6_zeroh_ & b6_cntl[1]); |
| 1382 | |
| 1383 | assign b6_cnt[2] = (~b6_zeroh_ & b6_zerol_); |
| 1384 | |
| 1385 | |
| 1386 | // ************************ BYTE 7 => 63:56 ************************** |
| 1387 | |
| 1388 | assign b7_nor_76 = ~(clth[63] | clth[62]); |
| 1389 | assign b7_nor_54 = ~(clth[61] | clth[60]); |
| 1390 | assign b7_nor_32 = ~(clth[59] | clth[58]); |
| 1391 | assign b7_nor_10 = ~(clth[57] | clth[56]); |
| 1392 | |
| 1393 | assign b7_zeroh_ = ~(b7_nor_76 & b7_nor_54); |
| 1394 | assign b7_zerol_ = ~(b7_nor_32 & b7_nor_10); |
| 1395 | assign b7_zero_ = ~(b7_nor_76 & b7_nor_54 & b7_nor_32 & b7_nor_10); |
| 1396 | |
| 1397 | assign b7_cnth[0] = (~clth[63] & clth[62] ) | |
| 1398 | (~clth[63] & ~clth[61] & clth[60]); |
| 1399 | |
| 1400 | assign b7_cnth[1] = (~clth[63] & ~clth[62] & clth[61] ) | |
| 1401 | (~clth[63] & ~clth[62] & clth[60]); |
| 1402 | |
| 1403 | assign b7_cntl[0] = (~clth[59] & clth[58] ) | |
| 1404 | (~clth[59] & ~clth[57] & clth[56]); |
| 1405 | |
| 1406 | assign b7_cntl[1] = (~clth[59] & ~clth[58] & clth[57] ) | |
| 1407 | (~clth[59] & ~clth[58] & clth[56]); |
| 1408 | |
| 1409 | assign b7_cnt[0] = ( b7_zeroh_ & b7_cnth[0]) | |
| 1410 | (~b7_zeroh_ & b7_cntl[0]); |
| 1411 | |
| 1412 | assign b7_cnt[1] = ( b7_zeroh_ & b7_cnth[1]) | |
| 1413 | (~b7_zeroh_ & b7_cntl[1]); |
| 1414 | |
| 1415 | assign b7_cnt[2] = (~b7_zeroh_ & b7_zerol_); |
| 1416 | |
| 1417 | |
| 1418 | |
| 1419 | // ************************ Global CNTL0 ************************** |
| 1420 | |
| 1421 | // When CNTL0[6] = 1 all other bits become a DON'T CARE |
| 1422 | |
| 1423 | assign b3_0sel = b3_zero_ ; |
| 1424 | assign b2_0sel = ~b3_zero_ & b2_zero_ ; |
| 1425 | assign b1_0sel = ~b3_zero_ & ~b2_zero_ & b1_zero_; |
| 1426 | assign b0_0sel = ~b3_zero_ & ~b2_zero_ & ~b1_zero_; |
| 1427 | |
| 1428 | assign cntl0l[4:0] = ({5{b3_0sel}} & {2'b00,b3_cnt[2:0]}) | |
| 1429 | ({5{b2_0sel}} & {2'b01,b2_cnt[2:0]}) | |
| 1430 | ({5{b1_0sel}} & {2'b10,b1_cnt[2:0]}) | |
| 1431 | ({5{b0_0sel}} & {2'b11,b0_cnt[2:0]}); |
| 1432 | |
| 1433 | |
| 1434 | assign b7_0sel = b7_zero_ ; |
| 1435 | assign b6_0sel = ~b7_zero_ & b6_zero_ ; |
| 1436 | assign b5_0sel = ~b7_zero_ & ~b6_zero_ & b5_zero_; |
| 1437 | assign b4_0sel = ~b7_zero_ & ~b6_zero_ & ~b5_zero_; |
| 1438 | |
| 1439 | assign cntl0h[4:0] = ({5{b7_0sel}} & {2'b00,b7_cnt[2:0]}) | |
| 1440 | ({5{b6_0sel}} & {2'b01,b6_cnt[2:0]}) | |
| 1441 | ({5{b5_0sel}} & {2'b10,b5_cnt[2:0]}) | |
| 1442 | ({5{b4_0sel}} & {2'b11,b4_cnt[2:0]}); |
| 1443 | |
| 1444 | assign cntl0_selh = b7_zero_ | b6_zero_ | b5_zero_ | b4_zero_; |
| 1445 | assign cntl0_sell = b3_zero_ | b2_zero_ | b1_zero_ | b0_zero_; |
| 1446 | assign cntl0[6] = ~(cntl0_selh | cntl0_sell); |
| 1447 | |
| 1448 | assign cntl0[5:0] = ({6{ cntl0_selh}} & {1'b0, cntl0h[4:0]}) | |
| 1449 | ({6{~cntl0_selh}} & {1'b1, cntl0l[4:0]}); |
| 1450 | |
| 1451 | |
| 1452 | // * * * * * * * * * * * * End : Integer CNTL0 * * * * * * * * * * * * * |
| 1453 | |
| 1454 | |
| 1455 | // * * * * * * * * * * * * Start : Integer CNTL1 * * * * * * * * * * * * * |
| 1456 | |
| 1457 | //reg [6:0] cntl1; |
| 1458 | // |
| 1459 | //always @ (fdd_pe_clth[63:0]) |
| 1460 | // |
| 1461 | // begin |
| 1462 | // |
| 1463 | // |
| 1464 | // casex (fdd_pe_clth[63:0]) |
| 1465 | // 64'b0???????????????????????????????????????????????????????????????: cntl1[6:0] = 7'b0000000; |
| 1466 | // |
| 1467 | // 64'b10??????????????????????????????????????????????????????????????: cntl1[6:0] = 7'b0000000; |
| 1468 | // 64'b110?????????????????????????????????????????????????????????????: cntl1[6:0] = 7'b0000001; |
| 1469 | // 64'b1110????????????????????????????????????????????????????????????: cntl1[6:0] = 7'b0000010; |
| 1470 | // 64'b11110???????????????????????????????????????????????????????????: cntl1[6:0] = 7'b0000011; |
| 1471 | // 64'b111110??????????????????????????????????????????????????????????: cntl1[6:0] = 7'b0000100; |
| 1472 | // 64'b1111110?????????????????????????????????????????????????????????: cntl1[6:0] = 7'b0000101; |
| 1473 | // 64'b11111110????????????????????????????????????????????????????????: cntl1[6:0] = 7'b0000110; |
| 1474 | // 64'b111111110???????????????????????????????????????????????????????: cntl1[6:0] = 7'b0000111; |
| 1475 | // |
| 1476 | // 64'b1111111110??????????????????????????????????????????????????????: cntl1[6:0] = 7'b0001000; |
| 1477 | // 64'b11111111110?????????????????????????????????????????????????????: cntl1[6:0] = 7'b0001001; |
| 1478 | // 64'b111111111110????????????????????????????????????????????????????: cntl1[6:0] = 7'b0001010; |
| 1479 | // 64'b1111111111110???????????????????????????????????????????????????: cntl1[6:0] = 7'b0001011; |
| 1480 | // 64'b11111111111110??????????????????????????????????????????????????: cntl1[6:0] = 7'b0001100; |
| 1481 | // 64'b111111111111110?????????????????????????????????????????????????: cntl1[6:0] = 7'b0001101; |
| 1482 | // 64'b1111111111111110????????????????????????????????????????????????: cntl1[6:0] = 7'b0001110; |
| 1483 | // 64'b11111111111111110???????????????????????????????????????????????: cntl1[6:0] = 7'b0001111; |
| 1484 | // |
| 1485 | // 64'b111111111111111110??????????????????????????????????????????????: cntl1[6:0] = 7'b0010000; |
| 1486 | // 64'b1111111111111111110?????????????????????????????????????????????: cntl1[6:0] = 7'b0010001; |
| 1487 | // 64'b11111111111111111110????????????????????????????????????????????: cntl1[6:0] = 7'b0010010; |
| 1488 | // 64'b111111111111111111110???????????????????????????????????????????: cntl1[6:0] = 7'b0010011; |
| 1489 | // 64'b1111111111111111111110??????????????????????????????????????????: cntl1[6:0] = 7'b0010100; |
| 1490 | // 64'b11111111111111111111110?????????????????????????????????????????: cntl1[6:0] = 7'b0010101; |
| 1491 | // 64'b111111111111111111111110????????????????????????????????????????: cntl1[6:0] = 7'b0010110; |
| 1492 | // 64'b1111111111111111111111110???????????????????????????????????????: cntl1[6:0] = 7'b0010111; |
| 1493 | // |
| 1494 | // 64'b11111111111111111111111110??????????????????????????????????????: cntl1[6:0] = 7'b0011000; |
| 1495 | // 64'b111111111111111111111111110?????????????????????????????????????: cntl1[6:0] = 7'b0011001; |
| 1496 | // 64'b1111111111111111111111111110????????????????????????????????????: cntl1[6:0] = 7'b0011010; |
| 1497 | // 64'b11111111111111111111111111110???????????????????????????????????: cntl1[6:0] = 7'b0011011; |
| 1498 | // 64'b111111111111111111111111111110??????????????????????????????????: cntl1[6:0] = 7'b0011100; |
| 1499 | // 64'b1111111111111111111111111111110?????????????????????????????????: cntl1[6:0] = 7'b0011101; |
| 1500 | // 64'b11111111111111111111111111111110????????????????????????????????: cntl1[6:0] = 7'b0011110; |
| 1501 | // 64'b111111111111111111111111111111110???????????????????????????????: cntl1[6:0] = 7'b0011111; |
| 1502 | // |
| 1503 | // 64'b1111111111111111111111111111111110??????????????????????????????: cntl1[6:0] = 7'b0100000; |
| 1504 | // 64'b11111111111111111111111111111111110?????????????????????????????: cntl1[6:0] = 7'b0100001; |
| 1505 | // 64'b111111111111111111111111111111111110????????????????????????????: cntl1[6:0] = 7'b0100010; |
| 1506 | // 64'b1111111111111111111111111111111111110???????????????????????????: cntl1[6:0] = 7'b0100011; |
| 1507 | // 64'b11111111111111111111111111111111111110??????????????????????????: cntl1[6:0] = 7'b0100100; |
| 1508 | // 64'b111111111111111111111111111111111111110?????????????????????????: cntl1[6:0] = 7'b0100101; |
| 1509 | // 64'b1111111111111111111111111111111111111110????????????????????????: cntl1[6:0] = 7'b0100110; |
| 1510 | // 64'b11111111111111111111111111111111111111110???????????????????????: cntl1[6:0] = 7'b0100111; |
| 1511 | // |
| 1512 | // 64'b111111111111111111111111111111111111111110??????????????????????: cntl1[6:0] = 7'b0101000; |
| 1513 | // 64'b1111111111111111111111111111111111111111110?????????????????????: cntl1[6:0] = 7'b0101001; |
| 1514 | // 64'b11111111111111111111111111111111111111111110????????????????????: cntl1[6:0] = 7'b0101010; |
| 1515 | // 64'b111111111111111111111111111111111111111111110???????????????????: cntl1[6:0] = 7'b0101011; |
| 1516 | // 64'b1111111111111111111111111111111111111111111110??????????????????: cntl1[6:0] = 7'b0101100; |
| 1517 | // 64'b11111111111111111111111111111111111111111111110?????????????????: cntl1[6:0] = 7'b0101101; |
| 1518 | // 64'b111111111111111111111111111111111111111111111110????????????????: cntl1[6:0] = 7'b0101110; |
| 1519 | // 64'b1111111111111111111111111111111111111111111111110???????????????: cntl1[6:0] = 7'b0101111; |
| 1520 | // |
| 1521 | // 64'b11111111111111111111111111111111111111111111111110??????????????: cntl1[6:0] = 7'b0110000; |
| 1522 | // 64'b111111111111111111111111111111111111111111111111110?????????????: cntl1[6:0] = 7'b0110001; |
| 1523 | // 64'b1111111111111111111111111111111111111111111111111110????????????: cntl1[6:0] = 7'b0110010; |
| 1524 | // 64'b11111111111111111111111111111111111111111111111111110???????????: cntl1[6:0] = 7'b0110011; |
| 1525 | // 64'b111111111111111111111111111111111111111111111111111110??????????: cntl1[6:0] = 7'b0110100; |
| 1526 | // 64'b1111111111111111111111111111111111111111111111111111110?????????: cntl1[6:0] = 7'b0110101; |
| 1527 | // 64'b11111111111111111111111111111111111111111111111111111110????????: cntl1[6:0] = 7'b0110110; |
| 1528 | // 64'b111111111111111111111111111111111111111111111111111111110???????: cntl1[6:0] = 7'b0110111; |
| 1529 | // |
| 1530 | // 64'b1111111111111111111111111111111111111111111111111111111110??????: cntl1[6:0] = 7'b0111000; |
| 1531 | // 64'b11111111111111111111111111111111111111111111111111111111110?????: cntl1[6:0] = 7'b0111001; |
| 1532 | // 64'b111111111111111111111111111111111111111111111111111111111110????: cntl1[6:0] = 7'b0111010; |
| 1533 | // 64'b1111111111111111111111111111111111111111111111111111111111110???: cntl1[6:0] = 7'b0111011; |
| 1534 | // 64'b11111111111111111111111111111111111111111111111111111111111110??: cntl1[6:0] = 7'b0111100; |
| 1535 | // 64'b111111111111111111111111111111111111111111111111111111111111110?: cntl1[6:0] = 7'b0111101; |
| 1536 | // 64'b1111111111111111111111111111111111111111111111111111111111111110: cntl1[6:0] = 7'b0111110; |
| 1537 | // 64'b1111111111111111111111111111111111111111111111111111111111111111: cntl1[6:0] = 7'b0111111; |
| 1538 | // |
| 1539 | // default: cntl1[6:0] = 7'b0000000; |
| 1540 | // |
| 1541 | // endcase |
| 1542 | // |
| 1543 | //end |
| 1544 | |
| 1545 | |
| 1546 | // The count leading one (CNTL1) here must compute "n-1" |
| 1547 | // leading 1's. To do this, each local byte will receive |
| 1548 | // an offset input. |
| 1549 | // Note : If clth[63] = 0 then CNTL1 is a DON'T CARE |
| 1550 | |
| 1551 | // byte |
| 1552 | // clth[7:0] | cnt[2:0] ones |
| 1553 | // -----------------|----------------- |
| 1554 | // 0 x x x x x x x | 0 0 0 0 |
| 1555 | // 1 0 x x x x x x | 0 0 1 0 |
| 1556 | // 1 1 0 x x x x x | 0 1 0 0 |
| 1557 | // 1 1 1 0 x x x x | 0 1 1 0 |
| 1558 | // 1 1 1 1 0 x x x | 1 0 0 0 |
| 1559 | // 1 1 1 1 1 0 x x | 1 0 1 0 |
| 1560 | // 1 1 1 1 1 1 0 x | 1 1 0 0 |
| 1561 | // 1 1 1 1 1 1 1 0 | 1 1 1 0 |
| 1562 | // 1 1 1 1 1 1 1 1 | 0 0 0 1 (byte 0 is '111' here) |
| 1563 | // |
| 1564 | // |
| 1565 | // Byte Ones_ |
| 1566 | // z7 z6 z5 z4 z3 z2 z1 z0 | cnt[6:3] |
| 1567 | // -------------------------|------------- |
| 1568 | // 1 x x x x x x x | 0 0 0 0 |
| 1569 | // 0 1 x x x x x x | 0 0 0 1 |
| 1570 | // 0 0 1 x x x x x | 0 0 1 0 |
| 1571 | // 0 0 0 1 x x x x | 0 0 1 1 |
| 1572 | // 0 0 0 0 1 x x x | 0 1 0 0 |
| 1573 | // 0 0 0 0 0 1 x x | 0 1 0 1 |
| 1574 | // 0 0 0 0 0 0 1 x | 0 1 1 0 |
| 1575 | // 0 0 0 0 0 0 0 1 | 0 1 1 1 |
| 1576 | // 0 0 0 0 0 0 0 0 | 1 x x x (divide ENDS!) |
| 1577 | // |
| 1578 | // |
| 1579 | // Estimated critical path : |
| 1580 | // NAND4 + NOR2 + INV + PE(3->4) + MUX4 + MUX2 + MUX3(merge CNTL0 + CNTL1) |
| 1581 | |
| 1582 | |
| 1583 | |
| 1584 | // ************************ BYTE 7 => 62:55 ************************** |
| 1585 | |
| 1586 | assign b7_nand_74 = ~(clth[62] & clth[61] & clth[60] & clth[59]); |
| 1587 | assign b7_nand_30 = ~(clth[58] & clth[57] & clth[56] & clth[55]); |
| 1588 | |
| 1589 | assign b7_ones = ~(b7_nand_74 | b7_nand_30); |
| 1590 | assign b7_ones_ = ~b7_ones; |
| 1591 | |
| 1592 | assign b7_cnt1h[0] = ( clth[62] & ~clth[61] ) | |
| 1593 | ( clth[62] & clth[60] & ~clth[59]); |
| 1594 | |
| 1595 | assign b7_cnt1h[1] = ( clth[62] & clth[61] & ~clth[60] ) | |
| 1596 | ( clth[62] & clth[61] & ~clth[59]); |
| 1597 | |
| 1598 | assign b7_cnt1l[0] = ( clth[58] & ~clth[57] ) | |
| 1599 | ( clth[58] & clth[56] & ~clth[55]); |
| 1600 | |
| 1601 | assign b7_cnt1l[1] = ( clth[58] & clth[57] & ~clth[56] ) | |
| 1602 | ( clth[58] & clth[57] & ~clth[55]); |
| 1603 | |
| 1604 | assign b7_cnt1[0] = ( b7_nand_74 & b7_cnt1h[0]) | |
| 1605 | (~b7_nand_74 & b7_cnt1l[0]); |
| 1606 | |
| 1607 | assign b7_cnt1[1] = ( b7_nand_74 & b7_cnt1h[1]) | |
| 1608 | (~b7_nand_74 & b7_cnt1l[1]); |
| 1609 | |
| 1610 | assign b7_cnt1[2] = (~b7_nand_74 & b7_nand_30); |
| 1611 | |
| 1612 | |
| 1613 | // ************************ BYTE 6 => 54:47 ************************** |
| 1614 | |
| 1615 | assign b6_nand_74 = ~(clth[54] & clth[53] & clth[52] & clth[51]); |
| 1616 | assign b6_nand_30 = ~(clth[50] & clth[49] & clth[48] & clth[47]); |
| 1617 | |
| 1618 | assign b6_ones = ~(b6_nand_74 | b6_nand_30); |
| 1619 | assign b6_ones_ = ~b6_ones; |
| 1620 | |
| 1621 | assign b6_cnt1h[0] = ( clth[54] & ~clth[53] ) | |
| 1622 | ( clth[54] & clth[52] & ~clth[51]); |
| 1623 | |
| 1624 | assign b6_cnt1h[1] = ( clth[54] & clth[53] & ~clth[52] ) | |
| 1625 | ( clth[54] & clth[53] & ~clth[51]); |
| 1626 | |
| 1627 | assign b6_cnt1l[0] = ( clth[50] & ~clth[49] ) | |
| 1628 | ( clth[50] & clth[48] & ~clth[47]); |
| 1629 | |
| 1630 | assign b6_cnt1l[1] = ( clth[50] & clth[49] & ~clth[48] ) | |
| 1631 | ( clth[50] & clth[49] & ~clth[47]); |
| 1632 | |
| 1633 | assign b6_cnt1[0] = ( b6_nand_74 & b6_cnt1h[0]) | |
| 1634 | (~b6_nand_74 & b6_cnt1l[0]); |
| 1635 | |
| 1636 | assign b6_cnt1[1] = ( b6_nand_74 & b6_cnt1h[1]) | |
| 1637 | (~b6_nand_74 & b6_cnt1l[1]); |
| 1638 | |
| 1639 | assign b6_cnt1[2] = (~b6_nand_74 & b6_nand_30); |
| 1640 | |
| 1641 | |
| 1642 | // ************************ BYTE 5 => 46:39 ************************** |
| 1643 | |
| 1644 | assign b5_nand_74 = ~(clth[46] & clth[45] & clth[44] & clth[43]); |
| 1645 | assign b5_nand_30 = ~(clth[42] & clth[41] & clth[40] & clth[39]); |
| 1646 | |
| 1647 | assign b5_ones = ~(b5_nand_74 | b5_nand_30); |
| 1648 | assign b5_ones_ = ~b5_ones; |
| 1649 | |
| 1650 | assign b5_cnt1h[0] = ( clth[46] & ~clth[45] ) | |
| 1651 | ( clth[46] & clth[44] & ~clth[43]); |
| 1652 | |
| 1653 | assign b5_cnt1h[1] = ( clth[46] & clth[45] & ~clth[44] ) | |
| 1654 | ( clth[46] & clth[45] & ~clth[43]); |
| 1655 | |
| 1656 | assign b5_cnt1l[0] = ( clth[42] & ~clth[41] ) | |
| 1657 | ( clth[42] & clth[40] & ~clth[39]); |
| 1658 | |
| 1659 | assign b5_cnt1l[1] = ( clth[42] & clth[41] & ~clth[40] ) | |
| 1660 | ( clth[42] & clth[41] & ~clth[39]); |
| 1661 | |
| 1662 | assign b5_cnt1[0] = ( b5_nand_74 & b5_cnt1h[0]) | |
| 1663 | (~b5_nand_74 & b5_cnt1l[0]); |
| 1664 | |
| 1665 | assign b5_cnt1[1] = ( b5_nand_74 & b5_cnt1h[1]) | |
| 1666 | (~b5_nand_74 & b5_cnt1l[1]); |
| 1667 | |
| 1668 | assign b5_cnt1[2] = (~b5_nand_74 & b5_nand_30); |
| 1669 | |
| 1670 | |
| 1671 | // ************************ BYTE 4 => 38:31 ************************** |
| 1672 | |
| 1673 | assign b4_nand_74 = ~(clth[38] & clth[37] & clth[36] & clth[35]); |
| 1674 | assign b4_nand_30 = ~(clth[34] & clth[33] & clth[32] & clth[31]); |
| 1675 | |
| 1676 | assign b4_ones = ~(b4_nand_74 | b4_nand_30); |
| 1677 | assign b4_ones_ = ~b4_ones; |
| 1678 | |
| 1679 | assign b4_cnt1h[0] = ( clth[38] & ~clth[37] ) | |
| 1680 | ( clth[38] & clth[36] & ~clth[35]); |
| 1681 | |
| 1682 | assign b4_cnt1h[1] = ( clth[38] & clth[37] & ~clth[36] ) | |
| 1683 | ( clth[38] & clth[37] & ~clth[35]); |
| 1684 | |
| 1685 | assign b4_cnt1l[0] = ( clth[34] & ~clth[33] ) | |
| 1686 | ( clth[34] & clth[32] & ~clth[31]); |
| 1687 | |
| 1688 | assign b4_cnt1l[1] = ( clth[34] & clth[33] & ~clth[32] ) | |
| 1689 | ( clth[34] & clth[33] & ~clth[31]); |
| 1690 | |
| 1691 | assign b4_cnt1[0] = ( b4_nand_74 & b4_cnt1h[0]) | |
| 1692 | (~b4_nand_74 & b4_cnt1l[0]); |
| 1693 | |
| 1694 | assign b4_cnt1[1] = ( b4_nand_74 & b4_cnt1h[1]) | |
| 1695 | (~b4_nand_74 & b4_cnt1l[1]); |
| 1696 | |
| 1697 | assign b4_cnt1[2] = (~b4_nand_74 & b4_nand_30); |
| 1698 | |
| 1699 | |
| 1700 | // ************************ BYTE 3 => 30:23 ************************** |
| 1701 | |
| 1702 | assign b3_nand_74 = ~(clth[30] & clth[29] & clth[28] & clth[27]); |
| 1703 | assign b3_nand_30 = ~(clth[26] & clth[25] & clth[24] & clth[23]); |
| 1704 | |
| 1705 | assign b3_ones = ~(b3_nand_74 | b3_nand_30); |
| 1706 | assign b3_ones_ = ~b3_ones; |
| 1707 | |
| 1708 | assign b3_cnt1h[0] = ( clth[30] & ~clth[29] ) | |
| 1709 | ( clth[30] & clth[28] & ~clth[27]); |
| 1710 | |
| 1711 | assign b3_cnt1h[1] = ( clth[30] & clth[29] & ~clth[28] ) | |
| 1712 | ( clth[30] & clth[29] & ~clth[27]); |
| 1713 | |
| 1714 | assign b3_cnt1l[0] = ( clth[26] & ~clth[25] ) | |
| 1715 | ( clth[26] & clth[24] & ~clth[23]); |
| 1716 | |
| 1717 | assign b3_cnt1l[1] = ( clth[26] & clth[25] & ~clth[24] ) | |
| 1718 | ( clth[26] & clth[25] & ~clth[23]); |
| 1719 | |
| 1720 | assign b3_cnt1[0] = ( b3_nand_74 & b3_cnt1h[0]) | |
| 1721 | (~b3_nand_74 & b3_cnt1l[0]); |
| 1722 | |
| 1723 | assign b3_cnt1[1] = ( b3_nand_74 & b3_cnt1h[1]) | |
| 1724 | (~b3_nand_74 & b3_cnt1l[1]); |
| 1725 | |
| 1726 | assign b3_cnt1[2] = (~b3_nand_74 & b3_nand_30); |
| 1727 | |
| 1728 | |
| 1729 | // ************************ BYTE 2 => 22:15 ************************** |
| 1730 | |
| 1731 | assign b2_nand_74 = ~(clth[22] & clth[21] & clth[20] & clth[19]); |
| 1732 | assign b2_nand_30 = ~(clth[18] & clth[17] & clth[16] & clth[15]); |
| 1733 | |
| 1734 | assign b2_ones = ~(b2_nand_74 | b2_nand_30); |
| 1735 | assign b2_ones_ = ~b2_ones; |
| 1736 | |
| 1737 | assign b2_cnt1h[0] = ( clth[22] & ~clth[21] ) | |
| 1738 | ( clth[22] & clth[20] & ~clth[19]); |
| 1739 | |
| 1740 | assign b2_cnt1h[1] = ( clth[22] & clth[21] & ~clth[20] ) | |
| 1741 | ( clth[22] & clth[21] & ~clth[19]); |
| 1742 | |
| 1743 | assign b2_cnt1l[0] = ( clth[18] & ~clth[17] ) | |
| 1744 | ( clth[18] & clth[16] & ~clth[15]); |
| 1745 | |
| 1746 | assign b2_cnt1l[1] = ( clth[18] & clth[17] & ~clth[16] ) | |
| 1747 | ( clth[18] & clth[17] & ~clth[15]); |
| 1748 | |
| 1749 | assign b2_cnt1[0] = ( b2_nand_74 & b2_cnt1h[0]) | |
| 1750 | (~b2_nand_74 & b2_cnt1l[0]); |
| 1751 | |
| 1752 | assign b2_cnt1[1] = ( b2_nand_74 & b2_cnt1h[1]) | |
| 1753 | (~b2_nand_74 & b2_cnt1l[1]); |
| 1754 | |
| 1755 | assign b2_cnt1[2] = (~b2_nand_74 & b2_nand_30); |
| 1756 | |
| 1757 | |
| 1758 | // ************************ BYTE 1 => 14:07 ************************** |
| 1759 | |
| 1760 | assign b1_nand_74 = ~(clth[14] & clth[13] & clth[12] & clth[11]); |
| 1761 | assign b1_nand_30 = ~(clth[10] & clth[9] & clth[8] & clth[7]); |
| 1762 | |
| 1763 | assign b1_ones = ~(b1_nand_74 | b1_nand_30); |
| 1764 | assign b1_ones_ = ~b1_ones; |
| 1765 | |
| 1766 | assign b1_cnt1h[0] = ( clth[14] & ~clth[13] ) | |
| 1767 | ( clth[14] & clth[12] & ~clth[11]); |
| 1768 | |
| 1769 | assign b1_cnt1h[1] = ( clth[14] & clth[13] & ~clth[12] ) | |
| 1770 | ( clth[14] & clth[13] & ~clth[11]); |
| 1771 | |
| 1772 | assign b1_cnt1l[0] = ( clth[10] & ~clth[9] ) | |
| 1773 | ( clth[10] & clth[8] & ~clth[7]); |
| 1774 | |
| 1775 | assign b1_cnt1l[1] = ( clth[10] & clth[9] & ~clth[8] ) | |
| 1776 | ( clth[10] & clth[9] & ~clth[7]); |
| 1777 | |
| 1778 | assign b1_cnt1[0] = ( b1_nand_74 & b1_cnt1h[0]) | |
| 1779 | (~b1_nand_74 & b1_cnt1l[0]); |
| 1780 | |
| 1781 | assign b1_cnt1[1] = ( b1_nand_74 & b1_cnt1h[1]) | |
| 1782 | (~b1_nand_74 & b1_cnt1l[1]); |
| 1783 | |
| 1784 | assign b1_cnt1[2] = (~b1_nand_74 & b1_nand_30); |
| 1785 | |
| 1786 | |
| 1787 | // ************************ BYTE 0 => 06:00 ************************** |
| 1788 | |
| 1789 | // Note : Byte 0 is unique since cnt1[2:0] must be 3'b111 for byte 'all ones' case! |
| 1790 | // 64'b1111111111111111111111111111111111111111111111111111111110??????: cntl1[6:0] = 7'b0111000; |
| 1791 | // 64'b11111111111111111111111111111111111111111111111111111111110?????: cntl1[6:0] = 7'b0111001; |
| 1792 | // 64'b111111111111111111111111111111111111111111111111111111111110????: cntl1[6:0] = 7'b0111010; |
| 1793 | // 64'b1111111111111111111111111111111111111111111111111111111111110???: cntl1[6:0] = 7'b0111011; |
| 1794 | // 64'b11111111111111111111111111111111111111111111111111111111111110??: cntl1[6:0] = 7'b0111100; |
| 1795 | // 64'b111111111111111111111111111111111111111111111111111111111111110?: cntl1[6:0] = 7'b0111101; |
| 1796 | // 64'b1111111111111111111111111111111111111111111111111111111111111110: cntl1[6:0] = 7'b0111110; |
| 1797 | // 64'b1111111111111111111111111111111111111111111111111111111111111111: cntl1[6:0] = 7'b0111111; |
| 1798 | |
| 1799 | |
| 1800 | assign b0_nand_74 = ~(clth[6] & clth[5] & clth[4] & clth[3]); |
| 1801 | |
| 1802 | assign b0_cnt1h[0] = ( clth[6] & ~clth[5] ) | |
| 1803 | ( clth[6] & clth[4] & ~clth[3]); |
| 1804 | |
| 1805 | assign b0_cnt1h[1] = ( clth[6] & clth[5] & ~clth[4] ) | |
| 1806 | ( clth[6] & clth[5] & ~clth[3]); |
| 1807 | |
| 1808 | assign b0_cnt1l[0] = ( clth[2] & ~clth[1] ) | |
| 1809 | ( clth[2] & clth[0] ); |
| 1810 | |
| 1811 | assign b0_cnt1l[1] = ( clth[2] & clth[1] ); |
| 1812 | |
| 1813 | assign b0_cnt1[0] = ( b0_nand_74 & b0_cnt1h[0]) | |
| 1814 | (~b0_nand_74 & b0_cnt1l[0]); |
| 1815 | |
| 1816 | assign b0_cnt1[1] = ( b0_nand_74 & b0_cnt1h[1]) | |
| 1817 | (~b0_nand_74 & b0_cnt1l[1]); |
| 1818 | |
| 1819 | assign b0_cnt1[2] = (~b0_nand_74 ); |
| 1820 | |
| 1821 | |
| 1822 | |
| 1823 | // ************************ Global CNTL1 ************************** |
| 1824 | |
| 1825 | assign b3_1sel = b3_ones_ ; |
| 1826 | assign b2_1sel = ~b3_ones_ & b2_ones_ ; |
| 1827 | assign b1_1sel = ~b3_ones_ & ~b2_ones_ & b1_ones_; |
| 1828 | assign b0_1sel = ~b3_ones_ & ~b2_ones_ & ~b1_ones_; |
| 1829 | |
| 1830 | assign cntl1l[4:0] = ({5{b3_1sel}} & {2'b00,b3_cnt1[2:0]}) | |
| 1831 | ({5{b2_1sel}} & {2'b01,b2_cnt1[2:0]}) | |
| 1832 | ({5{b1_1sel}} & {2'b10,b1_cnt1[2:0]}) | |
| 1833 | ({5{b0_1sel}} & {2'b11,b0_cnt1[2:0]}); |
| 1834 | |
| 1835 | |
| 1836 | assign b7_1sel = b7_ones_ ; |
| 1837 | assign b6_1sel = ~b7_ones_ & b6_ones_ ; |
| 1838 | assign b5_1sel = ~b7_ones_ & ~b6_ones_ & b5_ones_; |
| 1839 | assign b4_1sel = ~b7_ones_ & ~b6_ones_ & ~b5_ones_; |
| 1840 | |
| 1841 | assign cntl1h[4:0] = ({5{b7_1sel}} & {2'b00,b7_cnt1[2:0]}) | |
| 1842 | ({5{b6_1sel}} & {2'b01,b6_cnt1[2:0]}) | |
| 1843 | ({5{b5_1sel}} & {2'b10,b5_cnt1[2:0]}) | |
| 1844 | ({5{b4_1sel}} & {2'b11,b4_cnt1[2:0]}); |
| 1845 | |
| 1846 | |
| 1847 | |
| 1848 | assign cntl1_selh = b7_ones_ | b6_ones_ | b5_ones_ | b4_ones_; |
| 1849 | |
| 1850 | assign cntl1[5:0] = ({6{ cntl1_selh}} & {1'b0, cntl1h[4:0]}) | |
| 1851 | ({6{~cntl1_selh}} & {1'b1, cntl1l[4:0]}); |
| 1852 | |
| 1853 | |
| 1854 | // * * * * * * * * * * * * End : Integer CNTL1 * * * * * * * * * * * * * |
| 1855 | |
| 1856 | |
| 1857 | assign xsht_amt_sel10 = ~(fdd_pe_clth[63] & control_lth[0]) & fdc_pe_cycle[1]; |
| 1858 | assign xsht_amt_sel11 = (fdd_pe_clth[63] & control_lth[0]) & fdc_pe_cycle[1]; |
| 1859 | assign xsht_amt_sel20 = ~(fdd_pe_clth[63] & control_lth[0]) & fdc_pe_cycle[2]; |
| 1860 | assign xsht_amt_sel21 = (fdd_pe_clth[63] & control_lth[0]) & fdc_pe_cycle[2]; |
| 1861 | |
| 1862 | assign xsht_amt_in[7:0] = ({8{engine_on }} & 8'b11111101 ) | |
| 1863 | ({8{xsht_amt_sel10}} & {1'b0 , cntl0[6:0]}) | |
| 1864 | ({8{xsht_amt_sel11}} & {2'b00, cntl1[5:0]}) | |
| 1865 | ({8{xsht_amt_sel20}} & {1'b1 ,~cntl0[6:0]}) | |
| 1866 | ({8{xsht_amt_sel21}} & {2'b11,~cntl1[5:0]}); |
| 1867 | |
| 1868 | |
| 1869 | assign pe_ndq[7:0] = pe_hamt_lth[7:0] + pe_xsht_amt[7:0] + 8'b0000_0001; |
| 1870 | |
| 1871 | assign pe_hamt_in[7:0] = ({8{ pe_hmux_sel[0]}} & 8'b00110100) | // FLT DP |
| 1872 | ({8{ pe_hmux_sel[1]}} & 8'b00010111) | // FLT SP |
| 1873 | ({8{fdc_pe_smux_sel[0]}} & 8'b00000001) | // INT neg B correction |
| 1874 | ({8{ pe_hmux_sel[2]}} & pe_ndq[7:0]); // SRT loop counter |
| 1875 | |
| 1876 | |
| 1877 | |
| 1878 | fgu_fdc_ctl_msff_ctl_macro__width_8 xsht_lth ( |
| 1879 | .scan_in(xsht_lth_scanin), |
| 1880 | .scan_out(xsht_lth_scanout), |
| 1881 | .l1clk( l1clk_pm1 ), |
| 1882 | .din ( xsht_amt_in[7:0] ), |
| 1883 | .dout ( pe_xsht_amt[7:0] ), |
| 1884 | .siclk(siclk), |
| 1885 | .soclk(soclk)); |
| 1886 | |
| 1887 | |
| 1888 | fgu_fdc_ctl_msff_ctl_macro__width_8 hamt_lth ( |
| 1889 | .scan_in(hamt_lth_scanin), |
| 1890 | .scan_out(hamt_lth_scanout), |
| 1891 | .l1clk( l1clk_pm1 ), |
| 1892 | .din ( pe_hamt_in[7:0] ), |
| 1893 | .dout ( pe_hamt_lth[7:0] ), |
| 1894 | .siclk(siclk), |
| 1895 | .soclk(soclk)); |
| 1896 | |
| 1897 | |
| 1898 | assign xsht_ctl_in[5:0] = ({6{xsht_amt_sel10}} & cntl0[5:0]) | |
| 1899 | ({6{xsht_amt_sel11}} & cntl1[5:0]) | |
| 1900 | ({6{xsht_amt_sel20}} & cntl0[5:0]) | |
| 1901 | ({6{xsht_amt_sel21}} & cntl1[5:0]); |
| 1902 | |
| 1903 | fgu_fdc_ctl_msff_ctl_macro__width_6 xcntl_lth ( |
| 1904 | .scan_in(xcntl_lth_scanin), |
| 1905 | .scan_out(xcntl_lth_scanout), |
| 1906 | .l1clk( l1clk_pm1 ), |
| 1907 | .din ( xsht_ctl_in[5:0] ), |
| 1908 | .dout ( fdc_pe_xsht_ctl[5:0] ), |
| 1909 | .siclk(siclk), |
| 1910 | .soclk(soclk)); |
| 1911 | |
| 1912 | |
| 1913 | |
| 1914 | |
| 1915 | // *** Floating Point Rounding *** |
| 1916 | |
| 1917 | |
| 1918 | assign engine_valid_fx1 = fac_div_valid_fx1 & ~fac_divq_valid_fx1; |
| 1919 | assign engine_valid_fx2 = (queue_valid_lth_fx2 & (fac_div_valid_fx1 & fac_divq_valid_fx1)) | engine_valid_lth_fx2; |
| 1920 | assign engine_valid_fx3 = (queue_valid_lth_fx3 & (fac_div_valid_fx1 & fac_divq_valid_fx1)) | engine_valid_lth_fx3; |
| 1921 | |
| 1922 | assign queue_valid_fx1 = ~fac_div_valid_fx1 & fac_divq_valid_fx1; |
| 1923 | assign queue_valid_fx2 = queue_valid_lth_fx2 & ~(fac_div_valid_fx1 & fac_divq_valid_fx1); |
| 1924 | //sign queue_valid_fx3 = queue_valid_lth_fx3 & ~(fac_div_valid_fx1 & fac_divq_valid_fx1); |
| 1925 | |
| 1926 | assign q2e_fx3p = (fac_div_valid_fx1 & fac_divq_valid_fx1) & ~queue_valid_lth_fx2 & ~queue_valid_lth_fx3; |
| 1927 | |
| 1928 | |
| 1929 | fgu_fdc_ctl_msff_ctl_macro__width_4 xrnd_vld_lth ( |
| 1930 | .scan_in(xrnd_vld_lth_scanin), |
| 1931 | .scan_out(xrnd_vld_lth_scanout), |
| 1932 | .l1clk( l1clk_pm1 ), |
| 1933 | .din ({engine_valid_fx1 ,engine_valid_fx2 ,queue_valid_fx1 ,queue_valid_fx2} ), |
| 1934 | .dout ({engine_valid_lth_fx2,engine_valid_lth_fx3,queue_valid_lth_fx2,queue_valid_lth_fx3}), |
| 1935 | .siclk(siclk), |
| 1936 | .soclk(soclk)); |
| 1937 | |
| 1938 | |
| 1939 | // SPARC v9 : pg 44 |
| 1940 | // |
| 1941 | // RD | Round toward |
| 1942 | // --- | ------------ |
| 1943 | // 00 | Nearest (even if tie) |
| 1944 | // 01 | 0 |
| 1945 | // 10 | +INF |
| 1946 | // 11 | -INF |
| 1947 | |
| 1948 | |
| 1949 | assign eround_mode_in[1:0]= ({2{ engine_valid_fx3 }} & fpc_rd_mode_fx3[1:0]) | |
| 1950 | ({2{ q2e_fx3p}} & qround_mode_lth[1:0]) | |
| 1951 | ({2{~engine_valid_fx3 & ~q2e_fx3p}} & eround_mode_lth[1:0]); |
| 1952 | |
| 1953 | assign e_emin_in = ( engine_valid_fx3 & fpc_emin_fx3 ) | |
| 1954 | ( q2e_fx3p & q_emin_lth ) | |
| 1955 | ( ~engine_valid_fx3 & ~q2e_fx3p & fdc_emin_lth ); |
| 1956 | |
| 1957 | |
| 1958 | assign qround_mode_in[1:0]= ({2{ queue_valid_lth_fx3}} & fpc_rd_mode_fx3[1:0]) | |
| 1959 | ({2{~queue_valid_lth_fx3}} & qround_mode_lth[1:0]); |
| 1960 | |
| 1961 | assign q_emin_in = ( queue_valid_lth_fx3 & fpc_emin_fx3 ) | |
| 1962 | ( ~queue_valid_lth_fx3 & q_emin_lth ); |
| 1963 | |
| 1964 | |
| 1965 | assign float_sign_in = ( fac_div_valid_fx1 & ~fac_divq_valid_fx1 & incoming_sign_fx1 ) | |
| 1966 | ( fac_div_valid_fx1 & fac_divq_valid_fx1 & qcontrol_fx1[6] ) | |
| 1967 | ( ~fac_div_valid_fx1 & float_sign_lth ); |
| 1968 | |
| 1969 | assign fdc_dec_exp_early = fdc_pte_cycle[0] & ~control_lth[2] & ~fdd_result[63] & ~flt_sqrte_kill_dec; |
| 1970 | |
| 1971 | assign inexact_in = fdc_pte_cycle[0] & ~control_lth[2] & (final_sticky | final_guard); |
| 1972 | |
| 1973 | |
| 1974 | fgu_fdc_ctl_msff_ctl_macro__width_10 xrnd_lth ( |
| 1975 | .scan_in(xrnd_lth_scanin), |
| 1976 | .scan_out(xrnd_lth_scanout), |
| 1977 | .l1clk( l1clk_pm1 ), |
| 1978 | .din ({float_sign_in , eround_mode_in[1:0] , qround_mode_in[1:0] , fdd_cla_zero64_ , sticky_pte1 , inexact_in , e_emin_in , q_emin_in }), |
| 1979 | .dout ({float_sign_lth , eround_mode_lth[1:0] , qround_mode_lth[1:0] , sticky_pte1 , sticky_pte0 , fdc_flt_inexact , fdc_emin_lth , q_emin_lth}), |
| 1980 | .siclk(siclk), |
| 1981 | .soclk(soclk)); |
| 1982 | |
| 1983 | |
| 1984 | assign fdc_flt_round[1] = ~control_lth[2] & ~control_lth[1]; // SP |
| 1985 | assign fdc_flt_round[0] = ~control_lth[2] & control_lth[1]; // DP |
| 1986 | |
| 1987 | |
| 1988 | assign flt_shift_sel_ = fdd_result[63] | fdc_emin_lth; |
| 1989 | |
| 1990 | |
| 1991 | assign final_sticky = ( control_lth[1] & flt_shift_sel_ & (fdd_result[9] | sticky_pte0)) | // DP "1." |
| 1992 | ( control_lth[1] & ~flt_shift_sel_ & ( sticky_pte0)) | // DP "0." |
| 1993 | (~control_lth[1] & flt_shift_sel_ & (fdd_result[38] | sticky_pte0)) | // SP "1." |
| 1994 | (~control_lth[1] & ~flt_shift_sel_ & ( sticky_pte0)); // SP "0." |
| 1995 | |
| 1996 | assign final_guard = ( control_lth[1] & flt_shift_sel_ & fdd_result[10] ) | // DP "1." |
| 1997 | ( control_lth[1] & ~flt_shift_sel_ & fdd_result[9] ) | // DP "0." |
| 1998 | (~control_lth[1] & flt_shift_sel_ & fdd_result[39] ) | // SP "1." |
| 1999 | (~control_lth[1] & ~flt_shift_sel_ & fdd_result[38] ); // SP "0." |
| 2000 | |
| 2001 | assign final_lsb = ( control_lth[1] & flt_shift_sel_ & fdd_result[11] ) | // DP "1." |
| 2002 | ( control_lth[1] & ~flt_shift_sel_ & fdd_result[10] ) | // DP "0." |
| 2003 | (~control_lth[1] & flt_shift_sel_ & fdd_result[40] ) | // SP "1." |
| 2004 | (~control_lth[1] & ~flt_shift_sel_ & fdd_result[39] ); // SP "0." |
| 2005 | |
| 2006 | |
| 2007 | assign flt_rnd00_en = ~control_lth[2] & (eround_mode_lth[1:0] == 2'b00); |
| 2008 | assign flt_rnd1x_en = (~control_lth[2] & (eround_mode_lth[1:0] == 2'b10) & ~float_sign_lth) | |
| 2009 | (~control_lth[2] & (eround_mode_lth[1:0] == 2'b11) & float_sign_lth); |
| 2010 | |
| 2011 | assign fdc_flt_increment = ( flt_rnd00_en & final_guard & final_sticky ) | |
| 2012 | ( flt_rnd00_en & final_guard & final_lsb) | |
| 2013 | ( flt_rnd1x_en & final_guard ) | |
| 2014 | ( flt_rnd1x_en & final_sticky ); |
| 2015 | |
| 2016 | |
| 2017 | |
| 2018 | |
| 2019 | // *** Floating Point Square Root Special Case *** |
| 2020 | |
| 2021 | // For an odd exponent Square Root, the mantissa is shifted one bit position right. |
| 2022 | // In most cases, the final result will end up in the form of "0.1". We then normalize |
| 2023 | // this result and decrement the result exponent. However, if the mantissa is all ONES, |
| 2024 | // this does not hold. If you take the square root of 0.1111111...1 (after the 1-bit shift), |
| 2025 | // the result will move closer to 1.00000000. In the Round to +INF only, |
| 2026 | // the rounded result will be 1.000000 and no decrementing of the exponent will occur. |
| 2027 | |
| 2028 | // 1=DP , 0=SP SQRTE |
| 2029 | assign fsqrt_fract_all_ones = (~fac_div_control_fx1[1] & fac_div_control_fx1[3] & fpf_hi_bof_fx1 ) | |
| 2030 | ( fac_div_control_fx1[1] & fac_div_control_fx1[3] & fpf_hi_bof_fx1 & fpf_lo_bof_fx1); |
| 2031 | |
| 2032 | assign fsqrt_special_in = ( fac_div_valid_fx1 & ~fac_divq_valid_fx1 & fsqrt_fract_all_ones) | |
| 2033 | ( fac_div_valid_fx1 & fac_divq_valid_fx1 & qcontrol_fx1[7] ) | |
| 2034 | (~fac_div_valid_fx1 & fsqrt_special_lth ); |
| 2035 | |
| 2036 | fgu_fdc_ctl_msff_ctl_macro__width_1 spec_sqrt_lth ( |
| 2037 | .scan_in(spec_sqrt_lth_scanin), |
| 2038 | .scan_out(spec_sqrt_lth_scanout), |
| 2039 | .l1clk( l1clk_pm1 ), |
| 2040 | .din ( fsqrt_special_in ), |
| 2041 | .dout ( fsqrt_special_lth ), |
| 2042 | .siclk(siclk), |
| 2043 | .soclk(soclk)); |
| 2044 | |
| 2045 | assign flt_sqrte_kill_dec = fsqrt_special_lth & (eround_mode_lth[1:0] == 2'b10); // +inf |
| 2046 | |
| 2047 | |
| 2048 | |
| 2049 | |
| 2050 | // *** FDX Custom *** |
| 2051 | |
| 2052 | |
| 2053 | assign cla_64 = fdd_fdx_din0 ^ fdd_fdx_din1 ^ fdd_fdx_cin64; |
| 2054 | |
| 2055 | assign cin_in_raw = (~fdc_asign_lth & ~fdc_bsign_lth & ~cla_64 ) | |
| 2056 | (~fdc_asign_lth & fdc_bsign_lth & cla_64 ) | |
| 2057 | ( fdc_asign_lth & ~fdc_bsign_lth & ~cla_64 & fdd_cla_zero64_) | |
| 2058 | ( fdc_asign_lth & fdc_bsign_lth & ~fdd_cla_zero64_) | |
| 2059 | ( fdc_asign_lth & fdc_bsign_lth & cla_64 ); |
| 2060 | |
| 2061 | assign fdc_fdx_cin_in = fdc_pte_cycle2 & cin_in_raw; |
| 2062 | |
| 2063 | |
| 2064 | |
| 2065 | // *** FDQ00 Custom *** |
| 2066 | |
| 2067 | assign fdq00_sum[3:0] = fdd_fdq00_10_sum[4:1]; // s0[65:62] |
| 2068 | assign fdq00_carry[3:0] = fdd_fdq00_10_carry[4:1]; // c0[65:62] |
| 2069 | |
| 2070 | assign pr00[0] = fdq00_sum[0] | fdq00_carry[0]; |
| 2071 | assign pr00[3:1] = fdq00_sum[3:1] + fdq00_carry[3:1]; |
| 2072 | |
| 2073 | assign fdc_qsel00[0] = ( pr00[3] & ~pr00[2]) | // 10.0x ; 10.1x |
| 2074 | ( pr00[3] & ~pr00[1]) | // 10.0x ; 11.0x |
| 2075 | ( pr00[3] & ~pr00[0]); // 11.10 |
| 2076 | |
| 2077 | assign fdc_qsel00[1] = ( pr00[3] & pr00[2] & pr00[1] & pr00[0]) | // 11.11 |
| 2078 | (~pr00[3] & ~pr00[2] & ~pr00[1] & ~pr00[0]); // 00.00 |
| 2079 | |
| 2080 | |
| 2081 | assign fdc_qsel00[2] = (~pr00[3] & pr00[2]) | // 01.1x ; 01.0x |
| 2082 | (~pr00[3] & pr00[1]) | // 01.1x ; 00.1x |
| 2083 | (~pr00[3] & pr00[0]); // 00.01 |
| 2084 | |
| 2085 | |
| 2086 | // *** FDQ1p Custom *** |
| 2087 | |
| 2088 | assign pr1p[0] = fdd_fdq1p_sum[0] | fdd_fdq1p_carry[0]; |
| 2089 | assign pr1p[3:1] = fdd_fdq1p_sum[3:1] + fdd_fdq1p_carry[3:1]; |
| 2090 | |
| 2091 | assign qsel1p[0] = ( pr1p[3] & ~pr1p[2]) | // 10.0x ; 10.1x |
| 2092 | ( pr1p[3] & ~pr1p[1]) | // 10.0x ; 11.0x |
| 2093 | ( pr1p[3] & ~pr1p[0]); // 11.10 |
| 2094 | |
| 2095 | assign qsel1p[1] = ( pr1p[3] & pr1p[2] & pr1p[1] & pr1p[0]) | // 11.11 |
| 2096 | (~pr1p[3] & ~pr1p[2] & ~pr1p[1] & ~pr1p[0]); // 00.00 |
| 2097 | |
| 2098 | |
| 2099 | assign qsel1p[2] = (~pr1p[3] & pr1p[2]) | // 01.1x ; 01.0x |
| 2100 | (~pr1p[3] & pr1p[1]) | // 01.1x ; 00.1x |
| 2101 | (~pr1p[3] & pr1p[0]); // 00.01 |
| 2102 | |
| 2103 | |
| 2104 | // *** FDQ10 Custom *** |
| 2105 | |
| 2106 | assign fdq10_sum[3:0] = fdd_fdq00_10_sum[3:0]; // s0[64:61] |
| 2107 | assign fdq10_carry[3:0] = fdd_fdq00_10_carry[3:0]; // c0[64:61] |
| 2108 | |
| 2109 | assign pr10[0] = fdq10_sum[0] | fdq10_carry[0]; |
| 2110 | assign pr10[3:1] = fdq10_sum[3:1] + fdq10_carry[3:1]; |
| 2111 | |
| 2112 | assign qsel10[0] = ( pr10[3] & ~pr10[2]) | // 10.0x ; 10.1x |
| 2113 | ( pr10[3] & ~pr10[1]) | // 10.0x ; 11.0x |
| 2114 | ( pr10[3] & ~pr10[0]); // 11.10 |
| 2115 | |
| 2116 | assign qsel10[1] = ( pr10[3] & pr10[2] & pr10[1] & pr10[0]) | // 11.11 |
| 2117 | (~pr10[3] & ~pr10[2] & ~pr10[1] & ~pr10[0]); // 00.00 |
| 2118 | |
| 2119 | |
| 2120 | assign qsel10[2] = (~pr10[3] & pr10[2]) | // 01.1x ; 01.0x |
| 2121 | (~pr10[3] & pr10[1]) | // 01.1x ; 00.1x |
| 2122 | (~pr10[3] & pr10[0]); // 00.01 |
| 2123 | |
| 2124 | |
| 2125 | // *** FDQ1n Custom *** |
| 2126 | |
| 2127 | assign pr1n[0] = fdd_fdq1n_sum[0] | fdd_fdq1n_carry[0]; |
| 2128 | assign pr1n[3:1] = fdd_fdq1n_sum[3:1] + fdd_fdq1n_carry[3:1]; |
| 2129 | |
| 2130 | assign qsel1n[0] = ( pr1n[3] & ~pr1n[2]) | // 10.0x ; 10.1x |
| 2131 | ( pr1n[3] & ~pr1n[1]) | // 10.0x ; 11.0x |
| 2132 | ( pr1n[3] & ~pr1n[0]); // 11.10 |
| 2133 | |
| 2134 | assign qsel1n[1] = ( pr1n[3] & pr1n[2] & pr1n[1] & pr1n[0]) | // 11.11 |
| 2135 | (~pr1n[3] & ~pr1n[2] & ~pr1n[1] & ~pr1n[0]); // 00.00 |
| 2136 | |
| 2137 | |
| 2138 | assign qsel1n[2] = (~pr1n[3] & pr1n[2]) | // 01.1x ; 01.0x |
| 2139 | (~pr1n[3] & pr1n[1]) | // 01.1x ; 00.1x |
| 2140 | (~pr1n[3] & pr1n[0]); // 00.01 |
| 2141 | |
| 2142 | |
| 2143 | |
| 2144 | assign engine_start = fac_div_valid_fx1 | fdc_pe_cycle3; |
| 2145 | |
| 2146 | assign fdc_qsel1[2:0] = ({3{~engine_start & fdc_qsel00[0]}} & qsel1p[2:0]) | |
| 2147 | ({3{~engine_start & fdc_qsel00[1]}} & qsel10[2:0]) | |
| 2148 | ({3{~engine_start & fdc_qsel00[2]}} & qsel1n[2:0]); |
| 2149 | |
| 2150 | |
| 2151 | // *** Misc Logic from FDD *** |
| 2152 | |
| 2153 | assign fdc_q_in[1] = ( ~engine_start & fdc_qsel00[0] & fdc_bsign_lth ) | |
| 2154 | ( ~engine_start & fdc_qsel00[2] & fdc_bsign_lth_); |
| 2155 | |
| 2156 | assign fdc_qm1_in[1] = ( ~engine_start & fdc_qsel00[0] & fdc_bsign_lth_) | |
| 2157 | ( ~engine_start & fdc_qsel00[2] & fdc_bsign_lth ); |
| 2158 | |
| 2159 | assign fdc_q_in[0] = ( fdc_qsel1[0] & fdc_bsign_lth ) | |
| 2160 | ( fdc_qsel1[2] & fdc_bsign_lth_); |
| 2161 | |
| 2162 | assign fdc_qm1_in[0] = ( fdc_qsel1[0] & fdc_bsign_lth_) | |
| 2163 | ( fdc_qsel1[2] & fdc_bsign_lth ); |
| 2164 | |
| 2165 | |
| 2166 | supply0 vss; |
| 2167 | supply1 vdd; |
| 2168 | |
| 2169 | |
| 2170 | // fixscan start: |
| 2171 | assign spares_scanin = scan_in ; |
| 2172 | assign qdata_lth_scanin = spares_scanout ; |
| 2173 | assign cntl_lth_scanin = qdata_lth_scanout ; |
| 2174 | assign ovlf_lth_scanin = cntl_lth_scanout ; |
| 2175 | assign stall_lth_scanin = ovlf_lth_scanout ; |
| 2176 | assign data_lth_scanin = stall_lth_scanout ; |
| 2177 | assign xsht_lth_scanin = data_lth_scanout ; |
| 2178 | assign hamt_lth_scanin = xsht_lth_scanout ; |
| 2179 | assign xcntl_lth_scanin = hamt_lth_scanout ; |
| 2180 | assign xrnd_vld_lth_scanin = xcntl_lth_scanout ; |
| 2181 | assign xrnd_lth_scanin = xrnd_vld_lth_scanout ; |
| 2182 | assign spec_sqrt_lth_scanin = xrnd_lth_scanout ; |
| 2183 | assign scan_out = spec_sqrt_lth_scanout ; |
| 2184 | // fixscan end: |
| 2185 | endmodule |
| 2186 | |
| 2187 | |
| 2188 | |
| 2189 | |
| 2190 | |
| 2191 | |
| 2192 | // any PARAMS parms go into naming of macro |
| 2193 | |
| 2194 | module fgu_fdc_ctl_l1clkhdr_ctl_macro ( |
| 2195 | l2clk, |
| 2196 | l1en, |
| 2197 | pce_ov, |
| 2198 | stop, |
| 2199 | se, |
| 2200 | l1clk); |
| 2201 | |
| 2202 | |
| 2203 | input l2clk; |
| 2204 | input l1en; |
| 2205 | input pce_ov; |
| 2206 | input stop; |
| 2207 | input se; |
| 2208 | output l1clk; |
| 2209 | |
| 2210 | |
| 2211 | |
| 2212 | |
| 2213 | |
| 2214 | cl_sc1_l1hdr_8x c_0 ( |
| 2215 | |
| 2216 | |
| 2217 | .l2clk(l2clk), |
| 2218 | .pce(l1en), |
| 2219 | .l1clk(l1clk), |
| 2220 | .se(se), |
| 2221 | .pce_ov(pce_ov), |
| 2222 | .stop(stop) |
| 2223 | ); |
| 2224 | |
| 2225 | |
| 2226 | |
| 2227 | endmodule |
| 2228 | |
| 2229 | |
| 2230 | |
| 2231 | |
| 2232 | |
| 2233 | |
| 2234 | |
| 2235 | |
| 2236 | |
| 2237 | // Description: Spare gate macro for control blocks |
| 2238 | // |
| 2239 | // Param num controls the number of times the macro is added |
| 2240 | // flops=0 can be used to use only combination spare logic |
| 2241 | |
| 2242 | |
| 2243 | module fgu_fdc_ctl_spare_ctl_macro__num_3 ( |
| 2244 | l1clk, |
| 2245 | scan_in, |
| 2246 | siclk, |
| 2247 | soclk, |
| 2248 | scan_out); |
| 2249 | wire si_0; |
| 2250 | wire so_0; |
| 2251 | wire spare0_flop_unused; |
| 2252 | wire spare0_buf_32x_unused; |
| 2253 | wire spare0_nand3_8x_unused; |
| 2254 | wire spare0_inv_8x_unused; |
| 2255 | wire spare0_aoi22_4x_unused; |
| 2256 | wire spare0_buf_8x_unused; |
| 2257 | wire spare0_oai22_4x_unused; |
| 2258 | wire spare0_inv_16x_unused; |
| 2259 | wire spare0_nand2_16x_unused; |
| 2260 | wire spare0_nor3_4x_unused; |
| 2261 | wire spare0_nand2_8x_unused; |
| 2262 | wire spare0_buf_16x_unused; |
| 2263 | wire spare0_nor2_16x_unused; |
| 2264 | wire spare0_inv_32x_unused; |
| 2265 | wire si_1; |
| 2266 | wire so_1; |
| 2267 | wire spare1_flop_unused; |
| 2268 | wire spare1_buf_32x_unused; |
| 2269 | wire spare1_nand3_8x_unused; |
| 2270 | wire spare1_inv_8x_unused; |
| 2271 | wire spare1_aoi22_4x_unused; |
| 2272 | wire spare1_buf_8x_unused; |
| 2273 | wire spare1_oai22_4x_unused; |
| 2274 | wire spare1_inv_16x_unused; |
| 2275 | wire spare1_nand2_16x_unused; |
| 2276 | wire spare1_nor3_4x_unused; |
| 2277 | wire spare1_nand2_8x_unused; |
| 2278 | wire spare1_buf_16x_unused; |
| 2279 | wire spare1_nor2_16x_unused; |
| 2280 | wire spare1_inv_32x_unused; |
| 2281 | wire si_2; |
| 2282 | wire so_2; |
| 2283 | wire spare2_flop_unused; |
| 2284 | wire spare2_buf_32x_unused; |
| 2285 | wire spare2_nand3_8x_unused; |
| 2286 | wire spare2_inv_8x_unused; |
| 2287 | wire spare2_aoi22_4x_unused; |
| 2288 | wire spare2_buf_8x_unused; |
| 2289 | wire spare2_oai22_4x_unused; |
| 2290 | wire spare2_inv_16x_unused; |
| 2291 | wire spare2_nand2_16x_unused; |
| 2292 | wire spare2_nor3_4x_unused; |
| 2293 | wire spare2_nand2_8x_unused; |
| 2294 | wire spare2_buf_16x_unused; |
| 2295 | wire spare2_nor2_16x_unused; |
| 2296 | wire spare2_inv_32x_unused; |
| 2297 | |
| 2298 | |
| 2299 | input l1clk; |
| 2300 | input scan_in; |
| 2301 | input siclk; |
| 2302 | input soclk; |
| 2303 | output scan_out; |
| 2304 | |
| 2305 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 2306 | .siclk(siclk), |
| 2307 | .soclk(soclk), |
| 2308 | .si(si_0), |
| 2309 | .so(so_0), |
| 2310 | .d(1'b0), |
| 2311 | .q(spare0_flop_unused)); |
| 2312 | assign si_0 = scan_in; |
| 2313 | |
| 2314 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 2315 | .out(spare0_buf_32x_unused)); |
| 2316 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 2317 | .in1(1'b1), |
| 2318 | .in2(1'b1), |
| 2319 | .out(spare0_nand3_8x_unused)); |
| 2320 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 2321 | .out(spare0_inv_8x_unused)); |
| 2322 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 2323 | .in01(1'b1), |
| 2324 | .in10(1'b1), |
| 2325 | .in11(1'b1), |
| 2326 | .out(spare0_aoi22_4x_unused)); |
| 2327 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 2328 | .out(spare0_buf_8x_unused)); |
| 2329 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 2330 | .in01(1'b1), |
| 2331 | .in10(1'b1), |
| 2332 | .in11(1'b1), |
| 2333 | .out(spare0_oai22_4x_unused)); |
| 2334 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 2335 | .out(spare0_inv_16x_unused)); |
| 2336 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 2337 | .in1(1'b1), |
| 2338 | .out(spare0_nand2_16x_unused)); |
| 2339 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 2340 | .in1(1'b0), |
| 2341 | .in2(1'b0), |
| 2342 | .out(spare0_nor3_4x_unused)); |
| 2343 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 2344 | .in1(1'b1), |
| 2345 | .out(spare0_nand2_8x_unused)); |
| 2346 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 2347 | .out(spare0_buf_16x_unused)); |
| 2348 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 2349 | .in1(1'b0), |
| 2350 | .out(spare0_nor2_16x_unused)); |
| 2351 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 2352 | .out(spare0_inv_32x_unused)); |
| 2353 | |
| 2354 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 2355 | .siclk(siclk), |
| 2356 | .soclk(soclk), |
| 2357 | .si(si_1), |
| 2358 | .so(so_1), |
| 2359 | .d(1'b0), |
| 2360 | .q(spare1_flop_unused)); |
| 2361 | assign si_1 = so_0; |
| 2362 | |
| 2363 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 2364 | .out(spare1_buf_32x_unused)); |
| 2365 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 2366 | .in1(1'b1), |
| 2367 | .in2(1'b1), |
| 2368 | .out(spare1_nand3_8x_unused)); |
| 2369 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 2370 | .out(spare1_inv_8x_unused)); |
| 2371 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 2372 | .in01(1'b1), |
| 2373 | .in10(1'b1), |
| 2374 | .in11(1'b1), |
| 2375 | .out(spare1_aoi22_4x_unused)); |
| 2376 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 2377 | .out(spare1_buf_8x_unused)); |
| 2378 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 2379 | .in01(1'b1), |
| 2380 | .in10(1'b1), |
| 2381 | .in11(1'b1), |
| 2382 | .out(spare1_oai22_4x_unused)); |
| 2383 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 2384 | .out(spare1_inv_16x_unused)); |
| 2385 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 2386 | .in1(1'b1), |
| 2387 | .out(spare1_nand2_16x_unused)); |
| 2388 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 2389 | .in1(1'b0), |
| 2390 | .in2(1'b0), |
| 2391 | .out(spare1_nor3_4x_unused)); |
| 2392 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 2393 | .in1(1'b1), |
| 2394 | .out(spare1_nand2_8x_unused)); |
| 2395 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 2396 | .out(spare1_buf_16x_unused)); |
| 2397 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 2398 | .in1(1'b0), |
| 2399 | .out(spare1_nor2_16x_unused)); |
| 2400 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 2401 | .out(spare1_inv_32x_unused)); |
| 2402 | |
| 2403 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), |
| 2404 | .siclk(siclk), |
| 2405 | .soclk(soclk), |
| 2406 | .si(si_2), |
| 2407 | .so(so_2), |
| 2408 | .d(1'b0), |
| 2409 | .q(spare2_flop_unused)); |
| 2410 | assign si_2 = so_1; |
| 2411 | |
| 2412 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), |
| 2413 | .out(spare2_buf_32x_unused)); |
| 2414 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), |
| 2415 | .in1(1'b1), |
| 2416 | .in2(1'b1), |
| 2417 | .out(spare2_nand3_8x_unused)); |
| 2418 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), |
| 2419 | .out(spare2_inv_8x_unused)); |
| 2420 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), |
| 2421 | .in01(1'b1), |
| 2422 | .in10(1'b1), |
| 2423 | .in11(1'b1), |
| 2424 | .out(spare2_aoi22_4x_unused)); |
| 2425 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), |
| 2426 | .out(spare2_buf_8x_unused)); |
| 2427 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), |
| 2428 | .in01(1'b1), |
| 2429 | .in10(1'b1), |
| 2430 | .in11(1'b1), |
| 2431 | .out(spare2_oai22_4x_unused)); |
| 2432 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), |
| 2433 | .out(spare2_inv_16x_unused)); |
| 2434 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), |
| 2435 | .in1(1'b1), |
| 2436 | .out(spare2_nand2_16x_unused)); |
| 2437 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), |
| 2438 | .in1(1'b0), |
| 2439 | .in2(1'b0), |
| 2440 | .out(spare2_nor3_4x_unused)); |
| 2441 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), |
| 2442 | .in1(1'b1), |
| 2443 | .out(spare2_nand2_8x_unused)); |
| 2444 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), |
| 2445 | .out(spare2_buf_16x_unused)); |
| 2446 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), |
| 2447 | .in1(1'b0), |
| 2448 | .out(spare2_nor2_16x_unused)); |
| 2449 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), |
| 2450 | .out(spare2_inv_32x_unused)); |
| 2451 | assign scan_out = so_2; |
| 2452 | |
| 2453 | |
| 2454 | |
| 2455 | endmodule |
| 2456 | |
| 2457 | |
| 2458 | |
| 2459 | |
| 2460 | |
| 2461 | |
| 2462 | // any PARAMS parms go into naming of macro |
| 2463 | |
| 2464 | module fgu_fdc_ctl_msff_ctl_macro__width_8 ( |
| 2465 | din, |
| 2466 | l1clk, |
| 2467 | scan_in, |
| 2468 | siclk, |
| 2469 | soclk, |
| 2470 | dout, |
| 2471 | scan_out); |
| 2472 | wire [7:0] fdin; |
| 2473 | wire [6:0] so; |
| 2474 | |
| 2475 | input [7:0] din; |
| 2476 | input l1clk; |
| 2477 | input scan_in; |
| 2478 | |
| 2479 | |
| 2480 | input siclk; |
| 2481 | input soclk; |
| 2482 | |
| 2483 | output [7:0] dout; |
| 2484 | output scan_out; |
| 2485 | assign fdin[7:0] = din[7:0]; |
| 2486 | |
| 2487 | |
| 2488 | |
| 2489 | |
| 2490 | |
| 2491 | |
| 2492 | dff #(8) d0_0 ( |
| 2493 | .l1clk(l1clk), |
| 2494 | .siclk(siclk), |
| 2495 | .soclk(soclk), |
| 2496 | .d(fdin[7:0]), |
| 2497 | .si({scan_in,so[6:0]}), |
| 2498 | .so({so[6:0],scan_out}), |
| 2499 | .q(dout[7:0]) |
| 2500 | ); |
| 2501 | |
| 2502 | |
| 2503 | |
| 2504 | |
| 2505 | |
| 2506 | |
| 2507 | |
| 2508 | |
| 2509 | |
| 2510 | |
| 2511 | |
| 2512 | |
| 2513 | endmodule |
| 2514 | |
| 2515 | |
| 2516 | |
| 2517 | |
| 2518 | |
| 2519 | |
| 2520 | |
| 2521 | |
| 2522 | |
| 2523 | |
| 2524 | |
| 2525 | |
| 2526 | |
| 2527 | // any PARAMS parms go into naming of macro |
| 2528 | |
| 2529 | module fgu_fdc_ctl_msff_ctl_macro__width_10 ( |
| 2530 | din, |
| 2531 | l1clk, |
| 2532 | scan_in, |
| 2533 | siclk, |
| 2534 | soclk, |
| 2535 | dout, |
| 2536 | scan_out); |
| 2537 | wire [9:0] fdin; |
| 2538 | wire [8:0] so; |
| 2539 | |
| 2540 | input [9:0] din; |
| 2541 | input l1clk; |
| 2542 | input scan_in; |
| 2543 | |
| 2544 | |
| 2545 | input siclk; |
| 2546 | input soclk; |
| 2547 | |
| 2548 | output [9:0] dout; |
| 2549 | output scan_out; |
| 2550 | assign fdin[9:0] = din[9:0]; |
| 2551 | |
| 2552 | |
| 2553 | |
| 2554 | |
| 2555 | |
| 2556 | |
| 2557 | dff #(10) d0_0 ( |
| 2558 | .l1clk(l1clk), |
| 2559 | .siclk(siclk), |
| 2560 | .soclk(soclk), |
| 2561 | .d(fdin[9:0]), |
| 2562 | .si({scan_in,so[8:0]}), |
| 2563 | .so({so[8:0],scan_out}), |
| 2564 | .q(dout[9:0]) |
| 2565 | ); |
| 2566 | |
| 2567 | |
| 2568 | |
| 2569 | |
| 2570 | |
| 2571 | |
| 2572 | |
| 2573 | |
| 2574 | |
| 2575 | |
| 2576 | |
| 2577 | |
| 2578 | endmodule |
| 2579 | |
| 2580 | |
| 2581 | |
| 2582 | |
| 2583 | |
| 2584 | |
| 2585 | |
| 2586 | |
| 2587 | |
| 2588 | |
| 2589 | |
| 2590 | |
| 2591 | |
| 2592 | // any PARAMS parms go into naming of macro |
| 2593 | |
| 2594 | module fgu_fdc_ctl_msff_ctl_macro__width_4 ( |
| 2595 | din, |
| 2596 | l1clk, |
| 2597 | scan_in, |
| 2598 | siclk, |
| 2599 | soclk, |
| 2600 | dout, |
| 2601 | scan_out); |
| 2602 | wire [3:0] fdin; |
| 2603 | wire [2:0] so; |
| 2604 | |
| 2605 | input [3:0] din; |
| 2606 | input l1clk; |
| 2607 | input scan_in; |
| 2608 | |
| 2609 | |
| 2610 | input siclk; |
| 2611 | input soclk; |
| 2612 | |
| 2613 | output [3:0] dout; |
| 2614 | output scan_out; |
| 2615 | assign fdin[3:0] = din[3:0]; |
| 2616 | |
| 2617 | |
| 2618 | |
| 2619 | |
| 2620 | |
| 2621 | |
| 2622 | dff #(4) d0_0 ( |
| 2623 | .l1clk(l1clk), |
| 2624 | .siclk(siclk), |
| 2625 | .soclk(soclk), |
| 2626 | .d(fdin[3:0]), |
| 2627 | .si({scan_in,so[2:0]}), |
| 2628 | .so({so[2:0],scan_out}), |
| 2629 | .q(dout[3:0]) |
| 2630 | ); |
| 2631 | |
| 2632 | |
| 2633 | |
| 2634 | |
| 2635 | |
| 2636 | |
| 2637 | |
| 2638 | |
| 2639 | |
| 2640 | |
| 2641 | |
| 2642 | |
| 2643 | endmodule |
| 2644 | |
| 2645 | |
| 2646 | |
| 2647 | |
| 2648 | |
| 2649 | |
| 2650 | |
| 2651 | |
| 2652 | |
| 2653 | |
| 2654 | |
| 2655 | |
| 2656 | |
| 2657 | // any PARAMS parms go into naming of macro |
| 2658 | |
| 2659 | module fgu_fdc_ctl_msff_ctl_macro__width_9 ( |
| 2660 | din, |
| 2661 | l1clk, |
| 2662 | scan_in, |
| 2663 | siclk, |
| 2664 | soclk, |
| 2665 | dout, |
| 2666 | scan_out); |
| 2667 | wire [8:0] fdin; |
| 2668 | wire [7:0] so; |
| 2669 | |
| 2670 | input [8:0] din; |
| 2671 | input l1clk; |
| 2672 | input scan_in; |
| 2673 | |
| 2674 | |
| 2675 | input siclk; |
| 2676 | input soclk; |
| 2677 | |
| 2678 | output [8:0] dout; |
| 2679 | output scan_out; |
| 2680 | assign fdin[8:0] = din[8:0]; |
| 2681 | |
| 2682 | |
| 2683 | |
| 2684 | |
| 2685 | |
| 2686 | |
| 2687 | dff #(9) d0_0 ( |
| 2688 | .l1clk(l1clk), |
| 2689 | .siclk(siclk), |
| 2690 | .soclk(soclk), |
| 2691 | .d(fdin[8:0]), |
| 2692 | .si({scan_in,so[7:0]}), |
| 2693 | .so({so[7:0],scan_out}), |
| 2694 | .q(dout[8:0]) |
| 2695 | ); |
| 2696 | |
| 2697 | |
| 2698 | |
| 2699 | |
| 2700 | |
| 2701 | |
| 2702 | |
| 2703 | |
| 2704 | |
| 2705 | |
| 2706 | |
| 2707 | |
| 2708 | endmodule |
| 2709 | |
| 2710 | |
| 2711 | |
| 2712 | |
| 2713 | |
| 2714 | |
| 2715 | |
| 2716 | |
| 2717 | |
| 2718 | |
| 2719 | |
| 2720 | |
| 2721 | |
| 2722 | // any PARAMS parms go into naming of macro |
| 2723 | |
| 2724 | module fgu_fdc_ctl_msff_ctl_macro__width_6 ( |
| 2725 | din, |
| 2726 | l1clk, |
| 2727 | scan_in, |
| 2728 | siclk, |
| 2729 | soclk, |
| 2730 | dout, |
| 2731 | scan_out); |
| 2732 | wire [5:0] fdin; |
| 2733 | wire [4:0] so; |
| 2734 | |
| 2735 | input [5:0] din; |
| 2736 | input l1clk; |
| 2737 | input scan_in; |
| 2738 | |
| 2739 | |
| 2740 | input siclk; |
| 2741 | input soclk; |
| 2742 | |
| 2743 | output [5:0] dout; |
| 2744 | output scan_out; |
| 2745 | assign fdin[5:0] = din[5:0]; |
| 2746 | |
| 2747 | |
| 2748 | |
| 2749 | |
| 2750 | |
| 2751 | |
| 2752 | dff #(6) d0_0 ( |
| 2753 | .l1clk(l1clk), |
| 2754 | .siclk(siclk), |
| 2755 | .soclk(soclk), |
| 2756 | .d(fdin[5:0]), |
| 2757 | .si({scan_in,so[4:0]}), |
| 2758 | .so({so[4:0],scan_out}), |
| 2759 | .q(dout[5:0]) |
| 2760 | ); |
| 2761 | |
| 2762 | |
| 2763 | |
| 2764 | |
| 2765 | |
| 2766 | |
| 2767 | |
| 2768 | |
| 2769 | |
| 2770 | |
| 2771 | |
| 2772 | |
| 2773 | endmodule |
| 2774 | |
| 2775 | |
| 2776 | |
| 2777 | |
| 2778 | |
| 2779 | |
| 2780 | |
| 2781 | |
| 2782 | |
| 2783 | |
| 2784 | |
| 2785 | |
| 2786 | |
| 2787 | // any PARAMS parms go into naming of macro |
| 2788 | |
| 2789 | module fgu_fdc_ctl_msff_ctl_macro__width_1 ( |
| 2790 | din, |
| 2791 | l1clk, |
| 2792 | scan_in, |
| 2793 | siclk, |
| 2794 | soclk, |
| 2795 | dout, |
| 2796 | scan_out); |
| 2797 | wire [0:0] fdin; |
| 2798 | |
| 2799 | input [0:0] din; |
| 2800 | input l1clk; |
| 2801 | input scan_in; |
| 2802 | |
| 2803 | |
| 2804 | input siclk; |
| 2805 | input soclk; |
| 2806 | |
| 2807 | output [0:0] dout; |
| 2808 | output scan_out; |
| 2809 | assign fdin[0:0] = din[0:0]; |
| 2810 | |
| 2811 | |
| 2812 | |
| 2813 | |
| 2814 | |
| 2815 | |
| 2816 | dff #(1) d0_0 ( |
| 2817 | .l1clk(l1clk), |
| 2818 | .siclk(siclk), |
| 2819 | .soclk(soclk), |
| 2820 | .d(fdin[0:0]), |
| 2821 | .si(scan_in), |
| 2822 | .so(scan_out), |
| 2823 | .q(dout[0:0]) |
| 2824 | ); |
| 2825 | |
| 2826 | |
| 2827 | |
| 2828 | |
| 2829 | |
| 2830 | |
| 2831 | |
| 2832 | |
| 2833 | |
| 2834 | |
| 2835 | |
| 2836 | |
| 2837 | endmodule |
| 2838 | |
| 2839 | |
| 2840 | |
| 2841 | |
| 2842 | |
| 2843 | |
| 2844 | |
| 2845 | |