| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: lsu_sed_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module lsu_sed_dp ( |
| 36 | sbc_ramout_clken, |
| 37 | sbc_diag_wptr_w3, |
| 38 | sbc_inv_ecc, |
| 39 | stb_ram_rd_data, |
| 40 | sec_corr_bit, |
| 41 | stb_ram_rd_ecc, |
| 42 | stb_ram_rd_cparity, |
| 43 | stb_ram_rd_ctl, |
| 44 | sbd_st_data_b, |
| 45 | stb_cam_data, |
| 46 | dcc_stb_data_rd_w3, |
| 47 | dcc_stb_ecc_rd_w3, |
| 48 | dcc_stb_ctl_rd_w3, |
| 49 | dcc_stb_addr_sel_w3, |
| 50 | dcc_stb_ptr_rd_w3, |
| 51 | mbi_run, |
| 52 | mbi_wdata, |
| 53 | bist_cmp_data, |
| 54 | stb_ram_data, |
| 55 | stb_ram_data_corr, |
| 56 | stb_ram_ctl, |
| 57 | stb_ram_cparity, |
| 58 | sed_ecc_b, |
| 59 | sed_c1_lo, |
| 60 | sed_c1_hi, |
| 61 | sed_c2_lo, |
| 62 | sed_c2_hi, |
| 63 | sed_c4_lo, |
| 64 | sed_c4_hi, |
| 65 | sed_c8_lo, |
| 66 | sed_c8_hi, |
| 67 | sed_c16_lo, |
| 68 | sed_c16_hi, |
| 69 | sed_cf_lo, |
| 70 | sed_cf_hi, |
| 71 | sed_c32_hi, |
| 72 | sed_c32_lo, |
| 73 | stb_ldxa_asi_data_w, |
| 74 | sed_bist_cmp_0, |
| 75 | sed_bist_cmp_1, |
| 76 | sed_bist_cmp_2, |
| 77 | sed_bist_cmp_3, |
| 78 | l2clk, |
| 79 | scan_in, |
| 80 | tcu_pce_ov, |
| 81 | tcu_se_scancollar_out, |
| 82 | spc_aclk, |
| 83 | spc_bclk, |
| 84 | scan_out); |
| 85 | wire stop; |
| 86 | wire se; |
| 87 | wire pce_ov; |
| 88 | wire siclk; |
| 89 | wire soclk; |
| 90 | wire [31:0] wdh; |
| 91 | wire [31:0] wdl; |
| 92 | wire [6:0] inv; |
| 93 | wire p1_hi_l; |
| 94 | wire p1_hi_r; |
| 95 | wire p1_hi; |
| 96 | wire p2_hi_l; |
| 97 | wire p2_hi_r; |
| 98 | wire p2_hi; |
| 99 | wire p4_hi_l; |
| 100 | wire p4_hi_r; |
| 101 | wire p4_hi; |
| 102 | wire p8_hi_l; |
| 103 | wire p8_hi_r; |
| 104 | wire p8_hi; |
| 105 | wire p16_hi_l; |
| 106 | wire p16_hi_r; |
| 107 | wire p16_hi; |
| 108 | wire p32_hi_l; |
| 109 | wire p32_hi; |
| 110 | wire pf_hi_l; |
| 111 | wire pf_hi_r; |
| 112 | wire pf_hi; |
| 113 | wire p1_lo_l; |
| 114 | wire p1_lo_r; |
| 115 | wire p1_lo; |
| 116 | wire p2_lo_l; |
| 117 | wire p2_lo_r; |
| 118 | wire p2_lo; |
| 119 | wire p4_lo_l; |
| 120 | wire p4_lo_r; |
| 121 | wire p4_lo; |
| 122 | wire p8_lo_l; |
| 123 | wire p8_lo_r; |
| 124 | wire p8_lo; |
| 125 | wire p16_lo_l; |
| 126 | wire p16_lo_r; |
| 127 | wire p16_lo; |
| 128 | wire p32_lo_l; |
| 129 | wire p32_lo; |
| 130 | wire pf_lo_l; |
| 131 | wire pf_lo_r; |
| 132 | wire pf_lo; |
| 133 | wire mbi_run_; |
| 134 | wire mbi_run_local; |
| 135 | wire [31:0] rdh; |
| 136 | wire [31:0] rdl; |
| 137 | wire [13:0] ecc; |
| 138 | wire c1_hi_l; |
| 139 | wire c1_hi_r; |
| 140 | wire c2_hi_l; |
| 141 | wire c2_hi_r; |
| 142 | wire c4_hi_l; |
| 143 | wire c4_hi_r; |
| 144 | wire c8_hi_l; |
| 145 | wire c8_hi_r; |
| 146 | wire c16_hi_r; |
| 147 | wire c32_hi_l; |
| 148 | wire cf_hi_l; |
| 149 | wire cf_hi_r; |
| 150 | wire cf_hi_c; |
| 151 | wire c1_lo_l; |
| 152 | wire c1_lo_r; |
| 153 | wire c2_lo_l; |
| 154 | wire c2_lo_r; |
| 155 | wire c4_lo_l; |
| 156 | wire c4_lo_r; |
| 157 | wire c8_lo_l; |
| 158 | wire c8_lo_r; |
| 159 | wire c16_lo_r; |
| 160 | wire c32_lo_l; |
| 161 | wire cf_lo_l; |
| 162 | wire cf_lo_r; |
| 163 | wire cf_lo_c; |
| 164 | wire dff_prty_bits_scanin; |
| 165 | wire dff_prty_bits_scanout; |
| 166 | wire dff_rd_data_0_scanin; |
| 167 | wire dff_rd_data_0_scanout; |
| 168 | wire [13:0] stb_ram_ecc; |
| 169 | wire [1:0] unused; |
| 170 | wire dff_rd_data_1_scanin; |
| 171 | wire dff_rd_data_1_scanout; |
| 172 | wire [63:0] stb_ram_data_corr_; |
| 173 | wire [31:0] def_value; |
| 174 | wire [63:0] stb_diag_rd_data; |
| 175 | |
| 176 | |
| 177 | input sbc_ramout_clken; |
| 178 | input [2:0] sbc_diag_wptr_w3; |
| 179 | input [6:0] sbc_inv_ecc; |
| 180 | |
| 181 | input [63:0] stb_ram_rd_data; |
| 182 | input [63:0] sec_corr_bit; |
| 183 | input [13:0] stb_ram_rd_ecc; |
| 184 | input stb_ram_rd_cparity; |
| 185 | input [2:0] stb_ram_rd_ctl; |
| 186 | |
| 187 | input [63:0] sbd_st_data_b; |
| 188 | |
| 189 | input [44:0] stb_cam_data; |
| 190 | |
| 191 | input dcc_stb_data_rd_w3; |
| 192 | input dcc_stb_ecc_rd_w3; |
| 193 | input dcc_stb_ctl_rd_w3; |
| 194 | input dcc_stb_addr_sel_w3; |
| 195 | input dcc_stb_ptr_rd_w3; |
| 196 | |
| 197 | input mbi_run; |
| 198 | input [7:0] mbi_wdata; |
| 199 | input [7:0] bist_cmp_data; |
| 200 | |
| 201 | output [63:0] stb_ram_data; // Flopped data |
| 202 | output [63:0] stb_ram_data_corr; // Final formatted data |
| 203 | output [2:0] stb_ram_ctl; |
| 204 | output stb_ram_cparity; |
| 205 | output [13:0] sed_ecc_b; // generated ECC bits |
| 206 | |
| 207 | output [1:0] sed_c1_lo; |
| 208 | output [1:0] sed_c1_hi; |
| 209 | output [1:0] sed_c2_lo; |
| 210 | output [1:0] sed_c2_hi; |
| 211 | output [1:0] sed_c4_lo; |
| 212 | output [1:0] sed_c4_hi; |
| 213 | output [1:0] sed_c8_lo; |
| 214 | output [1:0] sed_c8_hi; |
| 215 | output [1:0] sed_c16_lo; |
| 216 | output [1:0] sed_c16_hi; |
| 217 | output [2:0] sed_cf_lo; |
| 218 | output [2:0] sed_cf_hi; |
| 219 | output sed_c32_hi; |
| 220 | output sed_c32_lo; |
| 221 | |
| 222 | output [63:0] stb_ldxa_asi_data_w; |
| 223 | output sed_bist_cmp_0; |
| 224 | output sed_bist_cmp_1; |
| 225 | output sed_bist_cmp_2; |
| 226 | output sed_bist_cmp_3; |
| 227 | |
| 228 | // Globals |
| 229 | input l2clk; |
| 230 | input scan_in; |
| 231 | input tcu_pce_ov; // scan signals |
| 232 | input tcu_se_scancollar_out; |
| 233 | input spc_aclk; |
| 234 | input spc_bclk; |
| 235 | output scan_out; |
| 236 | |
| 237 | // scan renames |
| 238 | assign stop = 1'b0; |
| 239 | // end scan |
| 240 | |
| 241 | lsu_sed_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 ( |
| 242 | .din ({tcu_se_scancollar_out,tcu_pce_ov,spc_aclk,spc_bclk}), |
| 243 | .dout({se,pce_ov,siclk,soclk}) |
| 244 | ); |
| 245 | |
| 246 | //////////////////////////////////////////////////////////////////////////////// |
| 247 | // ECC generation logic |
| 248 | |
| 249 | assign {wdh[31:0],wdl[31:0]} = sbd_st_data_b[63:0]; |
| 250 | assign inv[6:0] = sbc_inv_ecc[6:0]; |
| 251 | |
| 252 | // P1 - hi |
| 253 | lsu_sed_dp_prty_macro__width_16 pgen1_hi_l ( |
| 254 | .din ({inv[0],wdh[30],1'b0 ,wdh[28],1'b0 ,wdh[26],wdh[25],1'b0 , |
| 255 | wdh[23],1'b0 ,wdh[21],1'b0 ,wdh[19],1'b0 ,wdh[17],1'b0 }), |
| 256 | .dout (p1_hi_l) |
| 257 | ); |
| 258 | lsu_sed_dp_prty_macro__width_16 pgen1_hi_r ( |
| 259 | .din ({wdh[15],1'b0 ,wdh[13],1'b0 ,wdh[11],wdh[10],1'b0 ,wdh[8], |
| 260 | 1'b0 ,wdh[6],1'b0 ,wdh[4],wdh[3],1'b0 ,wdh[1],wdh[0]}), |
| 261 | .dout (p1_hi_r) |
| 262 | ); |
| 263 | lsu_sed_dp_xor_macro__ports_2__width_1 pgen1_hi ( |
| 264 | .din0 (p1_hi_l), |
| 265 | .din1 (p1_hi_r), |
| 266 | .dout (p1_hi) |
| 267 | ); |
| 268 | |
| 269 | // P2 - hi |
| 270 | lsu_sed_dp_prty_macro__width_16 pgen2_hi_l ( |
| 271 | .din ({wdh[31],inv[1],1'b0 ,wdh[28],wdh[27],1'b0 ,wdh[25],wdh[24], |
| 272 | 1'b0 ,1'b0 ,wdh[21],wdh[20],1'b0 ,1'b0 ,wdh[17],wdh[16]}), |
| 273 | .dout (p2_hi_l) |
| 274 | ); |
| 275 | lsu_sed_dp_prty_macro__width_16 pgen2_hi_r ( |
| 276 | .din ({1'b0 ,1'b0 ,wdh[13],wdh[12],1'b0 ,wdh[10],wdh[9],1'b0 , |
| 277 | 1'b0 ,wdh[6],wdh[5],1'b0 ,wdh[3],wdh[2],1'b0 ,wdh[0]}), |
| 278 | .dout (p2_hi_r) |
| 279 | ); |
| 280 | lsu_sed_dp_xor_macro__ports_2__width_1 pgen2_hi ( |
| 281 | .din0 (p2_hi_l), |
| 282 | .din1 (p2_hi_r), |
| 283 | .dout (p2_hi) |
| 284 | ); |
| 285 | |
| 286 | // P4 - hi |
| 287 | lsu_sed_dp_prty_macro__width_16 pgen4_hi_l ( |
| 288 | .din ({wdh[31],wdh[30],wdh[29],inv[2],1'b0 ,1'b0 ,wdh[25],wdh[24], |
| 289 | wdh[23],wdh[22],1'b0 ,1'b0 ,1'b0 ,1'b0 ,wdh[17],wdh[16]}), |
| 290 | .dout (p4_hi_l) |
| 291 | ); |
| 292 | lsu_sed_dp_prty_macro__width_16 pgen4_hi_r ( |
| 293 | .din ({wdh[15],wdh[14],1'b0 ,1'b0 ,1'b0 ,wdh[10],wdh[9],wdh[8], |
| 294 | wdh[7],1'b0 ,1'b0 ,1'b0 ,wdh[3],wdh[2],wdh[1],1'b0 }), |
| 295 | .dout (p4_hi_r) |
| 296 | ); |
| 297 | lsu_sed_dp_xor_macro__ports_2__width_1 pgen4_hi ( |
| 298 | .din0 (p4_hi_l), |
| 299 | .din1 (p4_hi_r), |
| 300 | .dout (p4_hi) |
| 301 | ); |
| 302 | |
| 303 | // P8 - hi |
| 304 | lsu_sed_dp_prty_macro__width_8 pgen8_hi_l ( |
| 305 | .din ({wdh[25],wdh[24],wdh[23],wdh[22],wdh[21],wdh[20],wdh[19],wdh[18]}), |
| 306 | .dout (p8_hi_l) |
| 307 | ); |
| 308 | lsu_sed_dp_prty_macro__width_8 pgen8_hi_r ( |
| 309 | .din ({inv[3],wdh[10],wdh[9],wdh[8],wdh[7],wdh[6],wdh[5],wdh[4]}), |
| 310 | .dout (p8_hi_r) |
| 311 | ); |
| 312 | lsu_sed_dp_xor_macro__ports_2__width_1 pgen8_hi ( |
| 313 | .din0 (p8_hi_l), |
| 314 | .din1 (p8_hi_r), |
| 315 | .dout (p8_hi) |
| 316 | ); |
| 317 | |
| 318 | // P16 - hi |
| 319 | assign p16_hi_l = p8_hi_l; // this one can be shared |
| 320 | |
| 321 | lsu_sed_dp_prty_macro__width_8 pgen16_hi_r ( |
| 322 | .din ({wdh[17],wdh[16],wdh[15],wdh[14],wdh[13],wdh[12],wdh[11],inv[4]}), |
| 323 | .dout (p16_hi_r) |
| 324 | ); |
| 325 | lsu_sed_dp_xor_macro__ports_2__width_1 pgen16_hi ( |
| 326 | .din0 (p16_hi_l), |
| 327 | .din1 (p16_hi_r), |
| 328 | .dout (p16_hi) |
| 329 | ); |
| 330 | |
| 331 | // P32 - hi |
| 332 | lsu_sed_dp_prty_macro__width_8 pgen32_hi_l ( |
| 333 | .din ({wdh[31],wdh[30],wdh[29],wdh[28],wdh[27],wdh[26],inv[5],1'b0 }), |
| 334 | .dout (p32_hi_l) |
| 335 | ); |
| 336 | lsu_sed_dp_buff_macro__width_1 pgen32_hi ( |
| 337 | .din (p32_hi_l), |
| 338 | .dout (p32_hi) |
| 339 | ); |
| 340 | |
| 341 | // PF - hi |
| 342 | lsu_sed_dp_prty_macro__width_16 pgenf_hi_l ( |
| 343 | .din ({inv[6],1'b0 ,wdh[29],1'b0 ,wdh[27],wdh[26],1'b0 ,wdh[24], |
| 344 | wdh[23],1'b0 ,wdh[21],1'b0 ,1'b0 ,wdh[18],wdh[17],1'b0 }), |
| 345 | .dout (pf_hi_l) |
| 346 | ); |
| 347 | lsu_sed_dp_prty_macro__width_16 pgenf_hi_r ( |
| 348 | .din ({1'b0 ,wdh[14],1'b0 ,wdh[12],wdh[11],wdh[10],1'b0 ,1'b0 , |
| 349 | wdh[7],1'b0 ,wdh[5],wdh[4],1'b0 ,wdh[2],wdh[1],wdh[0]}), |
| 350 | .dout (pf_hi_r) |
| 351 | ); |
| 352 | lsu_sed_dp_xor_macro__ports_2__width_1 pgenf_hi ( |
| 353 | .din0 (pf_hi_l), |
| 354 | .din1 (pf_hi_r), |
| 355 | .dout (pf_hi) |
| 356 | ); |
| 357 | |
| 358 | // P1 - lo |
| 359 | lsu_sed_dp_prty_macro__width_16 pgen1_lo_l ( |
| 360 | .din ({1'b0 ,wdl[30],1'b0 ,wdl[28],1'b0 ,wdl[26],wdl[25],1'b0 , |
| 361 | wdl[23],1'b0 ,wdl[21],1'b0 ,wdl[19],1'b0 ,wdl[17],1'b0 }), |
| 362 | .dout (p1_lo_l) |
| 363 | ); |
| 364 | lsu_sed_dp_prty_macro__width_16 pgen1_lo_r ( |
| 365 | .din ({wdl[15],1'b0 ,wdl[13],1'b0 ,wdl[11],wdl[10],1'b0 ,wdl[8], |
| 366 | 1'b0 ,wdl[6],1'b0 ,wdl[4],wdl[3],1'b0 ,wdl[1],wdl[0]}), |
| 367 | .dout (p1_lo_r) |
| 368 | ); |
| 369 | lsu_sed_dp_xor_macro__ports_2__width_1 pgen1_lo ( |
| 370 | .din0 (p1_lo_l), |
| 371 | .din1 (p1_lo_r), |
| 372 | .dout (p1_lo) |
| 373 | ); |
| 374 | |
| 375 | // P2 - lo |
| 376 | lsu_sed_dp_prty_macro__width_16 pgen2_lo_l ( |
| 377 | .din ({wdl[31],1'b0 ,1'b0 ,wdl[28],wdl[27],1'b0 ,wdl[25],wdl[24], |
| 378 | 1'b0 ,1'b0 ,wdl[21],wdl[20],1'b0 ,1'b0 ,wdl[17],wdl[16]}), |
| 379 | .dout (p2_lo_l) |
| 380 | ); |
| 381 | lsu_sed_dp_prty_macro__width_16 pgen2_lo_r ( |
| 382 | .din ({1'b0 ,1'b0 ,wdl[13],wdl[12],1'b0 ,wdl[10],wdl[9],1'b0 , |
| 383 | 1'b0 ,wdl[6],wdl[5],1'b0 ,wdl[3],wdl[2],1'b0 ,wdl[0]}), |
| 384 | .dout (p2_lo_r) |
| 385 | ); |
| 386 | lsu_sed_dp_xor_macro__ports_2__width_1 pgen2_lo ( |
| 387 | .din0 (p2_lo_l), |
| 388 | .din1 (p2_lo_r), |
| 389 | .dout (p2_lo) |
| 390 | ); |
| 391 | |
| 392 | // P4 - lo |
| 393 | lsu_sed_dp_prty_macro__width_16 pgen4_lo_l ( |
| 394 | .din ({wdl[31],wdl[30],wdl[29],1'b0 ,1'b0 ,1'b0 ,wdl[25],wdl[24], |
| 395 | wdl[23],wdl[22],1'b0 ,1'b0 ,1'b0 ,1'b0 ,wdl[17],wdl[16]}), |
| 396 | .dout (p4_lo_l) |
| 397 | ); |
| 398 | lsu_sed_dp_prty_macro__width_16 pgen4_lo_r ( |
| 399 | .din ({wdl[15],wdl[14],1'b0 ,1'b0 ,1'b0 ,wdl[10],wdl[9],wdl[8], |
| 400 | wdl[7],1'b0 ,1'b0 ,1'b0 ,wdl[3],wdl[2],wdl[1],1'b0 }), |
| 401 | .dout (p4_lo_r) |
| 402 | ); |
| 403 | lsu_sed_dp_xor_macro__ports_2__width_1 pgen4_lo ( |
| 404 | .din0 (p4_lo_l), |
| 405 | .din1 (p4_lo_r), |
| 406 | .dout (p4_lo) |
| 407 | ); |
| 408 | |
| 409 | // P8 - lo |
| 410 | lsu_sed_dp_prty_macro__width_8 pgen8_lo_l ( |
| 411 | .din ({wdl[25],wdl[24],wdl[23],wdl[22],wdl[21],wdl[20],wdl[19],wdl[18]}), |
| 412 | .dout (p8_lo_l) |
| 413 | ); |
| 414 | lsu_sed_dp_prty_macro__width_8 pgen8_lo_r ( |
| 415 | .din ({1'b0 ,wdl[10],wdl[9],wdl[8],wdl[7],wdl[6],wdl[5],wdl[4]}), |
| 416 | .dout (p8_lo_r) |
| 417 | ); |
| 418 | lsu_sed_dp_xor_macro__ports_2__width_1 pgen8_lo ( |
| 419 | .din0 (p8_lo_l), |
| 420 | .din1 (p8_lo_r), |
| 421 | .dout (p8_lo) |
| 422 | ); |
| 423 | |
| 424 | // P16 - lo |
| 425 | assign p16_lo_l = p8_lo_l; // this one can be shared |
| 426 | |
| 427 | lsu_sed_dp_prty_macro__width_8 pgen16_lo_r ( |
| 428 | .din ({wdl[17],wdl[16],wdl[15],wdl[14],wdl[13],wdl[12],wdl[11],1'b0 }), |
| 429 | .dout (p16_lo_r) |
| 430 | ); |
| 431 | lsu_sed_dp_xor_macro__ports_2__width_1 pgen16_lo ( |
| 432 | .din0 (p16_lo_l), |
| 433 | .din1 (p16_lo_r), |
| 434 | .dout (p16_lo) |
| 435 | ); |
| 436 | |
| 437 | // P32 - lo |
| 438 | lsu_sed_dp_prty_macro__width_8 pgen32_lo_l ( |
| 439 | .din ({wdl[31],wdl[30],wdl[29],wdl[28],wdl[27],wdl[26],1'b0 ,1'b0 }), |
| 440 | .dout (p32_lo_l) |
| 441 | ); |
| 442 | lsu_sed_dp_buff_macro__width_1 pgen32_lo ( |
| 443 | .din (p32_lo_l), |
| 444 | .dout (p32_lo) |
| 445 | ); |
| 446 | |
| 447 | // PF - lo |
| 448 | lsu_sed_dp_prty_macro__width_16 pgenf_lo_l ( |
| 449 | .din ({1'b0 ,1'b0 ,wdl[29],1'b0 ,wdl[27],wdl[26],1'b0 ,wdl[24], |
| 450 | wdl[23],1'b0 ,wdl[21],1'b0 ,1'b0 ,wdl[18],wdl[17],1'b0 }), |
| 451 | .dout (pf_lo_l) |
| 452 | ); |
| 453 | lsu_sed_dp_prty_macro__width_16 pgenf_lo_r ( |
| 454 | .din ({1'b0 ,wdl[14],1'b0 ,wdl[12],wdl[11],wdl[10],1'b0 ,1'b0 , |
| 455 | wdl[7],1'b0 ,wdl[5],wdl[4],1'b0 ,wdl[2],wdl[1],wdl[0]}), |
| 456 | .dout (pf_lo_r) |
| 457 | ); |
| 458 | lsu_sed_dp_xor_macro__ports_2__width_1 pgenf_lo ( |
| 459 | .din0 (pf_lo_l), |
| 460 | .din1 (pf_lo_r), |
| 461 | .dout (pf_lo) |
| 462 | ); |
| 463 | |
| 464 | lsu_sed_dp_inv_macro__width_2 mbi_run_buf ( |
| 465 | .din ({mbi_run, mbi_run_}), |
| 466 | .dout ({mbi_run_,mbi_run_local}) |
| 467 | ); |
| 468 | |
| 469 | lsu_sed_dp_mux_macro__buffsel_none__dmux_4x__mux_aonpe__ports_2__width_14 bist_ecc_mx ( |
| 470 | .din0 ({mbi_wdata[5:0],mbi_wdata[7:0]}), |
| 471 | .din1 ({pf_hi,p32_hi,p16_hi,p8_hi,p4_hi,p2_hi,p1_hi, |
| 472 | pf_lo,p32_lo,p16_lo,p8_lo,p4_lo,p2_lo,p1_lo}), |
| 473 | .sel0 (mbi_run_local), |
| 474 | .sel1 (mbi_run_), |
| 475 | .dout (sed_ecc_b[13:0]) |
| 476 | ); |
| 477 | |
| 478 | //////////////////////////////////////////////////////////////////////////////// |
| 479 | // ECC check logic |
| 480 | |
| 481 | assign {rdh[31:0],rdl[31:0]} = stb_ram_rd_data[63:0]; |
| 482 | assign ecc[13:0] = stb_ram_rd_ecc[13:0]; |
| 483 | |
| 484 | // C1 - hi |
| 485 | lsu_sed_dp_prty_macro__width_16 pchk1_hi_l ( |
| 486 | .din ({1'b0 ,rdh[30],1'b0 ,rdh[28],1'b0 ,rdh[26],rdh[25],1'b0 , |
| 487 | rdh[23],1'b0 ,rdh[21],1'b0 ,rdh[19],1'b0 ,rdh[17],ecc[7]}), |
| 488 | .dout (c1_hi_l) |
| 489 | ); |
| 490 | lsu_sed_dp_prty_macro__width_16 pchk1_hi_r ( |
| 491 | .din ({rdh[15],1'b0 ,rdh[13],1'b0 ,rdh[11],rdh[10],1'b0 ,rdh[8], |
| 492 | 1'b0 ,rdh[6],1'b0 ,rdh[4],rdh[3],1'b0 ,rdh[1],rdh[0]}), |
| 493 | .dout (c1_hi_r) |
| 494 | ); |
| 495 | |
| 496 | // C2 - hi |
| 497 | lsu_sed_dp_prty_macro__width_16 pchk2_hi_l ( |
| 498 | .din ({rdh[31],1'b0 ,1'b0 ,rdh[28],rdh[27],1'b0 ,rdh[25],rdh[24], |
| 499 | 1'b0 ,1'b0 ,rdh[21],rdh[20],1'b0 ,1'b0 ,rdh[17],rdh[16]}), |
| 500 | .dout (c2_hi_l) |
| 501 | ); |
| 502 | lsu_sed_dp_prty_macro__width_16 pchk2_hi_r ( |
| 503 | .din ({ecc[8],1'b0 ,rdh[13],rdh[12],1'b0 ,rdh[10],rdh[9],1'b0 , |
| 504 | 1'b0 ,rdh[6],rdh[5],1'b0 ,rdh[3],rdh[2],1'b0 ,rdh[0]}), |
| 505 | .dout (c2_hi_r) |
| 506 | ); |
| 507 | |
| 508 | // C4 - hi |
| 509 | lsu_sed_dp_prty_macro__width_16 pchk4_hi_l ( |
| 510 | .din ({rdh[31],rdh[30],rdh[29],1'b0 ,1'b0 ,1'b0 ,rdh[25],rdh[24], |
| 511 | rdh[23],rdh[22],1'b0 ,1'b0 ,1'b0 ,1'b0 ,rdh[17],rdh[16]}), |
| 512 | .dout (c4_hi_l) |
| 513 | ); |
| 514 | lsu_sed_dp_prty_macro__width_16 pchk4_hi_r ( |
| 515 | .din ({rdh[15],rdh[14],ecc[9],1'b0 ,1'b0 ,rdh[10],rdh[9],rdh[8], |
| 516 | rdh[7],1'b0 ,1'b0 ,1'b0 ,rdh[3],rdh[2],rdh[1],1'b0 }), |
| 517 | .dout (c4_hi_r) |
| 518 | ); |
| 519 | |
| 520 | // C8 - hi |
| 521 | lsu_sed_dp_prty_macro__width_8 pchk8_hi_l ( |
| 522 | .din ({rdh[25],rdh[24],rdh[23],rdh[22],rdh[21],rdh[20],rdh[19],rdh[18]}), |
| 523 | .dout (c8_hi_l) |
| 524 | ); |
| 525 | lsu_sed_dp_prty_macro__width_8 pchk8_hi_r ( |
| 526 | .din ({ecc[10],rdh[10],rdh[9],rdh[8],rdh[7],rdh[6],rdh[5],rdh[4]}), |
| 527 | .dout (c8_hi_r) |
| 528 | ); |
| 529 | |
| 530 | // C16 - hi |
| 531 | lsu_sed_dp_prty_macro__width_8 pchk16_hi_r ( |
| 532 | .din ({rdh[17],rdh[16],rdh[15],rdh[14],rdh[13],rdh[12],rdh[11],ecc[11]}), |
| 533 | .dout (c16_hi_r) |
| 534 | ); |
| 535 | |
| 536 | // C32 - hi |
| 537 | lsu_sed_dp_prty_macro__width_8 pchk32_hi_l ( |
| 538 | .din ({rdh[31],rdh[30],rdh[29],rdh[28],rdh[27],rdh[26],1'b0 ,ecc[12]}), |
| 539 | .dout (c32_hi_l) |
| 540 | ); |
| 541 | |
| 542 | // CF - hi |
| 543 | lsu_sed_dp_prty_macro__width_16 pchkf_hi_l ( |
| 544 | .din ({rdh[31],rdh[30],rdh[29],rdh[28],rdh[27],rdh[26],rdh[25],rdh[24], |
| 545 | rdh[23],rdh[22],rdh[21],rdh[20],rdh[19],rdh[18],rdh[17],rdh[16]}), |
| 546 | .dout (cf_hi_l) |
| 547 | ); |
| 548 | lsu_sed_dp_prty_macro__width_16 pchkf_hi_r ( |
| 549 | .din ({rdh[15],rdh[14],rdh[13],rdh[12],rdh[11],rdh[10],rdh[9],rdh[8], |
| 550 | rdh[7],rdh[6],rdh[5],rdh[4],rdh[3],rdh[2],rdh[1],rdh[0]}), |
| 551 | .dout (cf_hi_r) |
| 552 | ); |
| 553 | lsu_sed_dp_prty_macro__width_8 pchkf_hi_c ( |
| 554 | .din ({ecc[13],ecc[12],ecc[11],ecc[10],ecc[9],ecc[8],ecc[7],1'b0}), |
| 555 | .dout (cf_hi_c) |
| 556 | ); |
| 557 | |
| 558 | // C1 - lo |
| 559 | lsu_sed_dp_prty_macro__width_16 pchk1_lo_l ( |
| 560 | .din ({1'b0 ,rdl[30],1'b0 ,rdl[28],1'b0 ,rdl[26],rdl[25],1'b0 , |
| 561 | rdl[23],1'b0 ,rdl[21],1'b0 ,rdl[19],1'b0 ,rdl[17],1'b0}), |
| 562 | .dout (c1_lo_l) |
| 563 | ); |
| 564 | lsu_sed_dp_prty_macro__width_16 pchk1_lo_r ( |
| 565 | .din ({rdl[15],ecc[0],rdl[13],1'b0 ,rdl[11],rdl[10],1'b0 ,rdl[8], |
| 566 | 1'b0 ,rdl[6],1'b0 ,rdl[4],rdl[3],1'b0 ,rdl[1],rdl[0]}), |
| 567 | .dout (c1_lo_r) |
| 568 | ); |
| 569 | |
| 570 | // C2 - lo |
| 571 | lsu_sed_dp_prty_macro__width_16 pchk2_lo_l ( |
| 572 | .din ({rdl[31],1'b0 ,1'b0 ,rdl[28],rdl[27],1'b0 ,rdl[25],rdl[24], |
| 573 | 1'b0 ,1'b0 ,rdl[21],rdl[20],1'b0 ,1'b0,rdl[17],rdl[16]}), |
| 574 | .dout (c2_lo_l) |
| 575 | ); |
| 576 | lsu_sed_dp_prty_macro__width_16 pchk2_lo_r ( |
| 577 | .din ({ecc[1],1'b0 ,rdl[13],rdl[12],1'b0 ,rdl[10],rdl[9],1'b0 , |
| 578 | 1'b0 ,rdl[6],rdl[5],1'b0 ,rdl[3],rdl[2],1'b0 ,rdl[0]}), |
| 579 | .dout (c2_lo_r) |
| 580 | ); |
| 581 | |
| 582 | // C4 - lo |
| 583 | lsu_sed_dp_prty_macro__width_16 pchk4_lo_l ( |
| 584 | .din ({rdl[31],rdl[30],rdl[29],1'b0 ,1'b0 ,1'b0 ,rdl[25],rdl[24], |
| 585 | rdl[23],rdl[22],1'b0 ,1'b0 ,1'b0 ,1'b0,rdl[17],rdl[16]}), |
| 586 | .dout (c4_lo_l) |
| 587 | ); |
| 588 | lsu_sed_dp_prty_macro__width_16 pchk4_lo_r ( |
| 589 | .din ({rdl[15],rdl[14],ecc[2],1'b0 ,1'b0 ,rdl[10],rdl[9],rdl[8], |
| 590 | rdl[7],1'b0 ,1'b0 ,1'b0 ,rdl[3],rdl[2],rdl[1],1'b0 }), |
| 591 | .dout (c4_lo_r) |
| 592 | ); |
| 593 | |
| 594 | // C8 - lo |
| 595 | lsu_sed_dp_prty_macro__width_8 pchk8_lo_l ( |
| 596 | .din ({rdl[25],rdl[24],rdl[23],rdl[22],rdl[21],rdl[20],rdl[19],rdl[18]}), |
| 597 | .dout (c8_lo_l) |
| 598 | ); |
| 599 | lsu_sed_dp_prty_macro__width_8 pchk8_lo_r ( |
| 600 | .din ({ecc[3],rdl[10],rdl[9],rdl[8],rdl[7],rdl[6],rdl[5],rdl[4]}), |
| 601 | .dout (c8_lo_r) |
| 602 | ); |
| 603 | |
| 604 | // C16 - lo |
| 605 | lsu_sed_dp_prty_macro__width_8 pchk16_lo_r ( |
| 606 | .din ({ecc[4],rdl[17],rdl[16],rdl[15],rdl[14],rdl[13],rdl[12],rdl[11]}), |
| 607 | .dout (c16_lo_r) |
| 608 | ); |
| 609 | |
| 610 | // C32 - lo |
| 611 | lsu_sed_dp_prty_macro__width_8 pchk32_lo_l ( |
| 612 | .din ({rdl[31],rdl[30],rdl[29],rdl[28],rdl[27],rdl[26],1'b0 ,ecc[5]}), |
| 613 | .dout (c32_lo_l) |
| 614 | ); |
| 615 | |
| 616 | // CF - lo |
| 617 | lsu_sed_dp_prty_macro__width_16 pchkf_lo_l ( |
| 618 | .din ({rdl[31],rdl[30],rdl[29],rdl[28],rdl[27],rdl[26],rdl[25],rdl[24], |
| 619 | rdl[23],rdl[22],rdl[21],rdl[20],rdl[19],rdl[18],rdl[17],rdl[16]}), |
| 620 | .dout (cf_lo_l) |
| 621 | ); |
| 622 | lsu_sed_dp_prty_macro__width_16 pchkf_lo_r ( |
| 623 | .din ({rdl[15],rdl[14],rdl[13],rdl[12],rdl[11],rdl[10],rdl[9],rdl[8], |
| 624 | rdl[7],rdl[6],rdl[5],rdl[4],rdl[3],rdl[2],rdl[1],rdl[0]}), |
| 625 | .dout (cf_lo_r) |
| 626 | ); |
| 627 | lsu_sed_dp_prty_macro__width_8 pchkf_lo_c ( |
| 628 | .din ({ecc[6],ecc[5],ecc[4],ecc[3],ecc[2],ecc[1],ecc[0],1'b0}), |
| 629 | .dout (cf_lo_c) |
| 630 | ); |
| 631 | |
| 632 | lsu_sed_dp_msff_macro__stack_42l__width_26 dff_prty_bits ( |
| 633 | .scan_in(dff_prty_bits_scanin), |
| 634 | .scan_out(dff_prty_bits_scanout), |
| 635 | .din ({c32_hi_l,c32_lo_l,c1_hi_l,c1_lo_l,c2_hi_l,c2_lo_l,c4_hi_l,c4_lo_l, |
| 636 | cf_hi_l,cf_lo_l,c8_hi_l,c8_lo_l, |
| 637 | cf_hi_c,cf_lo_c, |
| 638 | c16_hi_r,c16_lo_r,c1_hi_r,c1_lo_r,c2_hi_r,c2_lo_r,c4_hi_r,c4_lo_r, |
| 639 | c8_hi_r,c8_lo_r,cf_hi_r,cf_lo_r |
| 640 | }), |
| 641 | .dout ({sed_c32_hi,sed_c32_lo,sed_c1_hi[1],sed_c1_lo[1],sed_c2_hi[1],sed_c2_lo[1],sed_c4_hi[1],sed_c4_lo[1], |
| 642 | sed_cf_hi[1],sed_cf_lo[1],sed_c8_hi[1],sed_c8_lo[1], |
| 643 | sed_cf_hi[2],sed_cf_lo[2], |
| 644 | sed_c16_hi[0],sed_c16_lo[0],sed_c1_hi[0],sed_c1_lo[0],sed_c2_hi[0],sed_c2_lo[0],sed_c4_hi[0],sed_c4_lo[0], |
| 645 | sed_c8_hi[0],sed_c8_lo[0],sed_cf_hi[0],sed_cf_lo[0] |
| 646 | }), |
| 647 | .clk (l2clk), |
| 648 | .en (sbc_ramout_clken), |
| 649 | .se(se), |
| 650 | .siclk(siclk), |
| 651 | .soclk(soclk), |
| 652 | .pce_ov(pce_ov), |
| 653 | .stop(stop) |
| 654 | ); |
| 655 | assign sed_c16_hi[1] = sed_c8_hi[1]; |
| 656 | assign sed_c16_lo[1] = sed_c8_lo[1]; |
| 657 | |
| 658 | //////////////////////////////////////////////////////////////////////////////// |
| 659 | // stb_ram output flops and correction xors |
| 660 | |
| 661 | lsu_sed_dp_msff_macro__minbuff_1__stack_42l__width_42 dff_rd_data_0 ( |
| 662 | .scan_in(dff_rd_data_0_scanin), |
| 663 | .scan_out(dff_rd_data_0_scanout), |
| 664 | .din ({stb_ram_rd_cparity,stb_ram_rd_ctl[2],stb_ram_rd_data[63:48],stb_ram_rd_ecc[13:7],1'b0, stb_ram_rd_data[47:32]}), |
| 665 | .dout ({stb_ram_cparity, stb_ram_ctl[2], stb_ram_data[63:48], stb_ram_ecc[13:7], unused[0],stb_ram_data[47:32]}), |
| 666 | .clk (l2clk), |
| 667 | .en (sbc_ramout_clken), |
| 668 | .se(se), |
| 669 | .siclk(siclk), |
| 670 | .soclk(soclk), |
| 671 | .pce_ov(pce_ov), |
| 672 | .stop(stop) |
| 673 | ); |
| 674 | lsu_sed_dp_msff_macro__minbuff_1__stack_42l__width_42 dff_rd_data_1 ( |
| 675 | .scan_in(dff_rd_data_1_scanin), |
| 676 | .scan_out(dff_rd_data_1_scanout), |
| 677 | .din ({stb_ram_rd_ctl[1:0],stb_ram_rd_data[31:16],stb_ram_rd_ecc[6:0],1'b0, stb_ram_rd_data[15:0]}), |
| 678 | .dout ({stb_ram_ctl[1:0], stb_ram_data[31:16], stb_ram_ecc[6:0], unused[1],stb_ram_data[15:0]}), |
| 679 | .clk (l2clk), |
| 680 | .en (sbc_ramout_clken), |
| 681 | .se(se), |
| 682 | .siclk(siclk), |
| 683 | .soclk(soclk), |
| 684 | .pce_ov(pce_ov), |
| 685 | .stop(stop) |
| 686 | ); |
| 687 | |
| 688 | lsu_sed_dp_xnor_macro__stack_32c__width_32 ecc_xnor_0 ( |
| 689 | .din0 (stb_ram_data[63:32]), |
| 690 | .din1 (sec_corr_bit[63:32]), |
| 691 | .dout (stb_ram_data_corr_[63:32]) |
| 692 | ); |
| 693 | lsu_sed_dp_inv_macro__stack_32c__width_32 ecc_inv_0 ( |
| 694 | .din (stb_ram_data_corr_[63:32]), |
| 695 | .dout (stb_ram_data_corr[63:32]) |
| 696 | ); |
| 697 | lsu_sed_dp_xnor_macro__stack_32c__width_32 ecc_xnor_1 ( |
| 698 | .din0 (stb_ram_data[31:0]), |
| 699 | .din1 (sec_corr_bit[31:0]), |
| 700 | .dout (stb_ram_data_corr_[31:0]) |
| 701 | ); |
| 702 | lsu_sed_dp_inv_macro__stack_32c__width_32 ecc_inv_1 ( |
| 703 | .din (stb_ram_data_corr_[31:0]), |
| 704 | .dout (stb_ram_data_corr[31:0]) |
| 705 | ); |
| 706 | |
| 707 | //////////////////////////////////////////////////////////////////////////////// |
| 708 | // STB diagnostic read and bist muxing |
| 709 | |
| 710 | lsu_sed_dp_and_macro__ports_2__stack_32c__width_32 def_value_mx ( |
| 711 | .din0 ({4{bist_cmp_data[7:0]}}), |
| 712 | .din1 ({32{mbi_run}}), |
| 713 | .dout (def_value[31:0]) |
| 714 | ); |
| 715 | |
| 716 | lsu_sed_dp_mux_macro__mux_aope__ports_3__stack_32c__width_32 stb_diag_mux1_0 ( |
| 717 | .din0 (stb_ram_data[63:32]), |
| 718 | .din1 ({def_value[31:16],stb_cam_data[7:0],stb_cam_data[44:37]}), |
| 719 | .din2 (def_value[31:0]), |
| 720 | .sel0 (dcc_stb_data_rd_w3), |
| 721 | .sel1 (dcc_stb_addr_sel_w3), |
| 722 | .dout (stb_diag_rd_data[63:32]) |
| 723 | ); |
| 724 | lsu_sed_dp_mux_macro__mux_aonpe__ports_5__stack_32c__width_32 stb_diag_mux1_1 ( |
| 725 | .din0 (stb_ram_data[31:0]), |
| 726 | .din1 ({def_value[31:14],stb_ram_ecc[13:0]}), |
| 727 | .din2 ({def_value[31:4],stb_ram_cparity,stb_ram_ctl[2:0]}), |
| 728 | .din3 ({stb_cam_data[36:8],def_value[2:0]}), |
| 729 | .din4 ({def_value[31:3],sbc_diag_wptr_w3[2:0]}), |
| 730 | .sel0 (dcc_stb_data_rd_w3), |
| 731 | .sel1 (dcc_stb_ecc_rd_w3), |
| 732 | .sel2 (dcc_stb_ctl_rd_w3), |
| 733 | .sel3 (dcc_stb_addr_sel_w3), |
| 734 | .sel4 (dcc_stb_ptr_rd_w3), |
| 735 | .dout (stb_diag_rd_data[31:0]) |
| 736 | ); |
| 737 | |
| 738 | lsu_sed_dp_cmp_macro__width_16 bist_cmp_0 ( |
| 739 | .din0 ({2{bist_cmp_data[7:0]}}), |
| 740 | .din1 (stb_diag_rd_data[63:48]), |
| 741 | .dout (sed_bist_cmp_0) |
| 742 | ); |
| 743 | lsu_sed_dp_cmp_macro__width_16 bist_cmp_1 ( |
| 744 | .din0 ({2{bist_cmp_data[7:0]}}), |
| 745 | .din1 (stb_diag_rd_data[47:32]), |
| 746 | .dout (sed_bist_cmp_1) |
| 747 | ); |
| 748 | lsu_sed_dp_cmp_macro__width_16 bist_cmp_2 ( |
| 749 | .din0 ({2{bist_cmp_data[7:0]}}), |
| 750 | .din1 (stb_diag_rd_data[31:16]), |
| 751 | .dout (sed_bist_cmp_2) |
| 752 | ); |
| 753 | lsu_sed_dp_cmp_macro__width_16 bist_cmp_3 ( |
| 754 | .din0 ({2{bist_cmp_data[7:0]}}), |
| 755 | .din1 (stb_diag_rd_data[15:0]), |
| 756 | .dout (sed_bist_cmp_3) |
| 757 | ); |
| 758 | |
| 759 | lsu_sed_dp_buff_macro__stack_32c__width_32 ldxa_asi_data_buf_0 ( |
| 760 | .din (stb_diag_rd_data[63:32]), |
| 761 | .dout (stb_ldxa_asi_data_w[63:32]) |
| 762 | ); |
| 763 | lsu_sed_dp_buff_macro__stack_32c__width_32 ldxa_asi_data_buf_1 ( |
| 764 | .din (stb_diag_rd_data[31:0]), |
| 765 | .dout (stb_ldxa_asi_data_w[31:0]) |
| 766 | ); |
| 767 | |
| 768 | // fixscan start: |
| 769 | assign dff_prty_bits_scanin = scan_in ; |
| 770 | assign dff_rd_data_0_scanin = dff_prty_bits_scanout ; |
| 771 | assign dff_rd_data_1_scanin = dff_rd_data_0_scanout ; |
| 772 | assign scan_out = dff_rd_data_1_scanout ; |
| 773 | // fixscan end: |
| 774 | endmodule |
| 775 | |
| 776 | |
| 777 | |
| 778 | // |
| 779 | // buff macro |
| 780 | // |
| 781 | // |
| 782 | |
| 783 | |
| 784 | |
| 785 | |
| 786 | |
| 787 | module lsu_sed_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 ( |
| 788 | din, |
| 789 | dout); |
| 790 | input [3:0] din; |
| 791 | output [3:0] dout; |
| 792 | |
| 793 | |
| 794 | |
| 795 | |
| 796 | |
| 797 | |
| 798 | buff #(4) d0_0 ( |
| 799 | .in(din[3:0]), |
| 800 | .out(dout[3:0]) |
| 801 | ); |
| 802 | |
| 803 | |
| 804 | |
| 805 | |
| 806 | |
| 807 | |
| 808 | |
| 809 | |
| 810 | endmodule |
| 811 | |
| 812 | |
| 813 | |
| 814 | |
| 815 | |
| 816 | // |
| 817 | // parity macro (even parity) |
| 818 | // |
| 819 | // |
| 820 | |
| 821 | |
| 822 | |
| 823 | |
| 824 | |
| 825 | module lsu_sed_dp_prty_macro__width_16 ( |
| 826 | din, |
| 827 | dout); |
| 828 | input [15:0] din; |
| 829 | output dout; |
| 830 | |
| 831 | |
| 832 | |
| 833 | |
| 834 | |
| 835 | |
| 836 | |
| 837 | prty #(16) m0_0 ( |
| 838 | .in(din[15:0]), |
| 839 | .out(dout) |
| 840 | ); |
| 841 | |
| 842 | |
| 843 | |
| 844 | |
| 845 | |
| 846 | |
| 847 | |
| 848 | |
| 849 | |
| 850 | |
| 851 | endmodule |
| 852 | |
| 853 | |
| 854 | |
| 855 | |
| 856 | |
| 857 | // |
| 858 | // xor macro for ports = 2,3 |
| 859 | // |
| 860 | // |
| 861 | |
| 862 | |
| 863 | |
| 864 | |
| 865 | |
| 866 | module lsu_sed_dp_xor_macro__ports_2__width_1 ( |
| 867 | din0, |
| 868 | din1, |
| 869 | dout); |
| 870 | input [0:0] din0; |
| 871 | input [0:0] din1; |
| 872 | output [0:0] dout; |
| 873 | |
| 874 | |
| 875 | |
| 876 | |
| 877 | |
| 878 | xor2 #(1) d0_0 ( |
| 879 | .in0(din0[0:0]), |
| 880 | .in1(din1[0:0]), |
| 881 | .out(dout[0:0]) |
| 882 | ); |
| 883 | |
| 884 | |
| 885 | |
| 886 | |
| 887 | |
| 888 | |
| 889 | |
| 890 | |
| 891 | endmodule |
| 892 | |
| 893 | |
| 894 | |
| 895 | |
| 896 | |
| 897 | // |
| 898 | // parity macro (even parity) |
| 899 | // |
| 900 | // |
| 901 | |
| 902 | |
| 903 | |
| 904 | |
| 905 | |
| 906 | module lsu_sed_dp_prty_macro__width_8 ( |
| 907 | din, |
| 908 | dout); |
| 909 | input [7:0] din; |
| 910 | output dout; |
| 911 | |
| 912 | |
| 913 | |
| 914 | |
| 915 | |
| 916 | |
| 917 | |
| 918 | prty #(8) m0_0 ( |
| 919 | .in(din[7:0]), |
| 920 | .out(dout) |
| 921 | ); |
| 922 | |
| 923 | |
| 924 | |
| 925 | |
| 926 | |
| 927 | |
| 928 | |
| 929 | |
| 930 | |
| 931 | |
| 932 | endmodule |
| 933 | |
| 934 | |
| 935 | |
| 936 | |
| 937 | |
| 938 | // |
| 939 | // buff macro |
| 940 | // |
| 941 | // |
| 942 | |
| 943 | |
| 944 | |
| 945 | |
| 946 | |
| 947 | module lsu_sed_dp_buff_macro__width_1 ( |
| 948 | din, |
| 949 | dout); |
| 950 | input [0:0] din; |
| 951 | output [0:0] dout; |
| 952 | |
| 953 | |
| 954 | |
| 955 | |
| 956 | |
| 957 | |
| 958 | buff #(1) d0_0 ( |
| 959 | .in(din[0:0]), |
| 960 | .out(dout[0:0]) |
| 961 | ); |
| 962 | |
| 963 | |
| 964 | |
| 965 | |
| 966 | |
| 967 | |
| 968 | |
| 969 | |
| 970 | endmodule |
| 971 | |
| 972 | |
| 973 | |
| 974 | |
| 975 | |
| 976 | // |
| 977 | // invert macro |
| 978 | // |
| 979 | // |
| 980 | |
| 981 | |
| 982 | |
| 983 | |
| 984 | |
| 985 | module lsu_sed_dp_inv_macro__width_2 ( |
| 986 | din, |
| 987 | dout); |
| 988 | input [1:0] din; |
| 989 | output [1:0] dout; |
| 990 | |
| 991 | |
| 992 | |
| 993 | |
| 994 | |
| 995 | |
| 996 | inv #(2) d0_0 ( |
| 997 | .in(din[1:0]), |
| 998 | .out(dout[1:0]) |
| 999 | ); |
| 1000 | |
| 1001 | |
| 1002 | |
| 1003 | |
| 1004 | |
| 1005 | |
| 1006 | |
| 1007 | |
| 1008 | |
| 1009 | endmodule |
| 1010 | |
| 1011 | |
| 1012 | |
| 1013 | |
| 1014 | |
| 1015 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1016 | // also for pass-gate with decoder |
| 1017 | |
| 1018 | |
| 1019 | |
| 1020 | |
| 1021 | |
| 1022 | // any PARAMS parms go into naming of macro |
| 1023 | |
| 1024 | module lsu_sed_dp_mux_macro__buffsel_none__dmux_4x__mux_aonpe__ports_2__width_14 ( |
| 1025 | din0, |
| 1026 | sel0, |
| 1027 | din1, |
| 1028 | sel1, |
| 1029 | dout); |
| 1030 | input [13:0] din0; |
| 1031 | input sel0; |
| 1032 | input [13:0] din1; |
| 1033 | input sel1; |
| 1034 | output [13:0] dout; |
| 1035 | |
| 1036 | |
| 1037 | |
| 1038 | |
| 1039 | |
| 1040 | mux2s #(14) d0_0 ( |
| 1041 | .sel0(sel0), |
| 1042 | .sel1(sel1), |
| 1043 | .in0(din0[13:0]), |
| 1044 | .in1(din1[13:0]), |
| 1045 | .dout(dout[13:0]) |
| 1046 | ); |
| 1047 | |
| 1048 | |
| 1049 | |
| 1050 | |
| 1051 | |
| 1052 | |
| 1053 | |
| 1054 | |
| 1055 | |
| 1056 | |
| 1057 | |
| 1058 | |
| 1059 | |
| 1060 | endmodule |
| 1061 | |
| 1062 | |
| 1063 | |
| 1064 | |
| 1065 | |
| 1066 | |
| 1067 | // any PARAMS parms go into naming of macro |
| 1068 | |
| 1069 | module lsu_sed_dp_msff_macro__stack_42l__width_26 ( |
| 1070 | din, |
| 1071 | clk, |
| 1072 | en, |
| 1073 | se, |
| 1074 | scan_in, |
| 1075 | siclk, |
| 1076 | soclk, |
| 1077 | pce_ov, |
| 1078 | stop, |
| 1079 | dout, |
| 1080 | scan_out); |
| 1081 | wire l1clk; |
| 1082 | wire siclk_out; |
| 1083 | wire soclk_out; |
| 1084 | wire [24:0] so; |
| 1085 | |
| 1086 | input [25:0] din; |
| 1087 | |
| 1088 | |
| 1089 | input clk; |
| 1090 | input en; |
| 1091 | input se; |
| 1092 | input scan_in; |
| 1093 | input siclk; |
| 1094 | input soclk; |
| 1095 | input pce_ov; |
| 1096 | input stop; |
| 1097 | |
| 1098 | |
| 1099 | |
| 1100 | output [25:0] dout; |
| 1101 | |
| 1102 | |
| 1103 | output scan_out; |
| 1104 | |
| 1105 | |
| 1106 | |
| 1107 | |
| 1108 | cl_dp1_l1hdr_8x c0_0 ( |
| 1109 | .l2clk(clk), |
| 1110 | .pce(en), |
| 1111 | .aclk(siclk), |
| 1112 | .bclk(soclk), |
| 1113 | .l1clk(l1clk), |
| 1114 | .se(se), |
| 1115 | .pce_ov(pce_ov), |
| 1116 | .stop(stop), |
| 1117 | .siclk_out(siclk_out), |
| 1118 | .soclk_out(soclk_out) |
| 1119 | ); |
| 1120 | dff #(26) d0_0 ( |
| 1121 | .l1clk(l1clk), |
| 1122 | .siclk(siclk_out), |
| 1123 | .soclk(soclk_out), |
| 1124 | .d(din[25:0]), |
| 1125 | .si({scan_in,so[24:0]}), |
| 1126 | .so({so[24:0],scan_out}), |
| 1127 | .q(dout[25:0]) |
| 1128 | ); |
| 1129 | |
| 1130 | |
| 1131 | |
| 1132 | |
| 1133 | |
| 1134 | |
| 1135 | |
| 1136 | |
| 1137 | |
| 1138 | |
| 1139 | |
| 1140 | |
| 1141 | |
| 1142 | |
| 1143 | |
| 1144 | |
| 1145 | |
| 1146 | |
| 1147 | |
| 1148 | |
| 1149 | endmodule |
| 1150 | |
| 1151 | |
| 1152 | |
| 1153 | |
| 1154 | |
| 1155 | |
| 1156 | |
| 1157 | |
| 1158 | |
| 1159 | |
| 1160 | |
| 1161 | |
| 1162 | |
| 1163 | // any PARAMS parms go into naming of macro |
| 1164 | |
| 1165 | module lsu_sed_dp_msff_macro__minbuff_1__stack_42l__width_42 ( |
| 1166 | din, |
| 1167 | clk, |
| 1168 | en, |
| 1169 | se, |
| 1170 | scan_in, |
| 1171 | siclk, |
| 1172 | soclk, |
| 1173 | pce_ov, |
| 1174 | stop, |
| 1175 | dout, |
| 1176 | scan_out); |
| 1177 | wire l1clk; |
| 1178 | wire siclk_out; |
| 1179 | wire soclk_out; |
| 1180 | wire [40:0] so; |
| 1181 | |
| 1182 | input [41:0] din; |
| 1183 | |
| 1184 | |
| 1185 | input clk; |
| 1186 | input en; |
| 1187 | input se; |
| 1188 | input scan_in; |
| 1189 | input siclk; |
| 1190 | input soclk; |
| 1191 | input pce_ov; |
| 1192 | input stop; |
| 1193 | |
| 1194 | |
| 1195 | |
| 1196 | output [41:0] dout; |
| 1197 | |
| 1198 | |
| 1199 | output scan_out; |
| 1200 | |
| 1201 | |
| 1202 | |
| 1203 | |
| 1204 | cl_dp1_l1hdr_8x c0_0 ( |
| 1205 | .l2clk(clk), |
| 1206 | .pce(en), |
| 1207 | .aclk(siclk), |
| 1208 | .bclk(soclk), |
| 1209 | .l1clk(l1clk), |
| 1210 | .se(se), |
| 1211 | .pce_ov(pce_ov), |
| 1212 | .stop(stop), |
| 1213 | .siclk_out(siclk_out), |
| 1214 | .soclk_out(soclk_out) |
| 1215 | ); |
| 1216 | dff #(42) d0_0 ( |
| 1217 | .l1clk(l1clk), |
| 1218 | .siclk(siclk_out), |
| 1219 | .soclk(soclk_out), |
| 1220 | .d(din[41:0]), |
| 1221 | .si({scan_in,so[40:0]}), |
| 1222 | .so({so[40:0],scan_out}), |
| 1223 | .q(dout[41:0]) |
| 1224 | ); |
| 1225 | |
| 1226 | |
| 1227 | |
| 1228 | |
| 1229 | |
| 1230 | |
| 1231 | |
| 1232 | |
| 1233 | |
| 1234 | |
| 1235 | |
| 1236 | |
| 1237 | |
| 1238 | |
| 1239 | |
| 1240 | |
| 1241 | |
| 1242 | |
| 1243 | |
| 1244 | |
| 1245 | endmodule |
| 1246 | |
| 1247 | |
| 1248 | |
| 1249 | |
| 1250 | |
| 1251 | |
| 1252 | |
| 1253 | |
| 1254 | |
| 1255 | // |
| 1256 | // xnor macro for ports = 2,3 |
| 1257 | // |
| 1258 | // |
| 1259 | |
| 1260 | |
| 1261 | |
| 1262 | |
| 1263 | |
| 1264 | module lsu_sed_dp_xnor_macro__stack_32c__width_32 ( |
| 1265 | din0, |
| 1266 | din1, |
| 1267 | dout); |
| 1268 | input [31:0] din0; |
| 1269 | input [31:0] din1; |
| 1270 | output [31:0] dout; |
| 1271 | |
| 1272 | |
| 1273 | |
| 1274 | |
| 1275 | |
| 1276 | |
| 1277 | xnor2 #(32) d0_0 ( |
| 1278 | .in0(din0[31:0]), |
| 1279 | .in1(din1[31:0]), |
| 1280 | .out(dout[31:0]) |
| 1281 | ); |
| 1282 | |
| 1283 | |
| 1284 | |
| 1285 | |
| 1286 | |
| 1287 | |
| 1288 | |
| 1289 | endmodule |
| 1290 | |
| 1291 | |
| 1292 | |
| 1293 | |
| 1294 | |
| 1295 | // |
| 1296 | // invert macro |
| 1297 | // |
| 1298 | // |
| 1299 | |
| 1300 | |
| 1301 | |
| 1302 | |
| 1303 | |
| 1304 | module lsu_sed_dp_inv_macro__stack_32c__width_32 ( |
| 1305 | din, |
| 1306 | dout); |
| 1307 | input [31:0] din; |
| 1308 | output [31:0] dout; |
| 1309 | |
| 1310 | |
| 1311 | |
| 1312 | |
| 1313 | |
| 1314 | |
| 1315 | inv #(32) d0_0 ( |
| 1316 | .in(din[31:0]), |
| 1317 | .out(dout[31:0]) |
| 1318 | ); |
| 1319 | |
| 1320 | |
| 1321 | |
| 1322 | |
| 1323 | |
| 1324 | |
| 1325 | |
| 1326 | |
| 1327 | |
| 1328 | endmodule |
| 1329 | |
| 1330 | |
| 1331 | |
| 1332 | |
| 1333 | |
| 1334 | // |
| 1335 | // and macro for ports = 2,3,4 |
| 1336 | // |
| 1337 | // |
| 1338 | |
| 1339 | |
| 1340 | |
| 1341 | |
| 1342 | |
| 1343 | module lsu_sed_dp_and_macro__ports_2__stack_32c__width_32 ( |
| 1344 | din0, |
| 1345 | din1, |
| 1346 | dout); |
| 1347 | input [31:0] din0; |
| 1348 | input [31:0] din1; |
| 1349 | output [31:0] dout; |
| 1350 | |
| 1351 | |
| 1352 | |
| 1353 | |
| 1354 | |
| 1355 | |
| 1356 | and2 #(32) d0_0 ( |
| 1357 | .in0(din0[31:0]), |
| 1358 | .in1(din1[31:0]), |
| 1359 | .out(dout[31:0]) |
| 1360 | ); |
| 1361 | |
| 1362 | |
| 1363 | |
| 1364 | |
| 1365 | |
| 1366 | |
| 1367 | |
| 1368 | |
| 1369 | |
| 1370 | endmodule |
| 1371 | |
| 1372 | |
| 1373 | |
| 1374 | |
| 1375 | |
| 1376 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1377 | // also for pass-gate with decoder |
| 1378 | |
| 1379 | |
| 1380 | |
| 1381 | |
| 1382 | |
| 1383 | // any PARAMS parms go into naming of macro |
| 1384 | |
| 1385 | module lsu_sed_dp_mux_macro__mux_aope__ports_3__stack_32c__width_32 ( |
| 1386 | din0, |
| 1387 | din1, |
| 1388 | din2, |
| 1389 | sel0, |
| 1390 | sel1, |
| 1391 | dout); |
| 1392 | wire psel0; |
| 1393 | wire psel1; |
| 1394 | wire psel2; |
| 1395 | |
| 1396 | input [31:0] din0; |
| 1397 | input [31:0] din1; |
| 1398 | input [31:0] din2; |
| 1399 | input sel0; |
| 1400 | input sel1; |
| 1401 | output [31:0] dout; |
| 1402 | |
| 1403 | |
| 1404 | |
| 1405 | |
| 1406 | |
| 1407 | cl_dp1_penc3_8x c0_0 ( |
| 1408 | .test(1'b1), |
| 1409 | .sel0(sel0), |
| 1410 | .sel1(sel1), |
| 1411 | .psel0(psel0), |
| 1412 | .psel1(psel1), |
| 1413 | .psel2(psel2) |
| 1414 | ); |
| 1415 | |
| 1416 | mux3s #(32) d0_0 ( |
| 1417 | .sel0(psel0), |
| 1418 | .sel1(psel1), |
| 1419 | .sel2(psel2), |
| 1420 | .in0(din0[31:0]), |
| 1421 | .in1(din1[31:0]), |
| 1422 | .in2(din2[31:0]), |
| 1423 | .dout(dout[31:0]) |
| 1424 | ); |
| 1425 | |
| 1426 | |
| 1427 | |
| 1428 | |
| 1429 | |
| 1430 | |
| 1431 | |
| 1432 | |
| 1433 | |
| 1434 | |
| 1435 | |
| 1436 | |
| 1437 | |
| 1438 | endmodule |
| 1439 | |
| 1440 | |
| 1441 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1442 | // also for pass-gate with decoder |
| 1443 | |
| 1444 | |
| 1445 | |
| 1446 | |
| 1447 | |
| 1448 | // any PARAMS parms go into naming of macro |
| 1449 | |
| 1450 | module lsu_sed_dp_mux_macro__mux_aonpe__ports_5__stack_32c__width_32 ( |
| 1451 | din0, |
| 1452 | sel0, |
| 1453 | din1, |
| 1454 | sel1, |
| 1455 | din2, |
| 1456 | sel2, |
| 1457 | din3, |
| 1458 | sel3, |
| 1459 | din4, |
| 1460 | sel4, |
| 1461 | dout); |
| 1462 | wire buffout0; |
| 1463 | wire buffout1; |
| 1464 | wire buffout2; |
| 1465 | wire buffout3; |
| 1466 | wire buffout4; |
| 1467 | |
| 1468 | input [31:0] din0; |
| 1469 | input sel0; |
| 1470 | input [31:0] din1; |
| 1471 | input sel1; |
| 1472 | input [31:0] din2; |
| 1473 | input sel2; |
| 1474 | input [31:0] din3; |
| 1475 | input sel3; |
| 1476 | input [31:0] din4; |
| 1477 | input sel4; |
| 1478 | output [31:0] dout; |
| 1479 | |
| 1480 | |
| 1481 | |
| 1482 | |
| 1483 | |
| 1484 | cl_dp1_muxbuff5_8x c0_0 ( |
| 1485 | .in0(sel0), |
| 1486 | .in1(sel1), |
| 1487 | .in2(sel2), |
| 1488 | .in3(sel3), |
| 1489 | .in4(sel4), |
| 1490 | .out0(buffout0), |
| 1491 | .out1(buffout1), |
| 1492 | .out2(buffout2), |
| 1493 | .out3(buffout3), |
| 1494 | .out4(buffout4) |
| 1495 | ); |
| 1496 | mux5s #(32) d0_0 ( |
| 1497 | .sel0(buffout0), |
| 1498 | .sel1(buffout1), |
| 1499 | .sel2(buffout2), |
| 1500 | .sel3(buffout3), |
| 1501 | .sel4(buffout4), |
| 1502 | .in0(din0[31:0]), |
| 1503 | .in1(din1[31:0]), |
| 1504 | .in2(din2[31:0]), |
| 1505 | .in3(din3[31:0]), |
| 1506 | .in4(din4[31:0]), |
| 1507 | .dout(dout[31:0]) |
| 1508 | ); |
| 1509 | |
| 1510 | |
| 1511 | |
| 1512 | |
| 1513 | |
| 1514 | |
| 1515 | |
| 1516 | |
| 1517 | |
| 1518 | |
| 1519 | |
| 1520 | |
| 1521 | |
| 1522 | endmodule |
| 1523 | |
| 1524 | |
| 1525 | // |
| 1526 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 1527 | // |
| 1528 | // |
| 1529 | |
| 1530 | |
| 1531 | |
| 1532 | |
| 1533 | |
| 1534 | module lsu_sed_dp_cmp_macro__width_16 ( |
| 1535 | din0, |
| 1536 | din1, |
| 1537 | dout); |
| 1538 | input [15:0] din0; |
| 1539 | input [15:0] din1; |
| 1540 | output dout; |
| 1541 | |
| 1542 | |
| 1543 | |
| 1544 | |
| 1545 | |
| 1546 | |
| 1547 | cmp #(16) m0_0 ( |
| 1548 | .in0(din0[15:0]), |
| 1549 | .in1(din1[15:0]), |
| 1550 | .out(dout) |
| 1551 | ); |
| 1552 | |
| 1553 | |
| 1554 | |
| 1555 | |
| 1556 | |
| 1557 | |
| 1558 | |
| 1559 | |
| 1560 | |
| 1561 | |
| 1562 | endmodule |
| 1563 | |
| 1564 | |
| 1565 | |
| 1566 | |
| 1567 | |
| 1568 | // |
| 1569 | // buff macro |
| 1570 | // |
| 1571 | // |
| 1572 | |
| 1573 | |
| 1574 | |
| 1575 | |
| 1576 | |
| 1577 | module lsu_sed_dp_buff_macro__stack_32c__width_32 ( |
| 1578 | din, |
| 1579 | dout); |
| 1580 | input [31:0] din; |
| 1581 | output [31:0] dout; |
| 1582 | |
| 1583 | |
| 1584 | |
| 1585 | |
| 1586 | |
| 1587 | |
| 1588 | buff #(32) d0_0 ( |
| 1589 | .in(din[31:0]), |
| 1590 | .out(dout[31:0]) |
| 1591 | ); |
| 1592 | |
| 1593 | |
| 1594 | |
| 1595 | |
| 1596 | |
| 1597 | |
| 1598 | |
| 1599 | |
| 1600 | endmodule |
| 1601 | |
| 1602 | |
| 1603 | |
| 1604 | |