| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: pmu_pdp_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module pmu_pdp_dp ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | tcu_pce_ov, |
| 39 | spc_aclk, |
| 40 | spc_bclk, |
| 41 | tcu_scan_en, |
| 42 | scan_out, |
| 43 | in_rngl_cdbus, |
| 44 | pct_rd_pic, |
| 45 | pct_rd_a_pic, |
| 46 | pct_rd_pic_pcr, |
| 47 | pct_bypass_asi, |
| 48 | pct_pcr_data, |
| 49 | pct_exception, |
| 50 | pct_pic_clken, |
| 51 | pct_pic07_w2_clken, |
| 52 | pct_wr_pic_w2, |
| 53 | pct_incr_pic_w1, |
| 54 | pct_incr_asi_w1, |
| 55 | pct_pich07_add_w2, |
| 56 | pct_picl07_add_w2, |
| 57 | pmu_asi_clken, |
| 58 | pmu_rngl_cdbus, |
| 59 | pdp_asi_din_to_pctl, |
| 60 | pdp_asi_ctlin_to_pctl_15_8, |
| 61 | pdp_asi_ctlin_to_pctl_4_0, |
| 62 | pdp_pich_cout07, |
| 63 | pdp_picl_cout07, |
| 64 | pdp_pich_wrap, |
| 65 | pdp_picl_wrap); |
| 66 | wire stop; |
| 67 | wire se; |
| 68 | wire pce_ov; |
| 69 | wire siclk; |
| 70 | wire soclk; |
| 71 | wire asi_din_scanin; |
| 72 | wire asi_din_scanout; |
| 73 | wire [63:0] pdp_asi_din; |
| 74 | wire pic0_scanin; |
| 75 | wire pic0_scanout; |
| 76 | wire [31:0] pich07_incr; |
| 77 | wire [31:0] picl07_incr; |
| 78 | wire [31:0] pich0; |
| 79 | wire [31:0] picl0; |
| 80 | wire [7:0] pdp_pich_wrapa; |
| 81 | wire [7:0] pdp_picl_wrapa; |
| 82 | wire [7:0] pdp_pich_wrapb; |
| 83 | wire [7:0] pdp_picl_wrapb; |
| 84 | wire pic1_scanin; |
| 85 | wire pic1_scanout; |
| 86 | wire [31:0] pich1; |
| 87 | wire [31:0] picl1; |
| 88 | wire pic2_scanin; |
| 89 | wire pic2_scanout; |
| 90 | wire [31:0] pich2; |
| 91 | wire [31:0] picl2; |
| 92 | wire pic3_scanin; |
| 93 | wire pic3_scanout; |
| 94 | wire [31:0] pich3; |
| 95 | wire [31:0] picl3; |
| 96 | wire pic4_scanin; |
| 97 | wire pic4_scanout; |
| 98 | wire [31:0] pich4; |
| 99 | wire [31:0] picl4; |
| 100 | wire pic5_scanin; |
| 101 | wire pic5_scanout; |
| 102 | wire [31:0] pich5; |
| 103 | wire [31:0] picl5; |
| 104 | wire pic6_scanin; |
| 105 | wire pic6_scanout; |
| 106 | wire [31:0] pich6; |
| 107 | wire [31:0] picl6; |
| 108 | wire pic7_scanin; |
| 109 | wire pic7_scanout; |
| 110 | wire [31:0] pich7; |
| 111 | wire [31:0] picl7; |
| 112 | wire [31:0] pich07_w1; |
| 113 | wire [31:0] picl07_w1; |
| 114 | wire pic07_w2_scanin; |
| 115 | wire pic07_w2_scanout; |
| 116 | wire [31:0] pich07_w2; |
| 117 | wire [31:0] picl07_w2; |
| 118 | wire [63:0] pdp_pic_data; |
| 119 | wire [63:0] picpcr_data; |
| 120 | wire asi_dout_scanin; |
| 121 | wire asi_dout_scanout; |
| 122 | wire [63:0] pmu_rngl_cdbus_nobuf; |
| 123 | |
| 124 | |
| 125 | // *** globals *** |
| 126 | input l2clk; |
| 127 | input scan_in; |
| 128 | input tcu_pce_ov; // scan signals |
| 129 | input spc_aclk; |
| 130 | input spc_bclk; |
| 131 | input tcu_scan_en; |
| 132 | output scan_out; |
| 133 | |
| 134 | // ASI write data bus |
| 135 | input [63:0] in_rngl_cdbus; // ASI ring data input |
| 136 | |
| 137 | // ASI read controls |
| 138 | input [7:0] pct_rd_pic; // ASI read of PIC (bit 7 == read PIC for tid 7) |
| 139 | input pct_rd_a_pic; // ASI read of any PIC |
| 140 | input pct_rd_pic_pcr; // ASI read of PIC or PCR (select PIC or PCR) |
| 141 | input pct_bypass_asi; // Flow this node's ASI data to the output |
| 142 | input [31:0] pct_pcr_data; // PCR data on ASI read |
| 143 | input pct_exception; // If a privileged exception on an ASR read or write to PIC or PCR |
| 144 | input [7:0] pct_pic_clken; // Clock enables for PIC |
| 145 | input pct_pic07_w2_clken; // Clock enable for pic07_w2 flop |
| 146 | // ASI write controls |
| 147 | input [7:0] pct_wr_pic_w2; // Write corresponding PICH/L from ASI (bit 7 == write PIC7) |
| 148 | input [6:0] pct_incr_pic_w1; // increment PIC (PICL is enabled for counting) W+1 cycle (mux prior to adding) |
| 149 | input pct_incr_asi_w1; // Select new ASI value to increment to deal with simultaneous ASI write and increment |
| 150 | |
| 151 | // Event inputs |
| 152 | input [3:0] pct_pich07_add_w2; // Add value for pich |
| 153 | input [3:0] pct_picl07_add_w2; // Add value for picl |
| 154 | |
| 155 | // ASI pwr mgmt |
| 156 | input pmu_asi_clken; // Gate ASI ring flops |
| 157 | |
| 158 | // ASI outputs |
| 159 | output [63:0] pmu_rngl_cdbus; // ASI ring data out |
| 160 | output [31:0] pdp_asi_din_to_pctl; // for PCR writes |
| 161 | output [7:0] pdp_asi_ctlin_to_pctl_15_8; // Bits 63:56 of registered data from PDP (save 8 flop bits) |
| 162 | output [4:0] pdp_asi_ctlin_to_pctl_4_0; // Bits 63:48 of registered data from PDP (save 5 flop bits) |
| 163 | |
| 164 | // Carry-out bits for PCR of each counter |
| 165 | output pdp_pich_cout07; // carry-outs of incrementors, to set OV bits in PCR's |
| 166 | output pdp_picl_cout07; |
| 167 | |
| 168 | // Wrap indicators for trap generation |
| 169 | output [7:0] pdp_pich_wrap; // If counter within -16..-1 |
| 170 | output [7:0] pdp_picl_wrap; // If counter within -16..-1 |
| 171 | |
| 172 | // scan renames |
| 173 | //assign pce_ov = tcu_pce_ov; |
| 174 | //assign stop = tcu_clk_stop; |
| 175 | assign stop = 1'b0; |
| 176 | //assign siclk = spc_aclk; |
| 177 | //assign soclk = spc_bclk; |
| 178 | //assign se = tcu_scan_en; |
| 179 | // end scan |
| 180 | |
| 181 | pmu_pdp_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 ( |
| 182 | .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}), |
| 183 | .dout({se,pce_ov,siclk,soclk}) |
| 184 | ); |
| 185 | |
| 186 | // First put in the ASI staging reg, bit 64 is flopped in ctl |
| 187 | pmu_pdp_dp_msff_macro__stack_64c__width_64 asi_din ( |
| 188 | .scan_in(asi_din_scanin), |
| 189 | .scan_out(asi_din_scanout), |
| 190 | .clk ( l2clk ), |
| 191 | .en ( pmu_asi_clken ), // powerdown pin |
| 192 | .din( in_rngl_cdbus[63:0]), |
| 193 | .dout( pdp_asi_din[63:0]), |
| 194 | .se(se), |
| 195 | .siclk(siclk), |
| 196 | .soclk(soclk), |
| 197 | .pce_ov(pce_ov), |
| 198 | .stop(stop)); |
| 199 | |
| 200 | assign pdp_asi_din_to_pctl[31:0] = pdp_asi_din[31:0]; // bus to pctl for PCR writes |
| 201 | assign pdp_asi_ctlin_to_pctl_15_8[7:0] = pdp_asi_din[63:56];// Bits 63:56 of registered data from PDP (save 8 flop bits) |
| 202 | assign pdp_asi_ctlin_to_pctl_4_0[4:0] = pdp_asi_din[52:48];// Bits 52:48 of registered data from PDP (save 5 flop bits) |
| 203 | |
| 204 | // PICs |
| 205 | // There are 8, 1 for each thread |
| 206 | |
| 207 | // split the 64 bit 3-input mux to two 32 bit ones |
| 208 | // and use AND to zero out the counter values |
| 209 | |
| 210 | // PIC0 |
| 211 | |
| 212 | pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic0 ( |
| 213 | .scan_in(pic0_scanin), |
| 214 | .scan_out(pic0_scanout), |
| 215 | .clk ( l2clk ), |
| 216 | .en ( pct_pic_clken[0] ), // powerdown pin |
| 217 | .din0( pdp_asi_din[63:0] ), |
| 218 | .din1( {pich07_incr[31:0],picl07_incr[31:0]} ), |
| 219 | .sel0( pct_wr_pic_w2[0] ), |
| 220 | .dout( {pich0[31:0],picl0[31:0]}), |
| 221 | .se(se), |
| 222 | .siclk(siclk), |
| 223 | .soclk(soclk), |
| 224 | .pce_ov(pce_ov), |
| 225 | .stop(stop) ); |
| 226 | |
| 227 | pmu_pdp_dp_cmp_macro__width_16 pic0hca ( |
| 228 | .din0(pich0[31:16]), |
| 229 | .din1(16'hffff), |
| 230 | .dout(pdp_pich_wrapa[0])); |
| 231 | pmu_pdp_dp_cmp_macro__width_16 pic0lca ( |
| 232 | .din0(picl0[31:16]), |
| 233 | .din1(16'hffff), |
| 234 | .dout(pdp_picl_wrapa[0])); |
| 235 | |
| 236 | pmu_pdp_dp_cmp_macro__width_12 pic0hcb ( |
| 237 | .din0(pich0[15:4]), |
| 238 | .din1(12'hfff), |
| 239 | .dout(pdp_pich_wrapb[0])); |
| 240 | pmu_pdp_dp_cmp_macro__width_12 pic0lcb ( |
| 241 | .din0(picl0[15:4]), |
| 242 | .din1(12'hfff), |
| 243 | .dout(pdp_picl_wrapb[0])); |
| 244 | |
| 245 | // the ANDing is done for all 8 threads after PIC7 |
| 246 | //and_macro pich0wrap (width=2, ports=2) ( |
| 247 | // .din0 ({pdp_pich_wrapa[0],pdp_picl_wrapa[0]}), |
| 248 | // .din1 ({pdp_pich_wrapb[0],pdp_picl_wrapb[0]}), |
| 249 | // .dout ({pdp_pich_wrap[0], pdp_picl_wrap[0]}); |
| 250 | |
| 251 | // PIC1 |
| 252 | pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic1 ( |
| 253 | .scan_in(pic1_scanin), |
| 254 | .scan_out(pic1_scanout), |
| 255 | .clk ( l2clk ), |
| 256 | .en ( pct_pic_clken[1] ), // powerdown pin |
| 257 | .din0( pdp_asi_din[63:0] ), |
| 258 | .din1( {pich07_incr[31:0],picl07_incr[31:0]} ), |
| 259 | .sel0( pct_wr_pic_w2[1] ), |
| 260 | .dout( {pich1[31:0],picl1[31:0]}), |
| 261 | .se(se), |
| 262 | .siclk(siclk), |
| 263 | .soclk(soclk), |
| 264 | .pce_ov(pce_ov), |
| 265 | .stop(stop) ); |
| 266 | |
| 267 | pmu_pdp_dp_cmp_macro__width_16 pic1hca ( |
| 268 | .din0(pich1[31:16]), |
| 269 | .din1(16'hffff), |
| 270 | .dout(pdp_pich_wrapa[1])); |
| 271 | pmu_pdp_dp_cmp_macro__width_16 pic1lca ( |
| 272 | .din0(picl1[31:16]), |
| 273 | .din1(16'hffff), |
| 274 | .dout(pdp_picl_wrapa[1])); |
| 275 | |
| 276 | pmu_pdp_dp_cmp_macro__width_12 pic1hcb ( |
| 277 | .din0(pich1[15:4]), |
| 278 | .din1(12'hfff), |
| 279 | .dout(pdp_pich_wrapb[1])); |
| 280 | pmu_pdp_dp_cmp_macro__width_12 pic1lcb ( |
| 281 | .din0(picl1[15:4]), |
| 282 | .din1(12'hfff), |
| 283 | .dout(pdp_picl_wrapb[1])); |
| 284 | |
| 285 | // PIC2 |
| 286 | pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic2 ( |
| 287 | .scan_in(pic2_scanin), |
| 288 | .scan_out(pic2_scanout), |
| 289 | .clk ( l2clk ), |
| 290 | .en ( pct_pic_clken[2] ), // powerdown pin |
| 291 | .din0( pdp_asi_din[63:0] ), |
| 292 | .din1( {pich07_incr[31:0],picl07_incr[31:0]} ), |
| 293 | .sel0( pct_wr_pic_w2[2] ), |
| 294 | .dout( {pich2[31:0],picl2[31:0]}), |
| 295 | .se(se), |
| 296 | .siclk(siclk), |
| 297 | .soclk(soclk), |
| 298 | .pce_ov(pce_ov), |
| 299 | .stop(stop) ); |
| 300 | |
| 301 | pmu_pdp_dp_cmp_macro__width_16 pic2hca ( |
| 302 | .din0(pich2[31:16]), |
| 303 | .din1(16'hffff), |
| 304 | .dout(pdp_pich_wrapa[2])); |
| 305 | pmu_pdp_dp_cmp_macro__width_16 pic2lca ( |
| 306 | .din0(picl2[31:16]), |
| 307 | .din1(16'hffff), |
| 308 | .dout(pdp_picl_wrapa[2])); |
| 309 | |
| 310 | pmu_pdp_dp_cmp_macro__width_12 pic2hcb ( |
| 311 | .din0(pich2[15:4]), |
| 312 | .din1(12'hfff), |
| 313 | .dout(pdp_pich_wrapb[2])); |
| 314 | pmu_pdp_dp_cmp_macro__width_12 pic2lcb ( |
| 315 | .din0(picl2[15:4]), |
| 316 | .din1(12'hfff), |
| 317 | .dout(pdp_picl_wrapb[2])); |
| 318 | |
| 319 | // PIC3 |
| 320 | pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic3 ( |
| 321 | .scan_in(pic3_scanin), |
| 322 | .scan_out(pic3_scanout), |
| 323 | .clk ( l2clk ), |
| 324 | .en ( pct_pic_clken[3] ), // powerdown pin |
| 325 | .din0( pdp_asi_din[63:0] ), |
| 326 | .din1( {pich07_incr[31:0],picl07_incr[31:0]} ), |
| 327 | .sel0( pct_wr_pic_w2[3] ), |
| 328 | .dout( {pich3[31:0],picl3[31:0]}), |
| 329 | .se(se), |
| 330 | .siclk(siclk), |
| 331 | .soclk(soclk), |
| 332 | .pce_ov(pce_ov), |
| 333 | .stop(stop) ); |
| 334 | |
| 335 | pmu_pdp_dp_cmp_macro__width_16 pic3hca ( |
| 336 | .din0(pich3[31:16]), |
| 337 | .din1(16'hffff), |
| 338 | .dout(pdp_pich_wrapa[3])); |
| 339 | pmu_pdp_dp_cmp_macro__width_16 pic3lca ( |
| 340 | .din0(picl3[31:16]), |
| 341 | .din1(16'hffff), |
| 342 | .dout(pdp_picl_wrapa[3])); |
| 343 | |
| 344 | pmu_pdp_dp_cmp_macro__width_12 pic3hcb ( |
| 345 | .din0(pich3[15:4]), |
| 346 | .din1(12'hfff), |
| 347 | .dout(pdp_pich_wrapb[3])); |
| 348 | pmu_pdp_dp_cmp_macro__width_12 pic3lcb ( |
| 349 | .din0(picl3[15:4]), |
| 350 | .din1(12'hfff), |
| 351 | .dout(pdp_picl_wrapb[3])); |
| 352 | |
| 353 | // PIC4 |
| 354 | pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic4 ( |
| 355 | .scan_in(pic4_scanin), |
| 356 | .scan_out(pic4_scanout), |
| 357 | .clk ( l2clk ), |
| 358 | .en ( pct_pic_clken[4] ), // powerdown pin |
| 359 | .din0( pdp_asi_din[63:0] ), |
| 360 | .din1( {pich07_incr[31:0],picl07_incr[31:0]} ), |
| 361 | .sel0( pct_wr_pic_w2[4] ), |
| 362 | .dout( {pich4[31:0],picl4[31:0]}), |
| 363 | .se(se), |
| 364 | .siclk(siclk), |
| 365 | .soclk(soclk), |
| 366 | .pce_ov(pce_ov), |
| 367 | .stop(stop) ); |
| 368 | |
| 369 | pmu_pdp_dp_cmp_macro__width_16 pic4hca ( |
| 370 | .din0(pich4[31:16]), |
| 371 | .din1(16'hffff), |
| 372 | .dout(pdp_pich_wrapa[4])); |
| 373 | pmu_pdp_dp_cmp_macro__width_16 pic4lca ( |
| 374 | .din0(picl4[31:16]), |
| 375 | .din1(16'hffff), |
| 376 | .dout(pdp_picl_wrapa[4])); |
| 377 | |
| 378 | pmu_pdp_dp_cmp_macro__width_12 pic4hcb ( |
| 379 | .din0(pich4[15:4]), |
| 380 | .din1(12'hfff), |
| 381 | .dout(pdp_pich_wrapb[4])); |
| 382 | pmu_pdp_dp_cmp_macro__width_12 pic4lcb ( |
| 383 | .din0(picl4[15:4]), |
| 384 | .din1(12'hfff), |
| 385 | .dout(pdp_picl_wrapb[4])); |
| 386 | |
| 387 | // PIC5 |
| 388 | pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic5 ( |
| 389 | .scan_in(pic5_scanin), |
| 390 | .scan_out(pic5_scanout), |
| 391 | .clk ( l2clk ), |
| 392 | .en ( pct_pic_clken[5] ), // powerdown pin |
| 393 | .din0( pdp_asi_din[63:0] ), |
| 394 | .din1( {pich07_incr[31:0],picl07_incr[31:0]} ), |
| 395 | .sel0( pct_wr_pic_w2[5] ), |
| 396 | .dout( {pich5[31:0],picl5[31:0]}), |
| 397 | .se(se), |
| 398 | .siclk(siclk), |
| 399 | .soclk(soclk), |
| 400 | .pce_ov(pce_ov), |
| 401 | .stop(stop) ); |
| 402 | |
| 403 | pmu_pdp_dp_cmp_macro__width_16 pic5hca ( |
| 404 | .din0(pich5[31:16]), |
| 405 | .din1(16'hffff), |
| 406 | .dout(pdp_pich_wrapa[5])); |
| 407 | pmu_pdp_dp_cmp_macro__width_16 pic5lca ( |
| 408 | .din0(picl5[31:16]), |
| 409 | .din1(16'hffff), |
| 410 | .dout(pdp_picl_wrapa[5])); |
| 411 | |
| 412 | pmu_pdp_dp_cmp_macro__width_12 pic5hcb ( |
| 413 | .din0(pich5[15:4]), |
| 414 | .din1(12'hfff), |
| 415 | .dout(pdp_pich_wrapb[5])); |
| 416 | pmu_pdp_dp_cmp_macro__width_12 pic5lcb ( |
| 417 | .din0(picl5[15:4]), |
| 418 | .din1(12'hfff), |
| 419 | .dout(pdp_picl_wrapb[5])); |
| 420 | |
| 421 | // PIC6 |
| 422 | pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic6 ( |
| 423 | .scan_in(pic6_scanin), |
| 424 | .scan_out(pic6_scanout), |
| 425 | .clk ( l2clk ), |
| 426 | .en ( pct_pic_clken[6] ), // powerdown pin |
| 427 | .din0( pdp_asi_din[63:0] ), |
| 428 | .din1( {pich07_incr[31:0],picl07_incr[31:0]} ), |
| 429 | .sel0( pct_wr_pic_w2[6] ), |
| 430 | .dout( {pich6[31:0],picl6[31:0]}), |
| 431 | .se(se), |
| 432 | .siclk(siclk), |
| 433 | .soclk(soclk), |
| 434 | .pce_ov(pce_ov), |
| 435 | .stop(stop) ); |
| 436 | |
| 437 | pmu_pdp_dp_cmp_macro__width_16 pic6hca ( |
| 438 | .din0(pich6[31:16]), |
| 439 | .din1(16'hffff), |
| 440 | .dout(pdp_pich_wrapa[6])); |
| 441 | pmu_pdp_dp_cmp_macro__width_16 pic6lca ( |
| 442 | .din0(picl6[31:16]), |
| 443 | .din1(16'hffff), |
| 444 | .dout(pdp_picl_wrapa[6])); |
| 445 | |
| 446 | pmu_pdp_dp_cmp_macro__width_12 pic6hcb ( |
| 447 | .din0(pich6[15:4]), |
| 448 | .din1(12'hfff), |
| 449 | .dout(pdp_pich_wrapb[6])); |
| 450 | pmu_pdp_dp_cmp_macro__width_12 pic6lcb ( |
| 451 | .din0(picl6[15:4]), |
| 452 | .din1(12'hfff), |
| 453 | .dout(pdp_picl_wrapb[6])); |
| 454 | |
| 455 | // PIC7 |
| 456 | pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic7 ( |
| 457 | .scan_in(pic7_scanin), |
| 458 | .scan_out(pic7_scanout), |
| 459 | .clk ( l2clk ), |
| 460 | .en ( pct_pic_clken[7] ), // powerdown pin |
| 461 | .din0( pdp_asi_din[63:0] ), |
| 462 | .din1( {pich07_incr[31:0],picl07_incr[31:0]} ), |
| 463 | .sel0( pct_wr_pic_w2[7] ), |
| 464 | .dout( {pich7[31:0],picl7[31:0]}), |
| 465 | .se(se), |
| 466 | .siclk(siclk), |
| 467 | .soclk(soclk), |
| 468 | .pce_ov(pce_ov), |
| 469 | .stop(stop) ); |
| 470 | |
| 471 | pmu_pdp_dp_cmp_macro__width_16 pic7hca ( |
| 472 | .din0(pich7[31:16]), |
| 473 | .din1(16'hffff), |
| 474 | .dout(pdp_pich_wrapa[7])); |
| 475 | pmu_pdp_dp_cmp_macro__width_16 pic7lca ( |
| 476 | .din0(picl7[31:16]), |
| 477 | .din1(16'hffff), |
| 478 | .dout(pdp_picl_wrapa[7])); |
| 479 | |
| 480 | pmu_pdp_dp_cmp_macro__width_12 pic7hcb ( |
| 481 | .din0(pich7[15:4]), |
| 482 | .din1(12'hfff), |
| 483 | .dout(pdp_pich_wrapb[7])); |
| 484 | pmu_pdp_dp_cmp_macro__width_12 pic7lcb ( |
| 485 | .din0(picl7[15:4]), |
| 486 | .din1(12'hfff), |
| 487 | .dout(pdp_picl_wrapb[7])); |
| 488 | |
| 489 | pmu_pdp_dp_and_macro__ports_2__width_16 pich0wrap ( |
| 490 | .din0 ({pdp_pich_wrapa[7:0],pdp_picl_wrapa[7:0]}), |
| 491 | .din1 ({pdp_pich_wrapb[7:0],pdp_picl_wrapb[7:0]}), |
| 492 | .dout ({pdp_pich_wrap[7:0], pdp_picl_wrap[7:0]})); |
| 493 | |
| 494 | // Mux PIC's 0-7 together to share one incrementor & adder |
| 495 | // Mux in W1 cycle, increment in W2 |
| 496 | pmu_pdp_dp_mux_macro__mux_aope__ports_8__width_64 pic07_mux ( |
| 497 | .din0({pich0[31:0], picl0[31:0]}), |
| 498 | .din1({pich1[31:0], picl1[31:0]}), |
| 499 | .din2({pich2[31:0], picl2[31:0]}), |
| 500 | .din3({pich3[31:0], picl3[31:0]}), |
| 501 | .din4({pich4[31:0], picl4[31:0]}), |
| 502 | .din5({pich5[31:0], picl5[31:0]}), |
| 503 | .din6({pich6[31:0], picl6[31:0]}), |
| 504 | .din7({pich7[31:0], picl7[31:0]}), |
| 505 | .sel0(pct_incr_pic_w1[0]), |
| 506 | .sel1(pct_incr_pic_w1[1]), |
| 507 | .sel2(pct_incr_pic_w1[2]), |
| 508 | .sel3(pct_incr_pic_w1[3]), |
| 509 | .sel4(pct_incr_pic_w1[4]), |
| 510 | .sel5(pct_incr_pic_w1[5]), |
| 511 | .sel6(pct_incr_pic_w1[6]), |
| 512 | // .sel7(pct_incr_pic_w1[7]), // pct_incr_pic_w1 is guaranteed to be one-hot |
| 513 | .dout({pich07_w1[31:0], picl07_w1[31:0]})); |
| 514 | |
| 515 | // all 8 threads sharing two comparators |
| 516 | // not practical, as wrap must be matched with tid in the ctl logic |
| 517 | //cmp_macro pic07hc (width=28) ( |
| 518 | // .din0(pich07_w1[31:4]), |
| 519 | // .din1(28'hfffffff), |
| 520 | // .dout(pdp_pich_wrap)); |
| 521 | |
| 522 | //cmp_macro pic07lc (width=28) ( |
| 523 | // .din0(pich07_w1[31:4]), |
| 524 | // .din1(28'hfffffff), |
| 525 | // .dout(pdp_picl_wrap)); |
| 526 | |
| 527 | // send these two wrap signals to the ctl logic and qualify with pct_incr_pic_w1 |
| 528 | |
| 529 | pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic07_w2 ( |
| 530 | .scan_in(pic07_w2_scanin), |
| 531 | .scan_out(pic07_w2_scanout), |
| 532 | .clk ( l2clk ), |
| 533 | .en ( pct_pic07_w2_clken ), // powerdown pin |
| 534 | .din0( pdp_asi_din[63:0]), |
| 535 | .din1( {pich07_w1[31:0], picl07_w1[31:0]} ), |
| 536 | .sel0( pct_incr_asi_w1 ), |
| 537 | .dout( {pich07_w2[31:0], picl07_w2[31:0]} ), |
| 538 | .se(se), |
| 539 | .siclk(siclk), |
| 540 | .soclk(soclk), |
| 541 | .pce_ov(pce_ov), |
| 542 | .stop(stop)); |
| 543 | |
| 544 | // PICH incrementor for PIC's 0-7 |
| 545 | pmu_pdp_dp_cla_macro__width_32 pich07_cla ( |
| 546 | .din0({28'b0, pct_pich07_add_w2[3:0]}), |
| 547 | .din1(pich07_w2[31:0]), |
| 548 | .cin(1'b0), |
| 549 | .dout(pich07_incr[31:0]), |
| 550 | .cout(pdp_pich_cout07) |
| 551 | ); |
| 552 | |
| 553 | pmu_pdp_dp_cla_macro__width_32 picl07_cla ( |
| 554 | .din0({28'b0, pct_picl07_add_w2[3:0]}), |
| 555 | .din1(picl07_w2[31:0]), |
| 556 | .cin(1'b0), |
| 557 | .dout(picl07_incr[31:0]), |
| 558 | .cout(pdp_picl_cout07) |
| 559 | ); |
| 560 | |
| 561 | // 8:1 mux for ASR reads to mux between PICs |
| 562 | |
| 563 | pmu_pdp_dp_mux_macro__mux_aonpe__ports_8__width_64 pic_mux ( |
| 564 | .din0({pich0[31:0],picl0[31:0]}), |
| 565 | .din1({pich1[31:0],picl1[31:0]}), |
| 566 | .din2({pich2[31:0],picl2[31:0]}), |
| 567 | .din3({pich3[31:0],picl3[31:0]}), |
| 568 | .din4({pich4[31:0],picl4[31:0]}), |
| 569 | .din5({pich5[31:0],picl5[31:0]}), |
| 570 | .din6({pich6[31:0],picl6[31:0]}), |
| 571 | .din7({pich7[31:0],picl7[31:0]}), |
| 572 | .sel0(pct_rd_pic[0]), |
| 573 | .sel1(pct_rd_pic[1]), |
| 574 | .sel2(pct_rd_pic[2]), |
| 575 | .sel3(pct_rd_pic[3]), |
| 576 | .sel4(pct_rd_pic[4]), |
| 577 | .sel5(pct_rd_pic[5]), |
| 578 | .sel6(pct_rd_pic[6]), |
| 579 | .sel7(pct_rd_pic[7]), |
| 580 | .dout(pdp_pic_data[63:0])); |
| 581 | |
| 582 | pmu_pdp_dp_mux_macro__mux_aope__ports_2__width_64 picpcr_mux ( |
| 583 | .din0(pdp_pic_data[63:0]), |
| 584 | .din1({32'b0, pct_pcr_data[31:0]}), |
| 585 | .sel0(pct_rd_a_pic), |
| 586 | .dout(picpcr_data[63:0])); |
| 587 | |
| 588 | // ASI output registers |
| 589 | pmu_pdp_dp_msff_macro__mux_aope__ports_3__stack_64c__width_64 asi_dout ( |
| 590 | .scan_in(asi_dout_scanin), |
| 591 | .scan_out(asi_dout_scanout), |
| 592 | .clk ( l2clk), |
| 593 | .en ( pmu_asi_clken ), // powerdown pin |
| 594 | .din0( pdp_asi_din[63:0]), |
| 595 | .din1( picpcr_data[63:0]), |
| 596 | .din2({pdp_asi_din[63],1'b1,pdp_asi_din[61:56],6'b0,pct_exception,1'b0,pdp_asi_din[47:0]}), |
| 597 | .sel0( pct_bypass_asi), |
| 598 | .sel1( pct_rd_pic_pcr), |
| 599 | .dout( pmu_rngl_cdbus_nobuf[63:0]), |
| 600 | .se(se), |
| 601 | .siclk(siclk), |
| 602 | .soclk(soclk), |
| 603 | .pce_ov(pce_ov), |
| 604 | .stop(stop)); |
| 605 | |
| 606 | // Add buffer to drive FGU since aope muxes can't drive big loads well... |
| 607 | pmu_pdp_dp_buff_macro__dbuff_32x__rep_1__stack_64c__width_64 rngl_out_buf ( |
| 608 | .din (pmu_rngl_cdbus_nobuf[63:0]), |
| 609 | .dout(pmu_rngl_cdbus[63:0])); |
| 610 | |
| 611 | |
| 612 | // fixscan start: |
| 613 | assign asi_din_scanin = scan_in ; |
| 614 | assign pic0_scanin = asi_din_scanout ; |
| 615 | assign pic1_scanin = pic0_scanout ; |
| 616 | assign pic2_scanin = pic1_scanout ; |
| 617 | assign pic3_scanin = pic2_scanout ; |
| 618 | assign pic4_scanin = pic3_scanout ; |
| 619 | assign pic5_scanin = pic4_scanout ; |
| 620 | assign pic6_scanin = pic5_scanout ; |
| 621 | assign pic7_scanin = pic6_scanout ; |
| 622 | assign pic07_w2_scanin = pic7_scanout ; |
| 623 | assign asi_dout_scanin = pic07_w2_scanout ; |
| 624 | assign scan_out = asi_dout_scanout ; |
| 625 | // fixscan end: |
| 626 | endmodule |
| 627 | |
| 628 | |
| 629 | // |
| 630 | // buff macro |
| 631 | // |
| 632 | // |
| 633 | |
| 634 | |
| 635 | |
| 636 | |
| 637 | |
| 638 | module pmu_pdp_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 ( |
| 639 | din, |
| 640 | dout); |
| 641 | input [3:0] din; |
| 642 | output [3:0] dout; |
| 643 | |
| 644 | |
| 645 | |
| 646 | |
| 647 | |
| 648 | |
| 649 | buff #(4) d0_0 ( |
| 650 | .in(din[3:0]), |
| 651 | .out(dout[3:0]) |
| 652 | ); |
| 653 | |
| 654 | |
| 655 | |
| 656 | |
| 657 | |
| 658 | |
| 659 | |
| 660 | |
| 661 | endmodule |
| 662 | |
| 663 | |
| 664 | |
| 665 | |
| 666 | |
| 667 | |
| 668 | |
| 669 | |
| 670 | |
| 671 | // any PARAMS parms go into naming of macro |
| 672 | |
| 673 | module pmu_pdp_dp_msff_macro__stack_64c__width_64 ( |
| 674 | din, |
| 675 | clk, |
| 676 | en, |
| 677 | se, |
| 678 | scan_in, |
| 679 | siclk, |
| 680 | soclk, |
| 681 | pce_ov, |
| 682 | stop, |
| 683 | dout, |
| 684 | scan_out); |
| 685 | wire l1clk; |
| 686 | wire siclk_out; |
| 687 | wire soclk_out; |
| 688 | wire [62:0] so; |
| 689 | |
| 690 | input [63:0] din; |
| 691 | |
| 692 | |
| 693 | input clk; |
| 694 | input en; |
| 695 | input se; |
| 696 | input scan_in; |
| 697 | input siclk; |
| 698 | input soclk; |
| 699 | input pce_ov; |
| 700 | input stop; |
| 701 | |
| 702 | |
| 703 | |
| 704 | output [63:0] dout; |
| 705 | |
| 706 | |
| 707 | output scan_out; |
| 708 | |
| 709 | |
| 710 | |
| 711 | |
| 712 | cl_dp1_l1hdr_8x c0_0 ( |
| 713 | .l2clk(clk), |
| 714 | .pce(en), |
| 715 | .aclk(siclk), |
| 716 | .bclk(soclk), |
| 717 | .l1clk(l1clk), |
| 718 | .se(se), |
| 719 | .pce_ov(pce_ov), |
| 720 | .stop(stop), |
| 721 | .siclk_out(siclk_out), |
| 722 | .soclk_out(soclk_out) |
| 723 | ); |
| 724 | dff #(64) d0_0 ( |
| 725 | .l1clk(l1clk), |
| 726 | .siclk(siclk_out), |
| 727 | .soclk(soclk_out), |
| 728 | .d(din[63:0]), |
| 729 | .si({scan_in,so[62:0]}), |
| 730 | .so({so[62:0],scan_out}), |
| 731 | .q(dout[63:0]) |
| 732 | ); |
| 733 | |
| 734 | |
| 735 | |
| 736 | |
| 737 | |
| 738 | |
| 739 | |
| 740 | |
| 741 | |
| 742 | |
| 743 | |
| 744 | |
| 745 | |
| 746 | |
| 747 | |
| 748 | |
| 749 | |
| 750 | |
| 751 | |
| 752 | |
| 753 | endmodule |
| 754 | |
| 755 | |
| 756 | |
| 757 | |
| 758 | |
| 759 | |
| 760 | |
| 761 | |
| 762 | |
| 763 | |
| 764 | |
| 765 | |
| 766 | |
| 767 | // any PARAMS parms go into naming of macro |
| 768 | |
| 769 | module pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 ( |
| 770 | din0, |
| 771 | din1, |
| 772 | sel0, |
| 773 | clk, |
| 774 | en, |
| 775 | se, |
| 776 | scan_in, |
| 777 | siclk, |
| 778 | soclk, |
| 779 | pce_ov, |
| 780 | stop, |
| 781 | dout, |
| 782 | scan_out); |
| 783 | wire psel0; |
| 784 | wire psel1; |
| 785 | wire [63:0] muxout; |
| 786 | wire l1clk; |
| 787 | wire siclk_out; |
| 788 | wire soclk_out; |
| 789 | wire [62:0] so; |
| 790 | |
| 791 | input [63:0] din0; |
| 792 | input [63:0] din1; |
| 793 | input sel0; |
| 794 | |
| 795 | |
| 796 | input clk; |
| 797 | input en; |
| 798 | input se; |
| 799 | input scan_in; |
| 800 | input siclk; |
| 801 | input soclk; |
| 802 | input pce_ov; |
| 803 | input stop; |
| 804 | |
| 805 | |
| 806 | |
| 807 | output [63:0] dout; |
| 808 | |
| 809 | |
| 810 | output scan_out; |
| 811 | |
| 812 | |
| 813 | |
| 814 | |
| 815 | cl_dp1_penc2_8x c1_0 ( |
| 816 | .sel0(sel0), |
| 817 | .psel0(psel0), |
| 818 | .psel1(psel1) |
| 819 | ); |
| 820 | |
| 821 | mux2s #(64) d1_0 ( |
| 822 | .sel0(psel0), |
| 823 | .sel1(psel1), |
| 824 | .in0(din0[63:0]), |
| 825 | .in1(din1[63:0]), |
| 826 | .dout(muxout[63:0]) |
| 827 | ); |
| 828 | cl_dp1_l1hdr_8x c0_0 ( |
| 829 | .l2clk(clk), |
| 830 | .pce(en), |
| 831 | .aclk(siclk), |
| 832 | .bclk(soclk), |
| 833 | .l1clk(l1clk), |
| 834 | .se(se), |
| 835 | .pce_ov(pce_ov), |
| 836 | .stop(stop), |
| 837 | .siclk_out(siclk_out), |
| 838 | .soclk_out(soclk_out) |
| 839 | ); |
| 840 | dff #(64) d0_0 ( |
| 841 | .l1clk(l1clk), |
| 842 | .siclk(siclk_out), |
| 843 | .soclk(soclk_out), |
| 844 | .d(muxout[63:0]), |
| 845 | .si({scan_in,so[62:0]}), |
| 846 | .so({so[62:0],scan_out}), |
| 847 | .q(dout[63:0]) |
| 848 | ); |
| 849 | |
| 850 | |
| 851 | |
| 852 | |
| 853 | |
| 854 | |
| 855 | |
| 856 | |
| 857 | |
| 858 | |
| 859 | |
| 860 | |
| 861 | |
| 862 | |
| 863 | |
| 864 | |
| 865 | |
| 866 | |
| 867 | |
| 868 | |
| 869 | endmodule |
| 870 | |
| 871 | |
| 872 | |
| 873 | |
| 874 | |
| 875 | |
| 876 | |
| 877 | |
| 878 | |
| 879 | // |
| 880 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 881 | // |
| 882 | // |
| 883 | |
| 884 | |
| 885 | |
| 886 | |
| 887 | |
| 888 | module pmu_pdp_dp_cmp_macro__width_16 ( |
| 889 | din0, |
| 890 | din1, |
| 891 | dout); |
| 892 | input [15:0] din0; |
| 893 | input [15:0] din1; |
| 894 | output dout; |
| 895 | |
| 896 | |
| 897 | |
| 898 | |
| 899 | |
| 900 | |
| 901 | cmp #(16) m0_0 ( |
| 902 | .in0(din0[15:0]), |
| 903 | .in1(din1[15:0]), |
| 904 | .out(dout) |
| 905 | ); |
| 906 | |
| 907 | |
| 908 | |
| 909 | |
| 910 | |
| 911 | |
| 912 | |
| 913 | |
| 914 | |
| 915 | |
| 916 | endmodule |
| 917 | |
| 918 | |
| 919 | |
| 920 | |
| 921 | |
| 922 | // |
| 923 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 924 | // |
| 925 | // |
| 926 | |
| 927 | |
| 928 | |
| 929 | |
| 930 | |
| 931 | module pmu_pdp_dp_cmp_macro__width_12 ( |
| 932 | din0, |
| 933 | din1, |
| 934 | dout); |
| 935 | input [11:0] din0; |
| 936 | input [11:0] din1; |
| 937 | output dout; |
| 938 | |
| 939 | |
| 940 | |
| 941 | |
| 942 | |
| 943 | |
| 944 | cmp #(12) m0_0 ( |
| 945 | .in0(din0[11:0]), |
| 946 | .in1(din1[11:0]), |
| 947 | .out(dout) |
| 948 | ); |
| 949 | |
| 950 | |
| 951 | |
| 952 | |
| 953 | |
| 954 | |
| 955 | |
| 956 | |
| 957 | |
| 958 | |
| 959 | endmodule |
| 960 | |
| 961 | |
| 962 | |
| 963 | |
| 964 | |
| 965 | // |
| 966 | // and macro for ports = 2,3,4 |
| 967 | // |
| 968 | // |
| 969 | |
| 970 | |
| 971 | |
| 972 | |
| 973 | |
| 974 | module pmu_pdp_dp_and_macro__ports_2__width_16 ( |
| 975 | din0, |
| 976 | din1, |
| 977 | dout); |
| 978 | input [15:0] din0; |
| 979 | input [15:0] din1; |
| 980 | output [15:0] dout; |
| 981 | |
| 982 | |
| 983 | |
| 984 | |
| 985 | |
| 986 | |
| 987 | and2 #(16) d0_0 ( |
| 988 | .in0(din0[15:0]), |
| 989 | .in1(din1[15:0]), |
| 990 | .out(dout[15:0]) |
| 991 | ); |
| 992 | |
| 993 | |
| 994 | |
| 995 | |
| 996 | |
| 997 | |
| 998 | |
| 999 | |
| 1000 | |
| 1001 | endmodule |
| 1002 | |
| 1003 | |
| 1004 | |
| 1005 | |
| 1006 | |
| 1007 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1008 | // also for pass-gate with decoder |
| 1009 | |
| 1010 | |
| 1011 | |
| 1012 | |
| 1013 | |
| 1014 | // any PARAMS parms go into naming of macro |
| 1015 | |
| 1016 | module pmu_pdp_dp_mux_macro__mux_aope__ports_8__width_64 ( |
| 1017 | din0, |
| 1018 | din1, |
| 1019 | din2, |
| 1020 | din3, |
| 1021 | din4, |
| 1022 | din5, |
| 1023 | din6, |
| 1024 | din7, |
| 1025 | sel0, |
| 1026 | sel1, |
| 1027 | sel2, |
| 1028 | sel3, |
| 1029 | sel4, |
| 1030 | sel5, |
| 1031 | sel6, |
| 1032 | dout); |
| 1033 | wire psel0; |
| 1034 | wire psel1; |
| 1035 | wire psel2; |
| 1036 | wire psel3; |
| 1037 | wire psel4; |
| 1038 | wire psel5; |
| 1039 | wire psel6; |
| 1040 | wire psel7; |
| 1041 | |
| 1042 | input [63:0] din0; |
| 1043 | input [63:0] din1; |
| 1044 | input [63:0] din2; |
| 1045 | input [63:0] din3; |
| 1046 | input [63:0] din4; |
| 1047 | input [63:0] din5; |
| 1048 | input [63:0] din6; |
| 1049 | input [63:0] din7; |
| 1050 | input sel0; |
| 1051 | input sel1; |
| 1052 | input sel2; |
| 1053 | input sel3; |
| 1054 | input sel4; |
| 1055 | input sel5; |
| 1056 | input sel6; |
| 1057 | output [63:0] dout; |
| 1058 | |
| 1059 | |
| 1060 | |
| 1061 | |
| 1062 | |
| 1063 | cl_dp1_penc8_8x c0_0 ( |
| 1064 | .test(1'b1), |
| 1065 | .sel0(sel0), |
| 1066 | .sel1(sel1), |
| 1067 | .sel2(sel2), |
| 1068 | .sel3(sel3), |
| 1069 | .sel4(sel4), |
| 1070 | .sel5(sel5), |
| 1071 | .sel6(sel6), |
| 1072 | .psel0(psel0), |
| 1073 | .psel1(psel1), |
| 1074 | .psel2(psel2), |
| 1075 | .psel3(psel3), |
| 1076 | .psel4(psel4), |
| 1077 | .psel5(psel5), |
| 1078 | .psel6(psel6), |
| 1079 | .psel7(psel7) |
| 1080 | ); |
| 1081 | |
| 1082 | mux8s #(64) d0_0 ( |
| 1083 | .sel0(psel0), |
| 1084 | .sel1(psel1), |
| 1085 | .sel2(psel2), |
| 1086 | .sel3(psel3), |
| 1087 | .sel4(psel4), |
| 1088 | .sel5(psel5), |
| 1089 | .sel6(psel6), |
| 1090 | .sel7(psel7), |
| 1091 | .in0(din0[63:0]), |
| 1092 | .in1(din1[63:0]), |
| 1093 | .in2(din2[63:0]), |
| 1094 | .in3(din3[63:0]), |
| 1095 | .in4(din4[63:0]), |
| 1096 | .in5(din5[63:0]), |
| 1097 | .in6(din6[63:0]), |
| 1098 | .in7(din7[63:0]), |
| 1099 | .dout(dout[63:0]) |
| 1100 | ); |
| 1101 | |
| 1102 | |
| 1103 | |
| 1104 | |
| 1105 | |
| 1106 | |
| 1107 | |
| 1108 | |
| 1109 | |
| 1110 | |
| 1111 | |
| 1112 | |
| 1113 | |
| 1114 | endmodule |
| 1115 | |
| 1116 | |
| 1117 | // |
| 1118 | // cla macro |
| 1119 | // |
| 1120 | // |
| 1121 | |
| 1122 | |
| 1123 | |
| 1124 | |
| 1125 | |
| 1126 | module pmu_pdp_dp_cla_macro__width_32 ( |
| 1127 | cin, |
| 1128 | din0, |
| 1129 | din1, |
| 1130 | dout, |
| 1131 | cout); |
| 1132 | input cin; |
| 1133 | input [31:0] din0; |
| 1134 | input [31:0] din1; |
| 1135 | output [31:0] dout; |
| 1136 | output cout; |
| 1137 | |
| 1138 | |
| 1139 | |
| 1140 | |
| 1141 | |
| 1142 | |
| 1143 | |
| 1144 | cla #(32) m0_0 ( |
| 1145 | .cin(cin), |
| 1146 | .in0(din0[31:0]), |
| 1147 | .in1(din1[31:0]), |
| 1148 | .out(dout[31:0]), |
| 1149 | .cout(cout) |
| 1150 | ); |
| 1151 | |
| 1152 | |
| 1153 | |
| 1154 | |
| 1155 | |
| 1156 | |
| 1157 | |
| 1158 | |
| 1159 | |
| 1160 | |
| 1161 | |
| 1162 | |
| 1163 | endmodule |
| 1164 | |
| 1165 | |
| 1166 | |
| 1167 | |
| 1168 | |
| 1169 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1170 | // also for pass-gate with decoder |
| 1171 | |
| 1172 | |
| 1173 | |
| 1174 | |
| 1175 | |
| 1176 | // any PARAMS parms go into naming of macro |
| 1177 | |
| 1178 | module pmu_pdp_dp_mux_macro__mux_aonpe__ports_8__width_64 ( |
| 1179 | din0, |
| 1180 | sel0, |
| 1181 | din1, |
| 1182 | sel1, |
| 1183 | din2, |
| 1184 | sel2, |
| 1185 | din3, |
| 1186 | sel3, |
| 1187 | din4, |
| 1188 | sel4, |
| 1189 | din5, |
| 1190 | sel5, |
| 1191 | din6, |
| 1192 | sel6, |
| 1193 | din7, |
| 1194 | sel7, |
| 1195 | dout); |
| 1196 | wire buffout0; |
| 1197 | wire buffout1; |
| 1198 | wire buffout2; |
| 1199 | wire buffout3; |
| 1200 | wire buffout4; |
| 1201 | wire buffout5; |
| 1202 | wire buffout6; |
| 1203 | wire buffout7; |
| 1204 | |
| 1205 | input [63:0] din0; |
| 1206 | input sel0; |
| 1207 | input [63:0] din1; |
| 1208 | input sel1; |
| 1209 | input [63:0] din2; |
| 1210 | input sel2; |
| 1211 | input [63:0] din3; |
| 1212 | input sel3; |
| 1213 | input [63:0] din4; |
| 1214 | input sel4; |
| 1215 | input [63:0] din5; |
| 1216 | input sel5; |
| 1217 | input [63:0] din6; |
| 1218 | input sel6; |
| 1219 | input [63:0] din7; |
| 1220 | input sel7; |
| 1221 | output [63:0] dout; |
| 1222 | |
| 1223 | |
| 1224 | |
| 1225 | |
| 1226 | |
| 1227 | cl_dp1_muxbuff8_8x c0_0 ( |
| 1228 | .in0(sel0), |
| 1229 | .in1(sel1), |
| 1230 | .in2(sel2), |
| 1231 | .in3(sel3), |
| 1232 | .in4(sel4), |
| 1233 | .in5(sel5), |
| 1234 | .in6(sel6), |
| 1235 | .in7(sel7), |
| 1236 | .out0(buffout0), |
| 1237 | .out1(buffout1), |
| 1238 | .out2(buffout2), |
| 1239 | .out3(buffout3), |
| 1240 | .out4(buffout4), |
| 1241 | .out5(buffout5), |
| 1242 | .out6(buffout6), |
| 1243 | .out7(buffout7) |
| 1244 | ); |
| 1245 | mux8s #(64) d0_0 ( |
| 1246 | .sel0(buffout0), |
| 1247 | .sel1(buffout1), |
| 1248 | .sel2(buffout2), |
| 1249 | .sel3(buffout3), |
| 1250 | .sel4(buffout4), |
| 1251 | .sel5(buffout5), |
| 1252 | .sel6(buffout6), |
| 1253 | .sel7(buffout7), |
| 1254 | .in0(din0[63:0]), |
| 1255 | .in1(din1[63:0]), |
| 1256 | .in2(din2[63:0]), |
| 1257 | .in3(din3[63:0]), |
| 1258 | .in4(din4[63:0]), |
| 1259 | .in5(din5[63:0]), |
| 1260 | .in6(din6[63:0]), |
| 1261 | .in7(din7[63:0]), |
| 1262 | .dout(dout[63:0]) |
| 1263 | ); |
| 1264 | |
| 1265 | |
| 1266 | |
| 1267 | |
| 1268 | |
| 1269 | |
| 1270 | |
| 1271 | |
| 1272 | |
| 1273 | |
| 1274 | |
| 1275 | |
| 1276 | |
| 1277 | endmodule |
| 1278 | |
| 1279 | |
| 1280 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1281 | // also for pass-gate with decoder |
| 1282 | |
| 1283 | |
| 1284 | |
| 1285 | |
| 1286 | |
| 1287 | // any PARAMS parms go into naming of macro |
| 1288 | |
| 1289 | module pmu_pdp_dp_mux_macro__mux_aope__ports_2__width_64 ( |
| 1290 | din0, |
| 1291 | din1, |
| 1292 | sel0, |
| 1293 | dout); |
| 1294 | wire psel0; |
| 1295 | wire psel1; |
| 1296 | |
| 1297 | input [63:0] din0; |
| 1298 | input [63:0] din1; |
| 1299 | input sel0; |
| 1300 | output [63:0] dout; |
| 1301 | |
| 1302 | |
| 1303 | |
| 1304 | |
| 1305 | |
| 1306 | cl_dp1_penc2_8x c0_0 ( |
| 1307 | .sel0(sel0), |
| 1308 | .psel0(psel0), |
| 1309 | .psel1(psel1) |
| 1310 | ); |
| 1311 | |
| 1312 | mux2s #(64) d0_0 ( |
| 1313 | .sel0(psel0), |
| 1314 | .sel1(psel1), |
| 1315 | .in0(din0[63:0]), |
| 1316 | .in1(din1[63:0]), |
| 1317 | .dout(dout[63:0]) |
| 1318 | ); |
| 1319 | |
| 1320 | |
| 1321 | |
| 1322 | |
| 1323 | |
| 1324 | |
| 1325 | |
| 1326 | |
| 1327 | |
| 1328 | |
| 1329 | |
| 1330 | |
| 1331 | |
| 1332 | endmodule |
| 1333 | |
| 1334 | |
| 1335 | |
| 1336 | |
| 1337 | |
| 1338 | |
| 1339 | // any PARAMS parms go into naming of macro |
| 1340 | |
| 1341 | module pmu_pdp_dp_msff_macro__mux_aope__ports_3__stack_64c__width_64 ( |
| 1342 | din0, |
| 1343 | din1, |
| 1344 | din2, |
| 1345 | sel0, |
| 1346 | sel1, |
| 1347 | clk, |
| 1348 | en, |
| 1349 | se, |
| 1350 | scan_in, |
| 1351 | siclk, |
| 1352 | soclk, |
| 1353 | pce_ov, |
| 1354 | stop, |
| 1355 | dout, |
| 1356 | scan_out); |
| 1357 | wire psel0; |
| 1358 | wire psel1; |
| 1359 | wire psel2; |
| 1360 | wire [63:0] muxout; |
| 1361 | wire l1clk; |
| 1362 | wire siclk_out; |
| 1363 | wire soclk_out; |
| 1364 | wire [62:0] so; |
| 1365 | |
| 1366 | input [63:0] din0; |
| 1367 | input [63:0] din1; |
| 1368 | input [63:0] din2; |
| 1369 | input sel0; |
| 1370 | input sel1; |
| 1371 | |
| 1372 | |
| 1373 | input clk; |
| 1374 | input en; |
| 1375 | input se; |
| 1376 | input scan_in; |
| 1377 | input siclk; |
| 1378 | input soclk; |
| 1379 | input pce_ov; |
| 1380 | input stop; |
| 1381 | |
| 1382 | |
| 1383 | |
| 1384 | output [63:0] dout; |
| 1385 | |
| 1386 | |
| 1387 | output scan_out; |
| 1388 | |
| 1389 | |
| 1390 | |
| 1391 | |
| 1392 | cl_dp1_penc3_8x c1_0 ( |
| 1393 | .test(1'b1), |
| 1394 | .sel0(sel0), |
| 1395 | .sel1(sel1), |
| 1396 | .psel0(psel0), |
| 1397 | .psel1(psel1), |
| 1398 | .psel2(psel2) |
| 1399 | ); |
| 1400 | |
| 1401 | mux3s #(64) d1_0 ( |
| 1402 | .sel0(psel0), |
| 1403 | .sel1(psel1), |
| 1404 | .sel2(psel2), |
| 1405 | .in0(din0[63:0]), |
| 1406 | .in1(din1[63:0]), |
| 1407 | .in2(din2[63:0]), |
| 1408 | .dout(muxout[63:0]) |
| 1409 | ); |
| 1410 | cl_dp1_l1hdr_8x c0_0 ( |
| 1411 | .l2clk(clk), |
| 1412 | .pce(en), |
| 1413 | .aclk(siclk), |
| 1414 | .bclk(soclk), |
| 1415 | .l1clk(l1clk), |
| 1416 | .se(se), |
| 1417 | .pce_ov(pce_ov), |
| 1418 | .stop(stop), |
| 1419 | .siclk_out(siclk_out), |
| 1420 | .soclk_out(soclk_out) |
| 1421 | ); |
| 1422 | dff #(64) d0_0 ( |
| 1423 | .l1clk(l1clk), |
| 1424 | .siclk(siclk_out), |
| 1425 | .soclk(soclk_out), |
| 1426 | .d(muxout[63:0]), |
| 1427 | .si({scan_in,so[62:0]}), |
| 1428 | .so({so[62:0],scan_out}), |
| 1429 | .q(dout[63:0]) |
| 1430 | ); |
| 1431 | |
| 1432 | |
| 1433 | |
| 1434 | |
| 1435 | |
| 1436 | |
| 1437 | |
| 1438 | |
| 1439 | |
| 1440 | |
| 1441 | |
| 1442 | |
| 1443 | |
| 1444 | |
| 1445 | |
| 1446 | |
| 1447 | |
| 1448 | |
| 1449 | |
| 1450 | |
| 1451 | endmodule |
| 1452 | |
| 1453 | |
| 1454 | |
| 1455 | |
| 1456 | |
| 1457 | |
| 1458 | |
| 1459 | |
| 1460 | |
| 1461 | // |
| 1462 | // buff macro |
| 1463 | // |
| 1464 | // |
| 1465 | |
| 1466 | |
| 1467 | |
| 1468 | |
| 1469 | |
| 1470 | module pmu_pdp_dp_buff_macro__dbuff_32x__rep_1__stack_64c__width_64 ( |
| 1471 | din, |
| 1472 | dout); |
| 1473 | input [63:0] din; |
| 1474 | output [63:0] dout; |
| 1475 | |
| 1476 | |
| 1477 | |
| 1478 | |
| 1479 | |
| 1480 | |
| 1481 | buff #(64) d0_0 ( |
| 1482 | .in(din[63:0]), |
| 1483 | .out(dout[63:0]) |
| 1484 | ); |
| 1485 | |
| 1486 | |
| 1487 | |
| 1488 | |
| 1489 | |
| 1490 | |
| 1491 | |
| 1492 | |
| 1493 | endmodule |
| 1494 | |
| 1495 | |
| 1496 | |
| 1497 | |