| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: clkgen_ccu_io2x.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module clkgen_ccu_io2x ( |
| 36 | l2clk, |
| 37 | aclk, |
| 38 | bclk, |
| 39 | so, |
| 40 | clk_stop, |
| 41 | pce_ov, |
| 42 | wmr_protect, |
| 43 | wmr_, |
| 44 | por_, |
| 45 | cmp_slow_sync_en, |
| 46 | slow_cmp_sync_en, |
| 47 | tcu_clk_stop, |
| 48 | tcu_pce_ov, |
| 49 | rst_wmr_protect, |
| 50 | rst_wmr_, |
| 51 | rst_por_, |
| 52 | ccu_cmp_slow_sync_en, |
| 53 | ccu_slow_cmp_sync_en, |
| 54 | tcu_div_bypass, |
| 55 | ccu_div_ph, |
| 56 | cluster_div_en, |
| 57 | gclk, |
| 58 | clk_ext, |
| 59 | tcu_aclk, |
| 60 | tcu_bclk, |
| 61 | se, |
| 62 | si |
| 63 | ); |
| 64 | |
| 65 | |
| 66 | // ************************** |
| 67 | // port declaration |
| 68 | // ************************** |
| 69 | |
| 70 | // clock & test out |
| 71 | output l2clk; // assume we do not need aclk, bclk outputs |
| 72 | output aclk; // buffered version of aclk |
| 73 | output bclk; // buffered version of bclk |
| 74 | output so; // unused as of today - feb 10, 05 |
| 75 | |
| 76 | // pipelined out |
| 77 | output clk_stop; // allows clk stop in flop-header |
| 78 | output pce_ov; // pce override to l1 header |
| 79 | output wmr_protect; // warm reset protect |
| 80 | output wmr_; // warm reset (active low) |
| 81 | output por_; // power-on-reset |
| 82 | output cmp_slow_sync_en; // cmp->slow clk sync pulse |
| 83 | output slow_cmp_sync_en; // slow->cmp clk sync pulse |
| 84 | |
| 85 | // ctrl in (for pipelining) |
| 86 | input tcu_clk_stop; |
| 87 | input tcu_pce_ov; |
| 88 | input rst_wmr_protect; |
| 89 | input rst_wmr_; |
| 90 | input rst_por_; |
| 91 | input ccu_cmp_slow_sync_en; |
| 92 | input ccu_slow_cmp_sync_en; |
| 93 | |
| 94 | // ctrl in (for clock gen) |
| 95 | input tcu_div_bypass; // bypasses clk divider to mux in ext clk |
| 96 | input ccu_div_ph; // phase signal from ccu (div/4 or div/2) |
| 97 | input cluster_div_en; // if enabled, l2clk is divided down |
| 98 | |
| 99 | // clock & test in |
| 100 | input gclk; // global clk - this is either cmp or dr |
| 101 | input clk_ext; // external clk muxed in for ioclk bypass |
| 102 | input se; // unused as of today - feb 10, 05 |
| 103 | input si; // unused as of today - feb 10, 05 |
| 104 | input tcu_aclk; |
| 105 | input tcu_bclk; |
| 106 | |
| 107 | |
| 108 | // ************************** |
| 109 | // wire declaration |
| 110 | // ************************** |
| 111 | wire l2clk; |
| 112 | wire aclk; |
| 113 | wire bclk; |
| 114 | wire so; |
| 115 | wire clk_stop; |
| 116 | wire pce_ov; |
| 117 | wire wmr_protect; |
| 118 | wire wmr_; |
| 119 | wire por_; |
| 120 | wire cmp_slow_sync_en; |
| 121 | wire slow_cmp_sync_en; |
| 122 | wire tcu_clk_stop; |
| 123 | wire tcu_pce_ov; |
| 124 | wire rst_wmr_protect; |
| 125 | wire rst_wmr_; |
| 126 | wire rst_por_; |
| 127 | wire ccu_cmp_slow_sync_en; |
| 128 | wire ccu_slow_cmp_sync_en; |
| 129 | wire tcu_div_bypass; |
| 130 | wire ccu_div_ph; |
| 131 | wire cluster_div_en; |
| 132 | wire gclk; |
| 133 | wire clk_ext; |
| 134 | wire se; // tie-low, unused as of today - feb 10, 05 |
| 135 | wire si; // tie-low, unused as of today - feb 10, 05 |
| 136 | wire tcu_aclk; |
| 137 | wire tcu_bclk; |
| 138 | |
| 139 | |
| 140 | |
| 141 | // ************************** |
| 142 | // instantiations |
| 143 | // ************************** |
| 144 | |
| 145 | // needs a few edits to cluster header def - mahmud.hassan |
| 146 | // modified custom cell name for avoiding |
| 147 | // collision with sparc core and other clusters - mhassan |
| 148 | n2_clk_clstr_hdr_cust xcluster_header ( |
| 149 | .cpu_divider_bypass (tcu_div_bypass ), |
| 150 | .tcu_pce_ov (tcu_pce_ov ), |
| 151 | .tcu_clk_stop (tcu_clk_stop ), |
| 152 | .clk_ext (clk_ext ), |
| 153 | .div_r (ccu_div_ph ), |
| 154 | .div_f (cluster_div_en ), |
| 155 | .se (se ), |
| 156 | .so (so ), |
| 157 | .clk_stop (clk_stop ), |
| 158 | .pce_ov (pce_ov ), |
| 159 | .wmr_ (wmr_ ), |
| 160 | .cclk (cclk ), |
| 161 | .tcu_bclk (tcu_bclk ), |
| 162 | .tcu_aclk (tcu_aclk ), |
| 163 | .si (si ), |
| 164 | .gclk (gclk ), |
| 165 | .rst_wmr_ (rst_wmr_ ), |
| 166 | .l2clk (l2clk ), |
| 167 | .rst_wmr_protect (rst_wmr_protect ), |
| 168 | .rst_por_ ( rst_por_ ), |
| 169 | .wmr_protect (wmr_protect ), |
| 170 | .por_ (por_ ), |
| 171 | .ccu_cmp_slow_sync_en (ccu_cmp_slow_sync_en ), |
| 172 | .ccu_slow_cmp_sync_en (ccu_slow_cmp_sync_en ), |
| 173 | .cmp_slow_sync_en (cmp_slow_sync_en ), |
| 174 | .slow_cmp_sync_en (slow_cmp_sync_en ), |
| 175 | .aclk (aclk), |
| 176 | .bclk (bclk) |
| 177 | ); |
| 178 | |
| 179 | |
| 180 | // cclk -> l2clk from right |
| 181 | n2_clk_ccu_io2x_cust xright ( |
| 182 | .l2clk (l2clk), |
| 183 | .cclk (cclk) |
| 184 | ); |
| 185 | |
| 186 | |
| 187 | |
| 188 | // cclk -> l2clk from left |
| 189 | n2_clk_ccu_io2x_cust xleft ( |
| 190 | .l2clk (l2clk), |
| 191 | .cclk (cclk) |
| 192 | ); |
| 193 | |
| 194 | endmodule |
| 195 | |