| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: n2_ras_vec_mcu_poison.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_HV_ALSO |
| 39 | |
| 40 | |
| 41 | #define L2_ENTRY_PA 0xa000000000 |
| 42 | #define TEST_DATA1 0x5555555555555555 |
| 43 | #define L2_ENTRY_PA0 0x2020000008 |
| 44 | #define L2_ES_W1C_VALUE 0xc03ffffc00000000 |
| 45 | #define TT_SW_Error 0x40 |
| 46 | #define DRAM_ERR_STAT_REG 0x8400000280 |
| 47 | #ifdef L2_0 |
| 48 | #define L2_BANK_ADDR 0x00 |
| 49 | #endif |
| 50 | #ifdef L2_1 |
| 51 | #define L2_BANK_ADDR 0x40 |
| 52 | #endif |
| 53 | |
| 54 | |
| 55 | |
| 56 | #include "hboot.s" |
| 57 | #include "asi_s.h" |
| 58 | #include "err_defines.h" |
| 59 | |
| 60 | .text |
| 61 | .global main |
| 62 | .global My_Recoverable_Sw_error_trap |
| 63 | |
| 64 | |
| 65 | main: |
| 66 | |
| 67 | |
| 68 | ! Boot code does not provide TLB translation for IO address space |
| 69 | ta T_CHANGE_HPRIV |
| 70 | |
| 71 | disable_l1_DCache: |
| 72 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 73 | ! Remove bit 2 |
| 74 | andn %l0, 0x2, %l0 |
| 75 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 76 | |
| 77 | |
| 78 | #ifdef MEM_POISN_Trap |
| 79 | enable_err_reporting: |
| 80 | setx L2EE_PA0, %l0, %l1 |
| 81 | ldx [%l1], %l2 |
| 82 | mov 0x3, %l0 |
| 83 | or %l2, %l0, %l2 |
| 84 | stx %l2, [%l1] |
| 85 | #endif |
| 86 | |
| 87 | clear_l2_ESR: |
| 88 | setx L2_ES_W1C_VALUE, %l0, %l1 |
| 89 | setx L2ES_PA0, %l6, %g1 |
| 90 | stx %l1, [%g1] |
| 91 | |
| 92 | |
| 93 | set_L2_Direct_Mapped_Mode: |
| 94 | setx L2CS_PA0, %l6, %g1 |
| 95 | add %g1,L2_BANK_ADDR,%g1 |
| 96 | mov 0x2, %l0 |
| 97 | stx %l0, [%g1] |
| 98 | |
| 99 | store_to_L2: |
| 100 | setx TEST_DATA1, %l0, %g5 |
| 101 | |
| 102 | store_to_L2_way0: |
| 103 | setx 0x22000000, %l0, %g2 |
| 104 | add %g2,L2_BANK_ADDR,%g2 |
| 105 | stx %g5, [%g2] |
| 106 | membar #Sync |
| 107 | |
| 108 | clr %i7 |
| 109 | set 0x1f,%l7 |
| 110 | loop: |
| 111 | inc %i7 |
| 112 | cmp %i7,%l7 |
| 113 | bne loop |
| 114 | nop |
| 115 | |
| 116 | L2_diag_load: |
| 117 | setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3] |
| 118 | setx L2_ENTRY_PA, %l0, %g4 |
| 119 | and %g2, %l2, %g5 |
| 120 | or %g5, %g4, %g5 |
| 121 | ldx [%g5], %g6 |
| 122 | membar #Sync |
| 123 | |
| 124 | ! Flip two bits |
| 125 | xor %g6, 0x600, %g6 |
| 126 | stx %g6, [%g5] |
| 127 | membar #Sync |
| 128 | |
| 129 | clr %i7 |
| 130 | set 0x7,%l7 |
| 131 | loop_diag: |
| 132 | inc %i7 |
| 133 | cmp %i7,%l7 |
| 134 | bne loop_diag |
| 135 | nop |
| 136 | |
| 137 | |
| 138 | store_to_mem: |
| 139 | setx 0x33000000, %l0, %g2 |
| 140 | add %g2,L2_BANK_ADDR,%g2 |
| 141 | stx %g5, [%g2] |
| 142 | membar #Sync |
| 143 | |
| 144 | clr %i7 |
| 145 | set 0xf,%l7 |
| 146 | loop_mem: |
| 147 | inc %i7 |
| 148 | cmp %i7,%l7 |
| 149 | bne loop_mem |
| 150 | nop |
| 151 | |
| 152 | load_UEdata: |
| 153 | setx 0x22000000, %l0, %g2 |
| 154 | add %g2,L2_BANK_ADDR,%g2 |
| 155 | ldx [%g2], %g3 |
| 156 | membar #Sync |
| 157 | |
| 158 | clr %i7 |
| 159 | set 0xf,%l7 |
| 160 | loop_UE: |
| 161 | inc %i7 |
| 162 | cmp %i7,%l7 |
| 163 | bne loop_UE |
| 164 | nop |
| 165 | |
| 166 | nop; nop; nop |
| 167 | nop; nop; nop |
| 168 | nop; nop; nop |
| 169 | nop; nop; nop |
| 170 | nop; nop; nop |
| 171 | nop; nop; nop |
| 172 | nop; nop; nop |
| 173 | nop; nop; nop |
| 174 | nop; nop; nop |
| 175 | |
| 176 | |
| 177 | enable_l1_DCache: |
| 178 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 179 | or %l0, 0x2, %l0 |
| 180 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 181 | |
| 182 | |
| 183 | check_l2_ESR: |
| 184 | setx L2ES_PA0, %l6, %g1 |
| 185 | add %g1,L2_BANK_ADDR,%g1 |
| 186 | ldx [%g1], %l4 |
| 187 | membar #Sync |
| 188 | |
| 189 | |
| 190 | compute_L2_ESR: |
| 191 | setx 0xf1fffffff0000000, %l3, %l0 ! MSA; ignore CoreID -> <59:57>; TH_ID <56:54> should be OK |
| 192 | andcc %l0, %l4, %l5 ! Donot check L2ESR SYND bits |
| 193 | |
| 194 | mov 0x1, %l1 |
| 195 | sllx %l1, L2ES_LDWU, %l0 |
| 196 | mov 0x1, %l1 |
| 197 | sllx %l1, L2ES_VEU, %l2 |
| 198 | or %l0, %l2, %l3 |
| 199 | mov 0x1, %l1 |
| 200 | sllx %l1, L2ES_MEU, %l2 ! MEU |
| 201 | or %l3, %l2, %l3 |
| 202 | |
| 203 | verify_L2_ESR: |
| 204 | cmp %l5, %l3 |
| 205 | bne %xcc, test_fail |
| 206 | nop |
| 207 | |
| 208 | |
| 209 | |
| 210 | check_l2_EAR: |
| 211 | setx L2EA_PA0, %l6, %l3 |
| 212 | add %l3,L2_BANK_ADDR,%l3 |
| 213 | ldx [%l3], %l4 |
| 214 | membar #Sync |
| 215 | |
| 216 | |
| 217 | verify_EAR: |
| 218 | setx 0x22000000, %l0, %g2 |
| 219 | add %g2,L2_BANK_ADDR,%g2 |
| 220 | |
| 221 | cmp %g2, %l4 |
| 222 | bne test_fail |
| 223 | nop |
| 224 | |
| 225 | check_DRAM_ESR_0: |
| 226 | setx DRAM_ERR_STAT_REG, %l3, %g5 |
| 227 | ldx [%g5], %l6 |
| 228 | setx 0xffc000000000ffff, %l0,%o2 |
| 229 | and %l6,%o2,%l6 |
| 230 | |
| 231 | compute_dram_ESR: |
| 232 | mov 0x1, %l1 |
| 233 | sllx %l1, DRAM_ES_DAU, %l0 ! %l0 has expected value |
| 234 | set 0x8221,%l3 |
| 235 | or %l0,%l3,%l0 |
| 236 | |
| 237 | verify_dram_ESR: |
| 238 | cmp %l0, %l6 |
| 239 | bne %xcc, test_fail |
| 240 | nop |
| 241 | |
| 242 | #ifdef MEM_POISN_Trap |
| 243 | ! Check if a Software Recoverable Error Trap happened |
| 244 | set EXECUTED, %l0 |
| 245 | cmp %o0, %l0 |
| 246 | bne test_fail |
| 247 | nop |
| 248 | mov TT_SW_Error, %l0 |
| 249 | cmp %o1, %l0 |
| 250 | bne test_fail |
| 251 | nop |
| 252 | #endif |
| 253 | |
| 254 | ba test_pass |
| 255 | nop |
| 256 | |
| 257 | My_Recoverable_Sw_error_trap: |
| 258 | ! Signal trap taken |
| 259 | setx EXECUTED, %l0, %o0 |
| 260 | ! save trap type value |
| 261 | rdpr %tt, %o1 |
| 262 | // retry |
| 263 | done |
| 264 | nop |
| 265 | |
| 266 | |
| 267 | |
| 268 | /******************************************************* |
| 269 | * Exit code |
| 270 | *******************************************************/ |
| 271 | |
| 272 | test_pass: |
| 273 | ta T_GOOD_TRAP |
| 274 | |
| 275 | test_fail: |
| 276 | ta T_BAD_TRAP |
| 277 | |
| 278 | |