| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: mcu_defines.h |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define DRAM_REG_COUNT 4 |
| 39 | #define DRAM_REG_STEP 4096 |
| 40 | #define DRAM_CAS_ADDR_WIDTH_REG 0x8400000000 |
| 41 | #define DRAM_RAS_ADDR_WIDTH_REG 0x8400000008 |
| 42 | #define DRAM_CAS_LAT_REG 0x8400000010 |
| 43 | #define DRAM_SCRUB_FREQ_REG 0x8400000018 |
| 44 | #define DRAM_REFRESH_FREQ_REG 0x8400000020 |
| 45 | #define DRAM_OPEN_BANK_MAX_REG 0x8400000028 |
| 46 | #define DRAM_REFRESH_COUNTER_REG 0x8400000038 |
| 47 | #define DRAM_SCRUB_ENABLE_REG 0x8400000040 |
| 48 | #define DRAM_PROG_TIME_CNTR_REG 0x8400000048 |
| 49 | #define DRAM_TRRD_REG 0x8400000080 |
| 50 | #define DRAM_TRC_REG 0x8400000088 |
| 51 | #define DRAM_TRCD_REG 0x8400000090 |
| 52 | #define DRAM_TWTR_REG 0x8400000098 |
| 53 | #define DRAM_TRTW_REG 0x84000000a0 |
| 54 | #define DRAM_TRTP_REG 0x84000000a8 |
| 55 | #define DRAM_TRAS_REG 0x84000000b0 |
| 56 | #define DRAM_TRP_REG 0x84000000b8 |
| 57 | #define DRAM_TWR_REG 0x84000000c0 |
| 58 | #define DRAM_TRFC_REG 0x84000000c8 |
| 59 | #define DRAM_TMRD_REG 0x84000000d0 |
| 60 | #define DRAM_TIWTR_REG 0x84000000e0 |
| 61 | #define DRAM_PRECHARGE_WAIT_REG 0x84000000e8 |
| 62 | #define DRAM_DIMM_STACK_REG 0x8400000108 |
| 63 | #define DRAM_EXT_WR_MODE2_REG 0x8400000110 |
| 64 | #define DRAM_EXT_WR_MODE1_REG 0x8400000118 |
| 65 | #define DRAM_EXT_WR_MODE3_REG 0x8400000120 |
| 66 | #define DRAM_8_BANK_MODE_REG 0x8400000128 |
| 67 | #define DRAM_CHANNEL_DISABLED_REG 0x8400000138 |
| 68 | #define DRAM_SEL_LO_ADDR_BITS_REG 0x8400000140 |
| 69 | #define DRAM_SNG_CHANNEL_MODE_REG 0x8400000148 |
| 70 | #define DRAM_DIMM_INIT_REG 0x84000001a0 |
| 71 | #define DRAM_MODE_WRITE_STATUS_REG 0x8400000208 |
| 72 | #define DRAM_INIT_STATUS_REG 0x8400000210 |
| 73 | #define DRAM_DIMM_PRESENT_REG 0x8400000218 |
| 74 | #define DRAM_FAILOVER_STATUS_REG 0x8400000220 |
| 75 | #define DRAM_FAILOVER_MASK_REG 0x8400000228 |
| 76 | #define DRAM_DEBUG_TRIG_ENABLE_REG 0x8400000230 |
| 77 | #define DRAM_POWER_DOWN_MODE_REG 0x8400000238 |
| 78 | #define DRAM_ERROR_STATUS_REG 0x8400000280 |
| 79 | #define DRAM_ERROR_ADDR_REG 0x8400000288 |
| 80 | #define DRAM_ERROR_INJECT_REG 0x8400000290 |
| 81 | #define DRAM_ERROR_COUNTER_REG 0x8400000298 |
| 82 | #define DRAM_ERROR_LOCATION_REG 0x84000002a0 |
| 83 | #define DRAM_PERF_CTL_REG 0x8400000400 |
| 84 | #define DRAM_PERF_COUNT_REG 0x8400000408 |
| 85 | #define FBD_CHANNEL_STATE_REG 0x8400000800 |
| 86 | #define FAST_RESET_FLAG_REG 0x8400000808 |
| 87 | #define CHANNEL_RESET_REG 0x8400000810 |
| 88 | #define TS1_SB_NB_MAPPING_REG 0x8400000818 |
| 89 | #define TS1_TEST_PARAMETER_REG 0x8400000820 |
| 90 | #define TS3_FAILOVER_CONFIG_REG 0x8400000828 |
| 91 | #define ELECTRICAL_IDLE_DETECTED_REG 0x8400000830 |
| 92 | #define DISABLE_STATE_PERIOD_REG 0x8400000838 |
| 93 | #define DISABLE_STATE_PERIOD_DONE_REG 0x8400000840 |
| 94 | #define CALIBRATE_STATE_PERIOD_REG 0x8400000848 |
| 95 | #define CALIBRATE_STATE_PERIOD_DONE_REG 0x8400000850 |
| 96 | #define TRAINING_STATE_MIN_TIME_REG 0x8400000858 |
| 97 | #define TRAINING_STATE_DONE_REG 0x8400000860 |
| 98 | #define TRAINING_STATE_TIMEOUT_REG 0x8400000868 |
| 99 | #define TESTING_STATE_DONE_REG 0x8400000870 |
| 100 | #define TESTING_STATE_TIMEOUT_REG 0x8400000878 |
| 101 | #define POLLING_STATE_DONE_REG 0x8400000880 |
| 102 | #define POLLING_STATE_TIMEOUT_REG 0x8400000888 |
| 103 | #define CONFIG_STATE_DONE_REG 0x8400000890 |
| 104 | #define CONFIG_STATE_TIMEOUT_PERIOD_REG 0x8400000898 |
| 105 | #define DRAM_PER_RANK_CKE_REG 0x84000008A0 |
| 106 | #define LOS_DURATION_REG 0x84000008A8 |
| 107 | #define SYNC_FRAME_FREQ_REG 0x84000008B0 |
| 108 | #define CHANNEL_READ_LATENCY_REG 0x84000008B8 |
| 109 | #define CHANNEL_CAPABILITY_REG 0x84000008C0 |
| 110 | #define LOOPBACK_MODE_CTRL_REG 0x84000008C8 |
| 111 | #define SERDES_CONFIG_BUS_REG 0x84000008D0 |
| 112 | #define SERDES_XMT_RCV_DIFF_INV_REG 0x84000008D8 |
| 113 | #define CONFIG_REG_ACCESS_ADDRESS_REG 0x8400000900 |
| 114 | #define CONFIG_REG_ACCESS_DATA_REG 0x8400000908 |
| 115 | #define MCU_SYNDROME_REG 0x8400000C00 |
| 116 | #define INJ_ERR_SOURCE_REG 0x8400000C08 |
| 117 | #define MCU_FBR_COUNT_REG 0x8400000C10 |
| 118 | |
| 119 | ! FBD_CHANNEL_STATE_REG 0x8400000800 ! new |
| 120 | ! FAST_RESET_FLAG_REG 0x8400000808 ! new |
| 121 | ! CHANNEL_RESET_REG 0x8400000810 ! new |
| 122 | ! TS1_SB_NB_MAPPING_REG 0x8400000818 ! new |
| 123 | ! TS1_TEST_PARAMETER_REG 0x8400000820 ! new |
| 124 | ! TS3_FAILOVER_CONFIG_REG 0x8400000828 ! new |
| 125 | ! ELECTRICAL_IDLE_DETECTED_REG 0x8400000830 ! new read only |
| 126 | ! DISABLE_STATE_PERIOD_REG 0x8400000838 ! new |
| 127 | ! DISABLE_STATE_PERIOD_DONE_REG 0x8400000840 ! new read only |
| 128 | ! CALIBRATE_STATE_PERIOD_REG 0x8400000848 ! new |
| 129 | ! CALIBRATE_STATE_PERIOD_DONE_REG 0x8400000850 ! new read only |
| 130 | ! TRAINING_STATE_MIN_TIME_REG 0x8400000858 ! new |
| 131 | ! TRAINING_STATE_DONE_REG 0x8400000860 ! new |
| 132 | ! TRAINING_STATE_TIMEOUT_REG 0x8400000868 ! new |
| 133 | ! TESTING_STATE_DONE_REG 0x8400000870 ! new |
| 134 | ! TESTING_STATE_TIMEOUT_REG 0x8400000878 ! new |
| 135 | ! POLLING_STATE_DONE_REG 0x8400000880 ! new |
| 136 | ! POLLING_STATE_TIMEOUT_REG 0x8400000888 ! new |
| 137 | ! CONFIG_STATE_DONE_REG 0x8400000890 ! new |
| 138 | ! CONFIG_STATE_TIMEOUT_PERIOD_REG 0x8400000898 ! new |
| 139 | ! DRAM_PER_RANK_CKE_REG 0x84000008A0 ! new |
| 140 | ! LOS_DURATION_REG 0x84000008A8 ! new |
| 141 | ! SYNC_FRAME_FREQ_REG 0x84000008B0 ! new |
| 142 | ! CHANNEL_READ_LATENCY_REG 0x84000008B8 ! new |
| 143 | ! CHANNEL_CAPABILITY_REG 0x84000008C0 ! new read only |
| 144 | ! LOOPBACK_MODE_CTRL_REG 0x84000008C8 ! new |
| 145 | ! SERDES_CONFIG_BUS_REG 0x84000008D0 ! new |
| 146 | ! SERDES_XMT_RCV_DIFF_INV_REG 0x84000008D8 ! new |
| 147 | ! CONFIG_REG_ACCESS_ADDRESS_REG 0x8400000900 ! new |
| 148 | ! CONFIG_REG_ACCESS_DATA_REG 0x8400000908 ! new |
| 149 | ! MCU_SYNDROME_REG 0x8400000C00 ! new |
| 150 | ! INJ_ERR_SOURCE_REG 0x8400000C08 ! new |
| 151 | ! MCU_FBR_COUNT_REG 0x8400000C10 ! new |