| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: niu_macros.h |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #ifndef ALREADY_INCLUDED_NIU_MACROS_DOT_H |
| 39 | #define ALREADY_INCLUDED_NIU_MACROS_DOT_H |
| 40 | |
| 41 | |
| 42 | |
| 43 | /**************************************************************** |
| 44 | * Objective: |
| 45 | * Set up to allow an interrupt on transmit frame completion of |
| 46 | * a marked frame. The registers LD_IM0, LDGIMGN, LDGITMRES, |
| 47 | * SID and TX_ENT_MSK are programmed. |
| 48 | * |
| 49 | * Syntax: |
| 50 | * NIU_TX_LD_IM0_INTR_ON_MARK( |
| 51 | * tx_dma_channel, tmp_reg_1, tmp_reg_2, tmp_reg_3, |
| 52 | * tmp_reg_4, ldg_number, device_number |
| 53 | * ) |
| 54 | * |
| 55 | * Args: |
| 56 | * tx_dma_channel -> NIU Tx DMA channel # to use, 0 to 15. |
| 57 | * tmp_reg_1/2/3/4 -> temporary registers |
| 58 | * ldg_number -> number of logical device group to use. |
| 59 | * device_number -> device number to send to NCU, NOT logical |
| 60 | * number nor logical group device number. |
| 61 | * |
| 62 | */ |
| 63 | |
| 64 | define(NIU_TX_LD_IM0_INTR_ON_MARK,` |
| 65 | mov $1, $5 |
| 66 | add $5, 32, $5 |
| 67 | mov $5, $2 |
| 68 | setx LD_IM0_STEP, $3, $4 |
| 69 | mulx $2, $4, $2 |
| 70 | setx LD_IM0, $3, $4 |
| 71 | add $4, $2, $4 |
| 72 | stxa %g0, [$4]ASI_PRIMARY_LITTLE |
| 73 | 1: |
| 74 | mov $5, $2 |
| 75 | setx LDG_NUM_STEP, $3, $4 |
| 76 | mulx $2, $4, $2 |
| 77 | setx LDG_NUM, $3, $4 |
| 78 | add $4, $2, $4 |
| 79 | setx $6, $3, $2 |
| 80 | stxa $2, [$4]ASI_PRIMARY_LITTLE |
| 81 | 2: |
| 82 | setx $6, $3, $2 |
| 83 | setx LDGIMGN_STEP, $3, $5 |
| 84 | mulx $2, $5, $2 |
| 85 | setx LDGIMGN, $3, $4 |
| 86 | add $4, $2, $4 |
| 87 | setx 0x80000001, $3, $2 |
| 88 | stxa $2, [$4]ASI_PRIMARY_LITTLE |
| 89 | 3: |
| 90 | setx LDGITMRES, $3, $4 |
| 91 | set 1, $2 |
| 92 | stxa $2, [$4]ASI_PRIMARY_LITTLE |
| 93 | 4: |
| 94 | setx SID_STEP, $3, $2 |
| 95 | mulx $2, $6, $2 |
| 96 | setx SID, $3, $4 |
| 97 | add $4, $2, $4 |
| 98 | setx $7, $2, $3 |
| 99 | stxa $3, [$4]ASI_PRIMARY_LITTLE |
| 100 | 5: |
| 101 | mov $1, $5 |
| 102 | sllx $5, 9, $5 |
| 103 | setx TX_ENT_MSK, $3, $4 |
| 104 | add $4, $5, $4 |
| 105 | stxa %g0, [$4]ASI_PRIMARY_LITTLE |
| 106 | membar #Sync |
| 107 | ') |
| 108 | |
| 109 | define(NIU_RX_LD_IM0_INTR_ON_MARK,` |
| 110 | mov $1, $5 |
| 111 | add $5, 0, $5 |
| 112 | mov $5, $2 |
| 113 | setx LD_IM0_STEP, $3, $4 |
| 114 | mulx $2, $4, $2 |
| 115 | setx LD_IM0, $3, $4 |
| 116 | add $4, $2, $4 |
| 117 | stxa %g0, [$4]ASI_PRIMARY_LITTLE |
| 118 | 1: |
| 119 | mov $5, $2 |
| 120 | setx LDG_NUM_STEP, $3, $4 |
| 121 | mulx $2, $4, $2 |
| 122 | setx LDG_NUM, $3, $4 |
| 123 | add $4, $2, $4 |
| 124 | setx $6, $3, $2 |
| 125 | stxa $2, [$4]ASI_PRIMARY_LITTLE |
| 126 | 2: |
| 127 | setx $6, $3, $2 |
| 128 | setx LDGIMGN_STEP, $3, $5 |
| 129 | mulx $2, $5, $2 |
| 130 | setx LDGIMGN, $3, $4 |
| 131 | add $4, $2, $4 |
| 132 | setx 0x80000001, $3, $2 |
| 133 | stxa $2, [$4]ASI_PRIMARY_LITTLE |
| 134 | 3: |
| 135 | setx LDGITMRES, $3, $4 |
| 136 | set 1, $2 |
| 137 | stxa $2, [$4]ASI_PRIMARY_LITTLE |
| 138 | 4: |
| 139 | setx SID_STEP, $3, $2 |
| 140 | mulx $2, $6, $2 |
| 141 | setx SID, $3, $4 |
| 142 | add $4, $2, $4 |
| 143 | setx $7, $2, $3 |
| 144 | stxa $3, [$4]ASI_PRIMARY_LITTLE |
| 145 | 5: |
| 146 | mov $1, $5 |
| 147 | mulx $5, RX_DMA_CTL_STAT_STEP, $5 |
| 148 | setx RX_DMA_ENT_MSK, $3, $4 |
| 149 | add $4, $5, $4 |
| 150 | ldxa [$4]ASI_PRIMARY_LITTLE, $2 |
| 151 | setx THRES_MASK, $3, $8 |
| 152 | and $2, $8, $2 |
| 153 | stxa $2, [$4]ASI_PRIMARY_LITTLE |
| 154 | |
| 155 | setx RX_DMA_CTL_STAT, $3, $4 |
| 156 | setx THRES_INT, $3, $8 |
| 157 | add $4, $5, $4 |
| 158 | ldxa [$4]ASI_PRIMARY_LITTLE, $2 |
| 159 | or $2, $8, $2 |
| 160 | stxa $2, [$4]ASI_PRIMARY_LITTLE |
| 161 | |
| 162 | /* |
| 163 | setx RCRCFIG_B, $3, $4 |
| 164 | ldxa [$4]ASI_PRIMARY_LITTLE, $2 |
| 165 | mov $2, $8 |
| 166 | srlx $2, 32, $2 |
| 167 | sllx $2, 16, $2 |
| 168 | set RXMAC_PKTCNT, $3 |
| 169 | sub $3, 1, $3 |
| 170 | add $2, $3, $2 |
| 171 | sllx $2, 16, $2 |
| 172 | setx 0x000000000000ffff, $3, $5 |
| 173 | and $8, $5, $8 |
| 174 | add $2, $8, $2 |
| 175 | stxa $2, [$4]ASI_PRIMARY_LITTLE |
| 176 | |
| 177 | */ |
| 178 | |
| 179 | membar #Sync |
| 180 | ') |
| 181 | |
| 182 | /**************************************************************** |
| 183 | * Objective: |
| 184 | * Set up to allow an interrupt on transmit packet completion |
| 185 | * from the MAC. The register TxMAC Mask, xtxmac_stat_msk, is programmed. |
| 186 | * |
| 187 | * Syntax: |
| 188 | * NIU_TX_MAC_COMPL_INTR ( |
| 189 | * mac_port, tmp_reg_2, tmp_reg_3 |
| 190 | * ) |
| 191 | * |
| 192 | * Args: |
| 193 | * mac_port -> 0 = MAC port 0, 1 = MAC port 1 |
| 194 | * tmp_reg_2/3 -> temporary registers |
| 195 | * |
| 196 | */ |
| 197 | |
| 198 | define(NIU_TX_MAC_COMPL_INTR,` |
| 199 | set $1, $2 |
| 200 | cmp $2, 0 |
| 201 | bne 1f |
| 202 | nop |
| 203 | setx xtxmac_stat_msk0_addr, $2, $3 |
| 204 | ba 2f |
| 205 | nop |
| 206 | 1: |
| 207 | setx xtxmac_stat_msk1_addr, $2, $3 |
| 208 | 2: |
| 209 | stxa %g0, [$3]ASI_PRIMARY_LITTLE |
| 210 | membar #Sync |
| 211 | ') |
| 212 | |
| 213 | |
| 214 | /**************************************************************** |
| 215 | * Objective: |
| 216 | * Set up to allow an interrupt on receive packet completion |
| 217 | * from the MAC. The register RxMAC Mask, xrxmac_stat_msk, is programmed. |
| 218 | * |
| 219 | * Syntax: |
| 220 | * NIU_RX_MAC_COMPL_INTR ( |
| 221 | * mac_port, tmp_reg_2, tmp_reg_3 |
| 222 | * ) |
| 223 | * |
| 224 | * Args: |
| 225 | * mac_port -> 0 = MAC port 0, 1 = MAC port 1 |
| 226 | * tmp_reg_2/3 -> temporary registers |
| 227 | * |
| 228 | */ |
| 229 | |
| 230 | define(NIU_RX_MAC_COMPL_INTR,` |
| 231 | set $1, $2 |
| 232 | cmp $2, 0 |
| 233 | bne 1f |
| 234 | nop |
| 235 | setx xrxmac_stat_msk0_addr, $2, $3 |
| 236 | ba 2f |
| 237 | nop |
| 238 | 1: |
| 239 | setx xrxmac_stat_msk1_addr, $2, $3 |
| 240 | 2: |
| 241 | stxa %g0, [$3]ASI_PRIMARY_LITTLE |
| 242 | membar #Sync |
| 243 | ') |
| 244 | |
| 245 | |
| 246 | /**************************************************************** |
| 247 | * Objective: |
| 248 | * Set up to allow an interrupt receive channel configuration logical |
| 249 | * page violation error. The registers LD_IM0, LDGNUM, LDGIMGN, LDGITMRES, |
| 250 | * SID, RXDMA_CFIG1 and RX_DMA_ENT_MSK are programmed. |
| 251 | * |
| 252 | * Syntax: |
| 253 | * NIU_RX_DMA_INTR_ON_CFIGLOGPAGE ( |
| 254 | * rx_dma_channel, ldg_number, device_number, tmp_reg_1, |
| 255 | * tmp_reg_2, tmp_reg_3, tmp_reg_4 ) |
| 256 | * ) |
| 257 | * |
| 258 | * Args: |
| 259 | * rx_dma_channel -> NIU Rx DMA channel #, 0 to 15, aka logical device number. |
| 260 | * ldg_number -> number of logical device group to use. |
| 261 | * device_number -> device number to send to NCU, NOT logical |
| 262 | * number nor logical group device number. |
| 263 | * tmp_reg_1/2/3/4 -> 4 temporary registers |
| 264 | * |
| 265 | */ |
| 266 | |
| 267 | define(NIU_RX_DMA_INTR_ON_CFIGLOGPAGE,` |
| 268 | setx LD_IM0, $4, $5 |
| 269 | setx LD_IM0_STEP, $4, $6 |
| 270 | mulx $6, $1, $6 |
| 271 | add $5, $6, $5 |
| 272 | stxa %g0, [$5]ASI_PRIMARY_LITTLE |
| 273 | 1: |
| 274 | setx LDG_NUM, $4, $5 |
| 275 | setx LDG_NUM_STEP, $4, $6 |
| 276 | mulx $6, $1, $6 |
| 277 | add $5, $6, $5 |
| 278 | mov $2, $7 |
| 279 | stxa $7, [$5]ASI_PRIMARY_LITTLE |
| 280 | 2: |
| 281 | setx LDGIMGN, $4, $5 |
| 282 | setx LDGIMGN_STEP, $4, $6 |
| 283 | mulx $6, $2, $6 |
| 284 | add $5, $6, $5 |
| 285 | setx 0x80000001, $4, $7 |
| 286 | stxa $7, [$5]ASI_PRIMARY_LITTLE |
| 287 | 3: |
| 288 | setx LDGITMRES, $4, $5 |
| 289 | set 1, $6 |
| 290 | stxa $6, [$5]ASI_PRIMARY_LITTLE |
| 291 | 4: |
| 292 | setx SID, $4, $5 |
| 293 | setx SID_STEP, $4, $6 |
| 294 | mulx $6, $2, $6 |
| 295 | add $5, $6, $5 |
| 296 | mov $3, $7 |
| 297 | stxa $7, [$5]ASI_PRIMARY_LITTLE |
| 298 | 5: |
| 299 | setx RX_DMA_ENT_MSK, $4, $5 |
| 300 | setx RX_DMA_CTL_STAT_STEP, $4, $6 |
| 301 | mulx $6, $1, $6 |
| 302 | add $5, $6, $5 |
| 303 | stxa %g0, [$5]ASI_PRIMARY_LITTLE |
| 304 | membar #Sync |
| 305 | ') |
| 306 | |
| 307 | |
| 308 | |
| 309 | /* following endif needs to be at very bottom -- 6/27/05 */ |
| 310 | #endif |