| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: FcNiuBasicTx.p0.xpcs.lback.cmp.NO_EV.NO_FC.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define MAIN_PAGE_HV_ALSO |
| 39 | |
| 40 | #include "hboot.s" |
| 41 | #include "niu_defines.h" |
| 42 | |
| 43 | /**********************************************************************************************/ |
| 44 | #define POLL_DELAY_VALUE 0xc00 /* 0x1000=4096; 0x800=2048; 0x400=1024; 0x200=512 */ |
| 45 | |
| 46 | #define addr_MIF_CONFIG mpeval(0x8100196020) /* 1 */ |
| 47 | #define addr_MIF_FRAME_OUTPUT_REG mpeval(0x8100196018) /* 2 */ |
| 48 | #define addr_XMAC_0_CONFIG mpeval(0x8100180060) /* 44 */ |
| 49 | #define addr_XMAC_0_TxSftRst mpeval(0x8100180000) /* 45 */ |
| 50 | #define addr_XMAC_0_RxSftRst mpeval(0x8100180008) /* 46 */ |
| 51 | #define addr_XMAC_0_RxMac_Hist_Cnt1 mpeval(0x8100180120) /* 47 */ |
| 52 | #define addr_XMAC_0_RxMac_Hist_Cnt2 mpeval(0x8100180128) /* 48 */ |
| 53 | #define addr_XMAC_0_RxMac_Hist_Cnt3 mpeval(0x8100180130) /* 49 */ |
| 54 | #define addr_XMAC_0_RxMac_Hist_Cnt4 mpeval(0x8100180138) /* 50 */ |
| 55 | #define addr_XMAC_0_RxMac_Hist_Cnt5 mpeval(0x8100180140) /* 51 */ |
| 56 | #define addr_XMAC_0_RxMac_Hist_Cnt6 mpeval(0x8100180148) /* 52 */ |
| 57 | #define addr_XMAC_0_RxMac_Hist_Cnt7 mpeval(0x8100180188) /* 53 */ |
| 58 | #define addr_XMAC_0_BASE10G_CONTROL1 mpeval(0x8100182000) /* 55 */ |
| 59 | #define addr_XMAC_1_BASE10G_CONTROL1 mpeval(0x8100188000) /* 56 */ |
| 60 | #define addr_IPP_CFIG_0 mpeval(0x8100280000) /* 57 */ |
| 61 | #define addr_TXC_CONTROL mpeval(0x81007a0000) /* 58 */ |
| 62 | #define addr_RDC_TaBLe mpeval(0x8100590000) /* 60 */ |
| 63 | #define addr_RBR_CFIG_B_0 mpeval(0x8100600018) /* 61 */ |
| 64 | #define addr_RX_LOG_MASK1_0 mpeval(0x81006a0008) /* 62 */ |
| 65 | #define addr_RX_LOG_VAL1_0 mpeval(0x81006a0010) /* 63 */ |
| 66 | #define addr_RX_LOG_PAGE_RELO1_0 mpeval(0x81006a0028) /* 64 */ |
| 67 | #define addr_RX_LOG_MASK2_0 mpeval(0x81006a0018) /* 65 */ |
| 68 | #define addr_RX_LOG_VAL2_0 mpeval(0x81006a0020) /* 66 */ |
| 69 | #define addr_RX_LOG_PAGE_RELO2_0 mpeval(0x81006a0030) /* 67 */ |
| 70 | #define addr_RX_LOG_PAGE_VLD_0 mpeval(0x81006a0000) /* 68 */ |
| 71 | #define addr_RBR_CFIG_A_0 mpeval(0x8100600010) /* 69 */ |
| 72 | #define addr_RCRCFIG_A_0 mpeval(0x8100600040) /* 70 */ |
| 73 | #define addr_RXDMA_CFIG1_0 mpeval(0x8100600000) /* 71 */ |
| 74 | #define addr_RXDMA_CFIG2_0 mpeval(0x8100600008) /* 72 */ |
| 75 | #define addr_RED_RANdom_INIT mpeval(0x8100680068) /* 74 */ |
| 76 | #define addr_RDC_RED_PARAmeter_0 mpeval(0x81006b0000) /* 75 */ |
| 77 | #define addr_RBR_KICK_0 mpeval(0x8100600020) /* 76 */ |
| 78 | #define addr_XMAC_0_ADDR3_da mpeval(0x8100180218) /* 77 */ |
| 79 | #define addr_XMAC_0_ADDR4_da mpeval(0x8100180220) /* 78 */ |
| 80 | #define addr_XMAC_0_ADDR5_da mpeval(0x8100180228) /* 79 */ |
| 81 | #define addr_TXC_PORT_DMA_enable mpeval(0x81007a0028) /* 81 */ |
| 82 | #define addr_TX_LOG_PAGE_VLD_0 mpeval(0x81006c0000) /* 82 */ |
| 83 | #define addr_TX_LOG_MASK1_0 mpeval(0x81006c0008) /* 83 */ |
| 84 | #define addr_TXC_DMA_MAX_burst_0 mpeval(0x8100780000) /* 84 */ |
| 85 | #define addr_TX_LOG_PAGE_VLD_1 mpeval(0x81006c0200) /* 85 */ |
| 86 | #define addr_TX_LOG_MASK1_1 mpeval(0x81006c0208) /* 86 */ |
| 87 | #define addr_TXC_DMA_MAX_burst_1 mpeval(0x8100781000) /* 87 */ |
| 88 | #define addr_TX_LOG_PAGE_VLD_2 mpeval(0x81006c0400) /* 88 */ |
| 89 | #define addr_TX_LOG_MASK1_2 mpeval(0x81006c0408) /* 89 */ |
| 90 | #define addr_TXC_DMA_MAX_burst_2 mpeval(0x8100782000) /* 90 */ |
| 91 | #define addr_TX_LOG_PAGE_VLD_3 mpeval(0x81006c0600) /* 91 */ |
| 92 | #define addr_TX_LOG_MASK1_3 mpeval(0x81006c0608) /* 92 */ |
| 93 | #define addr_TXC_DMA_MAX_burst_3 mpeval(0x8100783000) /* 93 */ |
| 94 | #define addr_TX_LOG_PAGE_VLD_4 mpeval(0x81006c0800) /* 94 */ |
| 95 | #define addr_TX_LOG_MASK1_4 mpeval(0x81006c0808) /* 95 */ |
| 96 | #define addr_TXC_DMA_MAX_burst_4 mpeval(0x8100784000) /* 96 */ |
| 97 | #define addr_TX_LOG_PAGE_VLD_5 mpeval(0x81006c0a00) /* 97 */ |
| 98 | #define addr_TX_LOG_MASK1_5 mpeval(0x81006c0a08) /* 98 */ |
| 99 | #define addr_TXC_DMA_MAX_burst_5 mpeval(0x8100785000) /* 99 */ |
| 100 | #define addr_TX_LOG_PAGE_VLD_6 mpeval(0x81006c0c00) /* 100 */ |
| 101 | #define addr_TX_LOG_MASK1_6 mpeval(0x81006c0c08) /* 101 */ |
| 102 | #define addr_TXC_DMA_MAX_burst_6 mpeval(0x8100786000) /* 102 */ |
| 103 | #define addr_TX_LOG_PAGE_VLD_7 mpeval(0x81006c0e00) /* 103 */ |
| 104 | #define addr_TX_LOG_MASK1_7 mpeval(0x81006c0e08) /* 104 */ |
| 105 | #define addr_TXC_DMA_MAX_burst_7 mpeval(0x8100787000) /* 105 */ |
| 106 | #define addr_TX_LOG_PAGE_VLD_8 mpeval(0x81006c1000) /* 106 */ |
| 107 | #define addr_TX_LOG_MASK1_8 mpeval(0x81006c1008) /* 107 */ |
| 108 | #define addr_TXC_DMA_MAX_burst_8 mpeval(0x8100788000) /* 108 */ |
| 109 | #define addr_TX_LOG_PAGE_VLD_9 mpeval(0x81006c1200) /* 109 */ |
| 110 | #define addr_TX_LOG_MASK1_9 mpeval(0x81006c1208) /* 110 */ |
| 111 | #define addr_TXC_DMA_MAX_burst_9 mpeval(0x8100789000) /* 111 */ |
| 112 | #define addr_TX_LOG_PAGE_VLD_a mpeval(0x81006c1400) /* 112 */ |
| 113 | #define addr_TX_LOG_MASK1_a mpeval(0x81006c1408) /* 113 */ |
| 114 | #define addr_TXC_DMA_MAX_burst_a mpeval(0x810078a000) /* 114 */ |
| 115 | #define addr_TX_LOG_PAGE_VLD_b mpeval(0x81006c1600) /* 115 */ |
| 116 | #define addr_TX_LOG_MASK1_b mpeval(0x81006c1608) /* 116 */ |
| 117 | #define addr_TXC_DMA_MAX_burst_b mpeval(0x810078b000) /* 117 */ |
| 118 | #define addr_TX_LOG_PAGE_VLD_c mpeval(0x81006c1800) /* 118 */ |
| 119 | #define addr_TX_LOG_MASK1_c mpeval(0x81006c1808) /* 119 */ |
| 120 | #define addr_TXC_DMA_MAX_burst_c mpeval(0x810078c000) /* 120 */ |
| 121 | #define addr_TX_LOG_PAGE_VLD_d mpeval(0x81006c1a00) /* 121 */ |
| 122 | #define addr_TX_LOG_MASK1_d mpeval(0x81006c1a08) /* 122 */ |
| 123 | #define addr_TXC_DMA_MAX_burst_d mpeval(0x810078d000) /* 123 */ |
| 124 | #define addr_TX_LOG_PAGE_VLD_e mpeval(0x81006c1c00) /* 124 */ |
| 125 | #define addr_TX_LOG_MASK1_e mpeval(0x81006c1c08) /* 125 */ |
| 126 | #define addr_TXC_DMA_MAX_burst_e mpeval(0x810078e000) /* 126 */ |
| 127 | #define addr_TX_LOG_PAGE_VLD_f mpeval(0x81006c1e00) /* 127 */ |
| 128 | #define addr_TX_LOG_MASK1_f mpeval(0x81006c1e08) /* 128 */ |
| 129 | #define addr_TXC_DMA_MAX_burst_f mpeval(0x810078f000) /* 129 */ |
| 130 | #define addr_TX_RNG_CFIG_0 mpeval(0x8100640000) /* 130 */ |
| 131 | #define addr_TX_RING_KICK_0 mpeval(0x8100640018) /* 131 */ |
| 132 | #define addr_TX_CS_0 mpeval(0x8100640028) /* 132 */ |
| 133 | |
| 134 | #define data_xpcs0_init_001 0x0000000000008008 /* MIF_CONFIG */ /* 1 */ |
| 135 | #define data_xpcs0_init_002 0x00000000007a8000 /* MIF_FRAME_OUTPUT_REG */ /* 2 */ |
| 136 | #define data_xpcs0_init_003 0x00000000107a0003 /* MIF_FRAME_OUTPUT_REG */ /* 3 */ |
| 137 | #define data_xpcs0_init_004 0x00000000007a8000 /* MIF_FRAME_OUTPUT_REG */ /* 4 */ |
| 138 | #define data_xpcs0_init_005 0x00000000207a0003 /* MIF_FRAME_OUTPUT_REG */ /* 5 */ |
| 139 | #define data_xpcs0_init_006 0x00000000007a8001 /* MIF_FRAME_OUTPUT_REG */ /* 6 */ |
| 140 | #define data_xpcs0_init_007 0x00000000107a0000 /* MIF_FRAME_OUTPUT_REG */ /* 7 */ |
| 141 | #define data_xpcs0_init_008 0x00000000007a8004 /* MIF_FRAME_OUTPUT_REG */ /* 8 */ |
| 142 | #define data_xpcs0_init_009 0x00000000107a0000 /* MIF_FRAME_OUTPUT_REG */ /* 9 */ |
| 143 | #define data_xpcs0_init_010 0x00000000007a8005 /* MIF_FRAME_OUTPUT_REG */ /* 10 */ |
| 144 | #define data_xpcs0_init_011 0x00000000107a0000 /* MIF_FRAME_OUTPUT_REG */ /* 11 */ |
| 145 | #define data_xpcs0_init_012 0x00000000007a8100 /* MIF_FRAME_OUTPUT_REG */ /* 12 */ |
| 146 | #define data_xpcs0_init_013 0x00000000107a0001 /* MIF_FRAME_OUTPUT_REG */ /* 13 */ |
| 147 | #define data_xpcs0_init_014 0x00000000007a8101 /* MIF_FRAME_OUTPUT_REG */ /* 14 */ |
| 148 | #define data_xpcs0_init_015 0x00000000107a0000 /* MIF_FRAME_OUTPUT_REG */ /* 15 */ |
| 149 | #define data_xpcs0_init_016 0x00000000007a8104 /* MIF_FRAME_OUTPUT_REG */ /* 16 */ |
| 150 | #define data_xpcs0_init_017 0x00000000107a0001 /* MIF_FRAME_OUTPUT_REG */ /* 17 */ |
| 151 | #define data_xpcs0_init_018 0x00000000007a8105 /* MIF_FRAME_OUTPUT_REG */ /* 18 */ |
| 152 | #define data_xpcs0_init_019 0x00000000107a0000 /* MIF_FRAME_OUTPUT_REG */ /* 19 */ |
| 153 | #define data_xpcs0_init_020 0x00000000007a8108 /* MIF_FRAME_OUTPUT_REG */ /* 20 */ |
| 154 | #define data_xpcs0_init_021 0x00000000107a0001 /* MIF_FRAME_OUTPUT_REG */ /* 21 */ |
| 155 | #define data_xpcs0_init_022 0x00000000007a8109 /* MIF_FRAME_OUTPUT_REG */ /* 22 */ |
| 156 | #define data_xpcs0_init_023 0x00000000107a0000 /* MIF_FRAME_OUTPUT_REG */ /* 23 */ |
| 157 | #define data_xpcs0_init_024 0x00000000007a810c /* MIF_FRAME_OUTPUT_REG */ /* 24 */ |
| 158 | #define data_xpcs0_init_025 0x00000000107a0001 /* MIF_FRAME_OUTPUT_REG */ /* 25 */ |
| 159 | #define data_xpcs0_init_026 0x00000000007a810d /* MIF_FRAME_OUTPUT_REG */ /* 26 */ |
| 160 | #define data_xpcs0_init_027 0x00000000107a0000 /* MIF_FRAME_OUTPUT_REG */ /* 27 */ |
| 161 | #define data_xpcs0_init_028 0x00000000007a8120 /* MIF_FRAME_OUTPUT_REG */ /* 28 */ |
| 162 | #define data_xpcs0_init_029 0x00000000107a5001 /* MIF_FRAME_OUTPUT_REG */ /* 29 */ |
| 163 | #define data_xpcs0_init_030 0x00000000007a8121 /* MIF_FRAME_OUTPUT_REG */ /* 30 */ |
| 164 | #define data_xpcs0_init_031 0x00000000107a0008 /* MIF_FRAME_OUTPUT_REG */ /* 31 */ |
| 165 | #define data_xpcs0_init_032 0x00000000007a8124 /* MIF_FRAME_OUTPUT_REG */ /* 32 */ |
| 166 | #define data_xpcs0_init_033 0x00000000107a5001 /* MIF_FRAME_OUTPUT_REG */ /* 33 */ |
| 167 | #define data_xpcs0_init_034 0x00000000007a8125 /* MIF_FRAME_OUTPUT_REG */ /* 34 */ |
| 168 | #define data_xpcs0_init_035 0x00000000107a0008 /* MIF_FRAME_OUTPUT_REG */ /* 35 */ |
| 169 | #define data_xpcs0_init_036 0x00000000007a8128 /* MIF_FRAME_OUTPUT_REG */ /* 36 */ |
| 170 | #define data_xpcs0_init_037 0x00000000107a5001 /* MIF_FRAME_OUTPUT_REG */ /* 37 */ |
| 171 | #define data_xpcs0_init_038 0x00000000007a8129 /* MIF_FRAME_OUTPUT_REG */ /* 38 */ |
| 172 | #define data_xpcs0_init_039 0x00000000107a0008 /* MIF_FRAME_OUTPUT_REG */ /* 39 */ |
| 173 | #define data_xpcs0_init_040 0x00000000007a812c /* MIF_FRAME_OUTPUT_REG */ /* 40 */ |
| 174 | #define data_xpcs0_init_041 0x00000000107a5001 /* MIF_FRAME_OUTPUT_REG */ /* 41 */ |
| 175 | #define data_xpcs0_init_042 0x00000000007a812d /* MIF_FRAME_OUTPUT_REG */ /* 42 */ |
| 176 | #define data_xpcs0_init_043 0x00000000107a0008 /* MIF_FRAME_OUTPUT_REG */ /* 43 */ |
| 177 | #define data_xpcs0_init_044 0x0000000001000e04 /* XMAC_0_CONFIG */ /* 44 */ |
| 178 | #define data_xpcs0_init_045 0x0000000000000001 /* XMAC_0_TxSftRst */ /* 45 */ |
| 179 | #define data_xpcs0_init_046 0x0000000000000001 /* XMAC_0_RxSftRst */ /* 46 */ |
| 180 | #define data_xpcs0_init_047 0x0000000000000000 /* XMAC_0_RxMac_Hist_Cnt1 */ /* 47 */ |
| 181 | #define data_xpcs0_init_048 0x0000000000000000 /* XMAC_0_RxMac_Hist_Cnt2 */ /* 48 */ |
| 182 | #define data_xpcs0_init_049 0x0000000000000000 /* XMAC_0_RxMac_Hist_Cnt3 */ /* 49 */ |
| 183 | #define data_xpcs0_init_050 0x0000000000000000 /* XMAC_0_RxMac_Hist_Cnt4 */ /* 50 */ |
| 184 | #define data_xpcs0_init_051 0x0000000000000000 /* XMAC_0_RxMac_Hist_Cnt5 */ /* 51 */ |
| 185 | #define data_xpcs0_init_052 0x0000000000000000 /* XMAC_0_RxMac_Hist_Cnt6 */ /* 52 */ |
| 186 | #define data_xpcs0_init_053 0x0000000000000000 /* XMAC_0_RxMac_Hist_Cnt7 */ /* 53 */ |
| 187 | #define data_xpcs0_init_054 0x0000000001000f05 /* XMAC_0_CONFIG */ /* 54 */ |
| 188 | #define data_xpcs0_init_055 0x0000000000008000 /* XMAC_0_BASE10G_CONTROL1 */ /* 55 */ |
| 189 | #define data_xpcs0_init_056 0x0000000000008000 /* XMAC_1_BASE10G_CONTROL1 */ /* 56 */ |
| 190 | #define data_xpcs0_init_057 0x0000000001ffff11 /* IPP_CFIG_0 */ /* 57 */ |
| 191 | #define data_xpcs0_init_058 0x000000000000001f /* TXC_CONTROL */ /* 58 */ |
| 192 | #define data_xpcs0_init_059 0x0000000000006040 /* XMAC_0_BASE10G_CONTROL1 */ /* 59 */ |
| 193 | #define data_xpcs0_init_060 0x0000000000000000 /* RDC_TaBLe */ /* 60 */ |
| 194 | #define data_xpcs0_init_061 0x0000000000808080 /* RBR_CFIG_B_0 */ /* 61 */ |
| 195 | #define data_xpcs0_init_062 0x00000000fffffc00 /* RX_LOG_MASK1_0 */ /* 62 */ |
| 196 | #define data_xpcs0_init_063 0x00000000043fe000 /* RX_LOG_VAL1_0 */ /* 63 */ |
| 197 | #define data_xpcs0_init_064 0x00000000001a6800 /* RX_LOG_PAGE_RELO1_0 */ /* 64 */ |
| 198 | #define data_xpcs0_init_065 0x00000000fffffc00 /* RX_LOG_MASK2_0 */ /* 65 */ |
| 199 | #define data_xpcs0_init_066 0x00000000058d3800 /* RX_LOG_VAL2_0 */ /* 66 */ |
| 200 | #define data_xpcs0_init_067 0x0000000002003c00 /* RX_LOG_PAGE_RELO2_0 */ /* 67 */ |
| 201 | #define data_xpcs0_init_068 0x0000000000000003 /* RX_LOG_PAGE_VLD_0 */ /* 68 */ |
| 202 | #define data_xpcs0_init_069 0x01ff0043fe140000 /* RBR_CFIG_A_0 */ /* 69 */ |
| 203 | #define data_xpcs0_init_070 0x20000043fe200000 /* RCRCFIG_A_0 */ /* 70 */ |
| 204 | #define data_xpcs0_init_071 0x0000000000000043 /* RXDMA_CFIG1_0 */ /* 71 */ |
| 205 | #define data_xpcs0_init_072 0x00000000fe05cf40 /* RXDMA_CFIG2_0 */ /* 72 */ |
| 206 | #define data_xpcs0_init_073 0x0000000080000043 /* RXDMA_CFIG1_0 */ /* 73 */ |
| 207 | #define data_xpcs0_init_074 0x0000000000016512 /* RED_RANdom_INIT */ /* 74 */ |
| 208 | #define data_xpcs0_init_075 0x00000000fe00fe00 /* RDC_RED_PARAmeter_0 */ /* 75 */ |
| 209 | #define data_xpcs0_init_076 0x00000000000000ff /* RBR_KICK_0 */ /* 76 */ |
| 210 | #define data_xpcs0_init_077 0x0000000000000000 /* XMAC_0_ADDR3_da */ /* 77 */ |
| 211 | #define data_xpcs0_init_078 0x000000000000ffff /* XMAC_0_ADDR4_da */ /* 78 */ |
| 212 | #define data_xpcs0_init_079 0x0000000000000100 /* XMAC_0_ADDR5_da */ /* 79 */ |
| 213 | #define data_xpcs0_init_080 0x0000000000000000 /* RDC_TaBLe */ /* 80 */ |
| 214 | #define data_xpcs0_init_081 0x2b96ad2300000001 /* TXC_PORT_DMA_enable */ /* 81 */ |
| 215 | #define data_xpcs0_init_082 0x0000000000000001 /* TX_LOG_PAGE_VLD_0 */ /* 82 */ |
| 216 | #define data_xpcs0_init_083 0x0000000000000000 /* TX_LOG_MASK1_0 */ /* 83 */ |
| 217 | #define data_xpcs0_init_084 0x00000000000001f4 /* TXC_DMA_MAX_burst_0 */ /* 84 */ |
| 218 | #define data_xpcs0_init_085 0x0000000000000001 /* TX_LOG_PAGE_VLD_1 */ /* 85 */ |
| 219 | #define data_xpcs0_init_086 0x0000000000000000 /* TX_LOG_MASK1_1 */ /* 86 */ |
| 220 | #define data_xpcs0_init_087 0x00000000000001f4 /* TXC_DMA_MAX_burst_1 */ /* 87 */ |
| 221 | #define data_xpcs0_init_088 0x0000000000000001 /* TX_LOG_PAGE_VLD_2 */ /* 88 */ |
| 222 | #define data_xpcs0_init_089 0x0000000000000000 /* TX_LOG_MASK1_2 */ /* 89 */ |
| 223 | #define data_xpcs0_init_090 0x00000000000001f4 /* TXC_DMA_MAX_burst_2 */ /* 90 */ |
| 224 | #define data_xpcs0_init_091 0x0000000000000001 /* TX_LOG_PAGE_VLD_3 */ /* 91 */ |
| 225 | #define data_xpcs0_init_092 0x0000000000000000 /* TX_LOG_MASK1_3 */ /* 92 */ |
| 226 | #define data_xpcs0_init_093 0x00000000000001f4 /* TXC_DMA_MAX_burst_3 */ /* 93 */ |
| 227 | #define data_xpcs0_init_094 0x0000000000000001 /* TX_LOG_PAGE_VLD_4 */ /* 94 */ |
| 228 | #define data_xpcs0_init_095 0x0000000000000000 /* TX_LOG_MASK1_4 */ /* 95 */ |
| 229 | #define data_xpcs0_init_096 0x00000000000001f4 /* TXC_DMA_MAX_burst_4 */ /* 96 */ |
| 230 | #define data_xpcs0_init_097 0x0000000000000001 /* TX_LOG_PAGE_VLD_5 */ /* 97 */ |
| 231 | #define data_xpcs0_init_098 0x0000000000000000 /* TX_LOG_MASK1_5 */ /* 98 */ |
| 232 | #define data_xpcs0_init_099 0x00000000000001f4 /* TXC_DMA_MAX_burst_5 */ /* 99 */ |
| 233 | #define data_xpcs0_init_100 0x0000000000000001 /* TX_LOG_PAGE_VLD_6 */ /* 100 */ |
| 234 | #define data_xpcs0_init_101 0x0000000000000000 /* TX_LOG_MASK1_6 */ /* 101 */ |
| 235 | #define data_xpcs0_init_102 0x00000000000001f4 /* TXC_DMA_MAX_burst_6 */ /* 102 */ |
| 236 | #define data_xpcs0_init_103 0x0000000000000001 /* TX_LOG_PAGE_VLD_7 */ /* 103 */ |
| 237 | #define data_xpcs0_init_104 0x0000000000000000 /* TX_LOG_MASK1_7 */ /* 104 */ |
| 238 | #define data_xpcs0_init_105 0x00000000000001f4 /* TXC_DMA_MAX_burst_7 */ /* 105 */ |
| 239 | #define data_xpcs0_init_106 0x0000000000000001 /* TX_LOG_PAGE_VLD_8 */ /* 106 */ |
| 240 | #define data_xpcs0_init_107 0x0000000000000000 /* TX_LOG_MASK1_8 */ /* 107 */ |
| 241 | #define data_xpcs0_init_108 0x00000000000001f4 /* TXC_DMA_MAX_burst_8 */ /* 108 */ |
| 242 | #define data_xpcs0_init_109 0x0000000000000001 /* TX_LOG_PAGE_VLD_9 */ /* 109 */ |
| 243 | #define data_xpcs0_init_110 0x0000000000000000 /* TX_LOG_MASK1_9 */ /* 110 */ |
| 244 | #define data_xpcs0_init_111 0x00000000000001f4 /* TXC_DMA_MAX_burst_9 */ /* 111 */ |
| 245 | #define data_xpcs0_init_112 0x0000000000000001 /* TX_LOG_PAGE_VLD_a */ /* 112 */ |
| 246 | #define data_xpcs0_init_113 0x0000000000000000 /* TX_LOG_MASK1_a */ /* 113 */ |
| 247 | #define data_xpcs0_init_114 0x00000000000001f4 /* TXC_DMA_MAX_burst_a */ /* 114 */ |
| 248 | #define data_xpcs0_init_115 0x0000000000000001 /* TX_LOG_PAGE_VLD_b */ /* 115 */ |
| 249 | #define data_xpcs0_init_116 0x0000000000000000 /* TX_LOG_MASK1_b */ /* 116 */ |
| 250 | #define data_xpcs0_init_117 0x00000000000001f4 /* TXC_DMA_MAX_burst_b */ /* 117 */ |
| 251 | #define data_xpcs0_init_118 0x0000000000000001 /* TX_LOG_PAGE_VLD_c */ /* 118 */ |
| 252 | #define data_xpcs0_init_119 0x0000000000000000 /* TX_LOG_MASK1_c */ /* 119 */ |
| 253 | #define data_xpcs0_init_120 0x00000000000001f4 /* TXC_DMA_MAX_burst_c */ /* 120 */ |
| 254 | #define data_xpcs0_init_121 0x0000000000000001 /* TX_LOG_PAGE_VLD_d */ /* 121 */ |
| 255 | #define data_xpcs0_init_122 0x0000000000000000 /* TX_LOG_MASK1_d */ /* 122 */ |
| 256 | #define data_xpcs0_init_123 0x00000000000001f4 /* TXC_DMA_MAX_burst_d */ /* 123 */ |
| 257 | #define data_xpcs0_init_124 0x0000000000000001 /* TX_LOG_PAGE_VLD_e */ /* 124 */ |
| 258 | #define data_xpcs0_init_125 0x0000000000000000 /* TX_LOG_MASK1_e */ /* 125 */ |
| 259 | #define data_xpcs0_init_126 0x00000000000001f4 /* TXC_DMA_MAX_burst_e */ /* 126 */ |
| 260 | #define data_xpcs0_init_127 0x0000000000000001 /* TX_LOG_PAGE_VLD_f */ /* 127 */ |
| 261 | #define data_xpcs0_init_128 0x0000000000000000 /* TX_LOG_MASK1_f */ /* 128 */ |
| 262 | #define data_xpcs0_init_129 0x00000000000001f4 /* TXC_DMA_MAX_burst_f */ /* 129 */ |
| 263 | ! #define data_xpcs0_init_130 0x0ffff0000000001c /* TX_RNG_CFIG_0 */ /* 130 */ |
| 264 | #define data_xpcs0_init_130 0x0ffff00020000000 /* TX_RNG_CFIG_0 */ /* 130 */ |
| 265 | #define data_xpcs0_init_131 0x0007d08a8490000c /* TX_RING_KICK_0 */ /* 131 */ |
| 266 | #define data_xpcs0_init_132 0x0000000000000000 /* TX_CS_0 */ /* 132 */ |
| 267 | /******************************************************************************************************/ |
| 268 | |
| 269 | /*********************************************** ***********************************************/ |
| 270 | !#define addr_IPP_CFIG_0 mpeval(IPP0_BASE + IPP_CONFIG) /*dupli*/ |
| 271 | #define addr_IPP_DFIFO_RD1_0 mpeval(IPP0_BASE + 0x00c0 ) /* 2 */ |
| 272 | #define addr_IPP_DFIFO_RD2_0 mpeval(IPP0_BASE + 0x00c8 ) /* 3 */ |
| 273 | #define addr_IPP_DFIFO_RD3_0 mpeval(IPP0_BASE + 0x00d0 ) /* 4 */ |
| 274 | #define addr_IPP_DFIFO_RD4_0 mpeval(IPP0_BASE + 0x00d8 ) /* 5 */ |
| 275 | #define addr_IPP_DFIFO_RD5_0 mpeval(IPP0_BASE + 0x00e0 ) /* 6 */ |
| 276 | #define addr_IPP_DFIFO_WR1_0 mpeval(IPP0_BASE + 0x00e8 ) /* 7 */ |
| 277 | #define addr_IPP_DFIFO_WR2_0 mpeval(IPP0_BASE + 0x00f0 ) /* 8 */ |
| 278 | #define addr_IPP_DFIFO_WR3_0 mpeval(IPP0_BASE + 0x00f8 ) /* 9 */ |
| 279 | #define addr_IPP_DFIFO_WR4_0 mpeval(IPP0_BASE + 0x0100 ) /* 10 */ |
| 280 | #define addr_IPP_DFIFO_WR5_0 mpeval(IPP0_BASE + 0x0108 ) /* 11 */ |
| 281 | #define addr_IPP_DFIFO_RD_PTR_0 mpeval(IPP0_BASE + 0x0110 ) /* 12 */ |
| 282 | #define addr_IPP_DFIFO_WR_PTR_0 mpeval(IPP0_BASE + 0x0118 ) /* 13 */ |
| 283 | |
| 284 | #define addr_IPP_CFIG_1 mpeval(IPP1_BASE + IPP_CONFIG) /* 1 */ |
| 285 | #define addr_IPP_DFIFO_RD1_1 mpeval(IPP1_BASE + 0x00c0 ) /* 2 */ |
| 286 | #define addr_IPP_DFIFO_RD2_1 mpeval(IPP1_BASE + 0x00c8 ) /* 3 */ |
| 287 | #define addr_IPP_DFIFO_RD3_1 mpeval(IPP1_BASE + 0x00d0 ) /* 4 */ |
| 288 | #define addr_IPP_DFIFO_RD4_1 mpeval(IPP1_BASE + 0x00d8 ) /* 5 */ |
| 289 | #define addr_IPP_DFIFO_RD5_1 mpeval(IPP1_BASE + 0x00e0 ) /* 6 */ |
| 290 | #define addr_IPP_DFIFO_WR1_1 mpeval(IPP1_BASE + 0x00e8 ) /* 7 */ |
| 291 | #define addr_IPP_DFIFO_WR2_1 mpeval(IPP1_BASE + 0x00f0 ) /* 8 */ |
| 292 | #define addr_IPP_DFIFO_WR3_1 mpeval(IPP1_BASE + 0x00f8 ) /* 9 */ |
| 293 | #define addr_IPP_DFIFO_WR4_1 mpeval(IPP1_BASE + 0x0100 ) /* 10 */ |
| 294 | #define addr_IPP_DFIFO_WR5_1 mpeval(IPP1_BASE + 0x0108 ) /* 11 */ |
| 295 | #define addr_IPP_DFIFO_RD_PTR_1 mpeval(IPP1_BASE + 0x0110 ) /* 12 */ |
| 296 | #define addr_IPP_DFIFO_WR_PTR_1 mpeval(IPP1_BASE + 0x0118 ) /* 13 */ |
| 297 | /*----------------------------------------------------------------------------------------------------*/ |
| 298 | /* loopback_dfifo_data.FcNiuBasicTx.s.06.09.2006.B064.Tcp */ |
| 299 | |
| 300 | #define data_conf_df_pio_w 0x01ffff31 /* dfifo_pio_w[5]=1, cksum[4]=1, ipp[0]=1 */ |
| 301 | |
| 302 | #define data_dfifo_reg1_000 0x02e50000 |
| 303 | #define data_dfifo_reg2_000 0x00001540 |
| 304 | #define data_dfifo_reg3_000 0x40000000 |
| 305 | #define data_dfifo_reg4_000 0x00001800 |
| 306 | #define data_dfifo_reg5_000 0x00000001 /* IPP_DFIFO_WR5 */ /* 5 */ |
| 307 | |
| 308 | #ifdef NIU_FORCE_XPCS_ERROR /* force data_dfifo_reg1_001 error, check error detection & EXIT_BAD trap */ |
| 309 | #define data_dfifo_reg1_001 0xaaaaaaaa |
| 310 | #else |
| 311 | #define data_dfifo_reg1_001 0x55555500 |
| 312 | #endif |
| 313 | #define data_dfifo_reg2_001 0x41725555 |
| 314 | #define data_dfifo_reg3_001 0x00003c62 |
| 315 | #define data_dfifo_reg4_001 0x00450008 |
| 316 | #define data_dfifo_reg5_001 0x00000000 /* IPP_DFIFO_WR5 */ /* 5 */ |
| 317 | |
| 318 | #define data_dfifo_reg1_002 0xf2002e00 |
| 319 | #define data_dfifo_reg2_002 0x06400000 |
| 320 | #define data_dfifo_reg3_002 0xf575635d |
| 321 | #define data_dfifo_reg4_002 0xa06f44cb |
| 322 | #define data_dfifo_reg5_002 0x00000000 /* IPP_DFIFO_WR5 */ /* 5 */ |
| 323 | |
| 324 | #define data_dfifo_reg1_003 0xa65a9b6b |
| 325 | #define data_dfifo_reg2_003 0x00003a18 |
| 326 | #define data_dfifo_reg3_003 0x00000000 |
| 327 | #define data_dfifo_reg4_003 0x02500000 |
| 328 | #define data_dfifo_reg5_003 0x00000000 /* IPP_DFIFO_WR5 */ /* 5 */ |
| 329 | |
| 330 | #define data_dfifo_reg1_004 0x851f0000 |
| 331 | #define data_dfifo_reg2_004 0x00000000 |
| 332 | #define data_dfifo_reg3_004 0x02010000 |
| 333 | #define data_dfifo_reg4_004 0x99927958 |
| 334 | #define data_dfifo_reg5_004 0x00000002 /* IPP_DFIFO_WR5 */ /* 5 */ |
| 335 | /******************************************************************************************************/ |
| 336 | |
| 337 | /*********************************************** ***********************************************/ |
| 338 | /* loopback_tx_info.FcNiuBasicTx.s.06.09.2006.B064.Tcp */ |
| 339 | |
| 340 | #define Tx_Descriptor 0x0000042000c00484 /* [43:0] address of the Tx control_header */ |
| 341 | /******** --- addr -- ********/ |
| 342 | |
| 343 | #define Tx_ctrl_header_lo8 0x00003c0019115740 |
| 344 | #define Tx_ctrl_header_hi8 0x0000000000000000 /* 16 byte of the Tx_pkt control_head */ |
| 345 | |
| 346 | #define Tx_pkt_dat_lo8_0001 0x0055555555557241 |
| 347 | #define Tx_pkt_dat_hi8_0001 0x623c000008004500 /* 1st 16 byte of the Tx_pkt raw_data */ |
| 348 | |
| 349 | #define Tx_pkt_dat_lo8_0002 0x002e00f200004006 |
| 350 | #define Tx_pkt_dat_hi8_0002 0x5d6375f5cb446fa0 /* 2nd 16 byte of the Tx_pkt raw_data */ |
| 351 | |
| 352 | #define Tx_pkt_dat_lo8_0003 0x6b9b5aa6183a0000 |
| 353 | #define Tx_pkt_dat_hi8_0003 0x0000000000005002 /* 3rd 16 byte of the Tx_pkt raw_data */ |
| 354 | |
| 355 | #define Tx_pkt_dat_lo8_0004 0x00001c9600000000 |
| 356 | #define Tx_pkt_dat_hi8_0004 0x0000010200000000 /* 4th 16 byte of the Tx_pkt raw_data */ |
| 357 | /******************************************************************************************************/ |
| 358 | |
| 359 | /************************************************************************ |
| 360 | Test case code start |
| 361 | ************************************************************************/ |
| 362 | .text |
| 363 | .global main |
| 364 | |
| 365 | main: |
| 366 | ta T_CHANGE_HPRIV |
| 367 | nop |
| 368 | |
| 369 | ! #include "niu_init.h" |
| 370 | ! |
| 371 | ! Thread 0 Start |
| 372 | ! |
| 373 | ! |
| 374 | ! thread_0: |
| 375 | |
| 376 | /*********************************************** ***********************************************/ |
| 377 | set_L2_DM: |
| 378 | set 0x40000, %l1 ! %l1 -> constant, address space for pkt_data |
| 379 | set 0x2, %l0 |
| 380 | setx 0xa900000000, %l6, %g1 ! %g1 -> L2 Control Status Register |
| 381 | stx %l0, [%g1] |
| 382 | add %g1, %l1, %g1 |
| 383 | stx %l0, [%g1] |
| 384 | add %g1, %l1, %g1 |
| 385 | |
| 386 | Store_TxDescriptor: |
| 387 | setx Tx_Descriptor, %l2, %g2 |
| 388 | set 0x20000000, %g3 ! %g3 -> L2$ address |
| 389 | stx %g2, [%g3] |
| 390 | membar #Sync |
| 391 | |
| 392 | Store_TxControl: |
| 393 | set 0x8, %l2 ! %l2 -> constant, address increment by 8-byte |
| 394 | |
| 395 | setx Tx_ctrl_header_lo8, %l0, %g4 |
| 396 | add %g3, %l1, %g3 ! Tx_data starts at 20040000 |
| 397 | stx %g4, [%g3] |
| 398 | membar #Sync |
| 399 | |
| 400 | setx Tx_ctrl_header_hi8, %l0, %g4 |
| 401 | add %g3, %l2, %g3 |
| 402 | stx %g4, [%g3] |
| 403 | membar #Sync |
| 404 | |
| 405 | Store_TxPktdata: |
| 406 | setx Tx_pkt_dat_lo8_0001, %l0, %g4 |
| 407 | add %g3, %l2, %g3 |
| 408 | stx %g4, [%g3] |
| 409 | membar #Sync |
| 410 | |
| 411 | setx Tx_pkt_dat_hi8_0001, %l0, %g4 |
| 412 | add %g3, %l2, %g3 |
| 413 | stx %g4, [%g3] |
| 414 | membar #Sync |
| 415 | |
| 416 | setx Tx_pkt_dat_lo8_0002, %l0, %g4 |
| 417 | add %g3, %l2, %g3 |
| 418 | stx %g4, [%g3] |
| 419 | membar #Sync |
| 420 | |
| 421 | setx Tx_pkt_dat_hi8_0002, %l0, %g4 |
| 422 | add %g3, %l2, %g3 |
| 423 | stx %g4, [%g3] |
| 424 | membar #Sync |
| 425 | |
| 426 | setx Tx_pkt_dat_lo8_0003, %l0, %g4 |
| 427 | add %g3, %l2, %g3 |
| 428 | stx %g4, [%g3] |
| 429 | membar #Sync |
| 430 | |
| 431 | setx Tx_pkt_dat_hi8_0003, %l0, %g4 |
| 432 | add %g3, %l2, %g3 |
| 433 | stx %g4, [%g3] |
| 434 | membar #Sync |
| 435 | |
| 436 | setx Tx_pkt_dat_lo8_0004, %l0, %g4 |
| 437 | add %g3, %l2, %g3 |
| 438 | stx %g4, [%g3] |
| 439 | membar #Sync |
| 440 | |
| 441 | setx Tx_pkt_dat_hi8_0004, %l0, %g4 |
| 442 | add %g3, %l2, %g3 |
| 443 | stx %g4, [%g3] |
| 444 | membar #Sync |
| 445 | /******************************************************************************************************/ |
| 446 | |
| 447 | #ifdef NIU_XPCS_LOOPBACK_CHECK_L2 |
| 448 | /*********************************************** ***********************************************/ |
| 449 | setx addr_IPP_CFIG_1, %o1, %o2; setx data_conf_df_pio_w, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 450 | |
| 451 | Read_TxDescriptor: |
| 452 | ! -----------------------------------------------------------------------vvv------------------------------------ |
| 453 | setx addr_IPP_DFIFO_WR_PTR_1, %o1, %o2; setx 0x000, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 454 | |
| 455 | set 0x20000000, %g3 ! --> g3 has L2$ address of tx_descriptor |
| 456 | ldx [%g3], %o3 |
| 457 | |
| 458 | setx addr_IPP_DFIFO_WR1_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 459 | srlx %o3, 32, %o3; |
| 460 | setx addr_IPP_DFIFO_WR2_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 461 | |
| 462 | ! setx addr_IPP_DFIFO_WR3_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 463 | ! srlx %o3, 32, %o3; |
| 464 | ! setx addr_IPP_DFIFO_WR4_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 465 | |
| 466 | setx addr_IPP_DFIFO_WR5_1, %o1, %o2; setx 0x0, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 467 | |
| 468 | Read_TxControl: |
| 469 | ! -----------------------------------------------------------------------vvv------------------------------------ |
| 470 | setx addr_IPP_DFIFO_WR_PTR_1, %o1, %o2; setx 0x001, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 471 | |
| 472 | set 0x20040000, %g3 ! --> g3 has L2$ address of tx_data |
| 473 | ldx [%g3], %o3 |
| 474 | |
| 475 | setx addr_IPP_DFIFO_WR1_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 476 | srlx %o3, 32, %o3; |
| 477 | setx addr_IPP_DFIFO_WR2_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 478 | |
| 479 | set 0x20040008, %g3 ! --> g3 has L2$ address of tx_data |
| 480 | ldx [%g3], %o3 |
| 481 | |
| 482 | setx addr_IPP_DFIFO_WR3_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 483 | srlx %o3, 32, %o3; |
| 484 | setx addr_IPP_DFIFO_WR4_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 485 | |
| 486 | setx addr_IPP_DFIFO_WR5_1, %o1, %o2; setx 0x0, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 487 | |
| 488 | ! -----------------------------------------------------------------------vvv------------------------------------ |
| 489 | setx addr_IPP_DFIFO_WR_PTR_1, %o1, %o2; setx 0x002, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 490 | |
| 491 | set 0x20040010, %g3 ! --> g3 has L2$ address of tx_data |
| 492 | ldx [%g3], %o3 |
| 493 | |
| 494 | setx addr_IPP_DFIFO_WR1_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 495 | srlx %o3, 32, %o3; |
| 496 | setx addr_IPP_DFIFO_WR2_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 497 | |
| 498 | set 0x20040018, %g3 ! --> g3 has L2$ address of tx_data |
| 499 | ldx [%g3], %o3 |
| 500 | |
| 501 | setx addr_IPP_DFIFO_WR3_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 502 | srlx %o3, 32, %o3; |
| 503 | setx addr_IPP_DFIFO_WR4_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 504 | |
| 505 | setx addr_IPP_DFIFO_WR5_1, %o1, %o2; setx 0x0, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 506 | |
| 507 | ! -----------------------------------------------------------------------vvv------------------------------------ |
| 508 | setx addr_IPP_DFIFO_WR_PTR_1, %o1, %o2; setx 0x003, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 509 | |
| 510 | set 0x20040020, %g3 ! --> g3 has L2$ address of tx_data |
| 511 | ldx [%g3], %o3 |
| 512 | |
| 513 | setx addr_IPP_DFIFO_WR1_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 514 | srlx %o3, 32, %o3; |
| 515 | setx addr_IPP_DFIFO_WR2_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 516 | |
| 517 | set 0x20040028, %g3 ! --> g3 has L2$ address of tx_data |
| 518 | ldx [%g3], %o3 |
| 519 | |
| 520 | setx addr_IPP_DFIFO_WR3_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 521 | srlx %o3, 32, %o3; |
| 522 | setx addr_IPP_DFIFO_WR4_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 523 | |
| 524 | setx addr_IPP_DFIFO_WR5_1, %o1, %o2; setx 0x0, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 525 | |
| 526 | ! -----------------------------------------------------------------------vvv------------------------------------ |
| 527 | setx addr_IPP_DFIFO_WR_PTR_1, %o1, %o2; setx 0x004, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 528 | |
| 529 | set 0x20040030, %g3 ! --> g3 has L2$ address of tx_data |
| 530 | ldx [%g3], %o3 |
| 531 | |
| 532 | setx addr_IPP_DFIFO_WR1_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 533 | srlx %o3, 32, %o3; |
| 534 | setx addr_IPP_DFIFO_WR2_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 535 | |
| 536 | set 0x20040038, %g3 ! --> g3 has L2$ address of tx_data |
| 537 | ldx [%g3], %o3 |
| 538 | |
| 539 | setx addr_IPP_DFIFO_WR3_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 540 | srlx %o3, 32, %o3; |
| 541 | setx addr_IPP_DFIFO_WR4_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 542 | |
| 543 | setx addr_IPP_DFIFO_WR5_1, %o1, %o2; setx 0x0, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 544 | |
| 545 | ! -----------------------------------------------------------------------vvv------------------------------------ |
| 546 | setx addr_IPP_DFIFO_WR_PTR_1, %o1, %o2; setx 0x005, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 547 | |
| 548 | set 0x20040040, %g3 ! --> g3 has L2$ address of tx_data |
| 549 | ldx [%g3], %o3 |
| 550 | |
| 551 | setx addr_IPP_DFIFO_WR1_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 552 | srlx %o3, 32, %o3; |
| 553 | setx addr_IPP_DFIFO_WR2_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 554 | |
| 555 | set 0x20040048, %g3 ! --> g3 has L2$ address of tx_data |
| 556 | ldx [%g3], %o3 |
| 557 | |
| 558 | setx addr_IPP_DFIFO_WR3_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 559 | srlx %o3, 32, %o3; |
| 560 | setx addr_IPP_DFIFO_WR4_1, %o1, %o2; call ST_ad_o2_da_o3; nop |
| 561 | |
| 562 | setx addr_IPP_DFIFO_WR5_1, %o1, %o2; setx 0x0, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 563 | |
| 564 | /** ---------------------------------------------------------------------vvv------------------------ **/ |
| 565 | setx addr_IPP_DFIFO_RD_PTR_1, %l1, %o2; setx 0x000, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 566 | setx addr_IPP_DFIFO_RD1_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 567 | setx addr_IPP_DFIFO_RD2_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 568 | |
| 569 | setx 0x001, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 570 | setx addr_IPP_DFIFO_RD1_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 571 | setx addr_IPP_DFIFO_RD2_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 572 | setx addr_IPP_DFIFO_RD3_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 573 | setx addr_IPP_DFIFO_RD4_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 574 | |
| 575 | setx 0x002, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 576 | setx addr_IPP_DFIFO_RD1_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 577 | setx addr_IPP_DFIFO_RD2_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 578 | setx addr_IPP_DFIFO_RD3_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 579 | setx addr_IPP_DFIFO_RD4_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 580 | |
| 581 | setx 0x003, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 582 | setx addr_IPP_DFIFO_RD1_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 583 | setx addr_IPP_DFIFO_RD2_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 584 | setx addr_IPP_DFIFO_RD3_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 585 | setx addr_IPP_DFIFO_RD4_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 586 | |
| 587 | setx 0x004, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 588 | setx addr_IPP_DFIFO_RD1_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 589 | setx addr_IPP_DFIFO_RD2_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 590 | setx addr_IPP_DFIFO_RD3_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 591 | setx addr_IPP_DFIFO_RD4_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 592 | |
| 593 | setx 0x005, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 594 | setx addr_IPP_DFIFO_RD1_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 595 | setx addr_IPP_DFIFO_RD2_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 596 | setx addr_IPP_DFIFO_RD3_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 597 | setx addr_IPP_DFIFO_RD4_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 598 | /******************************************************************************************************/ |
| 599 | #endif |
| 600 | |
| 601 | /*********************************************** ***********************************************/ |
| 602 | #ifdef NIU_XPCS_LOOPBACK |
| 603 | setx addr_MIF_CONFIG, %o1, %o2; setx data_xpcs0_init_001, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 604 | |
| 605 | setx addr_MIF_FRAME_OUTPUT_REG, %o1, %o2; setx data_xpcs0_init_002, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 606 | setx data_xpcs0_init_003, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 607 | setx data_xpcs0_init_004, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 608 | setx data_xpcs0_init_005, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 609 | setx data_xpcs0_init_006, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 610 | setx data_xpcs0_init_007, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 611 | setx data_xpcs0_init_008, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 612 | setx data_xpcs0_init_009, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 613 | setx data_xpcs0_init_010, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 614 | setx data_xpcs0_init_011, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 615 | setx data_xpcs0_init_012, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 616 | setx data_xpcs0_init_013, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 617 | setx data_xpcs0_init_014, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 618 | setx data_xpcs0_init_015, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 619 | setx data_xpcs0_init_016, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 620 | setx data_xpcs0_init_017, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 621 | setx data_xpcs0_init_018, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 622 | setx data_xpcs0_init_019, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 623 | setx data_xpcs0_init_020, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 624 | setx data_xpcs0_init_021, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 625 | setx data_xpcs0_init_022, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 626 | setx data_xpcs0_init_023, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 627 | setx data_xpcs0_init_024, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 628 | setx data_xpcs0_init_025, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 629 | setx data_xpcs0_init_026, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 630 | setx data_xpcs0_init_027, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 631 | setx data_xpcs0_init_028, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 632 | setx data_xpcs0_init_029, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 633 | setx data_xpcs0_init_030, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 634 | setx data_xpcs0_init_031, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 635 | setx data_xpcs0_init_032, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 636 | setx data_xpcs0_init_033, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 637 | setx data_xpcs0_init_034, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 638 | setx data_xpcs0_init_035, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 639 | setx data_xpcs0_init_036, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 640 | setx data_xpcs0_init_037, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 641 | setx data_xpcs0_init_038, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 642 | setx data_xpcs0_init_039, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 643 | setx data_xpcs0_init_040, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 644 | setx data_xpcs0_init_041, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 645 | setx data_xpcs0_init_042, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 646 | setx data_xpcs0_init_043, %o1, %o3; call ST_ad_o2_da_o3; nop; call WA_po_ad_o2; nop |
| 647 | #endif |
| 648 | |
| 649 | setx addr_XMAC_0_CONFIG, %o1, %o2; setx data_xpcs0_init_044, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 650 | setx addr_XMAC_0_TxSftRst, %o1, %o2; setx data_xpcs0_init_045, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 651 | setx addr_XMAC_0_RxSftRst, %o1, %o2; setx data_xpcs0_init_046, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 652 | setx addr_XMAC_0_RxMac_Hist_Cnt1, %o1, %o2; setx data_xpcs0_init_047, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 653 | setx addr_XMAC_0_RxMac_Hist_Cnt2, %o1, %o2; setx data_xpcs0_init_048, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 654 | setx addr_XMAC_0_RxMac_Hist_Cnt3, %o1, %o2; setx data_xpcs0_init_049, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 655 | |
| 656 | setx addr_XMAC_0_RxMac_Hist_Cnt4, %o1, %o2; setx data_xpcs0_init_050, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 657 | setx addr_XMAC_0_RxMac_Hist_Cnt5, %o1, %o2; setx data_xpcs0_init_051, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 658 | setx addr_XMAC_0_RxMac_Hist_Cnt6, %o1, %o2; setx data_xpcs0_init_052, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 659 | setx addr_XMAC_0_RxMac_Hist_Cnt7, %o1, %o2; setx data_xpcs0_init_053, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 660 | setx addr_XMAC_0_CONFIG, %o1, %o2; setx data_xpcs0_init_054, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 661 | setx addr_XMAC_0_BASE10G_CONTROL1, %o1, %o2; setx data_xpcs0_init_055, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 662 | setx addr_XMAC_1_BASE10G_CONTROL1, %o1, %o2; setx data_xpcs0_init_056, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 663 | setx addr_IPP_CFIG_0, %o1, %o2; setx data_xpcs0_init_057, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 664 | setx addr_TXC_CONTROL, %o1, %o2; setx data_xpcs0_init_058, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 665 | #ifdef NIU_XPCS_LOOPBACK |
| 666 | setx addr_XMAC_0_BASE10G_CONTROL1, %o1, %o2; setx data_xpcs0_init_059, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 667 | #endif |
| 668 | |
| 669 | setx addr_RDC_TaBLe, %o1, %o2; setx data_xpcs0_init_060, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 670 | setx addr_RBR_CFIG_B_0, %o1, %o2; setx data_xpcs0_init_061, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 671 | setx addr_RX_LOG_MASK1_0, %o1, %o2; setx data_xpcs0_init_062, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 672 | setx addr_RX_LOG_VAL1_0, %o1, %o2; setx data_xpcs0_init_063, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 673 | setx addr_RX_LOG_PAGE_RELO1_0, %o1, %o2; setx data_xpcs0_init_064, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 674 | setx addr_RX_LOG_MASK2_0, %o1, %o2; setx data_xpcs0_init_065, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 675 | setx addr_RX_LOG_VAL2_0, %o1, %o2; setx data_xpcs0_init_066, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 676 | setx addr_RX_LOG_PAGE_RELO2_0, %o1, %o2; setx data_xpcs0_init_067, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 677 | setx addr_RX_LOG_PAGE_VLD_0, %o1, %o2; setx data_xpcs0_init_068, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 678 | setx addr_RBR_CFIG_A_0, %o1, %o2; setx data_xpcs0_init_069, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 679 | |
| 680 | setx addr_RCRCFIG_A_0, %o1, %o2; setx data_xpcs0_init_070, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 681 | setx addr_RXDMA_CFIG1_0, %o1, %o2; setx data_xpcs0_init_071, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 682 | setx addr_RXDMA_CFIG2_0, %o1, %o2; setx data_xpcs0_init_072, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 683 | setx addr_RXDMA_CFIG1_0, %o1, %o2; setx data_xpcs0_init_073, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 684 | setx addr_RED_RANdom_INIT, %o1, %o2; setx data_xpcs0_init_074, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 685 | setx addr_RDC_RED_PARAmeter_0, %o1, %o2; setx data_xpcs0_init_075, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 686 | ! setx addr_RBR_KICK_0, %o1, %o2; setx data_xpcs0_init_076, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 687 | setx addr_XMAC_0_ADDR3_da, %o1, %o2; setx data_xpcs0_init_077, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 688 | setx addr_XMAC_0_ADDR4_da, %o1, %o2; setx data_xpcs0_init_078, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 689 | setx addr_XMAC_0_ADDR5_da, %o1, %o2; setx data_xpcs0_init_079, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 690 | |
| 691 | ! setx addr_RDC_TaBLe, %o1, %o2; setx data_xpcs0_init_080, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 692 | setx addr_TXC_PORT_DMA_enable, %o1, %o2; setx data_xpcs0_init_081, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 693 | setx addr_TX_LOG_PAGE_VLD_0, %o1, %o2; setx data_xpcs0_init_082, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 694 | setx addr_TX_LOG_MASK1_0, %o1, %o2; setx data_xpcs0_init_083, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 695 | setx addr_TXC_DMA_MAX_burst_0, %o1, %o2; setx data_xpcs0_init_084, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 696 | ! setx addr_TX_LOG_PAGE_VLD_1, %o1, %o2; setx data_xpcs0_init_085, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 697 | ! setx addr_TX_LOG_MASK1_1, %o1, %o2; setx data_xpcs0_init_086, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 698 | ! setx addr_TXC_DMA_MAX_burst_1, %o1, %o2; setx data_xpcs0_init_087, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 699 | ! setx addr_TX_LOG_PAGE_VLD_2, %o1, %o2; setx data_xpcs0_init_088, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 700 | ! setx addr_TX_LOG_MASK1_2, %o1, %o2; setx data_xpcs0_init_089, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 701 | |
| 702 | ! setx addr_TXC_DMA_MAX_burst_2, %o1, %o2; setx data_xpcs0_init_090, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 703 | ! setx addr_TX_LOG_PAGE_VLD_3, %o1, %o2; setx data_xpcs0_init_091, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 704 | ! setx addr_TX_LOG_MASK1_3, %o1, %o2; setx data_xpcs0_init_092, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 705 | ! setx addr_TXC_DMA_MAX_burst_3, %o1, %o2; setx data_xpcs0_init_093, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 706 | ! setx addr_TX_LOG_PAGE_VLD_4, %o1, %o2; setx data_xpcs0_init_094, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 707 | ! setx addr_TX_LOG_MASK1_4, %o1, %o2; setx data_xpcs0_init_095, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 708 | ! setx addr_TXC_DMA_MAX_burst_4, %o1, %o2; setx data_xpcs0_init_096, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 709 | ! setx addr_TX_LOG_PAGE_VLD_5, %o1, %o2; setx data_xpcs0_init_097, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 710 | ! setx addr_TX_LOG_MASK1_5, %o1, %o2; setx data_xpcs0_init_098, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 711 | ! setx addr_TXC_DMA_MAX_burst_5, %o1, %o2; setx data_xpcs0_init_099, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 712 | |
| 713 | ! setx addr_TX_LOG_PAGE_VLD_6, %o1, %o2; setx data_xpcs0_init_100, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 714 | ! setx addr_TX_LOG_MASK1_6, %o1, %o2; setx data_xpcs0_init_101, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 715 | ! setx addr_TXC_DMA_MAX_burst_6, %o1, %o2; setx data_xpcs0_init_102, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 716 | ! setx addr_TX_LOG_PAGE_VLD_7, %o1, %o2; setx data_xpcs0_init_103, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 717 | ! setx addr_TX_LOG_MASK1_7, %o1, %o2; setx data_xpcs0_init_104, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 718 | ! setx addr_TXC_DMA_MAX_burst_7, %o1, %o2; setx data_xpcs0_init_105, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 719 | ! setx addr_TX_LOG_PAGE_VLD_8, %o1, %o2; setx data_xpcs0_init_106, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 720 | ! setx addr_TX_LOG_MASK1_8, %o1, %o2; setx data_xpcs0_init_107, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 721 | ! setx addr_TXC_DMA_MAX_burst_8, %o1, %o2; setx data_xpcs0_init_108, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 722 | ! setx addr_TX_LOG_PAGE_VLD_9, %o1, %o2; setx data_xpcs0_init_109, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 723 | |
| 724 | ! setx addr_TX_LOG_MASK1_9, %o1, %o2; setx data_xpcs0_init_110, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 725 | ! setx addr_TXC_DMA_MAX_burst_9, %o1, %o2; setx data_xpcs0_init_111, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 726 | ! setx addr_TX_LOG_PAGE_VLD_a, %o1, %o2; setx data_xpcs0_init_112, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 727 | ! setx addr_TX_LOG_MASK1_a, %o1, %o2; setx data_xpcs0_init_113, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 728 | ! setx addr_TXC_DMA_MAX_burst_a, %o1, %o2; setx data_xpcs0_init_114, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 729 | ! setx addr_TX_LOG_PAGE_VLD_b, %o1, %o2; setx data_xpcs0_init_115, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 730 | ! setx addr_TX_LOG_MASK1_b, %o1, %o2; setx data_xpcs0_init_116, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 731 | ! setx addr_TXC_DMA_MAX_burst_b, %o1, %o2; setx data_xpcs0_init_117, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 732 | ! setx addr_TX_LOG_PAGE_VLD_c, %o1, %o2; setx data_xpcs0_init_118, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 733 | ! setx addr_TX_LOG_MASK1_c, %o1, %o2; setx data_xpcs0_init_119, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 734 | |
| 735 | ! setx addr_TXC_DMA_MAX_burst_c, %o1, %o2; setx data_xpcs0_init_120, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 736 | ! setx addr_TX_LOG_PAGE_VLD_d, %o1, %o2; setx data_xpcs0_init_121, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 737 | ! setx addr_TX_LOG_MASK1_d, %o1, %o2; setx data_xpcs0_init_122, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 738 | ! setx addr_TXC_DMA_MAX_burst_d, %o1, %o2; setx data_xpcs0_init_123, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 739 | ! setx addr_TX_LOG_PAGE_VLD_e, %o1, %o2; setx data_xpcs0_init_124, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 740 | ! setx addr_TX_LOG_MASK1_e, %o1, %o2; setx data_xpcs0_init_125, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 741 | ! setx addr_TXC_DMA_MAX_burst_e, %o1, %o2; setx data_xpcs0_init_126, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 742 | ! setx addr_TX_LOG_PAGE_VLD_f, %o1, %o2; setx data_xpcs0_init_127, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 743 | ! setx addr_TX_LOG_MASK1_f, %o1, %o2; setx data_xpcs0_init_128, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 744 | ! setx addr_TXC_DMA_MAX_burst_f, %o1, %o2; setx data_xpcs0_init_129, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 745 | |
| 746 | setx addr_TX_RNG_CFIG_0, %o1, %o2; setx data_xpcs0_init_130, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 747 | setx addr_TX_RING_KICK_0, %o1, %o2; setx data_xpcs0_init_131, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 748 | setx addr_TX_CS_0, %o1, %o2; setx data_xpcs0_init_132, %o1, %o3; call ST_ad_o2_da_o3; nop; |
| 749 | /******************************************************************************************************/ |
| 750 | |
| 751 | /*********************************************** ***********************************************/ |
| 752 | setx addr_IPP_CFIG_1, %o1, %o2; setx data_conf_df_pio_w, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 753 | |
| 754 | setx addr_IPP_DFIFO_WR_PTR_1, %o1, %o2; setx 0x000, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 755 | setx addr_IPP_DFIFO_WR1_1, %o1, %o2; setx data_dfifo_reg1_000, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 756 | setx addr_IPP_DFIFO_WR2_1, %o1, %o2; setx data_dfifo_reg2_000, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 757 | setx addr_IPP_DFIFO_WR3_1, %o1, %o2; setx data_dfifo_reg3_000, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 758 | setx addr_IPP_DFIFO_WR4_1, %o1, %o2; setx data_dfifo_reg4_000, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 759 | setx addr_IPP_DFIFO_WR5_1, %o1, %o2; setx data_dfifo_reg5_000, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 760 | |
| 761 | setx addr_IPP_DFIFO_WR_PTR_1, %o1, %o2; setx 0x001, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 762 | setx addr_IPP_DFIFO_WR1_1, %o1, %o2; setx data_dfifo_reg1_001, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 763 | setx addr_IPP_DFIFO_WR2_1, %o1, %o2; setx data_dfifo_reg2_001, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 764 | setx addr_IPP_DFIFO_WR3_1, %o1, %o2; setx data_dfifo_reg3_001, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 765 | setx addr_IPP_DFIFO_WR4_1, %o1, %o2; setx data_dfifo_reg4_001, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 766 | setx addr_IPP_DFIFO_WR5_1, %o1, %o2; setx data_dfifo_reg5_001, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 767 | |
| 768 | setx addr_IPP_DFIFO_WR_PTR_1, %o1, %o2; setx 0x002, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 769 | setx addr_IPP_DFIFO_WR1_1, %o1, %o2; setx data_dfifo_reg1_002, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 770 | setx addr_IPP_DFIFO_WR2_1, %o1, %o2; setx data_dfifo_reg2_002, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 771 | setx addr_IPP_DFIFO_WR3_1, %o1, %o2; setx data_dfifo_reg3_002, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 772 | setx addr_IPP_DFIFO_WR4_1, %o1, %o2; setx data_dfifo_reg4_002, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 773 | setx addr_IPP_DFIFO_WR5_1, %o1, %o2; setx data_dfifo_reg5_002, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 774 | |
| 775 | setx addr_IPP_DFIFO_WR_PTR_1, %o1, %o2; setx 0x003, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 776 | setx addr_IPP_DFIFO_WR1_1, %o1, %o2; setx data_dfifo_reg1_003, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 777 | setx addr_IPP_DFIFO_WR2_1, %o1, %o2; setx data_dfifo_reg2_003, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 778 | setx addr_IPP_DFIFO_WR3_1, %o1, %o2; setx data_dfifo_reg3_003, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 779 | setx addr_IPP_DFIFO_WR4_1, %o1, %o2; setx data_dfifo_reg4_003, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 780 | setx addr_IPP_DFIFO_WR5_1, %o1, %o2; setx data_dfifo_reg5_003, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 781 | |
| 782 | setx addr_IPP_DFIFO_WR_PTR_1, %o1, %o2; setx 0x004, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 783 | setx addr_IPP_DFIFO_WR1_1, %o1, %o2; setx data_dfifo_reg1_004, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 784 | setx addr_IPP_DFIFO_WR2_1, %o1, %o2; setx data_dfifo_reg2_004, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 785 | setx addr_IPP_DFIFO_WR3_1, %o1, %o2; setx data_dfifo_reg3_004, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 786 | setx addr_IPP_DFIFO_WR4_1, %o1, %o2; setx data_dfifo_reg4_004, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 787 | setx addr_IPP_DFIFO_WR5_1, %o1, %o2; setx data_dfifo_reg5_004, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 788 | /******************************************************************************************************/ |
| 789 | |
| 790 | #ifdef NIU_XPCS_LOOPBACK |
| 791 | /*********************************************** ***********************************************/ |
| 792 | setx addr_IPP_CFIG_0, %o1, %o2; setx data_conf_df_pio_w, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 793 | !du setx addr_IPP_CFIG_1, %o1, %o2; setx data_conf_df_pio_w, %o1, %o3; call ST_ad_o2_da_o3; nop |
| 794 | |
| 795 | setx 0x000, %o1, %o3; call CH_da_o3; nop |
| 796 | setx 0x001, %o1, %o3; call CH_da_o3; nop |
| 797 | setx 0x002, %o1, %o3; call CH_da_o3; nop |
| 798 | setx 0x003, %o1, %o3; call CH_da_o3; nop |
| 799 | setx 0x004, %o1, %o3; call CH_da_o3; nop |
| 800 | /******************************************************************************************************/ |
| 801 | #endif |
| 802 | |
| 803 | !------------------------------------------------------------------------- |
| 804 | setx loop_count, %g1, %g4 |
| 805 | delay_loop_end: |
| 806 | nop |
| 807 | nop |
| 808 | nop |
| 809 | nop |
| 810 | dec %g4 |
| 811 | brnz %g4, delay_loop_end |
| 812 | nop |
| 813 | !------------------------------------------------------------------------- |
| 814 | |
| 815 | test_passed: |
| 816 | nop |
| 817 | EXIT_GOOD |
| 818 | |
| 819 | test_failed: |
| 820 | nop |
| 821 | EXIT_BAD |
| 822 | |
| 823 | !++++++++++++++++ end of the main test +++++++++++++++++++++++++++++++++++ |
| 824 | |
| 825 | !------------------------------------------------------------------------- |
| 826 | ST_ad_o2_da_o3: |
| 827 | save |
| 828 | mov %i2, %l2 |
| 829 | stxa %i3, [%l2]ASI_PRIMARY_LITTLE |
| 830 | nop |
| 831 | ret |
| 832 | restore |
| 833 | !------------------------------------------------------------------------- |
| 834 | |
| 835 | !------------------------------------------------------------------------- |
| 836 | WA_po_ad_o2: |
| 837 | save |
| 838 | mov %i2, %l2 |
| 839 | |
| 840 | set_delay_counter: |
| 841 | setx POLL_DELAY_VALUE, %l1, %l6 |
| 842 | |
| 843 | delay_loop_instr_compl: |
| 844 | dec %l6 |
| 845 | brnz %l6, delay_loop_instr_compl |
| 846 | nop |
| 847 | |
| 848 | ldxa [%l2]ASI_PRIMARY_LITTLE, %l4 |
| 849 | setx 0x10000, %l1, %l5 |
| 850 | and %l5, %l4, %l4 |
| 851 | brz %l4, set_delay_counter |
| 852 | nop |
| 853 | ret |
| 854 | restore |
| 855 | !------------------------------------------------------------------------- |
| 856 | |
| 857 | !------------------------------------------------------------------------- |
| 858 | CH_da_o3: |
| 859 | save |
| 860 | mov %i3, %o3 |
| 861 | |
| 862 | setx addr_IPP_DFIFO_RD_PTR_0, %l1, %o2; call ST_ad_o2_da_o3; nop |
| 863 | setx addr_IPP_DFIFO_RD_PTR_1, %l1, %o2; call ST_ad_o2_da_o3; nop |
| 864 | |
| 865 | setx addr_IPP_DFIFO_RD1_0, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l3; nop |
| 866 | setx addr_IPP_DFIFO_RD1_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 867 | cmp %l3, %l4; |
| 868 | bne test_failed |
| 869 | nop |
| 870 | |
| 871 | setx addr_IPP_DFIFO_RD2_0, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l3; nop |
| 872 | setx addr_IPP_DFIFO_RD2_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 873 | cmp %l3, %l4; |
| 874 | bne test_failed |
| 875 | nop |
| 876 | |
| 877 | setx addr_IPP_DFIFO_RD3_0, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l3; nop |
| 878 | setx addr_IPP_DFIFO_RD3_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 879 | cmp %l3, %l4; |
| 880 | bne test_failed |
| 881 | nop |
| 882 | |
| 883 | setx addr_IPP_DFIFO_RD4_0, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l3; nop |
| 884 | setx addr_IPP_DFIFO_RD4_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 885 | cmp %l3, %l4; |
| 886 | bne test_failed |
| 887 | nop |
| 888 | |
| 889 | setx addr_IPP_DFIFO_RD5_0, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l3; nop |
| 890 | setx addr_IPP_DFIFO_RD5_1, %l1, %l2; ldxa [%l2]ASI_PRIMARY_LITTLE, %l4; nop |
| 891 | cmp %l3, %l4; |
| 892 | bne test_failed |
| 893 | nop |
| 894 | |
| 895 | ret |
| 896 | restore |
| 897 | !------------------------------------------------------------------------- |
| 898 | |
| 899 | !.global test_failed |
| 900 | !test_failed: |
| 901 | ! EXIT_BAD |
| 902 | |
| 903 | |
| 904 | /************************************************************************ |
| 905 | Test case data start |
| 906 | ************************************************************************/ |
| 907 | /* These initialization is temporary, as there looks some bug in mempli */ |
| 908 | |
| 909 | SECTION SetRngConfig_init data_va=0x100000000 |
| 910 | attr_data { |
| 911 | Name = SetRngConfig_init, |
| 912 | hypervisor, |
| 913 | compressimage |
| 914 | } |
| 915 | .data |
| 916 | SetRngConfig_init: |
| 917 | .xword 0x0060452301000484 |
| 918 | /************************************************************************/ |
| 919 | |
| 920 | SECTION SetTxRingKick_init data_va=0x100000100 |
| 921 | attr_data { |
| 922 | Name = SetTxRingKick_init, |
| 923 | hypervisor, |
| 924 | compressimage |
| 925 | } |
| 926 | .data |
| 927 | SetTxRingKick_init: |
| 928 | .xword 0x0060452301000484 |
| 929 | /************************************************************************/ |
| 930 | |
| 931 | SECTION SetTxLPMask1_init data_va=0x100000200 |
| 932 | attr_data { |
| 933 | Name = SetTxLPMask1_init, |
| 934 | hypervisor, |
| 935 | compressimage |
| 936 | } |
| 937 | .data |
| 938 | SetTxLPMask1_init: |
| 939 | .xword 0x0060452301000484 |
| 940 | /************************************************************************/ |
| 941 | |
| 942 | SECTION SetTxLPValue1_init data_va=0x100000300 |
| 943 | attr_data { |
| 944 | Name = SetTxLPValue1_init, |
| 945 | hypervisor, |
| 946 | compressimage |
| 947 | } |
| 948 | .data |
| 949 | SetTxLPValue1_init: |
| 950 | .xword 0x0060452301000484 |
| 951 | /************************************************************************/ |
| 952 | |
| 953 | SECTION SetTxLPRELOC1_init data_va=0x100000400 |
| 954 | attr_data { |
| 955 | Name = SetTxLPRELOC1_init, |
| 956 | hypervisor, |
| 957 | compressimage |
| 958 | } |
| 959 | .data |
| 960 | SetTxLPRELOC1_init: |
| 961 | .xword 0x0060452301000484 |
| 962 | /************************************************************************/ |
| 963 | SECTION SetTxLPMask2_init data_va=0x100000500 |
| 964 | attr_data { |
| 965 | Name = SetTxLPMask2_init, |
| 966 | hypervisor, |
| 967 | compressimage |
| 968 | } |
| 969 | .data |
| 970 | SetTxLPMask2_init: |
| 971 | .xword 0x0060452301000484 |
| 972 | /************************************************************************/ |
| 973 | SECTION SetTxLPValue2_init data_va=0x100000600 |
| 974 | attr_data { |
| 975 | Name = SetTxLPValue2_init, |
| 976 | hypervisor, |
| 977 | compressimage |
| 978 | } |
| 979 | .data |
| 980 | SetTxLPValue2_init: |
| 981 | .xword 0x0060452301000484 |
| 982 | |
| 983 | /************************************************************************/ |
| 984 | SECTION SetTxLPRELOC2_init data_va=0x100000700 |
| 985 | attr_data { |
| 986 | Name = SetTxLPRELOC2_init, |
| 987 | hypervisor, |
| 988 | compressimage |
| 989 | } |
| 990 | .data |
| 991 | SetTxLPRELOC2_init: |
| 992 | .xword 0x0060452301000484 |
| 993 | |
| 994 | /************************************************************************/ |
| 995 | SECTION SetTxLPValid_init data_va=0x100000800 |
| 996 | attr_data { |
| 997 | Name = SetTxLPValid_init, |
| 998 | hypervisor, |
| 999 | compressimage |
| 1000 | } |
| 1001 | .data |
| 1002 | SetTxLPValid_init: |
| 1003 | .xword 0x0060452301000484 |
| 1004 | |
| 1005 | /************************************************************************/ |
| 1006 | |