| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: PCIeDMARw_bug116647.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define ENABLE_PCIE_LINK_TRAINING |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | #include "hboot.s" |
| 42 | #include "peu_defines.h" |
| 43 | |
| 44 | !!!----- addrs for PCI-e DMA and JTAG L2 access ----- |
| 45 | |
| 46 | #define BANK0_ADDR_FOR_DMA 0xfffc000123456000 |
| 47 | #define BANK0_ADDR_FOR_JTAG 0xfffc000123456800 |
| 48 | #define BANK1_ADDR_FOR_DMA 0xfffc000123456040 |
| 49 | #define BANK1_ADDR_FOR_JTAG 0xfffc000123456840 |
| 50 | #define BANK2_ADDR_FOR_DMA 0xfffc000123456080 |
| 51 | #define BANK2_ADDR_FOR_JTAG 0xfffc000123456880 |
| 52 | #define BANK3_ADDR_FOR_DMA 0xfffc0001234560c0 |
| 53 | #define BANK3_ADDR_FOR_JTAG 0xfffc0001234568c0 |
| 54 | #define BANK4_ADDR_FOR_DMA 0xfffc000123456100 |
| 55 | #define BANK4_ADDR_FOR_JTAG 0xfffc000123456900 |
| 56 | #define BANK5_ADDR_FOR_DMA 0xfffc000123456140 |
| 57 | #define BANK5_ADDR_FOR_JTAG 0xfffc000123456940 |
| 58 | #define BANK6_ADDR_FOR_DMA 0xfffc000123456180 |
| 59 | #define BANK6_ADDR_FOR_JTAG 0xfffc000123456980 |
| 60 | #define BANK7_ADDR_FOR_DMA 0xfffc0001234561c0 |
| 61 | #define BANK7_ADDR_FOR_JTAG 0xfffc0001234569c0 |
| 62 | |
| 63 | !!!----- original code from PCIeDMARw.s ----- |
| 64 | |
| 65 | #define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA) |
| 66 | |
| 67 | #define DMA_DATA_ADDR 0x0000000123456000 |
| 68 | #define DMA_DATA_BYP_SADDR 0xfffc000123456000 |
| 69 | #define DMA_DATA_BYP_EADDR 0xfffc000123456800 |
| 70 | |
| 71 | #define DMA_DATA_BYP_ADDR1 0xfffc000123457000 |
| 72 | #define DMA_DATA_BYP_ADDR2 0xfffc000123457100 |
| 73 | #define DMA_DATA_BYP_ADDR3 0xfffc000123457200 |
| 74 | #define DMA_DATA_BYP_ADDR4 0xfffc000123457300 |
| 75 | #define DMA_DATA_BYP_ADDR5 0xfffc000123457400 |
| 76 | #define DMA_DATA_BYP_ADDR6 0xfffc000123457500 |
| 77 | #define DMA_DATA_BYP_ADDR7 0xfffc000123457600 |
| 78 | #define DMA_DATA_BYP_ADDR8 0xfffc000123457700 |
| 79 | #define DMA_DATA_BYP_ADDR9 0xfffc000123457800 |
| 80 | |
| 81 | /************************************************************************ |
| 82 | Test case code start |
| 83 | ************************************************************************/ |
| 84 | .text |
| 85 | .global main |
| 86 | |
| 87 | main: |
| 88 | ta T_CHANGE_HPRIV |
| 89 | nop |
| 90 | |
| 91 | !!!----- inform Vera diag the addr to use for L2 access |
| 92 | UsrEvnt0: |
| 93 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt0)) -> generic_ev ("addr", BANK0_ADDR_FOR_JTAG, BANK0_ADDR_FOR_JTAG) |
| 94 | nop |
| 95 | |
| 96 | !!!----- runtime arg: NEXT_DMA_LOOP_DELAY is loop delay before next DMA |
| 97 | |
| 98 | #ifdef NEXT_DMA_LOOP_DELAY |
| 99 | setx NEXT_DMA_LOOP_DELAY, %g1, %g6 |
| 100 | #else |
| 101 | setx 10, %g1, %g6 |
| 102 | #endif |
| 103 | |
| 104 | !!!----- runtime arg: NUMBER_DMA_WRITES is number of DMA write from PCI-e |
| 105 | |
| 106 | #ifdef NUMBER_DMA_WRITES |
| 107 | setx NUMBER_DMA_WRITES, %g1, %g5 |
| 108 | #else |
| 109 | setx 150, %g1, %g5 |
| 110 | #endif |
| 111 | |
| 112 | !!!----- DMA writes from PCI-e ----- |
| 113 | |
| 114 | dma_write_loop: |
| 115 | nop |
| 116 | or %g0, %g6, %g4 !!! %g4 is delay loop counter |
| 117 | UsrEvnt1: |
| 118 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", BANK0_ADDR_FOR_DMA, BANK0_ADDR_FOR_DMA, "64'h1", 1 ) |
| 119 | 1: !!! delay loop |
| 120 | or %g0, 0x1, %g1 !!! dummy operation |
| 121 | or %g0, 0x1, %g1 !!! dummy operation |
| 122 | or %g0, 0x1, %g1 !!! dummy operation |
| 123 | dec %g4 |
| 124 | brnz %g4, 1b |
| 125 | nop |
| 126 | nop |
| 127 | |
| 128 | dec %g5 |
| 129 | brnz %g5, dma_write_loop |
| 130 | nop |
| 131 | nop |
| 132 | |
| 133 | |
| 134 | |
| 135 | !!!----- original code from PCIeDMARw.s ----- |
| 136 | |
| 137 | ! select a MEM32 address in PCI address range and transmit the command to NCU |
| 138 | |
| 139 | setx MEM32_RD_ADDR, %g1, %g2 |
| 140 | |
| 141 | stx %g1, [%g2] ! MEM32 PIO Write |
| 142 | stx %g2, [%g2+8] ! MEM32 PIO Write |
| 143 | stx %g3, [%g2+16] ! MEM32 PIO Write |
| 144 | |
| 145 | ldx [%g2], %l0 ! MEM32 PIO READ |
| 146 | ldx [%g2+8], %l1 ! MEM32 PIO READ |
| 147 | ldx [%g2+16], %l2 ! MEM32 PIO READ |
| 148 | |
| 149 | |
| 150 | test_passed: |
| 151 | EXIT_GOOD |
| 152 | |
| 153 | |
| 154 | test_failed: |
| 155 | EXIT_BAD |
| 156 | |
| 157 | |
| 158 | |
| 159 | /************************************************************************ |
| 160 | Test case data start |
| 161 | ************************************************************************/ |
| 162 | |
| 163 | SECTION .DATA DATA_VA=DMA_DATA_ADDR |
| 164 | attr_data { |
| 165 | Name = .DATA, |
| 166 | hypervisor, |
| 167 | compressimage |
| 168 | } |
| 169 | .data |
| 170 | init_mem(0x0101010201030104, 256, 8, +, 0, +, 0x0004000400040004) |
| 171 | /************************************************************************/ |