| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_coverage.vrpal |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #inc "dmu_cov_inc.pal"; |
| 36 | |
| 37 | #include <vera_defines.vrh> |
| 38 | #include <ListMacros.vrh> |
| 39 | |
| 40 | #include "std_display_class.vrh" |
| 41 | #include "std_display_defines.vri" |
| 42 | |
| 43 | #include "dmu_cov.if.vrh" |
| 44 | #include "dmu_cov_ports_binds.vrh" |
| 45 | |
| 46 | extern event dmu_diag_done; |
| 47 | |
| 48 | |
| 49 | class dmu_coverage { |
| 50 | // for dispmon |
| 51 | StandardDisplay dbg; |
| 52 | local string myname; |
| 53 | |
| 54 | #include "dmu_cov_defines.vrh" |
| 55 | |
| 56 | // ----------- start of coverage object 1 ---------------- |
| 57 | // this coverage group samples on dmu clock |
| 58 | |
| 59 | event dmu_clu_cl2ps_sample_evnt_trig; |
| 60 | event dmu_clu_ps2pm_sample_evnt_trig; |
| 61 | event dmu_d2j_cmd_vld_sample_evnt_trig; |
| 62 | |
| 63 | coverage_group ncu_dmu_pio_coverage_group { |
| 64 | |
| 65 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 66 | sample_event = sync (ANY, pio_sample_evnt_trig ); |
| 67 | |
| 68 | #include "ncu_dmu_pio_sample.vrh" |
| 69 | } |
| 70 | |
| 71 | coverage_group dmu_sii_coverage_group { |
| 72 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 73 | sample_event = sync (ANY, dmu_sii_sample_evnt_trig ); |
| 74 | |
| 75 | #ifndef DMU_INTF_COV |
| 76 | #include "dmu_sii_sample.vrh" |
| 77 | #endif |
| 78 | } // dmu_sii_coverage_group |
| 79 | |
| 80 | // ----------- coverage_group ---------------- |
| 81 | coverage_group sio_dmu_coverage_group { |
| 82 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 83 | sample_event = sync (ANY, sio_dmu_sample_evnt_trig ); |
| 84 | |
| 85 | #ifndef DMU_INTF_COV |
| 86 | #include "sio_dmu_sample.vrh" |
| 87 | #endif |
| 88 | } // siu_dmu_coverage_group |
| 89 | |
| 90 | coverage_group dmu_ilu_iHdr_coverage_group { |
| 91 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 92 | sample_event = sync (ANY, ilu_dmu_iHdr_sample_evnt_trig ); |
| 93 | |
| 94 | #include "dmu_ilu_ingress_sample.vrh" |
| 95 | |
| 96 | } // ilu_dmu_ingress_coverage_group |
| 97 | |
| 98 | //coverage_group dmu_ilu_ingress_dp_coverage_group |
| 99 | // { |
| 100 | // const_sample_reference = 1; // ref. to sample vars. is constant |
| 101 | // sample_event = sync (ANY, dmu_ilu_ingress_dp_sample_evnt_trig ); |
| 102 | // |
| 103 | //#ifndef DMU_INTF_COV |
| 104 | //// #include "dmu_ilu_ingress_dp_sample.vrh" |
| 105 | //#endif |
| 106 | // |
| 107 | // } // dmu_ilu_ingress_dp_coverage_group |
| 108 | // |
| 109 | //coverage_group dmu_ilu_ingress_rel_coverage_group |
| 110 | // { |
| 111 | // const_sample_reference = 1; // ref. to sample vars. is constant |
| 112 | // sample_event = sync (ANY, dmu_ilu_ingress_rel_sample_evnt_trig ); |
| 113 | // |
| 114 | //#ifndef DMU_INTF_COV |
| 115 | //// #include "dmu_ilu_ingress_rel_sample.vrh" |
| 116 | //#endif |
| 117 | // |
| 118 | // } // dmu_ilu_ingress_rel_coverage_group |
| 119 | |
| 120 | coverage_group dmu_ilu_iBufAddr_coverage_group { |
| 121 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 122 | sample_event = sync (ANY, dmu_ilu_iBufAddr_sample_evnt_trig ); |
| 123 | #ifndef DMU_INTF_COV |
| 124 | #include "dmu_ilu_ingress_data_sample.vrh" |
| 125 | #endif |
| 126 | } |
| 127 | |
| 128 | coverage_group dmu_ilu_iRelRcd_coverage_group { |
| 129 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 130 | sample_event = sync (ANY, dmu_ilu_iRel_sample_evnt_trig); |
| 131 | |
| 132 | #ifndef DMU_INTF_COV |
| 133 | #include "dmu_ilu_rel_sample.vrh" |
| 134 | #endif |
| 135 | } |
| 136 | |
| 137 | coverage_group dmu_ilu_eHdr_coverage_group { |
| 138 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 139 | sample_event = sync (ANY, dmu_ilu_eHdr_sample_evnt_trig ); |
| 140 | |
| 141 | #ifndef DMU_INTF_COV |
| 142 | #include "dmu_ilu_egress_sample.vrh" |
| 143 | #endif |
| 144 | } // dmu_ilu_egress_coverage_group |
| 145 | |
| 146 | coverage_group dmu_ilu_eBufAddr_coverage_group { |
| 147 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 148 | sample_event = sync (ANY, ilu_dmu_eBufAddr_sample_evnt_trig); |
| 149 | #ifndef DMU_INTF_COV |
| 150 | #include "dmu_ilu_egress_data_sample.vrh" |
| 151 | #endif |
| 152 | } |
| 153 | |
| 154 | coverage_group dmu_ilu_eRelRcd_coverage_group { |
| 155 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 156 | sample_event = sync (ANY, ilu_dmu_eRel_sample_evnt_trig); |
| 157 | |
| 158 | #ifndef DMU_INTF_COV |
| 159 | #include "dmu_ilu_egress_rel_sample.vrh" |
| 160 | #endif |
| 161 | } |
| 162 | |
| 163 | coverage_group dmu_ncu_error_coverage_group { |
| 164 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 165 | sample_event = @(posedge dmu_ncu_error_if.clk); |
| 166 | |
| 167 | #ifndef DMU_INTF_COV |
| 168 | #include "dmu_ncu_error_sample.vrh" |
| 169 | #endif |
| 170 | } |
| 171 | |
| 172 | coverage_group dmu_sii_wrack_coverage_group { |
| 173 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 174 | sample_event = @(posedge dmu_coverage_ifc.dmu_gclk); |
| 175 | |
| 176 | #ifndef DMU_INTF_COV |
| 177 | sample dmu_siu_intf_DMA_WrackTag_cov (dmu_coverage_ifc.dmuwrack_tag) |
| 178 | { |
| 179 | m_state (0:15) if (dmu_coverage_ifc.dmuwrack_vld == 1'b1); |
| 180 | } |
| 181 | sample dmu_siu_intf_DMA_WrackTagPar_cov (dmu_coverage_ifc.dmuwrack_par) |
| 182 | { |
| 183 | m_state (0:1) if (dmu_coverage_ifc.dmuwrack_vld == 1'b1); |
| 184 | } |
| 185 | #endif |
| 186 | } |
| 187 | |
| 188 | coverage_group dmu_ncu_wrack_coverage_group { |
| 189 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 190 | sample_event = @(posedge dmu_cov_dmupio.clk); |
| 191 | |
| 192 | #ifndef DMU_INTF_COV |
| 193 | sample dmu_ncu_intf_PIOWrackTag_cov (dmu_cov_dmupio.dmu_ncu_wrack_tag) |
| 194 | { |
| 195 | m_state (0:15) if (dmu_cov_dmupio.dmu_ncu_wrack_vld == 1'b1); |
| 196 | } |
| 197 | sample dmu_ncu_intf_PIOWrackTagPar_cov (dmu_cov_dmupio.dmu_ncu_wrack_par) |
| 198 | { |
| 199 | m_state (0:1) if (dmu_cov_dmupio.dmu_ncu_wrack_vld); |
| 200 | } |
| 201 | #endif |
| 202 | } |
| 203 | |
| 204 | coverage_group dmu_ncu_mondo_coverage_group { |
| 205 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 206 | sample_event = @(posedge dmu_ncu_mondo_if.clk); |
| 207 | |
| 208 | #ifndef DMU_INTF_COV |
| 209 | sample dmu_ncu_intf_MondoAck_cov (dmu_ncu_mondo_if.ncu_dmu_mondo_id) |
| 210 | { |
| 211 | m_state (0:63) if (dmu_ncu_mondo_if.ncu_dmu_mondo_ack == 1'b1); |
| 212 | } |
| 213 | sample dmu_ncu_intf_MondoNack_cov (dmu_ncu_mondo_if.ncu_dmu_mondo_id) |
| 214 | { |
| 215 | m_state (0:63) if (dmu_ncu_mondo_if.ncu_dmu_mondo_nack == 1'b1); |
| 216 | } |
| 217 | sample dmu_ncu_intf_MondoPar_cov (dmu_ncu_mondo_if.ncu_dmu_mondo_id_par) |
| 218 | { |
| 219 | m_state ACK_PAR (0:1) if (dmu_ncu_mondo_if.ncu_dmu_mondo_ack == 1'b1); |
| 220 | m_state NACK_PAR (0:1) if (dmu_ncu_mondo_if.ncu_dmu_mondo_nack == 1'b1); |
| 221 | } |
| 222 | #endif |
| 223 | } |
| 224 | |
| 225 | coverage_group dmu_ncu_iommuinv_coverage_group { |
| 226 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 227 | sample_event = sync (ANY, iommu_inv_sample_evnt_trig); |
| 228 | |
| 229 | // Only PA[38:0] will toggle since PA[39] must be 0 for cacheable address |
| 230 | // this equates to bits 32:0 on the inv_addr |
| 231 | |
| 232 | #ifndef DMU_INTF_COV |
| 233 | sample dmu_ncu_intf_IommuInv_cov (ncu_iommu_inv_addr[32:0]) |
| 234 | { |
| 235 | . &toggle(33); |
| 236 | } |
| 237 | #endif |
| 238 | } |
| 239 | |
| 240 | coverage_group dmu_ncu_csr_coverage_group { |
| 241 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 242 | sample_event = @(posedge dmu_ncu_csr_if.clk); |
| 243 | |
| 244 | #ifndef DMU_INTF_COV |
| 245 | sample dmu_ncu_intf_csr_stall_cov ({dmu_ncu_csr_if.dmu_ncu_stall,dmu_ncu_csr_if.ncu_dmu_stall}) |
| 246 | { |
| 247 | m_state (1:3); |
| 248 | } |
| 249 | #endif |
| 250 | } |
| 251 | |
| 252 | |
| 253 | coverage_group dmu_clu_cm2cl_rcd_coverage_group |
| 254 | { |
| 255 | sample_event = @(posedge dmu_clu_coverage.cm2cl_rcd_full); |
| 256 | #ifndef DMU_INTF_COV |
| 257 | sample dmu_clu_cm2cl_rcd_full (dmu_clu_coverage.cm2cl_rcd_full) |
| 258 | { |
| 259 | state s_1 (1'b1); |
| 260 | } |
| 261 | #endif |
| 262 | } |
| 263 | |
| 264 | coverage_group dmu_pmu_pm2cm_rcd_coverage_group |
| 265 | { |
| 266 | sample_event = @(posedge dmu_pmu_coverage.pm2cm_rcd_full); |
| 267 | #ifndef DMU_INTF_COV |
| 268 | sample dmu_pmu_pm2cm_rcd_full (dmu_pmu_coverage.pm2cm_rcd_full) |
| 269 | { |
| 270 | state s_1 (1'b1); |
| 271 | } |
| 272 | #endif |
| 273 | } |
| 274 | |
| 275 | coverage_group dmu_pmu_cl2pm_rcd_coverage_group |
| 276 | { |
| 277 | sample_event = @(posedge dmu_pmu_coverage.cl2pm_rcd_full); |
| 278 | #ifndef DMU_INTF_COV |
| 279 | sample dmu_pmu_cl2pm_rcd_full (dmu_pmu_coverage.cl2pm_rcd_full) |
| 280 | { |
| 281 | state s_1 (1'b1); |
| 282 | } |
| 283 | #endif |
| 284 | } |
| 285 | |
| 286 | coverage_group dmu_psb_ps2pm_coverage_group |
| 287 | { |
| 288 | sample_event = @(posedge dmu_psb_coverage.ps2pm_i_full); |
| 289 | #ifndef DMU_INTF_COV |
| 290 | sample dmu_psb_ps2pm_i_full (dmu_psb_coverage.ps2pm_i_full) |
| 291 | { |
| 292 | state s_1 (1'b1); |
| 293 | } |
| 294 | #endif |
| 295 | } |
| 296 | |
| 297 | coverage_group dmu_clu_cl2ps_coverage_group |
| 298 | { |
| 299 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 300 | sample_event = sync (ANY, dmu_clu_cl2ps_sample_evnt_trig ); |
| 301 | #ifndef DMU_INTF_COV |
| 302 | #include "dmu_clu_sample.vrh" |
| 303 | #endif |
| 304 | } |
| 305 | |
| 306 | coverage_group dmu_clu_ps2pm_coverage_group |
| 307 | { |
| 308 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 309 | sample_event = sync (ANY, dmu_clu_ps2pm_sample_evnt_trig ); |
| 310 | #ifndef DMU_INTF_COV |
| 311 | #include "dmu_psb_sample.vrh" |
| 312 | #endif |
| 313 | } |
| 314 | |
| 315 | coverage_group dmu_cmu_maxpyld_coverage_group |
| 316 | { |
| 317 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 318 | sample_event = @(posedge dmu_dmc_coverage.l2clk); |
| 319 | |
| 320 | #ifndef DMU_INTF_COV |
| 321 | #include "dmu_cmu_maxpyld_sample.vrh" |
| 322 | #endif |
| 323 | } |
| 324 | |
| 325 | coverage_group dmu_cmu_coverage_group |
| 326 | { |
| 327 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 328 | sample_event = sync (ANY, dmu_cmu_sample_evnt_trig ); |
| 329 | |
| 330 | #ifndef DMU_INTF_COV |
| 331 | #include "dmu_cmu_sample.vrh" |
| 332 | #endif |
| 333 | } |
| 334 | |
| 335 | coverage_group dmu_im2di_addr_coverage_group |
| 336 | { |
| 337 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 338 | sample_event = sync (ANY, dmu_im2di_sample_evnt_trig ); |
| 339 | #ifndef DMU_INTF_COV |
| 340 | #include "dmu_im2di_sample.vrh" |
| 341 | #endif |
| 342 | } |
| 343 | |
| 344 | coverage_group dmu_cl2di_addr_coverage_group |
| 345 | { |
| 346 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 347 | sample_event = sync (ANY, dmu_cl2di_sample_evnt_trig ); |
| 348 | #ifndef DMU_INTF_COV |
| 349 | #include "dmu_cl2di_sample.vrh" |
| 350 | #endif |
| 351 | } |
| 352 | |
| 353 | coverage_group dmu_d2j_cmd_vld_coverage_group |
| 354 | { |
| 355 | const_sample_reference = 1; // ref. to sample vars. is constant |
| 356 | sample_event = sync (ANY, dmu_d2j_cmd_vld_sample_evnt_trig ); |
| 357 | #ifndef DMU_INTF_COV |
| 358 | #include "dmu_d2j_cmd_sample.vrh" |
| 359 | #endif |
| 360 | } |
| 361 | |
| 362 | //coverage_group dmu_intcnt_fsm_coverage_group |
| 363 | // { |
| 364 | // const_sample_reference = 1; // |
| 365 | // sample_event = @(posedge dmu_intcnt_fsm_if.clk); |
| 366 | // |
| 367 | // #include "dmu_int_controller.vrh" |
| 368 | // } |
| 369 | |
| 370 | #ifdef FC_COVERAGE |
| 371 | coverage_group dmu_int_relocation_coverage_group |
| 372 | { |
| 373 | const_sample_reference = 1; // |
| 374 | sample_event = @(posedge dmu_int_relocation_if.clk); |
| 375 | |
| 376 | #include "dmu_int_relocation_sample.vrh" |
| 377 | } |
| 378 | #endif |
| 379 | coverage_group dmu_peu_intf_intr_msi_msg_cov_group |
| 380 | { |
| 381 | const_sample_reference = 1; // |
| 382 | sample_event = @(negedge dmu_cov_ios.clk); |
| 383 | |
| 384 | sample dmu_peu_intf_intr_msi_msg_cov (dmu_cov_ios.rcd_is_msi){ |
| 385 | state (1'b1); |
| 386 | } |
| 387 | |
| 388 | } |
| 389 | |
| 390 | |
| 391 | task new(StandardDisplay dbg); |
| 392 | task set_cov_cond_bits (); |
| 393 | task set_dmu_cov_points (); |
| 394 | task set_ilu_dmu_cov_points (); |
| 395 | task set_dmu_ilu_cov_points (); |
| 396 | task set_pio_cov_point (string myname, dmu_cov_pio_port piopt); |
| 397 | |
| 398 | } |
| 399 | |
| 400 | ///////////////////////////////////////////////////////////////// |
| 401 | // Class creation |
| 402 | ///////////////////////////////////////////////////////////////// |
| 403 | task dmu_coverage::new(StandardDisplay dbg) |
| 404 | { |
| 405 | // for dispmon |
| 406 | reg [3:0] dummy_data; |
| 407 | |
| 408 | bit coverage_on; |
| 409 | integer j; |
| 410 | |
| 411 | myname = "dmu_coverage"; |
| 412 | this.dbg = dbg; |
| 413 | //dbg = new(); |
| 414 | |
| 415 | if (get_plus_arg (CHECK, "dmu_coverage") || |
| 416 | get_plus_arg (CHECK, "coverage_on")) { |
| 417 | coverage_on = 1; |
| 418 | } else { |
| 419 | coverage_on = 0; |
| 420 | } |
| 421 | |
| 422 | if (coverage_on) { |
| 423 | |
| 424 | dmu_sii_coverage_group = new(); |
| 425 | sio_dmu_coverage_group = new(); |
| 426 | ncu_dmu_pio_coverage_group = new(); |
| 427 | |
| 428 | fork |
| 429 | set_cov_cond_bits (); |
| 430 | set_pio_cov_point ({myname, ".cpx"}, dmu_cov_pio_dw_bind); |
| 431 | set_ilu_dmu_cov_points (); |
| 432 | set_dmu_ilu_cov_points (); |
| 433 | set_dmu_cov_points (); |
| 434 | join none |
| 435 | |
| 436 | dbg.dispmon(myname, MON_INFO, psprintf("Coverage turned on for DMU objects")); |
| 437 | //printf("\n\n %d :Coverage turned on for DMU objects\n\n"); |
| 438 | |
| 439 | fork { |
| 440 | sync(ANY,dmu_diag_done); |
| 441 | dbg.dispmon(myname, MON_INFO, psprintf("After dmu_diag_done")); |
| 442 | coverage_save_database(1); |
| 443 | dbg.dispmon(myname, MON_INFO, psprintf("Coverage for DMU objects generated", get_time(LO))); |
| 444 | } join none |
| 445 | } // if coverage_on |
| 446 | } // dmu_coverage::new() |
| 447 | |
| 448 | |
| 449 | /////////////////////////////////////////////////////////////////////////// |
| 450 | // This task is a psuedo coverage object that combines a few conditions |
| 451 | // so that the actual coverage objects' state space doesn't get too big |
| 452 | ////////////////////////////////////////////////////////////////////////// |
| 453 | |
| 454 | task dmu_coverage:: set_cov_cond_bits () { |
| 455 | //------------------- DMU_INTERFACE --------------------------------- |
| 456 | bit dmureq; |
| 457 | integer dmu_this_cmd_cycle, dmu_last_cmd_cycle; |
| 458 | |
| 459 | integer sio_dmu_last_cmd_cycle, sio_dmu_this_cmd_cycle; |
| 460 | |
| 461 | dmu_this_cmd_cycle = get_cycle(dmu_coverage_ifc.dmu_gclk); |
| 462 | sio_dmu_this_cmd_cycle = get_cycle(dmu_coverage_ifc.dmu_gclk); |
| 463 | |
| 464 | |
| 465 | fork |
| 466 | { |
| 467 | while (1) { |
| 468 | @ (posedge dmu_coverage_ifc.dmu_gclk); |
| 469 | |
| 470 | //---------------DMU-SII--------------------- |
| 471 | if( dmu_coverage_ifc.dmureq ) |
| 472 | { |
| 473 | dmubypass = dmu_coverage_ifc.dmubypass; |
| 474 | dmudata = dmu_coverage_ifc.dmudata; |
| 475 | dmu_sii_byte_en = dmu_coverage_ifc.dmube; |
| 476 | dmu_sii_parity = dmu_coverage_ifc.dmuparity; |
| 477 | dmu_sii_datareq = dmu_coverage_ifc.dmudatareq; |
| 478 | dmu_sii_datareq16 = dmu_coverage_ifc.dmudatareq16; |
| 479 | dmu_sii_reqtype = {dmu_sii_datareq,dmu_sii_datareq16}; |
| 480 | |
| 481 | |
| 482 | dmu_last_cmd_cycle = dmu_this_cmd_cycle; |
| 483 | dmu_this_cmd_cycle = get_cycle(dmu_coverage_ifc.dmu_gclk); |
| 484 | |
| 485 | dmu_back_to_back = dmu_this_cmd_cycle - dmu_last_cmd_cycle; |
| 486 | |
| 487 | dmu_cmd = dmudata[127:122]; |
| 488 | dmc_tag = dmudata[79:64]; |
| 489 | dmu_sii_even_addr_par = dmudata[83]; |
| 490 | dmu_sii_odd_addr_par = dmudata[84]; |
| 491 | dmu_sii_pio_cpl_to_err = dmudata[82]; |
| 492 | dmu_sii_pio_cpl_bus_err = dmudata[81]; |
| 493 | dmu_sii_pio_cpl_ue_err = dmudata[80]; |
| 494 | |
| 495 | last_dmu_cmd = this_dmu_cmd; |
| 496 | this_dmu_cmd = {dmu_cmd,dmubypass}; |
| 497 | |
| 498 | dbg.dispmon(myname, MON_INFO, psprintf("dmurequest comes in")); |
| 499 | if(last_dmu_cmd_valid) { |
| 500 | // only sample when both "last_dmu_cmd" and "this_dmu_cmd" |
| 501 | // contain valid data, so the first command is never sampled |
| 502 | trigger (dmu_sii_sample_evnt_trig); |
| 503 | dbg.dispmon(myname, MON_INFO, psprintf("dmu_sample_evnt_triggered")); |
| 504 | } |
| 505 | else |
| 506 | { |
| 507 | last_dmu_cmd_valid = 1'b1; |
| 508 | } |
| 509 | } //dmu_coverage_ifc.dmureq |
| 510 | |
| 511 | |
| 512 | /************** SIO-DMU *****************/ |
| 513 | if( dmu_coverage_ifc.sio_dmu_req ) |
| 514 | { |
| 515 | sio_dmu_data = dmu_coverage_ifc.sio_dmu_data; |
| 516 | |
| 517 | sio_dmu_rd_return_ue = sio_dmu_data[81]; |
| 518 | sio_dmu_rd_return_de = sio_dmu_data[80]; |
| 519 | dmu_id_out = sio_dmu_data[79:64]; |
| 520 | sio_dmu_rd_return_ctagecc = sio_dmu_data[61:56]; |
| 521 | |
| 522 | dbg.dispmon(myname, MON_INFO, psprintf("siu request comes in to dmu")); |
| 523 | sio_dmu_last_cmd_cycle = sio_dmu_this_cmd_cycle; |
| 524 | sio_dmu_this_cmd_cycle = get_cycle(dmu_coverage_ifc.dmu_gclk); |
| 525 | |
| 526 | sio_dmu_back_to_back = sio_dmu_this_cmd_cycle - sio_dmu_last_cmd_cycle; |
| 527 | |
| 528 | sio_dmu_last_cmd = sio_dmu_this_cmd; |
| 529 | sio_dmu_this_cmd = sio_dmu_data[127:122]; |
| 530 | |
| 531 | if(sio_dmu_last_cmd_valid) { |
| 532 | // only sample when both "last_dmu_cmd" and "this_dmu_cmd" |
| 533 | // contain valid data, so the first command is never sampled |
| 534 | trigger (sio_dmu_sample_evnt_trig); |
| 535 | dbg.dispmon(myname, MON_INFO, psprintf("sio_dmu_sample_evnt_triggered")); |
| 536 | } |
| 537 | else |
| 538 | { |
| 539 | sio_dmu_last_cmd_valid = 1'b1; |
| 540 | } |
| 541 | } // dmu_coverage_ifc.sio_dmu_req |
| 542 | |
| 543 | |
| 544 | } // while (1) |
| 545 | } // fork |
| 546 | join none |
| 547 | } // task dmu_intf_coverage |
| 548 | |
| 549 | task dmu_coverage::set_pio_cov_point (string myname, dmu_cov_pio_port piopt) { |
| 550 | |
| 551 | reg [63:0] rev_hdr, inv_addr; |
| 552 | reg data_valid; |
| 553 | data_valid = 0; |
| 554 | ncu_pio_b2b=0; |
| 555 | while (1) { |
| 556 | @(posedge piopt.\$clk); |
| 557 | |
| 558 | if (piopt.\$hdr_vld) { |
| 559 | rev_hdr = piopt.\$data; |
| 560 | ncu_pio_credit = rev_hdr[59:56]; |
| 561 | ncu_pio_wr = rev_hdr[60]; // 1= PIO Read, 0= PIO Write |
| 562 | ncu_pio_size = rev_hdr[50:48]; // for PIO READSds |
| 563 | ncu_pio_bmsk = rev_hdr[55:48]; // for PIO WRITES |
| 564 | ncu_pio_cmap = rev_hdr[49:48]; ncu_pio_bufid = rev_hdr[47:46]; ncu_pio_cpu = rev_hdr[45:40]; |
| 565 | ncu_pio_cmd = rev_hdr[37:36]; // 11= MEM64, 10= MEM32, 01=IO, 00=Cnfg |
| 566 | ncu_pio_add = rev_hdr[35:0]; |
| 567 | ncu_pio_b2b++; |
| 568 | if (!rev_hdr[54]){ data_valid = 1; } |
| 569 | trigger (pio_sample_evnt_trig); |
| 570 | dbg.dispmon(myname, MON_INFO, psprintf("from ncu_dmu_pio_coverage: wr %h credid %h size %h, bufid %h cpuid %h b2b_cnt %0d", |
| 571 | ncu_pio_wr, ncu_pio_credit, ncu_pio_size, ncu_pio_bufid, ncu_pio_cpu, ncu_pio_b2b)); |
| 572 | } else if (data_valid){ |
| 573 | data_valid = 0; |
| 574 | } else { |
| 575 | ncu_pio_b2b = 0; |
| 576 | } |
| 577 | |
| 578 | if (piopt.\$mmu_vld) { |
| 579 | inv_addr = piopt.\$data; |
| 580 | ncu_iommu_inv_addr = inv_addr[39:6]; |
| 581 | trigger (iommu_inv_sample_evnt_trig); |
| 582 | dbg.dispmon(myname, MON_INFO, psprintf("iommu inv event triggered: addr %h",ncu_iommu_inv_addr)); |
| 583 | } |
| 584 | } |
| 585 | } |
| 586 | // This task covers all the ingress record, buffer data, release transactions |
| 587 | task dmu_coverage:: set_ilu_dmu_cov_points () { |
| 588 | reg [115:0] pec_ingress_rcd; |
| 589 | |
| 590 | while (1) { |
| 591 | @(posedge ilu_dmu_coverage.clk); |
| 592 | |
| 593 | // Ingress PEC record |
| 594 | if (ilu_dmu_coverage.y2k_rcd_enq) { |
| 595 | pec_ingress_rcd = ilu_dmu_coverage.y2k_rcd[115:0]; |
| 596 | // field definitions per Fire ASIC spec, pg 7-586, table 7-1 |
| 597 | ilu_dmu_hdr_F = pec_ingress_rcd[115:114]; |
| 598 | ilu_dmu_hdr_Type = pec_ingress_rcd[113:109]; |
| 599 | ilu_dmu_hdr_F_Type = pec_ingress_rcd[115:109]; |
| 600 | ilu_dmu_hdr_TC = pec_ingress_rcd[108:106]; |
| 601 | ilu_dmu_hdr_Atr = pec_ingress_rcd[105:104]; |
| 602 | ilu_dmu_hdr_Len = pec_ingress_rcd[103:94]; |
| 603 | ilu_dmu_hdr_ReqID = pec_ingress_rcd[93:78]; |
| 604 | ilu_dmu_hdr_TLPTag = pec_ingress_rcd[77:70]; |
| 605 | ilu_dmu_hdr_LastDWBE = pec_ingress_rcd[69:66]; |
| 606 | ilu_dmu_hdr_FirstDWBE = pec_ingress_rcd[65:62]; |
| 607 | ilu_dmu_hdr_Addr = pec_ingress_rcd[61:0]; |
| 608 | ilu_dmu_mps = ilu_dmu_coverage.mps; // max payload size |
| 609 | if ( ilu_dmu_hdr_F_Type[6:3] == 4'b0110){ |
| 610 | ilu_dmu_hdr_msg_code = pec_ingress_rcd [69:62]; |
| 611 | } |
| 612 | |
| 613 | if (ilu_dmu_hdr_F_Type == 7'b0110100){ |
| 614 | if (ilu_dmu_hdr_msg_code == 8'b00100000){ |
| 615 | assert_inta_b2b++; |
| 616 | if (assert_inta_b2b >= 2){ |
| 617 | intx_dup_reg[0] = 1'b1; |
| 618 | } |
| 619 | } else if (ilu_dmu_hdr_msg_code == 8'b00100100){ |
| 620 | assert_inta_b2b = 0; |
| 621 | } |
| 622 | if (ilu_dmu_hdr_msg_code == 8'b00100001){ |
| 623 | assert_intb_b2b++; |
| 624 | if (assert_intb_b2b >= 2){ |
| 625 | intx_dup_reg[1] = 1'b1; |
| 626 | } |
| 627 | } else if (ilu_dmu_hdr_msg_code == 8'b00100101){ |
| 628 | assert_intb_b2b = 0; |
| 629 | } |
| 630 | if (ilu_dmu_hdr_msg_code == 8'b00100010){ |
| 631 | assert_intc_b2b++; |
| 632 | if (assert_intc_b2b >= 2){ |
| 633 | intx_dup_reg[2] = 1'b1; |
| 634 | } |
| 635 | } else if (ilu_dmu_hdr_msg_code == 8'b00100110){ |
| 636 | assert_intc_b2b = 0; |
| 637 | } |
| 638 | if (ilu_dmu_hdr_msg_code == 8'b00100011){ |
| 639 | assert_intd_b2b++; |
| 640 | if (assert_intd_b2b >= 2){ |
| 641 | intx_dup_reg[3] = 1'b1; |
| 642 | } |
| 643 | } else if (ilu_dmu_hdr_msg_code == 8'b00100111){ |
| 644 | assert_intd_b2b = 0; |
| 645 | } |
| 646 | if (ilu_dmu_hdr_msg_code == 8'b00100100){ |
| 647 | de_assert_inta_b2b++; |
| 648 | if (de_assert_inta_b2b >= 2){ |
| 649 | intx_dup_reg[4] = 1'b1; |
| 650 | } |
| 651 | } else if (ilu_dmu_hdr_msg_code == 8'b00100000){ |
| 652 | de_assert_inta_b2b = 0; |
| 653 | } |
| 654 | if (ilu_dmu_hdr_msg_code == 8'b00100101){ |
| 655 | de_assert_intb_b2b++; |
| 656 | if (de_assert_intb_b2b >= 2){ |
| 657 | intx_dup_reg[5] = 1'b1; |
| 658 | } |
| 659 | } else if (ilu_dmu_hdr_msg_code == 8'b00100001){ |
| 660 | de_assert_intb_b2b = 0; |
| 661 | } |
| 662 | if (ilu_dmu_hdr_msg_code == 8'b00100110){ |
| 663 | de_assert_intc_b2b++; |
| 664 | if (de_assert_intc_b2b >= 2){ |
| 665 | intx_dup_reg[6] = 1'b1; |
| 666 | } |
| 667 | } else if (ilu_dmu_hdr_msg_code == 8'b00100010){ |
| 668 | de_assert_intc_b2b = 0; |
| 669 | } |
| 670 | if (ilu_dmu_hdr_msg_code == 8'b00100111){ |
| 671 | de_assert_intd_b2b++; |
| 672 | if (de_assert_intd_b2b >= 2){ |
| 673 | intx_dup_reg[7] = 1'b1; |
| 674 | } |
| 675 | } else if (ilu_dmu_hdr_msg_code == 8'b00100011){ |
| 676 | de_assert_intd_b2b = 0; |
| 677 | } |
| 678 | } |
| 679 | |
| 680 | ilu_dmu_b2b++; |
| 681 | trigger (ilu_dmu_iHdr_sample_evnt_trig); |
| 682 | dbg.dispmon(myname, MON_INFO, psprintf("from ilu_dmu_ingress_coverage: mps %x ilu_dmu_coverage.mps %x", |
| 683 | ilu_dmu_mps, ilu_dmu_coverage.mps)); |
| 684 | } else { |
| 685 | ilu_dmu_b2b = 0; |
| 686 | } |
| 687 | |
| 688 | // Ingress data pull from PEU IDB to DMU DIU |
| 689 | if (ilu_dmu_coverage.k2y_buf_addr_vld) { |
| 690 | //ilu_dmu_edp_addr = ilu_dmu_coverage.k2y_buf_addr; |
| 691 | trigger (dmu_ilu_iBufAddr_sample_evnt_trig); |
| 692 | } |
| 693 | |
| 694 | // Ingress release record |
| 695 | if (ilu_dmu_coverage.k2y_rel_enq) { |
| 696 | dmu_ilu_irel_rcd = ilu_dmu_coverage.k2y_rel_rcd; |
| 697 | trigger (dmu_ilu_iRel_sample_evnt_trig); |
| 698 | } |
| 699 | |
| 700 | } |
| 701 | } |
| 702 | |
| 703 | // This task covers all the egress record, buffer data, release transactions |
| 704 | task dmu_coverage:: set_dmu_ilu_cov_points () { |
| 705 | reg [123:0] pec_egress_rcd; |
| 706 | |
| 707 | while (1) { |
| 708 | @(posedge dmu_ilu_coverage.clk); |
| 709 | |
| 710 | // Egress PEC record |
| 711 | if (dmu_ilu_coverage.k2y_rcd_enq) { |
| 712 | pec_egress_rcd = dmu_ilu_coverage.k2y_rcd[123:0]; |
| 713 | dmu_ilu_hdr_F = pec_egress_rcd[123:122]; |
| 714 | dmu_ilu_hdr_Type = pec_egress_rcd[121:117]; |
| 715 | dmu_ilu_hdr_F_Type = pec_egress_rcd[123:117]; |
| 716 | dmu_ilu_hdr_TC = pec_egress_rcd[116:114]; |
| 717 | dmu_ilu_hdr_Atr = pec_egress_rcd[113:112]; |
| 718 | dmu_ilu_hdr_Len = pec_egress_rcd[111:102]; |
| 719 | dmu_ilu_hdr_ReqID = pec_egress_rcd[101:86]; |
| 720 | dmu_ilu_hdr_TLPTag = pec_egress_rcd[85:78]; |
| 721 | dmu_ilu_hdr_LastDWBE = pec_egress_rcd[77:74]; |
| 722 | dmu_ilu_hdr_FirstDWBE = pec_egress_rcd[73:70]; |
| 723 | dmu_ilu_hdr_Addr = pec_egress_rcd[69:6]; |
| 724 | dmu_ilu_hdr_Dptr = pec_egress_rcd[5:0]; |
| 725 | dmu_ilu_b2b++; |
| 726 | trigger (dmu_ilu_eHdr_sample_evnt_trig); |
| 727 | dbg.dispmon(myname, MON_INFO, psprintf("from dmu_ilu_egress_coverage:")); |
| 728 | } else { |
| 729 | dmu_ilu_b2b = 0; |
| 730 | } |
| 731 | |
| 732 | // Egress data pull from DMU DOU to PEU EDB |
| 733 | if (dmu_ilu_coverage.y2k_buf_addr_vld) { |
| 734 | //dmu_ilu_idp_addr = dmu_ilu_coverage.y2k_buf_addr; |
| 735 | trigger (ilu_dmu_eBufAddr_sample_evnt_trig); |
| 736 | } |
| 737 | |
| 738 | // Egress release record |
| 739 | if (dmu_ilu_coverage.y2k_rel_enq) { |
| 740 | ilu_dmu_erel_rcd = dmu_ilu_coverage.y2k_rel_rcd; |
| 741 | trigger (ilu_dmu_eRel_sample_evnt_trig); |
| 742 | } |
| 743 | |
| 744 | } |
| 745 | } |
| 746 | |
| 747 | |
| 748 | task dmu_coverage:: set_dmu_cov_points () { |
| 749 | reg [92:0] cmu_ingress_rcd; |
| 750 | while (1) { |
| 751 | @(posedge dmu_dmc_coverage.l2clk); |
| 752 | |
| 753 | if (dmu_clu_coverage.cl2ps_e_req) { |
| 754 | trigger (dmu_clu_cl2ps_sample_evnt_trig); |
| 755 | } |
| 756 | |
| 757 | if (dmu_psb_coverage.ps2pm_i_gnt) { |
| 758 | trigger (dmu_clu_ps2pm_sample_evnt_trig); |
| 759 | } |
| 760 | |
| 761 | if (dmu_dmc_coverage.im2di_wr) { |
| 762 | diu_im2di_addr = dmu_dmc_coverage.im2di_addr; |
| 763 | diu_im2di_bmask = dmu_dmc_coverage.im2di_bmask; |
| 764 | trigger (dmu_im2di_sample_evnt_trig); |
| 765 | } |
| 766 | |
| 767 | if (dmu_dmc_coverage.cl2di_rd) { |
| 768 | diu_cl2di_addr = dmu_dmc_coverage.cl2di_addr; |
| 769 | trigger (dmu_cl2di_sample_evnt_trig); |
| 770 | } |
| 771 | |
| 772 | if (dmu_dmc_coverage.d2j_cmd_vld) { |
| 773 | trigger (dmu_d2j_cmd_vld_sample_evnt_trig); |
| 774 | } |
| 775 | |
| 776 | if (dmu_cmu_coverage.cm2pm_rcd_enq) { |
| 777 | cmu_ingress_rcd = dmu_cmu_coverage.cm2pm_rcd[92:0]; |
| 778 | dmu_cmu_Type = cmu_ingress_rcd[92:86]; |
| 779 | dmu_cmu_Len = cmu_ingress_rcd[85:76]; |
| 780 | dmu_cmu_Byte = cmu_ingress_rcd[75:64]; |
| 781 | dmu_cmu_Cntxt = cmu_ingress_rcd[63:59]; |
| 782 | dmu_cmu_Pkseq = cmu_ingress_rcd[58:54]; |
| 783 | dmu_cmu_Addr = cmu_ingress_rcd[53:13]; |
| 784 | dmu_cmu_Addr_err = cmu_ingress_rcd[12:12]; |
| 785 | dmu_cmu_b2b++; |
| 786 | trigger (dmu_cmu_sample_evnt_trig); |
| 787 | dbg.dispmon(myname, MON_INFO, psprintf("from cmu_ingress_coverage:")); |
| 788 | } else { |
| 789 | dmu_cmu_b2b = 0; |
| 790 | } |
| 791 | |
| 792 | |
| 793 | } |
| 794 | } |
| 795 | |