| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2_inline.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `ifdef FC_BENCH |
| 36 | `define TB_TOP tb_top |
| 37 | `else |
| 38 | `ifdef CCM |
| 39 | `define TB_TOP tb_top |
| 40 | `else |
| 41 | `define TB_TOP l2sat_top |
| 42 | `endif |
| 43 | `endif |
| 44 | |
| 45 | module l2_inline; |
| 46 | |
| 47 | // |
| 48 | // Delay for reset and x propogation and RTL to stabilize |
| 49 | // This delay is introduced since reset is multi clock and |
| 50 | // for zero in's to work correctly. |
| 51 | // |
| 52 | |
| 53 | wire myrst; |
| 54 | //assign myrst = `TB_TOP.reset; |
| 55 | assign myrst = `TB_TOP.cpu.rst_l2_wmr_; |
| 56 | reg reset_l_1; |
| 57 | reg reset_l_2; |
| 58 | reg reset_l_3; |
| 59 | reg reset_l_4; |
| 60 | reg reset_l_5; |
| 61 | reg reset_l_6; |
| 62 | reg reset_l_7; |
| 63 | reg reset_l_8; |
| 64 | reg reset_l_9; |
| 65 | reg my_reset_10; |
| 66 | |
| 67 | wire myl2clk; |
| 68 | |
| 69 | reg[2:0] l2t0_sii_req_count; |
| 70 | reg[2:0] l2t1_sii_req_count; |
| 71 | reg[2:0] l2t2_sii_req_count; |
| 72 | reg[2:0] l2t3_sii_req_count; |
| 73 | reg[2:0] l2t4_sii_req_count; |
| 74 | reg[2:0] l2t5_sii_req_count; |
| 75 | reg[2:0] l2t6_sii_req_count; |
| 76 | reg[2:0] l2t7_sii_req_count; |
| 77 | |
| 78 | reg[2:0] l2t0_wri_req_count; |
| 79 | reg[2:0] l2t1_wri_req_count; |
| 80 | reg[2:0] l2t2_wri_req_count; |
| 81 | reg[2:0] l2t3_wri_req_count; |
| 82 | reg[2:0] l2t4_wri_req_count; |
| 83 | reg[2:0] l2t5_wri_req_count; |
| 84 | reg[2:0] l2t6_wri_req_count; |
| 85 | reg[2:0] l2t7_wri_req_count; |
| 86 | |
| 87 | |
| 88 | initial |
| 89 | begin |
| 90 | l2t0_sii_req_count = 1; |
| 91 | l2t1_sii_req_count = 1; |
| 92 | l2t2_sii_req_count = 1; |
| 93 | l2t3_sii_req_count = 1; |
| 94 | l2t4_sii_req_count = 1; |
| 95 | l2t5_sii_req_count = 1; |
| 96 | l2t6_sii_req_count = 1; |
| 97 | l2t7_sii_req_count = 1; |
| 98 | |
| 99 | l2t0_wri_req_count = 1; |
| 100 | l2t1_wri_req_count = 1; |
| 101 | l2t2_wri_req_count = 1; |
| 102 | l2t3_wri_req_count = 1; |
| 103 | l2t4_wri_req_count = 1; |
| 104 | l2t5_wri_req_count = 1; |
| 105 | l2t6_wri_req_count = 1; |
| 106 | l2t7_wri_req_count = 1; |
| 107 | |
| 108 | end |
| 109 | |
| 110 | assign myl2clk = `TB_TOP.cpu.l2clk; |
| 111 | |
| 112 | always@(posedge myl2clk) |
| 113 | begin |
| 114 | reset_l_1 <= #1 myrst; |
| 115 | reset_l_2 <= #1 reset_l_1; |
| 116 | reset_l_3 <= #1 reset_l_2; |
| 117 | reset_l_4 <= #1 reset_l_3; |
| 118 | reset_l_5 <= #1 reset_l_4; |
| 119 | reset_l_6 <= #1 reset_l_5; |
| 120 | reset_l_7 <= #1 reset_l_6; |
| 121 | reset_l_8 <= #1 reset_l_7; |
| 122 | reset_l_9 <= #1 reset_l_8; |
| 123 | my_reset_10 <= #1 reset_l_9; |
| 124 | end |
| 125 | //sii req counter. The valid range of values are 1, 2, 3. Assertion should fire if counter goes over 2 or drop below 1. |
| 126 | always@ (posedge `TB_TOP.cpu.l2clk) |
| 127 | begin |
| 128 | if(`TB_TOP.reset == 1'b1) begin |
| 129 | |
| 130 | if(`TB_TOP.cpu.l2t0.rst_wmr_ == 1'b1) |
| 131 | begin |
| 132 | if(`TB_TOP.cpu.l2t0.sii_l2t_req_vld) |
| 133 | l2t0_sii_req_count = l2t0_sii_req_count + 1; |
| 134 | if (`TB_TOP.cpu.l2t0.l2t_sii_iq_dequeue) |
| 135 | l2t0_sii_req_count = l2t0_sii_req_count - 1; |
| 136 | end |
| 137 | else |
| 138 | l2t0_sii_req_count = 3'b1; |
| 139 | |
| 140 | if(`TB_TOP.cpu.l2t1.sii_l2t_req_vld) |
| 141 | l2t1_sii_req_count = l2t1_sii_req_count + 1; |
| 142 | if (`TB_TOP.cpu.l2t1.l2t_sii_iq_dequeue) |
| 143 | l2t1_sii_req_count = l2t1_sii_req_count - 1; |
| 144 | |
| 145 | |
| 146 | if(`TB_TOP.cpu.l2t2.sii_l2t_req_vld) |
| 147 | l2t2_sii_req_count = l2t2_sii_req_count + 1; |
| 148 | if (`TB_TOP.cpu.l2t2.l2t_sii_iq_dequeue) |
| 149 | l2t2_sii_req_count = l2t2_sii_req_count - 1; |
| 150 | |
| 151 | |
| 152 | if(`TB_TOP.cpu.l2t3.sii_l2t_req_vld) |
| 153 | l2t3_sii_req_count = l2t3_sii_req_count + 1; |
| 154 | if (`TB_TOP.cpu.l2t3.l2t_sii_iq_dequeue) |
| 155 | l2t3_sii_req_count = l2t3_sii_req_count - 1; |
| 156 | |
| 157 | |
| 158 | if(`TB_TOP.cpu.l2t4.sii_l2t_req_vld) |
| 159 | l2t4_sii_req_count = l2t4_sii_req_count + 1; |
| 160 | if (`TB_TOP.cpu.l2t4.l2t_sii_iq_dequeue) |
| 161 | l2t4_sii_req_count = l2t4_sii_req_count - 1; |
| 162 | |
| 163 | |
| 164 | if(`TB_TOP.cpu.l2t5.sii_l2t_req_vld) |
| 165 | l2t5_sii_req_count = l2t5_sii_req_count + 1; |
| 166 | if (`TB_TOP.cpu.l2t5.l2t_sii_iq_dequeue) |
| 167 | l2t5_sii_req_count = l2t5_sii_req_count - 1; |
| 168 | |
| 169 | if(`TB_TOP.cpu.l2t6.sii_l2t_req_vld) |
| 170 | l2t6_sii_req_count = l2t6_sii_req_count + 1; |
| 171 | if (`TB_TOP.cpu.l2t6.l2t_sii_iq_dequeue) |
| 172 | l2t6_sii_req_count = l2t6_sii_req_count - 1; |
| 173 | |
| 174 | if(`TB_TOP.cpu.l2t7.sii_l2t_req_vld) |
| 175 | l2t7_sii_req_count = l2t7_sii_req_count + 1; |
| 176 | if (`TB_TOP.cpu.l2t7.l2t_sii_iq_dequeue) |
| 177 | l2t7_sii_req_count = l2t7_sii_req_count - 1; |
| 178 | |
| 179 | //wri req counters The valid range of values are 1, 2, 3, 4, 5. Assertion should fire if counter goes over 2 or drop below 1. |
| 180 | |
| 181 | |
| 182 | if(`TB_TOP.cpu.l2t0.rst_wmr_ == 1'b1) |
| 183 | begin |
| 184 | if(`TB_TOP.cpu.l2t0.sii_l2t_req_vld & `TB_TOP.cpu.l2t0.sii_l2t_req[26]) |
| 185 | l2t0_wri_req_count = l2t0_wri_req_count + 1; |
| 186 | if (`TB_TOP.cpu.l2t0.l2t_sii_wib_dequeue) |
| 187 | l2t0_wri_req_count = l2t0_wri_req_count - 1; |
| 188 | end |
| 189 | else |
| 190 | l2t0_wri_req_count = 3'b1; |
| 191 | |
| 192 | |
| 193 | if(`TB_TOP.cpu.l2t1.sii_l2t_req_vld & `TB_TOP.cpu.l2t1.sii_l2t_req[26]) |
| 194 | l2t1_wri_req_count = l2t1_wri_req_count + 1; |
| 195 | if (`TB_TOP.cpu.l2t1.l2t_sii_wib_dequeue) |
| 196 | l2t1_wri_req_count = l2t1_wri_req_count - 1; |
| 197 | |
| 198 | |
| 199 | if(`TB_TOP.cpu.l2t2.sii_l2t_req_vld & `TB_TOP.cpu.l2t2.sii_l2t_req[26]) |
| 200 | l2t2_wri_req_count = l2t2_wri_req_count + 1; |
| 201 | if (`TB_TOP.cpu.l2t2.l2t_sii_wib_dequeue) |
| 202 | l2t2_wri_req_count = l2t2_wri_req_count - 1; |
| 203 | |
| 204 | |
| 205 | if(`TB_TOP.cpu.l2t3.sii_l2t_req_vld & `TB_TOP.cpu.l2t3.sii_l2t_req[26]) |
| 206 | l2t3_wri_req_count = l2t3_wri_req_count + 1; |
| 207 | if (`TB_TOP.cpu.l2t3.l2t_sii_wib_dequeue) |
| 208 | l2t3_wri_req_count = l2t3_wri_req_count - 1; |
| 209 | |
| 210 | |
| 211 | if(`TB_TOP.cpu.l2t4.sii_l2t_req_vld & `TB_TOP.cpu.l2t4.sii_l2t_req[26]) |
| 212 | l2t4_wri_req_count = l2t4_wri_req_count + 1; |
| 213 | if (`TB_TOP.cpu.l2t4.l2t_sii_wib_dequeue) |
| 214 | l2t4_wri_req_count = l2t4_wri_req_count - 1; |
| 215 | |
| 216 | |
| 217 | if(`TB_TOP.cpu.l2t5.sii_l2t_req_vld & `TB_TOP.cpu.l2t5.sii_l2t_req[26]) |
| 218 | l2t5_wri_req_count = l2t5_wri_req_count + 1; |
| 219 | if (`TB_TOP.cpu.l2t5.l2t_sii_wib_dequeue) |
| 220 | l2t5_wri_req_count = l2t5_wri_req_count - 1; |
| 221 | |
| 222 | if(`TB_TOP.cpu.l2t6.sii_l2t_req_vld & `TB_TOP.cpu.l2t6.sii_l2t_req[26]) |
| 223 | l2t6_wri_req_count = l2t6_wri_req_count + 1; |
| 224 | if (`TB_TOP.cpu.l2t6.l2t_sii_wib_dequeue) |
| 225 | l2t6_wri_req_count = l2t6_wri_req_count - 1; |
| 226 | |
| 227 | if(`TB_TOP.cpu.l2t7.sii_l2t_req_vld & `TB_TOP.cpu.l2t7.sii_l2t_req[26]) |
| 228 | l2t7_wri_req_count = l2t7_wri_req_count + 1; |
| 229 | if (`TB_TOP.cpu.l2t7.l2t_sii_wib_dequeue) |
| 230 | l2t7_wri_req_count = l2t7_wri_req_count - 1; |
| 231 | |
| 232 | end |
| 233 | end |
| 234 | // |
| 235 | // MBTAG |
| 236 | // |
| 237 | |
| 238 | // 0in known_driven -var rd_addr -module n2_com_cm_32x40_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 239 | // 0in known_driven -var wr_addr -module n2_com_cm_32x40_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 240 | // 0in known_driven -var rd_en -module n2_com_cm_32x40_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 241 | // 0in known_driven -var wr_en -module n2_com_cm_32x40_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 242 | // 0in known_driven -var lookup_en -module n2_com_cm_32x40_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 243 | |
| 244 | // |
| 245 | // Directories |
| 246 | // |
| 247 | |
| 248 | |
| 249 | // 0in known_driven -var rd_en -module dc_panel_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 250 | // 0in known_driven -var cam_en -module dc_panel_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 251 | // 0in known_driven -var wr_en -module dc_panel_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 252 | |
| 253 | |
| 254 | // |
| 255 | // wbtag,iowb and rdma |
| 256 | // |
| 257 | |
| 258 | // 0in known_driven -var rd_en -module n2_com_cm_8x40_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 259 | // 0in known_driven -var wr_en -module n2_com_cm_8x40_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 260 | // 0in known_driven -var wr_addr -module n2_com_cm_8x40_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 261 | // 0in known_driven -var rd_addr -module n2_com_cm_8x40_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 262 | // 0in known_driven -var lookup_en -module n2_com_cm_8x40_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 263 | |
| 264 | |
| 265 | // |
| 266 | // n2_l2t_dp_32x160_cust RF interface known driven checkers |
| 267 | // |
| 268 | |
| 269 | // 0in known_driven -var wr_en -module n2_l2t_dp_32x160_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 270 | // 0in known_driven -var rd_en -module n2_l2t_dp_32x160_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 271 | // 0in known_driven -var word_wen -module n2_l2t_dp_32x160_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 272 | // 0in known_driven -var write_disable -module n2_l2t_dp_32x160_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 273 | // 0in known_driven -var wr_addr -module n2_l2t_dp_32x160_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 274 | // 0in known_driven -var rd_addr -module n2_l2t_dp_32x160_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 275 | |
| 276 | |
| 277 | // |
| 278 | // n2_l2t_dp_32x128_cust_array RF interface known driven checkers |
| 279 | // |
| 280 | |
| 281 | // 0in known_driven -var rd_en -module n2_l2t_dp_32x128_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 282 | // 0in known_driven -var rd_addr -module n2_l2t_dp_32x128_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 283 | // 0in known_driven -var wr_en -module n2_l2t_dp_32x128_cust_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 284 | // 0in known_driven -var wrptr_d1 -module n2_l2t_dp_32x128_cust_array -active wr_en -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 285 | |
| 286 | // |
| 287 | // n2_l2t_dp_16x160_cust_array RF interface known driven checkers |
| 288 | // |
| 289 | |
| 290 | // 0in known_driven -var wr_en -module n2_l2t_dp_16x160_cust_array -active my_reset_10 -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 291 | // 0in known_driven -var rd_en -module n2_l2t_dp_16x160_cust_array -active my_reset_10 -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 292 | // 0in known_driven -var reset_l -module n2_l2t_dp_16x160_cust_array -active my_reset_10 -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 293 | // 0in known_driven -var word_wen -module n2_l2t_dp_16x160_cust_array -active my_reset_10 -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 294 | // 0in known_driven -var wr_addr -module n2_l2t_dp_16x160_cust_array -active my_reset_10 -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 295 | // 0in known_driven -var rd_addr -module n2_l2t_dp_16x160_cust_array -active my_reset_10 -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 296 | // 0in known_driven -var byte_wen -module n2_l2t_dp_16x160_cust_array -active my_reset_10 -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 297 | |
| 298 | |
| 299 | // |
| 300 | // l2tag_array tag array interface known driven checkers |
| 301 | // |
| 302 | |
| 303 | // 0in known_driven -var index -module n2_l2t_quad -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 304 | // 0in known_driven -var wr_en_a -module n2_l2t_quad -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 305 | // 0in known_driven -var rd_en_a -module n2_l2t_quad -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 306 | // 0in known_driven -var way -module n2_l2t_quad -active wr_en_a -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 307 | |
| 308 | // x0in known_driven -var acc_idx -module l2tag_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 309 | // x0in known_driven -var acc_wr -module l2tag_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 310 | // x0in known_driven -var acc_rd -module l2tag_array -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 311 | // x0in known_driven -var acc_wr_way -module l2tag_array -active acc_wr -reset ~(`TB_TOP.cpu.l2t0.rst_wmr_) |
| 312 | |
| 313 | |
| 314 | // |
| 315 | // Data Array |
| 316 | // |
| 317 | |
| 318 | |
| 319 | // 0in assert_follower -follower (~(`TB_TOP.cpu.l2d0.ctr.l2t_l2d_col_offset_c2[0] | `TB_TOP.cpu.l2d0.ctr.l2t_l2d_col_offset_c2[2])) -leader (`TB_TOP.cpu.l2d0.ctr.cache_col_offset_c3[0] | `TB_TOP.cpu.l2d0.ctr.cache_col_offset_c3[2]) -active ((|(`TB_TOP.cpu.l2d0.l2t_l2d_way_sel_c2) & |(`TB_TOP.cpu.l2d0.ctr.l2t_l2d_col_offset_c2)) & (|(`TB_TOP.cpu.l2d0.l2t_l2d_way_sel_c3) & |(`TB_TOP.cpu.l2d0.ctr.cache_col_offset_c3))) -clock `TB_TOP.cpu.l2clk |
| 320 | |
| 321 | |
| 322 | |
| 323 | // 0in assert_follower -follower (~(`TB_TOP.cpu.l2d0.ctr.l2t_l2d_col_offset_c2[1] | `TB_TOP.cpu.l2d0.ctr.l2t_l2d_col_offset_c2[3])) -leader (`TB_TOP.cpu.l2d0.ctr.cache_col_offset_c3[1] | `TB_TOP.cpu.l2d0.ctr.cache_col_offset_c3[3]) -active ((|(`TB_TOP.cpu.l2d0.l2t_l2d_way_sel_c2) & |(`TB_TOP.cpu.l2d0.ctr.l2t_l2d_col_offset_c2)) & (|(`TB_TOP.cpu.l2d0.l2t_l2d_way_sel_c3) & |(`TB_TOP.cpu.l2d0.ctr.cache_col_offset_c3))) -clock `TB_TOP.cpu.l2clk |
| 324 | |
| 325 | |
| 326 | |
| 327 | |
| 328 | |
| 329 | |
| 330 | |
| 331 | |
| 332 | |
| 333 | |
| 334 | |
| 335 | ///////////////////////// |
| 336 | |
| 337 | |
| 338 | //0in assert -var (snp.snpq_valid[1] | snp.snpq_valid[0]) -active $0in_delay(sii_l2t_req_vld & (sii_l2t_req[25] | sii_l2t_req[24]), 5) -module l2t |
| 339 | |
| 340 | /*0in assert -var (snp.snpq_valid[1] | snp.snpq_valid[0]) -active $0in_delay(sii_l2t_req_vld & sii_l2t_req[26], 19) |
| 341 | -module l2t*/ |
| 342 | |
| 343 | |
| 344 | //0in assert -var (l2t0_sii_req_count < 4) -message "L2 bank0 have more than 2 outstanding sii requests" -clock `TB_TOP.cpu.l2clk |
| 345 | //0in assert -var (l2t0_sii_req_count > 0) -message "L2 bank0 received and unmatched l2t_sii_iq_dequeue" -clock `TB_TOP.cpu.l2clk |
| 346 | //0in assert -var (l2t1_sii_req_count < 4) -message "L2 bank1 have more than 2 outstanding sii requests" -clock `TB_TOP.cpu.l2clk |
| 347 | //0in assert -var (l2t1_sii_req_count > 0) -message "L2 bank1 received and unmatched l2t_sii_iq_dequeue" -clock `TB_TOP.cpu.l2clk |
| 348 | //0in assert -var (l2t2_sii_req_count < 4) -message "L2 bank2 have more than 2 outstanding sii requests" -clock `TB_TOP.cpu.l2clk |
| 349 | //0in assert -var (l2t2_sii_req_count > 0) -message "L2 bank2 received and unmatched l2t_sii_iq_dequeue" -clock `TB_TOP.cpu.l2clk |
| 350 | //0in assert -var (l2t3_sii_req_count < 4) -message "L2 bank3 have more than 2 outstanding sii requests" -clock `TB_TOP.cpu.l2clk |
| 351 | //0in assert -var (l2t3_sii_req_count > 0) -message "L2 bank3 received and unmatched l2t_sii_iq_dequeue" -clock `TB_TOP.cpu.l2clk |
| 352 | //0in assert -var (l2t4_sii_req_count < 4) -message "L2 bank4 have more than 2 outstanding sii requests" -clock `TB_TOP.cpu.l2clk |
| 353 | //0in assert -var (l2t4_sii_req_count > 0) -message "L2 bank4 received and unmatched l2t_sii_iq_dequeue" -clock `TB_TOP.cpu.l2clk |
| 354 | //0in assert -var (l2t5_sii_req_count < 4) -message "L2 bank5 have more than 2 outstanding sii requests" -clock `TB_TOP.cpu.l2clk |
| 355 | //0in assert -var (l2t5_sii_req_count > 0) -message "L2 bank5 received and unmatched l2t_sii_iq_dequeue" -clock `TB_TOP.cpu.l2clk |
| 356 | //0in assert -var (l2t6_sii_req_count < 4) -message "L2 bank6 have more than 2 outstanding sii requests" -clock `TB_TOP.cpu.l2clk |
| 357 | //0in assert -var (l2t6_sii_req_count > 0) -message "L2 bank6 received and unmatched l2t_sii_iq_dequeue" -clock `TB_TOP.cpu.l2clk |
| 358 | //0in assert -var (l2t7_sii_req_count < 4) -message "L2 bank7 have more than 2 outstanding sii requests" -clock `TB_TOP.cpu.l2clk |
| 359 | //0in assert -var (l2t7_sii_req_count > 0) -message "L2 bank7 received and unmatched l2t_sii_iq_dequeue" -clock `TB_TOP.cpu.l2clk |
| 360 | |
| 361 | |
| 362 | //0in assert -var (l2t0_wri_req_count < 6) -message "L2 bank0 have more than 4 outstanding wri requests" -clock `TB_TOP.cpu.l2clk |
| 363 | //0in assert -var (l2t0_wri_req_count > 0) -message "L2 bank0 received and unmatched l2t_sii_wib_dequeue" -clock `TB_TOP.cpu.l2clk |
| 364 | //0in assert -var (l2t1_wri_req_count < 6) -message "L2 bank1 have more than 4 outstanding wri requests" -clock `TB_TOP.cpu.l2clk |
| 365 | //0in assert -var (l2t1_wri_req_count > 0) -message "L2 bank1 received and unmatched l2t_sii_wib_dequeue" -clock `TB_TOP.cpu.l2clk |
| 366 | //0in assert -var (l2t2_wri_req_count < 6) -message "L2 bank2 have more than 4 outstanding wri requests" -clock `TB_TOP.cpu.l2clk |
| 367 | //0in assert -var (l2t2_wri_req_count > 0) -message "L2 bank2 received and unmatched l2t_sii_wib_dequeue" -clock `TB_TOP.cpu.l2clk |
| 368 | //0in assert -var (l2t3_wri_req_count < 6) -message "L2 bank3 have more than 4 outstanding wri requests" -clock `TB_TOP.cpu.l2clk |
| 369 | //0in assert -var (l2t3_wri_req_count > 0) -message "L2 bank3 received and unmatched l2t_sii_wib_dequeue" -clock `TB_TOP.cpu.l2clk |
| 370 | //0in assert -var (l2t4_wri_req_count < 6) -message "L2 bank4 have more than 4 outstanding wri requests" -clock `TB_TOP.cpu.l2clk |
| 371 | //0in assert -var (l2t4_wri_req_count > 0) -message "L2 bank4 received and unmatched l2t_sii_wib_dequeue" -clock `TB_TOP.cpu.l2clk |
| 372 | //0in assert -var (l2t5_wri_req_count < 6) -message "L2 bank5 have more than 4 outstanding wri requests" -clock `TB_TOP.cpu.l2clk |
| 373 | //0in assert -var (l2t5_wri_req_count > 0) -message "L2 bank5 received and unmatched l2t_sii_wib_dequeue" -clock `TB_TOP.cpu.l2clk |
| 374 | //0in assert -var (l2t6_wri_req_count < 6) -message "L2 bank6 have more than 4 outstanding wri requests" -clock `TB_TOP.cpu.l2clk |
| 375 | //0in assert -var (l2t6_wri_req_count > 0) -message "L2 bank6 received and unmatched l2t_sii_wib_dequeue" -clock `TB_TOP.cpu.l2clk |
| 376 | //0in assert -var (l2t7_wri_req_count < 6) -message "L2 bank7 have more than 4 outstanding wri requests" -clock `TB_TOP.cpu.l2clk |
| 377 | //0in assert -var (l2t7_wri_req_count > 0) -message "L2 bank7 received and unmatched l2t_sii_wib_dequeue" -clock `TB_TOP.cpu.l2clk |
| 378 | |
| 379 | /*0in assert_leader -leader $0in_rising_edge(`TB_TOP.cpu.l2b0.evict_l2b_mcu_data_vld_r5) -follower $0in_rising_edge(`TB_TOP.cpu.l2t0.l2t_sii_wib_dequeue) |
| 380 | -min 8 -max 8 -clock `TB_TOP.cpu.l2clk |
| 381 | */ |
| 382 | |
| 383 | /*0in assert_leader -leader $0in_rising_edge(`TB_TOP.cpu.l2b1.evict_l2b_mcu_data_vld_r5) -follower $0in_rising_edge(`TB_TOP.cpu.l2t1.l2t_sii_wib_dequeue) |
| 384 | -min 7 -max 7 -clock `TB_TOP.cpu.l2clk |
| 385 | */ |
| 386 | |
| 387 | /*0in assert_leader -leader $0in_rising_edge(`TB_TOP.cpu.l2b2.evict_l2b_mcu_data_vld_r5) -follower $0in_rising_edge(`TB_TOP.cpu.l2t2.l2t_sii_wib_dequeue) |
| 388 | -min 8 -max 8 -clock `TB_TOP.cpu.l2clk |
| 389 | */ |
| 390 | |
| 391 | /*0in assert_leader -leader $0in_rising_edge(`TB_TOP.cpu.l2b3.evict_l2b_mcu_data_vld_r5) -follower $0in_rising_edge(`TB_TOP.cpu.l2t3.l2t_sii_wib_dequeue) |
| 392 | -min 7 -max 7 -clock `TB_TOP.cpu.l2clk |
| 393 | */ |
| 394 | |
| 395 | /*0in assert_leader -leader $0in_rising_edge(`TB_TOP.cpu.l2b4.evict_l2b_mcu_data_vld_r5) -follower $0in_rising_edge(`TB_TOP.cpu.l2t4.l2t_sii_wib_dequeue) |
| 396 | -min 8 -max 8 -clock `TB_TOP.cpu.l2clk |
| 397 | */ |
| 398 | |
| 399 | /*0in assert_leader -leader $0in_rising_edge(`TB_TOP.cpu.l2b5.evict_l2b_mcu_data_vld_r5) -follower $0in_rising_edge(`TB_TOP.cpu.l2t5.l2t_sii_wib_dequeue) |
| 400 | -min 7 -max 7 -clock `TB_TOP.cpu.l2clk |
| 401 | */ |
| 402 | |
| 403 | /*0in assert_leader -leader $0in_rising_edge(`TB_TOP.cpu.l2b6.evict_l2b_mcu_data_vld_r5) -follower $0in_rising_edge(`TB_TOP.cpu.l2t6.l2t_sii_wib_dequeue) |
| 404 | -min 8 -max 8 -clock `TB_TOP.cpu.l2clk |
| 405 | */ |
| 406 | |
| 407 | /*0in assert_leader -leader $0in_rising_edge(`TB_TOP.cpu.l2b7.evict_l2b_mcu_data_vld_r5) -follower $0in_rising_edge(`TB_TOP.cpu.l2t7.l2t_sii_wib_dequeue) |
| 408 | -min 7 -max 7 -clock `TB_TOP.cpu.l2clk |
| 409 | */ |
| 410 | |
| 411 | /*0in assert -var ~wb_valid[0] -active set_wb_valid[0] |
| 412 | -module l2t_wbuf_ctl |
| 413 | */ |
| 414 | /*0in assert -var ~wb_valid[1] -active set_wb_valid[1] |
| 415 | -module l2t_wbuf_ctl |
| 416 | */ |
| 417 | /*0in assert -var ~wb_valid[2] -active set_wb_valid[2] |
| 418 | -module l2t_wbuf_ctl |
| 419 | */ |
| 420 | /*0in assert -var ~wb_valid[3] -active set_wb_valid[3] |
| 421 | -module l2t_wbuf_ctl |
| 422 | */ |
| 423 | /*0in assert -var ~wb_valid[4] -active set_wb_valid[4] |
| 424 | -module l2t_wbuf_ctl |
| 425 | */ |
| 426 | /*0in assert -var ~wb_valid[5] -active set_wb_valid[5] |
| 427 | -module l2t_wbuf_ctl |
| 428 | */ |
| 429 | /*0in assert -var ~wb_valid[6] -active set_wb_valid[6] |
| 430 | -module l2t_wbuf_ctl |
| 431 | */ |
| 432 | /*0in assert -var ~wb_valid[7] -active set_wb_valid[7] |
| 433 | -module l2t_wbuf_ctl |
| 434 | */ |
| 435 | |
| 436 | |
| 437 | /*0in assert -var wb_valid[0] -active reset_wb_valid[0] |
| 438 | -module l2t_wbuf_ctl |
| 439 | */ |
| 440 | /*0in assert -var wb_valid[1] -active reset_wb_valid[1] |
| 441 | -module l2t_wbuf_ctl |
| 442 | */ |
| 443 | /*0in assert -var wb_valid[2] -active reset_wb_valid[2] |
| 444 | -module l2t_wbuf_ctl |
| 445 | */ |
| 446 | /*0in assert -var wb_valid[3] -active reset_wb_valid[3] |
| 447 | -module l2t_wbuf_ctl |
| 448 | */ |
| 449 | /*0in assert -var wb_valid[4] -active reset_wb_valid[4] |
| 450 | -module l2t_wbuf_ctl |
| 451 | */ |
| 452 | /*0in assert -var wb_valid[5] -active reset_wb_valid[5] |
| 453 | -module l2t_wbuf_ctl |
| 454 | */ |
| 455 | /*0in assert -var wb_valid[6] -active reset_wb_valid[6] |
| 456 | -module l2t_wbuf_ctl |
| 457 | */ |
| 458 | /*0in assert -var wb_valid[7] -active reset_wb_valid[7] |
| 459 | -module l2t_wbuf_ctl |
| 460 | */ |
| 461 | |
| 462 | /*0in assert -var ~rdma_valid[0] -active (rdma_wr_ptr_s2[0] & snp_rdmatag_wr_en_s2) |
| 463 | -module l2t_rdmat_ctl |
| 464 | */ |
| 465 | /*0in assert -var ~rdma_valid[1] -active (rdma_wr_ptr_s2[1] & snp_rdmatag_wr_en_s2) |
| 466 | -module l2t_rdmat_ctl |
| 467 | */ |
| 468 | /*0in assert -var ~rdma_valid[2] -active (rdma_wr_ptr_s2[2] & snp_rdmatag_wr_en_s2) |
| 469 | -module l2t_rdmat_ctl |
| 470 | */ |
| 471 | /*0in assert -var ~rdma_valid[3] -active (rdma_wr_ptr_s2[3] & snp_rdmatag_wr_en_s2) |
| 472 | -module l2t_rdmat_ctl |
| 473 | */ |
| 474 | |
| 475 | /*0in assert -var (rdma_valid[0]) -active (wbuf_reset_rdmat_vld[0]) |
| 476 | -module l2t_rdmat_ctl |
| 477 | */ |
| 478 | /*0in assert -var (rdma_valid[1]) -active (wbuf_reset_rdmat_vld[1]) |
| 479 | -module l2t_rdmat_ctl |
| 480 | */ |
| 481 | /*0in assert -var (rdma_valid[2]) -active (wbuf_reset_rdmat_vld[2]) |
| 482 | -module l2t_rdmat_ctl |
| 483 | */ |
| 484 | /*0in assert -var (rdma_valid[3]) -active (wbuf_reset_rdmat_vld[3]) |
| 485 | -module l2t_rdmat_ctl |
| 486 | */ |
| 487 | |
| 488 | /*0in assert -var (wbuf.wb_valid[0]) -active (wb_read_wl[0] & wb_read_en) |
| 489 | -module l2t |
| 490 | */ |
| 491 | /*0in assert -var (wbuf.wb_valid[1]) -active (wb_read_wl[1] & wb_read_en) |
| 492 | -module l2t |
| 493 | */ |
| 494 | /*0in assert -var (wbuf.wb_valid[2]) -active (wb_read_wl[2] & wb_read_en) |
| 495 | -module l2t |
| 496 | */ |
| 497 | /*0in assert -var (wbuf.wb_valid[3]) -active (wb_read_wl[3] & wb_read_en) |
| 498 | -module l2t |
| 499 | */ |
| 500 | /*0in assert -var (wbuf.wb_valid[4]) -active (wb_read_wl[4] & wb_read_en) |
| 501 | -module l2t |
| 502 | */ |
| 503 | /*0in assert -var (wbuf.wb_valid[5]) -active (wb_read_wl[5] & wb_read_en) |
| 504 | -module l2t |
| 505 | */ |
| 506 | /*0in assert -var (wbuf.wb_valid[6]) -active (wb_read_wl[6] & wb_read_en) |
| 507 | -module l2t |
| 508 | */ |
| 509 | /*0in assert -var (wbuf.wb_valid[7]) -active (wb_read_wl[7] & wb_read_en) |
| 510 | -module l2t |
| 511 | */ |
| 512 | |
| 513 | /*0in assert -var (rdmat.rdma_valid[0]) -active (rdmat_read_wl[0] & rdmat_read_en) |
| 514 | -module l2t |
| 515 | */ |
| 516 | /*0in assert -var (rdmat.rdma_valid[1]) -active (rdmat_read_wl[1] & rdmat_read_en) |
| 517 | -module l2t |
| 518 | */ |
| 519 | /*0in assert -var (rdmat.rdma_valid[2]) -active (rdmat_read_wl[2] & rdmat_read_en) |
| 520 | -module l2t |
| 521 | */ |
| 522 | /*0in assert -var (rdmat.rdma_valid[3]) -active (rdmat_read_wl[3] & rdmat_read_en) |
| 523 | -module l2t |
| 524 | */ |
| 525 | |
| 526 | /* 0in fifo -enq (iq_array_wr_en & ~(arb_iqsel_px2 & iqu_sel_pcx)) -deq (arb_iqsel_px2 & ~(iq_array_wr_en & iqu_sel_pcx)) |
| 527 | -enq_data {iqu_pcx_l2t_atm_px2_p, pcx_l2t_data_px2_fnl[`PCX_WIDTH-1:104],ique_pcx_l2t_data_103_px2, pcx_l2t_data_px2_fnl[102:0]} |
| 528 | -deq_data ique.inst[130:0] |
| 529 | -depth 16 |
| 530 | -module l2t |
| 531 | -reset ~(rst_wmr_) |
| 532 | */ |
| 533 | |
| 534 | /* x0in fifo -enq (oqarray_wr_en & ~(oqarray_rd_en & (oqarray_rd_ptr==4'b0) & (oqarray_wr_ptr==4'b0))) -deq (oqarray_rd_en & ~(oqarray_wr_en & (oqarray_rd_ptr==4'b0) & (oqarray_wr_ptr==4'b0)) & (oqarray_rd_ptr_0 != oqarray_rd_ptr_prev_0)) |
| 535 | -enq_data {14'b0,oq_array_data_in[`CPX_WIDTH-1:0]} |
| 536 | -deq_data oq_array_data_out[159:0] |
| 537 | -depth 16 |
| 538 | -module l2t |
| 539 | -reset ~(rst_wmr_) |
| 540 | */ |
| 541 | |
| 542 | /*0in mutex -var l2t_l2d_way_sel_c2 -module l2t |
| 543 | */ |
| 544 | |
| 545 | //debug logic |
| 546 | |
| 547 | /*0in assert_together -follower l2t_dbg_pa_match -leader $0in_delay((csr.arb_inst_vld_c6 && ((arbdec.arbdp_inst_c6[25:21] & csr.l2_mask_register[52:48]) == csr.l2_compare_register[52:48]) && ((arbdec.arbdp_inst_c6[18:13] & csr.l2_mask_register[45:40]) == csr.l2_compare_register[45:40]) && ((arbadr.arbdp_addr_c6[33:2] & csr.l2_mask_register[33:2]) == csr.l2_compare_register[33:2])), 2) -module l2t |
| 548 | */ |
| 549 | |
| 550 | /*x0in assert -var l2t_dbg_pa_match -active $0in_delay((csr.arb_inst_vld_c6 && ((arbdec.arbdp_inst_c6[25:21] & csr.l2_mask_register[52:48]) == csr.l2_compare_register[52:48]) && ((arbdec.arbdp_inst_c6[18:13] & csr.l2_mask_register[45:40]) == csr.l2_compare_register[45:40]) && ((arbadr.arbdp_addr_c6[33:2] & csr.l2_mask_register[33:2]) == csr.l2_compare_register[33:2])), 1) -module l2t |
| 551 | */ |
| 552 | |
| 553 | /*0in assert_follower -follower l2t_dbg_err_event -leader (csr.dbg_trigger && (csr.csr_l2_errstate_reg[36] | csr.csr_l2_errstate_reg[35] | csr.csr_l2_notdata_reg[49] | csr.csr_l2_notdata_reg[48])) -min 1 -max 1 -module l2t |
| 554 | */ |
| 555 | |
| 556 | /*x0in assert -var l2t_dbg_err_event -active (csr.dbg_trigger && (csr.csr_l2_errstate_reg[36] | csr.csr_l2_errstate_reg[35] | csr.csr_l2_notdata_reg[49] | csr.csr_l2_notdata_reg[48])) -module l2t |
| 557 | */ |
| 558 | |
| 559 | /*0in custom -module l2t -clock shadow_scan.l2clk -name l2t_shadow_scan_erraddr_reg -fire (({shadow_scan.shdw_rd_errstate_reg_unused[3:0],shadow_scan.shdw_rd_errstate_reg_unused[63:32]}) != $0in_delay(csr.csr_l2_erraddr_reg[39:4],1)) -active $0in_delay((~shadow_scan.tcu_l2t_shscan_scan_en & ~shadow_scan.tcu_l2t_shscan_clk_stop_d2),1) -message ("l2t Shadow scan mismatch on erraddr_reg ; Exp=%h, Act=%h%h, l2t_shscan_scan_en: %b, tcu_l2t_shscan_clk_stop_d2: %b",csr.csr_l2_erraddr_reg[39:4], shadow_scan.shdw_rd_errstate_reg_unused[3:0],shadow_scan.shdw_rd_errstate_reg_unused[63:32],shadow_scan.tcu_l2t_shscan_scan_en,shadow_scan.tcu_l2t_shscan_clk_stop_d2) |
| 560 | */ |
| 561 | |
| 562 | /*0in custom -module l2t -clock shadow_scan.l2clk -name l2t_shadow_scan_notdata_reg -fire (({shadow_scan.shdw_rd_notdata_reg_unused[51:32],shadow_scan.shdw_rd_errstate_reg_unused[31:4]}) != $0in_delay(csr.csr_l2_notdata_reg[51:4],1)) -active $0in_delay((~shadow_scan.tcu_l2t_shscan_scan_en & ~shadow_scan.tcu_l2t_shscan_clk_stop_d2),1) -message ("l2t Shadow scan mismatch on notdata_reg; Exp=%h, Act=%h%h, l2t_shscan_scan_en: %b, tcu_l2t_shscan_clk_stop_d2: %b",csr.csr_l2_notdata_reg[51:4], shadow_scan.shdw_rd_notdata_reg_unused[51:32],shadow_scan.shdw_rd_errstate_reg_unused[31:4],shadow_scan.tcu_l2t_shscan_scan_en,shadow_scan.tcu_l2t_shscan_clk_stop_d2) |
| 563 | */ |
| 564 | |
| 565 | /*0in custom -module l2t -clock shadow_scan.l2clk -name l2t_shadow_scan_errstate_reg -fire (({shadow_scan.shdw_csr_l2_erraddr_reg_unused[45:32],shadow_scan.shdw_rd_notdata_reg_unused[31:0],shadow_scan.shdw_rd_notdata_reg_unused[63:52]}) != $0in_delay(({csr.rd_errstate_reg[63:34],csr.rd_errstate_reg[27:0]}),1)) -active $0in_delay((~shadow_scan.tcu_l2t_shscan_scan_en & ~shadow_scan.tcu_l2t_shscan_clk_stop_d2),1) -message ("l2t Shadow scan mismatch on errstate_reg; Exp=%h%h, Act=%h%h%h, l2t_shscan_scan_en: %b, tcu_l2t_shscan_clk_stop_d2: %b",csr.rd_errstate_reg[63:34],csr.rd_errstate_reg[27:0], shadow_scan.shdw_csr_l2_erraddr_reg_unused[45:32],shadow_scan.shdw_rd_notdata_reg_unused[31:0],shadow_scan.shdw_rd_notdata_reg_unused[63:52],shadow_scan.tcu_l2t_shscan_scan_en,shadow_scan.tcu_l2t_shscan_clk_stop_d2) |
| 566 | */ |
| 567 | |
| 568 | endmodule //l2_inline |