| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: pll_bypass.vh |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | integer sys_clk_per; // clk period of PLL_CMP_CLK_P pkg pin (aka sys clk). |
| 36 | integer ext_cmp_clk_half_per, ext_dr_clk_half_per; // half clk period of ext_cmp_clk and ext_dr_clk |
| 37 | // reg ext_dr_clk_reg, ext_cmp_clk_reg; // clock generators for ext_cmp_clk and ext_dr_clk |
| 38 | |
| 39 | //---- generate external cmp and dr clocks and drive them onto pkg pins --- |
| 40 | //---- NOTE: cmp-to-sys clk ratio is 4:1 and dr-sys-clk clk ratio is 2:1 ---- |
| 41 | initial begin |
| 42 | if ($test$plusargs("pll_bypass")) begin |
| 43 | //ext_cmp_clk_reg = 1'b0; |
| 44 | //ext_dr_clk_reg = 1'b0; |
| 45 | dbg_dq_reg[138] = 1'b0; |
| 46 | dbg_dq_reg[139] = 1'b0; |
| 47 | |
| 48 | //--- get sys clk period from pkg pin. Compute clk periods for ext cmp/dr clks. Sync cmp/dr clks edges to sys clk--- |
| 49 | @(posedge `CPU.PLL_CMP_CLK_P); |
| 50 | sys_clk_per = $time; |
| 51 | @(posedge `CPU.PLL_CMP_CLK_P); |
| 52 | sys_clk_per = $time - sys_clk_per; |
| 53 | ext_cmp_clk_half_per = sys_clk_per / 8; // cmp-to-sys clk ratio is 4:1 |
| 54 | ext_dr_clk_half_per = sys_clk_per / 4; // dr-to-sys clk ratio is 2:1 |
| 55 | `PR_ALWAYS("tb_top", `ALWAYS, "pll bypass mode: sys clk per=%0d, ext_dr_clk per=%0d, ext_cmp_clk per=%0d", sys_clk_per, ext_dr_clk_half_per * 2, ext_cmp_clk_half_per * 2); |
| 56 | |
| 57 | //--- generate clocks for ext_cmp_clk and ext_dr_clk --- |
| 58 | fork begin |
| 59 | @(posedge `CPU.PWRON_RST_L); // not toggle ext_cmp_clk until PWRON_RST_L deasserted. |
| 60 | @(posedge `CPU.PLL_CMP_CLK_P); // sync ext_cmp_clk with sys clk rising edge |
| 61 | //ext_cmp_clk_reg = 1'b1; // sync rising edge of ext_cmp_clk to sys clk |
| 62 | //forever #ext_cmp_clk_half_per ext_cmp_clk_reg = ~ext_cmp_clk_reg; |
| 63 | dbg_dq_reg[138] = 1'b1; // sync rising edge of ext_cmp_clk to sys clk |
| 64 | `ifndef AXIS_TL |
| 65 | forever #ext_cmp_clk_half_per dbg_dq_reg[138] = ~dbg_dq_reg[138]; |
| 66 | `endif |
| 67 | end |
| 68 | begin |
| 69 | @(posedge `CPU.PWRON_RST_L); // not toggle ext_dr_clk until PWRON_RST_L deasserted |
| 70 | @(posedge `CPU.PLL_CMP_CLK_P); // sync ext_dr_clk with sys clk rising edge |
| 71 | //ext_dr_clk_reg = 1'b1; // sync rising edge of ext_dr_clk to sys clk |
| 72 | //forever #ext_dr_clk_half_per ext_dr_clk_reg = ~ext_dr_clk_reg; |
| 73 | dbg_dq_reg[139] = 1'b1; // sync rising edge of ext_dr_clk to sys clk |
| 74 | `ifndef AXIS_TL |
| 75 | forever #ext_dr_clk_half_per dbg_dq_reg[139] = ~dbg_dq_reg[139]; |
| 76 | `endif |
| 77 | end |
| 78 | join |
| 79 | end // if ($test$plusargs |
| 80 | end // initial |
| 81 | |
| 82 | //---- setup for PLL bypass mode ------ |
| 83 | initial begin |
| 84 | if ($test$plusargs("pll_bypass")) begin |
| 85 | `PR_ALWAYS("tb_top", `ALWAYS, "+pll_bypass is used. Config for PLL BYPASS: PLL_TESTMODE=1, PLL_CMP_BYPASS=1. Drive ext_dr/cmp_clk from pkg pins"); |
| 86 | pll_testmode_reg = 1'b1; |
| 87 | pll_cmp_bypass_reg = 1'b1; |
| 88 | dbg_dq_reg[150] = 1'b0; // aka PLL_TRST_L. Reset PLL (see MIO MAS for name mapping) |
| 89 | dbg_dq_reg[149] = 1'b0; // aka PLL_CLAMP_FLTR (see MIO MAS for name mapping) |
| 90 | //dbg_dq_reg[139] = ext_dr_clk_reg; // aka EXT_DR_CLK (see MIO MAS for name mapping) |
| 91 | //dbg_dq_reg[138] = ext_cmp_clk_reg; // aka EXT_CMP_CLK (see MIO MAS for name mapping) |
| 92 | dbg_dq_reg[156:151] = 6'h7; // aka PLL_DIV2[5:0]. 7 means divided by 8 |
| 93 | dbg_dq_reg[146:140] = 7'h8; // aka PLL_DIV4[6:0]. 8 means divided by 4.0 (ie. fractional divider) |
| 94 | `ifndef GATESIM |
| 95 | `ifndef FAST_AXIS |
| 96 | force `CPU.ccu.ccu_pll.vco_out = 1'b0; // WARNING: force PLL output to 0, so we know pll bypass works |
| 97 | `endif |
| 98 | `endif |
| 99 | //--- when PLL_TESTMODE is 1, reset PLL with pkg pin PLL_TRST_L --- |
| 100 | @(posedge `CPU.PWRON_RST_L); |
| 101 | repeat (3) @(posedge `CPU.PLL_CMP_CLK_P); |
| 102 | dbg_dq_reg[150] = 1'b1; // aka PLL_TRST_L |
| 103 | end |
| 104 | end |
| 105 | |