| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ilupeuLinkTrainingStrategy.vr |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 29 | // |
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| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #include <vera_defines.vrh> |
| 36 | |
| 37 | class ilupeuLinkTrainingStrategy extends ilupeuStrategyBase { |
| 38 | |
| 39 | bit[ ILUPEU_CSR_WIDTH-1:0 ] ilupeuRegTmpData, ilupeuRegTmpData1, ilupeuRegTmpData2; |
| 40 | bit[ FNX_PCIE_XTR_REG_DEN_WIDTH-1:0 ] denRegTmpData; |
| 41 | bit[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CAP_WIDTH_WIDTH-1:0 ] calculatedWidth; |
| 42 | bit Retrain = 0; |
| 43 | bit goto_polling = 0; |
| 44 | |
| 45 | task new( ReportClass _Report, |
| 46 | CSRCollection _CSR, |
| 47 | ilupeuPodClass _Pod, |
| 48 | ilupeuScenario _Scenario ); |
| 49 | |
| 50 | task Execute(); |
| 51 | |
| 52 | task Check_Flow_Control_Init(); |
| 53 | task Check_Link_Status(); |
| 54 | task Check_Denali_Status(); |
| 55 | task Denali_Flow_Control_Timers(); |
| 56 | /* |
| 57 | task Check_LPUSD_Link_Layer_Status(); |
| 58 | task Check_LPUSD_LTSSM_Status1(); |
| 59 | task Check_LPUSD_Rx_Phy_Stat2(); |
| 60 | task Check_LPUSD_Rx_Phy_Stat3(); |
| 61 | //review N2- task Check_LPUSD_Transmit_Phy_Status(); |
| 62 | */ |
| 63 | |
| 64 | task RetrainLink(); |
| 65 | task toLtssmState( bit [4:0] ltssmState, |
| 66 | (integer timer=2000), |
| 67 | (integer accessMethod=OMNI) ); |
| 68 | |
| 69 | |
| 70 | |
| 71 | } |
| 72 | |
| 73 | task ilupeuLinkTrainingStrategy::new( ReportClass _Report, |
| 74 | CSRCollection _CSR, |
| 75 | ilupeuPodClass _Pod, |
| 76 | ilupeuScenario _Scenario ){ |
| 77 | super.new( _Report, |
| 78 | _CSR, |
| 79 | _Pod, |
| 80 | _Scenario ); |
| 81 | } |
| 82 | |
| 83 | task ilupeuLinkTrainingStrategy::RetrainLink(){ |
| 84 | //Use this after a warm reset |
| 85 | bit Retrain = 1; |
| 86 | } |
| 87 | |
| 88 | |
| 89 | task ilupeuLinkTrainingStrategy::Execute(){ |
| 90 | |
| 91 | integer linkTrainingCycles = 0; |
| 92 | integer linkTrainingTimeout; |
| 93 | integer rdDelay = 30; |
| 94 | bit inProgressSet = 0; |
| 95 | bit [2:0] dataLinkState = 0; |
| 96 | bit [7:0] lanes = 0; |
| 97 | integer timer; |
| 98 | |
| 99 | |
| 100 | //FNXPCIEXtr Transaction used to access Denali registers |
| 101 | regTrans = new( Pod.FNXPCIEBldr ); |
| 102 | |
| 103 | if( Scenario.FastLinkTraining ){ |
| 104 | linkTrainingTimeout = ILUPEU_FAST_LINK_TRAIN_TO; |
| 105 | } |
| 106 | else{ |
| 107 | linkTrainingTimeout = ILUPEU_DEFAULT_LINK_TRAIN_TO; |
| 108 | } |
| 109 | |
| 110 | //Check if SDS_READY_ serdes are ready |
| 111 | ilupeuRegTmpData = Pod.CSRXtr.CSR.fire_plc_tlu_ctb_tlr_csr_a_core_status.read(CSRT_OMNI); |
| 112 | if( (ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_SDS_READY_0_SLC ] == 0) || |
| 113 | (ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_SDS_READY_1_SLC ] == 0) ){ |
| 114 | Report.report(RTYP_TEST_ERROR, "PEU DLPL Core Status register SDS_READY_0=%0h SDS_READY_1=%0h and both should be 1.\n",ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_SDS_READY_0_SLC ],ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_SDS_READY_1_SLC ] ); |
| 115 | } |
| 116 | |
| 117 | |
| 118 | #ifndef N2_FC |
| 119 | //This moved from InitStrategy to here! |
| 120 | repeat( Scenario.ilupeuDetectQuietDelay ) @(posedge CLOCK); |
| 121 | //Make sure LTSSM is still in detect.quiet |
| 122 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_core_status.read(CSRT_OMNI); |
| 123 | if( ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_LTSSM_STATE_SLC ] !== 5'h0 ){ //Detect.Quiet |
| 124 | Report.report(RTYP_TEST_ERROR, "LinkTrainingStrategy PEU DLPL Core Status register LTSSM_STATE=%0h is not in Detect.Quiet\n",ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_LTSSM_STATE_SLC ] ); |
| 125 | } |
| 126 | |
| 127 | // turn on RX_HIGH_IMP_DIS bit 3 of PEU DLPL MACL/PCS control register for the link to proceed to train |
| 128 | // note: in simulation, Denali works without having to set this bit to 1. |
| 129 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_link_ctl.read(); |
| 130 | ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_RX_HIGH_IMP_DIS_SLC] = 1; //Turn on RX_HIGH_IMP_DIS |
| 131 | CSR.fire_plc_tlu_ctb_tlr_csr_a_link_ctl.write(ilupeuRegTmpData,CSRT_OMNI); |
| 132 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_link_ctl.read(); |
| 133 | Report.report(RTYP_INFO,"AC: before training, RX_HIGH_IMP_DIS = %d , term should be = 3'b100 \n", ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_RX_HIGH_IMP_DIS_SLC]); |
| 134 | |
| 135 | |
| 136 | // Turn off remain in detect.quiet |
| 137 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_tlu_ctl.read(); |
| 138 | ilupeuRegTmpData[8] = 0; //Turn off remain in detect.quiet |
| 139 | //// CSR.fire_plc_tlu_ctb_tlr_csr_a_tlu_ctl.write(ilupeuRegTmpData,CSRT_DAEMON); |
| 140 | CSR.fire_plc_tlu_ctb_tlr_csr_a_tlu_ctl.write(ilupeuRegTmpData,CSRT_OMNI); |
| 141 | |
| 142 | #endif |
| 143 | |
| 144 | //Receive Detect Lanes set |
| 145 | { |
| 146 | //Wait until Detect.Active is entered |
| 147 | fork |
| 148 | { |
| 149 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_core_status.read(CSRT_OMNI); |
| 150 | while( ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_LTSSM_STATE_SLC ] !== ILUPEU_LTSSM_DETECT_ACT ){ |
| 151 | if( !Scenario.FastLinkTraining ){ |
| 152 | repeat(100) @(posedge CLOCK); |
| 153 | } |
| 154 | else{ |
| 155 | repeat(10) @(posedge CLOCK); |
| 156 | } |
| 157 | |
| 158 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_core_status.read(CSRT_OMNI); |
| 159 | } |
| 160 | } |
| 161 | { |
| 162 | //Timeout for Detect.Quiet |
| 163 | if( !Scenario.FastLinkTraining ){ |
| 164 | //12ms = ~4512000 375MHz clock cycles |
| 165 | timer = 4512000 - Scenario.ilupeuDetectQuietDelay; |
| 166 | } |
| 167 | else{ |
| 168 | timer = 4512 - Scenario.ilupeuDetectQuietDelay; |
| 169 | } |
| 170 | while( timer ){ |
| 171 | @(posedge CLOCK); |
| 172 | timer--; |
| 173 | if( !(timer%1000) ){ |
| 174 | printf("ilupeuLinkTrainingStrategy Detect.Quiet to Detect.Active timer=%0d",timer); |
| 175 | } |
| 176 | } |
| 177 | } |
| 178 | join any |
| 179 | if( !timer ){ |
| 180 | Report.report(RTYP_TEST_ERROR, "ilupeuLinkTrainingStrategy timed out waiting to enter Detect.Active"); |
| 181 | } |
| 182 | terminate; //Kill timer if transition happens |
| 183 | |
| 184 | |
| 185 | //Create the Transaction used for Denali register access |
| 186 | regTrans = new( Pod.FNXPCIEBldr ); |
| 187 | //Delay for Fast or Slow Link Training |
| 188 | //Determine that Receive Detect has started and time how much time(cycles) |
| 189 | // is needed before driving lanes for receive detect |
| 190 | //Set which lanes will detect a receiver |
| 191 | if( !Scenario.FastLinkTraining ){ |
| 192 | |
| 193 | // Turn on remain in detect.quiet |
| 194 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_tlu_ctl.read(CSRT_OMNI); |
| 195 | ilupeuRegTmpData[8] = 1; //Turn off remain in detect.quiet |
| 196 | CSR.fire_plc_tlu_ctb_tlr_csr_a_tlu_ctl.write(ilupeuRegTmpData,CSRT_OMNI); |
| 197 | |
| 198 | //Delay for correct Receiver Detect Timing |
| 199 | //12-1-05 New Serdes //100uS prep - 38270 375MHz Clocks - actually 101.8uS |
| 200 | //1mS prep - 382700 375MHz Clocks - actually 1018uS |
| 201 | // <1uS - No Receiver - 382 375MHz Clocks |
| 202 | //12-1-05 New Serdes // >30uS - Receiver - 11278 375MHz Clocks |
| 203 | // >5uS - Receiver - 1880 375MHz Clocks |
| 204 | timer = 377300; |
| 205 | while( timer ){ |
| 206 | @(posedge CLOCK); |
| 207 | timer--; |
| 208 | if( !(timer%1000) ){ |
| 209 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_core_status.read(CSRT_OMNI); |
| 210 | if( ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_LTSSM_STATE_SLC ] !== ILUPEU_LTSSM_DETECT_ACT ){ |
| 211 | Report.report(RTYP_TEST_ERROR, "ilupeuLinkTrainingStrategy NOT in Detect.Active during prep period timer=%0d",timer); |
| 212 | } |
| 213 | printf("ilupeuLinkTrainingStrategy Detect.Active receiver detect 1mS prep period timer=%0d cycle=%0d \n",timer,get_cycle()); |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | // 1uS delay for lanes NOT detected |
| 218 | //review timer = urandom_range(350,300); |
| 219 | timer = 200; |
| 220 | printf("ilupeuLinkTrainingStrategy 1uS timer=%0d for NO Receiver\n",timer); |
| 221 | while( timer ){ |
| 222 | @(posedge CLOCK); |
| 223 | timer--; |
| 224 | } |
| 225 | } //end !FastLinkTraining |
| 226 | |
| 227 | if( Scenario.FastLinkTraining ){ |
| 228 | case( Scenario.denaliLinkCapMaxLinkWdth ){ |
| 229 | 8: regTrans.SetRcvDetLanes( 8'hff ); |
| 230 | 4: regTrans.SetRcvDetLanes( 8'h0f ); |
| 231 | 2: regTrans.SetRcvDetLanes( 8'h03 ); |
| 232 | 1: regTrans.SetRcvDetLanes( 8'h01 ); |
| 233 | default: regTrans.SetRcvDetLanes( 8'hff ); |
| 234 | } |
| 235 | }else{ |
| 236 | case( Scenario.denaliLinkCapMaxLinkWdth ){ |
| 237 | 8: regTrans.SetRcvDetLanes( 8'h00 ); |
| 238 | 4: regTrans.SetRcvDetLanes( 8'hf0 ); |
| 239 | 2: regTrans.SetRcvDetLanes( 8'hfc ); |
| 240 | 1: regTrans.SetRcvDetLanes( 8'hfe ); |
| 241 | default: regTrans.SetRcvDetLanes( 8'h00 ); |
| 242 | } |
| 243 | } |
| 244 | |
| 245 | //Should stay here for 3uS more |
| 246 | if( !Scenario.FastLinkTraining ){ |
| 247 | // 4uS delay |
| 248 | timer = 1100; |
| 249 | printf("ilupeuLinkTrainingStrategy 4uS timer=%0d for Receiver\n",timer); |
| 250 | while( timer ){ |
| 251 | @(posedge CLOCK); |
| 252 | timer--; |
| 253 | if( !(timer%100) ){ |
| 254 | printf("ilupeuLinkTrainingStrategy 4uS delay timer=%0d cycle=%0d \n",timer,get_cycle()); |
| 255 | toLtssmState( ILUPEU_LTSSM_DETECT_ACT,1,OMNI ); |
| 256 | |
| 257 | } |
| 258 | } |
| 259 | printf("ilupeuLinkTrainingStrategy 4uS delay timer=%0d cycle=%0d \n",timer,get_cycle()); |
| 260 | toLtssmState( ILUPEU_LTSSM_DETECT_ACT,1,OMNI ); |
| 261 | } |
| 262 | |
| 263 | |
| 264 | fork |
| 265 | { |
| 266 | //After exiting Detect.Active don't force any more |
| 267 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_core_status.read(CSRT_OMNI); |
| 268 | while( ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_LTSSM_STATE_SLC ] == ILUPEU_LTSSM_DETECT_ACT ){ |
| 269 | @(posedge CLOCK); |
| 270 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_core_status.read(CSRT_OMNI); |
| 271 | } |
| 272 | } |
| 273 | |
| 274 | { |
| 275 | timer=10000; |
| 276 | while( timer ){ |
| 277 | @(posedge CLOCK); |
| 278 | timer--; |
| 279 | if( !(timer%1000) ){ |
| 280 | printf("ilupeuLinkTrainingStrategy exiting Detect.Active timer=%0d",timer); |
| 281 | } |
| 282 | } |
| 283 | |
| 284 | } |
| 285 | join any |
| 286 | if( !timer ){ |
| 287 | Report.report(RTYP_TEST_ERROR, "ilupeuLinkTrainingStrategy timed out waiting to exit Detect.Active"); |
| 288 | } |
| 289 | terminate; //Kill timer if transition happens |
| 290 | |
| 291 | |
| 292 | printf("ilupeuLinkTrainingStrategy finished 1st detect.active STATUS_LTSSM_STATE=%h cycle=%0d \n",ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_LTSSM_STATE_SLC ],get_cycle()); |
| 293 | |
| 294 | //Release the Receive Detect forces |
| 295 | if( Scenario.FastLinkTraining ){ |
| 296 | regTrans.SetRcvDetLanes( 8'hff ); |
| 297 | }else{ |
| 298 | regTrans.SetRcvDetLanes( 8'h00 ); |
| 299 | } |
| 300 | |
| 301 | printf("ilupeuLinkTrainingStrategy after Release the Receive Detect forces STATUS_LTSSM_STATE=%h cycle=%0d \n",ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_LTSSM_STATE_SLC ],get_cycle()); |
| 302 | |
| 303 | //If less then x8 then we need 12ms timeout and then another Receive Detect sequence |
| 304 | if( Scenario.denaliLinkCapMaxLinkWdth < 8 ){ |
| 305 | printf("Trying to train for less lanes then capable so going to Detect.Wait\n"); |
| 306 | toLtssmState( ILUPEU_LTSSM_DETECT_WAIT,1,OMNI ); |
| 307 | //This is the 12mS timeout |
| 308 | //Timeout for Detect.Active |
| 309 | if( !Scenario.FastLinkTraining ){ |
| 310 | //12ms = ~4592000 375MHz clock cycles |
| 311 | timer = 4580000 - Scenario.ilupeuDetectQuietDelay; |
| 312 | } |
| 313 | else{ |
| 314 | timer = 4512 - Scenario.ilupeuDetectQuietDelay; |
| 315 | } |
| 316 | while( timer ){ |
| 317 | @(posedge CLOCK); |
| 318 | timer--; |
| 319 | if( !(timer%1000) ){ |
| 320 | printf("ilupeuLinkTrainingStrategy Detect.Wait 12mS timer=%0d\n cycle=%0d",timer,get_cycle() ); |
| 321 | toLtssmState( ILUPEU_LTSSM_DETECT_WAIT,1,OMNI ); |
| 322 | } |
| 323 | } |
| 324 | |
| 325 | toLtssmState( ILUPEU_LTSSM_DETECT_ACT,250000,OMNI ); |
| 326 | printf("Trying to train for less lanes then capable so another receive detect sequence is needed in Detect.Active cycle=%0d\n",get_cycle() ); |
| 327 | |
| 328 | if( !Scenario.FastLinkTraining ){ |
| 329 | //Delay for correct Receiver Detect Timing |
| 330 | //12-1-05 New Serdes //100uS prep - 38270 375MHz Clocks - actually 101.8uS |
| 331 | //1mS prep - 382700 375MHz Clocks - actually 1018uS |
| 332 | // <1uS - No Receiver - 382 375MHz Clocks |
| 333 | //12-1-05 New Serdes // >30uS - Receiver - 11278 375MHz Clocks |
| 334 | // >5uS - Receiver - 1880 375MHz Clocks |
| 335 | |
| 336 | |
| 337 | |
| 338 | timer = 377300; |
| 339 | while( timer ){ |
| 340 | @(posedge CLOCK); |
| 341 | timer--; |
| 342 | if( !(timer%1000) ){ |
| 343 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_core_status.read(CSRT_OMNI); |
| 344 | if( ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_LTSSM_STATE_SLC ] !== ILUPEU_LTSSM_DETECT_ACT ){ |
| 345 | Report.report(RTYP_TEST_ERROR, "ilupeuLinkTrainingStrategy NOT in Detect.Active during 2nd prep period timer=%0d",timer); |
| 346 | } |
| 347 | printf("ilupeuLinkTrainingStrategy Detect.Active receiver detect 2nd prep period timer=%0d cycle=%0d \n",timer,get_cycle()); |
| 348 | } |
| 349 | } |
| 350 | |
| 351 | // 1uS delay for lanes NOT detected |
| 352 | timer = urandom_range(300,200); |
| 353 | printf("ilupeuLinkTrainingStrategy 1uS timer=%0d for No Receiver\n",timer); |
| 354 | while( timer ){ |
| 355 | @(posedge CLOCK); |
| 356 | timer--; |
| 357 | } |
| 358 | } //end !FastLinkTraining |
| 359 | |
| 360 | if( Scenario.FastLinkTraining ){ |
| 361 | case( Scenario.denaliLinkCapMaxLinkWdth ){ |
| 362 | 8: regTrans.SetRcvDetLanes( 8'hff ); |
| 363 | 4: regTrans.SetRcvDetLanes( 8'h0f ); |
| 364 | 2: regTrans.SetRcvDetLanes( 8'h03 ); |
| 365 | 1: regTrans.SetRcvDetLanes( 8'h01 ); |
| 366 | default: regTrans.SetRcvDetLanes( 8'hff ); |
| 367 | } |
| 368 | }else{ |
| 369 | case( Scenario.denaliLinkCapMaxLinkWdth ){ |
| 370 | 8: regTrans.SetRcvDetLanes( 8'h00 ); |
| 371 | 4: regTrans.SetRcvDetLanes( 8'hf0 ); |
| 372 | 2: regTrans.SetRcvDetLanes( 8'hfc ); |
| 373 | 1: regTrans.SetRcvDetLanes( 8'hfe ); |
| 374 | default: regTrans.SetRcvDetLanes( 8'h00 ); |
| 375 | } |
| 376 | } |
| 377 | |
| 378 | |
| 379 | //Should stay here for 3uS more |
| 380 | if( !Scenario.FastLinkTraining ){ |
| 381 | // 3uS delay |
| 382 | timer = 1100; |
| 383 | printf("ilupeuLinkTrainingStrategy 3uS timer=%0d for Receiver\n",timer); |
| 384 | while( timer ){ |
| 385 | @(posedge CLOCK); |
| 386 | timer--; |
| 387 | if( !(timer%100) ){ |
| 388 | printf("ilupeuLinkTrainingStrategy 3uS delay timer=%0d cycle=%0d \n",timer,get_cycle()); |
| 389 | toLtssmState( ILUPEU_LTSSM_DETECT_ACT,1,OMNI ); |
| 390 | |
| 391 | } |
| 392 | } |
| 393 | } |
| 394 | |
| 395 | //Wait until Polling.Active is entered |
| 396 | toLtssmState( ILUPEU_LTSSM_POLL_ACTIVE,*,OMNI ); |
| 397 | |
| 398 | //Release the Receive Detect forces |
| 399 | if( Scenario.FastLinkTraining ){ |
| 400 | regTrans.SetRcvDetLanes( 8'hff ); |
| 401 | }else{ |
| 402 | regTrans.SetRcvDetLanes( 8'h00 ); |
| 403 | } |
| 404 | |
| 405 | } //end less then x8 |
| 406 | } |
| 407 | |
| 408 | |
| 409 | if (!goto_polling) { |
| 410 | |
| 411 | fork |
| 412 | { |
| 413 | //Read the TLU Status register to see if the Data Link Active state has been reached |
| 414 | //review - The lxLinkUp is not available in the PTL so add it when Cascade registers are available |
| 415 | |
| 416 | //Make sure Polling.Active is entered |
| 417 | toLtssmState( ILUPEU_LTSSM_POLL_ACTIVE,1000,OMNI ); |
| 418 | |
| 419 | |
| 420 | |
| 421 | |
| 422 | //12-2-05 New Serdes toggles the TX lanes causing Denali to Detect Receivers |
| 423 | // on lanes that won't be transmitting so force Denali back to Detect |
| 424 | if( (Scenario.ilupeuLinkCapMaxLinkWdth < Scenario.denaliLinkCapMaxLinkWdth) |
| 425 | && ( Scenario.FastLinkTraining ) ){ |
| 426 | //Write Denali to force LTSSM to Detect so it doesn't try to enter |
| 427 | // polling.compliance |
| 428 | regTrans.WriteDenaliReg( PCIE_REG_DEN_LINK_CTRL, 32'h80 ); |
| 429 | } |
| 430 | |
| 431 | #ifndef N2_FC |
| 432 | //If this is for slow link training then PEU must send 1024 TS1s in polling.active |
| 433 | // so wait for that to happen |
| 434 | if( !Scenario.FastLinkTraining ){ |
| 435 | toLtssmState( ILUPEU_LTSSM_POLL_CONFIG,25000,OMNI ); |
| 436 | } |
| 437 | //Make sure Configuration is entered |
| 438 | toLtssmState( ILUPEU_LTSSM_CFG_LINKWD_START,1000,OMNI ); |
| 439 | //then Reenable LOS error |
| 440 | ilupeuRegTmpData2 = CSR.fire_plc_tlu_ctb_tlr_csr_a_event_err_log_en.read(CSRT_OMNI); |
| 441 | ilupeuRegTmpData2[0] = 1; |
| 442 | CSR.fire_plc_tlu_ctb_tlr_csr_a_event_err_log_en.write(ilupeuRegTmpData2,CSRT_OMNI); |
| 443 | #endif |
| 444 | |
| 445 | ilupeuRegTmpData2 = CSR.fire_plc_tlu_ctb_tlr_csr_a_tlu_sts.read(CSRT_OMNI); |
| 446 | while( !( ilupeuRegTmpData2[ FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_STATUS_SLC ] === {5'h0,ILUPEU_DL_ACTIVE} ) ){ |
| 447 | |
| 448 | repeat(rdDelay) @(posedge CLOCK); |
| 449 | |
| 450 | //Increment the cycle count and see if a timeout has occured |
| 451 | linkTrainingCycles = linkTrainingCycles+rdDelay; |
| 452 | |
| 453 | if( linkTrainingCycles > linkTrainingTimeout ){ |
| 454 | Report.report(RTYP_TEST_ERROR, "LinkTrainingStrategy timed out waiting for link to train linkState=%0h.\n",ilupeuRegTmpData2[2:0] ); |
| 455 | } |
| 456 | |
| 457 | if( ilupeuRegTmpData2[ FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_STATUS_SLC ] === {5'h0,ILUPEU_DL_INIT} ){ |
| 458 | rdDelay=5; |
| 459 | } |
| 460 | |
| 461 | ilupeuRegTmpData2 = CSR.fire_plc_tlu_ctb_tlr_csr_a_tlu_sts.read(CSRT_OMNI); |
| 462 | |
| 463 | } |
| 464 | Report.report(RTYP_INFO, "LINK TRAINED linkState=%0h.\n", ilupeuRegTmpData2[2:0] ); |
| 465 | |
| 466 | } |
| 467 | |
| 468 | { //Check that the link training in progress bit is 1 during link training |
| 469 | |
| 470 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_lnk_sts.read(CSRT_OMNI); |
| 471 | while( !ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_TRAIN_SLC ] ){ |
| 472 | repeat(15) @(posedge CLOCK); |
| 473 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_lnk_sts.read(CSRT_OMNI); |
| 474 | } |
| 475 | inProgressSet = 1; |
| 476 | |
| 477 | //Make sure PCS bit/byte alignment is set |
| 478 | case( Scenario.denaliLinkCapMaxLinkWdth ){ |
| 479 | 8: lanes = 8'hff; |
| 480 | 4: lanes = 8'h0f; |
| 481 | 2: lanes = 8'h03; |
| 482 | 1: lanes = 8'h01; |
| 483 | default: lanes = 8'hff; |
| 484 | } |
| 485 | ilupeuRegTmpData = Pod.CSRXtr.CSR.fire_plc_tlu_ctb_tlr_csr_a_core_status.read(CSRT_OMNI); |
| 486 | if( (ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_PCS_LOCK_STS_SLC ] !== lanes) ){ |
| 487 | //N2 review THIS USED TO WORK |
| 488 | Report.report(RTYP_INFO, "\n\n PEU DLPL Core Status register PCS_LOCK_STS= %0h and should be %0h.\n\n",ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_PCS_LOCK_STS_SLC ], lanes ); |
| 489 | // Report.report(RTYP_TEST_ERROR, "PEU DLPL Core Status register PCS_LOCK_STS= %0h and should be %0h.\n",ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_PCS_LOCK_STS_SLC ], lanes ); |
| 490 | } |
| 491 | |
| 492 | |
| 493 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_lnk_sts.read(CSRT_OMNI); |
| 494 | while( ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_TRAIN_SLC ] ){ //Only care about Train bit 11 |
| 495 | |
| 496 | //RFE P2157 - Speed and Link width should be 0 until link is up |
| 497 | if( (ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_SPEED_INT_SLC ] !== 0) && |
| 498 | (ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_WIDTH_SLC ] !== 0) ){ |
| 499 | Report.report(RTYP_TEST_ERROR, "LinkTrainingStrategy PEU Link Status register SPEED=%0h WIDTH=%0h.\n",ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_SPEED_INT_SLC ],ilupeuRegTmpData2[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_WIDTH_SLC ] ); |
| 500 | } |
| 501 | |
| 502 | repeat(25) @(posedge CLOCK); |
| 503 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_lnk_sts.read(CSRT_OMNI); |
| 504 | } |
| 505 | } |
| 506 | |
| 507 | //Verify that LPUSD_Link_Layer_Status transitions through Flow control states |
| 508 | |
| 509 | |
| 510 | join any |
| 511 | |
| 512 | //If the inProgress bit was never set before link training completes then its an error |
| 513 | if( !inProgressSet ){ |
| 514 | Report.report(RTYP_TEST_ERROR, "LinkTrainingStrategy never detected link training in progress bit set in the PTL(TLU) Link Status register Train bit=%0h linkState=%0h.\n",ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_TRAIN_SLC ],ilupeuRegTmpData2[ FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_STATUS_SLC ] ); |
| 515 | } |
| 516 | |
| 517 | //The inProgress bit should be set first and then the link training should complete so wait for it here |
| 518 | wait_child(); |
| 519 | |
| 520 | |
| 521 | //Links should be trained here so launch a set slot power limit |
| 522 | // expect that automatically gets generated when transitioning |
| 523 | // to DL_Up status - PCIE rev 1.0a 2.2.8.5 |
| 524 | |
| 525 | //Determine the right link width |
| 526 | if( Scenario.ilupeuLinkCapMaxLinkWdth >= Scenario.denaliLinkCapMaxLinkWdth ){ |
| 527 | calculatedWidth = Scenario.denaliLinkCapMaxLinkWdth; |
| 528 | } |
| 529 | else{ |
| 530 | calculatedWidth = Scenario.ilupeuLinkCapMaxLinkWdth; |
| 531 | } |
| 532 | |
| 533 | |
| 534 | //Denali seems to change the timers after link comes up |
| 535 | //Set the Denali ACK/NAK and Replay timers |
| 536 | regTrans.WriteDenaliReg( PCIE_REG_DEN_ACK_NAK_FREQ_TIMER, Scenario.denaliAckNakLatencyTimerThreshold ); |
| 537 | regTrans.WriteDenaliReg( PCIE_REG_DEN_REPLAY_TIMER, Scenario.denaliReplayTimerThreshold |
| 538 | ); |
| 539 | |
| 540 | |
| 541 | //Check the flow control init registers in both the ilupeu and denali |
| 542 | Check_Flow_Control_Init(); |
| 543 | |
| 544 | //Check the link status register |
| 545 | Check_Link_Status(); |
| 546 | |
| 547 | //Check the denali status registers |
| 548 | Check_Denali_Status(); |
| 549 | |
| 550 | //Make sure PCS alignment is set |
| 551 | ilupeuRegTmpData = Pod.CSRXtr.CSR.fire_plc_tlu_ctb_tlr_csr_a_core_status.read(CSRT_OMNI); |
| 552 | if( (ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_PCS_ALIGN_STS_SLC ] == 0) ){ |
| 553 | Report.report(RTYP_TEST_ERROR, "PEU DLPL Core Status register PCS_ALIGN_STS= %0h and should be 1.\n",ilupeuRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_PCS_ALIGN_STS_SLC ] ); |
| 554 | } |
| 555 | |
| 556 | /*review - Enable 1 at a time! |
| 557 | //Disable the automatic Denali Flow Control DLLPs so no unexpected FC Updates are generated |
| 558 | |
| 559 | //Check the lpusd status register |
| 560 | Check_LPUSD_Link_Layer_Status(); |
| 561 | |
| 562 | //Check the lpusd LTSSM status1 register |
| 563 | Check_LPUSD_LTSSM_Status1(); |
| 564 | |
| 565 | //Check the lpusd Receive Phy Status 2 register |
| 566 | Check_LPUSD_Rx_Phy_Stat2(); |
| 567 | |
| 568 | //Check the lpusd Receive Phy Status 3 register |
| 569 | Check_LPUSD_Rx_Phy_Stat3(); |
| 570 | |
| 571 | //Check the Transmit Phy Status register |
| 572 | //review N2- Check_LPUSD_Transmit_Phy_Status(); |
| 573 | |
| 574 | //Check Initial Retry Credits advertised by lpusd |
| 575 | if( Pod.LPUXtr._config._retryCredits !== LPUSD_DEFAULT_RETRY_CREDITS ){ |
| 576 | Report.report(RTYP_TEST_ERROR, "LinkTrainingStrategy detected wrong initial retry credits:lpusd credits=%0h LPUSD_DEFAULT_RETRY_CREDITS=%0h .\n",Pod.LPUXtr._config._retryCredits,LPUSD_DEFAULT_RETRY_CREDITS); |
| 577 | } |
| 578 | |
| 579 | |
| 580 | |
| 581 | */ |
| 582 | |
| 583 | //Print value of Denali_Flow_Control_Timers |
| 584 | //review Denali_Flow_Control_Timers(); |
| 585 | |
| 586 | } |
| 587 | else { |
| 588 | printf("AC: link training goes to polling active state only \n"); |
| 589 | } |
| 590 | } |
| 591 | |
| 592 | /* |
| 593 | |
| 594 | //Check status registers in the lpusd to make sure link training occured correctly |
| 595 | task ilupeuLinkTrainingStrategy::Check_LPUSD_Link_Layer_Status(){ |
| 596 | |
| 597 | //Read Link Layer Status registers in the PTL to make sure they are correct |
| 598 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_lnk_sts.read(); |
| 599 | |
| 600 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_SLC] !== ILUPEU_DL_ACTIVE){ //3'b100 |
| 601 | Report.report(RTYP_TEST_ERROR, "Link Layer status register NOT in DL_Active state LPU_LL_STAT_LNK_STATE_MACH_STS_SLC=%h linkStatus=%0h linkState=%0h.\n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_SLC],Pod.LPUXtr._config._linkStatus,Pod.LPUXtr._config._linkState); |
| 602 | } |
| 603 | |
| 604 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_SLC] !== LPUSD_LINK_UP){ //1'b1 |
| 605 | Report.report(RTYP_TEST_ERROR, "Link Layer status register NOT in DL Up state LPU_LL_STAT_DLUP_STS_SLC=%h linkStatus=%0h linkState=%0h.\n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_SLC],Pod.LPUXtr._config._linkStatus,Pod.LPUXtr._config._linkState); |
| 606 | } |
| 607 | |
| 608 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_SLC] !== LPUSD_FC_INIT_DONE){ //2'b10 |
| 609 | Report.report(RTYP_TEST_ERROR, "Link Layer status register NOT in Flow Control Init Done state LPU_LL_STAT_INIT_FC_SM_STS_SLC=%h linkStatus=%0h linkState=%0h.\n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_SLC],Pod.LPUXtr._config._linkStatus,Pod.LPUXtr._config._linkState); |
| 610 | } |
| 611 | |
| 612 | } |
| 613 | |
| 614 | task ilupeuLinkTrainingStrategy::Check_LPUSD_LTSSM_Status1(){ |
| 615 | |
| 616 | //Read the LTSSM Status register to make sure it is correct |
| 617 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_stat1.read(); |
| 618 | |
| 619 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_SLC] !== LPUSD_LANE_NOT_REVERSED){ //1'b0 |
| 620 | Report.report(RTYP_TEST_ERROR, "LTSSM status1 register NOT in lane not reversed state LPU_LTSSM_STAT1_LN_RVRSD_SLC=%h linkStatus=%0h linkState=%0h.\n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_SLC],Pod.LPUXtr._config._linkStatus,Pod.LPUXtr._config._linkState); |
| 621 | } |
| 622 | |
| 623 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_SLC] !== LPUSD_LINK_UP){ //1'b1 |
| 624 | Report.report(RTYP_TEST_ERROR, "LTSSM status1 register NOT in link up state LPU_LTSSM_STAT1_LNK_UP_DWN_STS_SLC=%h linkStatus=%0h linkState=%0h.\n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_SLC],Pod.LPUXtr._config._linkStatus,Pod.LPUXtr._config._linkState); |
| 625 | } |
| 626 | |
| 627 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_SLC] !== LPUSD_LTSSM_L0){ //5'h0d |
| 628 | Report.report(RTYP_TEST_ERROR, "LTSSM status1 register NOT in LTSSM L0 state LPU_LTSSM_STAT1_LTSSM_STATE_SLC=%h linkStatus=%0h linkState=%0h.\n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_SLC],Pod.LPUXtr._config._linkStatus,Pod.LPUXtr._config._linkState); |
| 629 | } |
| 630 | |
| 631 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_SLC] != calculatedWidth-1){ |
| 632 | Report.report(RTYP_TEST_ERROR, "LTSSM status1 register NOT in Correct Link Width LPU_LTSSM_STAT1_CNFG_LNK_WDTH_SLC=%h linkStatus=%0h linkState=%0h.\n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_SLC],Pod.LPUXtr._config._linkStatus,Pod.LPUXtr._config._linkState); |
| 633 | } |
| 634 | |
| 635 | } |
| 636 | */ |
| 637 | |
| 638 | |
| 639 | |
| 640 | //Check that the initial flow control values got sent and received correctly |
| 641 | task ilupeuLinkTrainingStrategy::Check_Flow_Control_Init(){ |
| 642 | |
| 643 | |
| 644 | //Make sure the right transmitted initialization flow control credits got captured by denali |
| 645 | //You must first write to the FC Control register and then read it |
| 646 | denRegTmpData = 0; |
| 647 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_OP_SLC] = PCIE_FCCTRL_get; |
| 648 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_VC_SLC] = 0; //VC 0 |
| 649 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_PH; |
| 650 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_ID_SLC] = PCIE_FCID_TX_LIMIT; |
| 651 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] = 0; |
| 652 | |
| 653 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 654 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_FC_CTRL ); |
| 655 | if( Scenario.ilupeuInitialPostedHeaderCredit !== denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] ){ |
| 656 | |
| 657 | Report.report(RTYP_TEST_ERROR, "Test failed with wrong Transmitted Flow Control Initialization value InitialPostedHeaderCredit=%0d Denali_PCIE_FCTYPEPH=%0d reg_id=%0h.\n",Scenario.ilupeuInitialPostedHeaderCredit,denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC], denRegTmpData ); |
| 658 | } |
| 659 | |
| 660 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_PD; |
| 661 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] = 0; |
| 662 | //You must first write to the FC Control register and then read it |
| 663 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 664 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_FC_CTRL ); |
| 665 | if( Scenario.ilupeuInitialPostedDataCredit !== denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] ){ |
| 666 | |
| 667 | Report.report(RTYP_TEST_ERROR, "Test failed with wrong Transmitted Flow Control Initialization value InitialPostedDataCredit=%0d Denali_PCIE_FCTYPE_PH=%0d reg_id=%0h.\n",Scenario.ilupeuInitialPostedDataCredit, denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC], denRegTmpData ); |
| 668 | } |
| 669 | |
| 670 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_NPH; |
| 671 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] = 0; |
| 672 | //You must first write to the FC Control register and then read it |
| 673 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 674 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_FC_CTRL ); |
| 675 | if( Scenario.ilupeuInitialNonPostedHeaderCredit !== denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] ){ |
| 676 | |
| 677 | Report.report(RTYP_TEST_ERROR, "Test failed with wrong Transmitted Flow Control Initialization value InitialNonPostedHeaderCredit=%0d Denali_PCIE_FCTYPE_NPH=%0d .\n",Scenario.ilupeuInitialNonPostedHeaderCredit, denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] ); |
| 678 | } |
| 679 | |
| 680 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_NPD; |
| 681 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] = 0; |
| 682 | //You must first write to the FC Control register and then read it |
| 683 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 684 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_FC_CTRL ); |
| 685 | if( Scenario.ilupeuInitialNonPostedDataCredit !== denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] ){ |
| 686 | |
| 687 | Report.report(RTYP_TEST_ERROR, "Test failed with wrong Transmitted Flow Control Initialization value InitialNonPostedDataCredit=%0d Denali_PCIE_FCTYPE_NPH=%0d .\n",Scenario.ilupeuInitialNonPostedDataCredit, denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] ); |
| 688 | } |
| 689 | |
| 690 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_CPLH; |
| 691 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] = 0; |
| 692 | //You must first write to the FC Control register and then read it |
| 693 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 694 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_FC_CTRL ); |
| 695 | //Since Denali's infinite credit is 12'hfff than concatenate a 4'hf to msb of InitialCompletionHeaderCredit |
| 696 | if( {4'hf,Scenario.ilupeuInitialCompletionHeaderCredit} !== denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] ){ |
| 697 | |
| 698 | Report.report(RTYP_TEST_ERROR, "Test failed with wrong Transmitted Flow Control Initialization value InitialCompletionHeaderCredit=%0d Denali_PCIE_FCTYPE_CPLH=%0d .\n",Scenario.ilupeuInitialCompletionHeaderCredit, denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] ); |
| 699 | } |
| 700 | |
| 701 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_CPLD; |
| 702 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] = 0; |
| 703 | //You must first write to the FC Control register and then read it |
| 704 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 705 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_FC_CTRL ); |
| 706 | if( Scenario.ilupeuInitialCompletionDataCredit !== denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] ){ |
| 707 | |
| 708 | Report.report(RTYP_TEST_ERROR, "Test failed with wrong Transmitted Flow Control Initialization value InitialCompletionDataCredit=%0d Denali_PCIE_FCTYPE_CPLH=%0d .\n",Scenario.ilupeuInitialCompletionDataCredit, denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_DATA_VAL_SLC] ); |
| 709 | } |
| 710 | |
| 711 | |
| 712 | //Read the PTL Egress Credit Limit register and verify correct values |
| 713 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_tlu_ecl.read(); |
| 714 | printf("ilupeuLinkTrainingStrategy fire_plc_tlu_ctb_tlr_csr_a_tlu_ecl=%0h denaliInitialCompletionHeaderCredit=%0h ECL_CHC_SLC=%0h denaliInitialNonPostedHeaderCredit=%0h ECL_NHC_SLC=%0h \n",ilupeuRegTmpData,Scenario.denaliInitialCompletionHeaderCredit,ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_CHC_SLC],Scenario.denaliInitialNonPostedHeaderCredit,ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_NHC_SLC]); |
| 715 | |
| 716 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_CHC_SLC] !== Scenario.denaliInitialCompletionHeaderCredit ){ |
| 717 | Report.report(RTYP_TEST_ERROR, "Test failed with wrong Received Flow Control Initialization value denaliInitialCompletionHeaderCredit=%0d PTL Egress Credit Limit Completion Header = %0d .\n", |
| 718 | Scenario.denaliInitialCompletionHeaderCredit, ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_CHC_SLC] ); |
| 719 | } |
| 720 | |
| 721 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_CDC_SLC] !== Scenario.denaliInitialCompletionDataCredit ){ |
| 722 | Report.report(RTYP_TEST_ERROR, "Test failed with wrong Received Flow Control Initialization value denaliInitialCompletionDataCredit=%0d PTL Egress Credit Limit Completion Data = %0d .\n", |
| 723 | Scenario.denaliInitialCompletionDataCredit, ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_CDC_SLC] ); |
| 724 | } |
| 725 | |
| 726 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_NHC_SLC] !== Scenario.denaliInitialNonPostedHeaderCredit ){ |
| 727 | Report.report(RTYP_TEST_ERROR, "Test failed with wrong Received Flow Control Initialization value denaliInitialNonPostedHeaderCredit=%0d PTL Egress Credit Limit Non Posted Header = %0d .\n", |
| 728 | Scenario.denaliInitialNonPostedHeaderCredit, ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_NHC_SLC] ); |
| 729 | } |
| 730 | |
| 731 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_NDC_SLC] !== Scenario.denaliInitialNonPostedDataCredit ){ |
| 732 | Report.report(RTYP_TEST_ERROR, "Test failed with wrong Received Flow Control Initialization value denaliInitialNonPostedDataCredit=%0d PTL Egress Credit Limit Non Posted Data = %0d .\n", |
| 733 | Scenario.denaliInitialNonPostedDataCredit, ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_NDC_SLC] ); |
| 734 | } |
| 735 | |
| 736 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_PHC_SLC] !== Scenario.denaliInitialPostedHeaderCredit ){ |
| 737 | Report.report(RTYP_TEST_ERROR, "Test failed with wrong Received Flow Control Initialization value denaliInitialPostedHeaderCredit=%0d PTL Egress Credit Limit Posted Header = %0d .\n", |
| 738 | Scenario.denaliInitialPostedHeaderCredit, ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_PHC_SLC] ); |
| 739 | } |
| 740 | |
| 741 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_PDC_SLC] !== Scenario.denaliInitialPostedDataCredit ){ |
| 742 | Report.report(RTYP_TEST_ERROR, "Test failed with wrong Received Flow Control Initialization value denaliInitialPostedDataCredit=%0d PTL Egress Credit Limit Posted Data = %0d .\n", |
| 743 | Scenario.denaliInitialPostedDataCredit, ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_PDC_SLC] ); |
| 744 | } |
| 745 | |
| 746 | |
| 747 | } |
| 748 | |
| 749 | task ilupeuLinkTrainingStrategy::Check_Link_Status(){ |
| 750 | #ifndef N2_FC |
| 751 | |
| 752 | //Read Link Status registers in the PEU to make sure they are correct |
| 753 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_lnk_sts.read(); |
| 754 | |
| 755 | |
| 756 | //Make sure link speed is the default value |
| 757 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_SPEED_SLC] !== 4'b0001){ // 2.5Gb/S |
| 758 | Report.report(RTYP_TEST_ERROR, "Link Status register link_speed is NOT 2.5Gb/S(only) value link_speed=%0b\n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_SPEED_SLC] ); |
| 759 | } |
| 760 | |
| 761 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_WIDTH_SLC] !== calculatedWidth ){ |
| 762 | Report.report(RTYP_TEST_ERROR, "Link Status register negotiated_width is NOT the correct value negotiated_width=%0b calculatedWidth=%0b \n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_WIDTH_SLC], calculatedWidth ); |
| 763 | } |
| 764 | |
| 765 | /* Removed in PRM 1.1 8/26/05 |
| 766 | //Make sure there is no link training error |
| 767 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_ERROR_SLC] ){ |
| 768 | Report.report(RTYP_TEST_ERROR, "Link Status register has the Link Training Error bit set \n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_ERROR_SLC] ); |
| 769 | } |
| 770 | */ |
| 771 | |
| 772 | //Make sure link training in progress bit isn't set still |
| 773 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_TRAIN_SLC] ){ |
| 774 | Report.report(RTYP_TEST_ERROR, "Link Status register has the Link Training In Progress bit set \n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_TRAIN_SLC] ); |
| 775 | } |
| 776 | #endif |
| 777 | } |
| 778 | |
| 779 | /* |
| 780 | task ilupeuLinkTrainingStrategy::Check_LPUSD_Transmit_Phy_Status(){ |
| 781 | |
| 782 | -N2 after prm 0.7 implemented |
| 783 | //Check the Transmit Phy Status negotiated width here |
| 784 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_stat.read(); |
| 785 | |
| 786 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_SLC] !== calculatedWidth-1 ){ |
| 787 | Report.report(RTYP_TEST_ERROR, "Transmit Phy Status register negotiated_width is NOT the correct value negotiated_width=%0b calculatedWidth=%0b \n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_SLC], calculatedWidth ); |
| 788 | } |
| 789 | |
| 790 | //Make sure the Scrambling bit is set correctly - it is a disable scrambling status bit and not a received |
| 791 | // bit only like the lpusd Rx Phy Stat |
| 792 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_SLC] !== !( Scenario.lpusdLtssmDisableScrambling || Scenario.denaliLtssmDisableScrambling ) ){ |
| 793 | Report.report(RTYP_TEST_ERROR, "Transmit Phy Status register does NOT have the Scrambling bit set correctly denaliLtssmDisableScrambling=%0h lpusdLtssmDisableScrambling=%0h LPUSD Transmit Phy Reg =%0h \n",Scenario.denaliLtssmDisableScrambling, Scenario.lpusdLtssmDisableScrambling,ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_SLC]); |
| 794 | } |
| 795 | |
| 796 | //Since Lane Reversal is not supportred in FNX1 than this should never be set |
| 797 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_SLC] ){ |
| 798 | Report.report(RTYP_TEST_ERROR, "Transmit Phy Status register has the Lane Reversal bit set \n" ); |
| 799 | } |
| 800 | |
| 801 | } |
| 802 | */ |
| 803 | |
| 804 | |
| 805 | /* |
| 806 | |
| 807 | task ilupeuLinkTrainingStrategy::Check_LPUSD_Rx_Phy_Stat2(){ |
| 808 | |
| 809 | //Read Receive Phy Status2 registers in the LPUSD to make sure they are correct |
| 810 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat2.read(); |
| 811 | |
| 812 | //Make sure received disable scrambling bit is correctly set |
| 813 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_SLC] !== Scenario.denaliLtssmDisableScrambling ){ |
| 814 | Report.report(RTYP_TEST_ERROR, "Receive Phy Status2 register does NOT have the Received Disable Scrambling bit set correctly \n" ); |
| 815 | } |
| 816 | |
| 817 | //Make sure hot reset bit is correctly set |
| 818 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_SLC] !== Scenario.denaliLtssmHotReset ){ |
| 819 | Report.report(RTYP_TEST_ERROR, "Receive Phy Status2 register does NOT have the Received Hot Reset bit set \n" ); |
| 820 | } |
| 821 | |
| 822 | //Make sure link disable bit is correctly set |
| 823 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_SLC] !== Scenario.denaliLtssmLinkDisable ){ |
| 824 | Report.report(RTYP_TEST_ERROR, "Receive Phy Status2 register does NOT have the Received Disable Link bit set \n" ); |
| 825 | } |
| 826 | |
| 827 | //Make sure enable loopback bit is correctly set |
| 828 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_SLC] !== Scenario.denaliLtssmLinkLoopback ){ |
| 829 | Report.report(RTYP_TEST_ERROR, "Receive Phy Status2 register does NOT have the Received Enable Loopback bit set \n" ); |
| 830 | } |
| 831 | |
| 832 | //Make sure N_FTS bits are correctly set in lpusd |
| 833 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_SLC] !== Scenario.denaliLtssmNFTS ){ |
| 834 | Report.report(RTYP_TEST_ERROR, "Receive Phy Status2 register does NOT have the correct NFTS value STAT2_N_FTS_TSX_INT=%0b denaliLtssmNFTS=%0b \n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_SLC], Scenario.denaliLtssmNFTS ); |
| 835 | } |
| 836 | |
| 837 | //Make sure the Received Link Number is correct |
| 838 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_SLC] !== Scenario.ilupeuLtssmLinkNumber ){ |
| 839 | Report.report(RTYP_TEST_ERROR, "Receive Phy Status2 register does NOT have the correct Link Number=%0b denaliLtssmLinkNumber=%0b \n",ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_SLC], Scenario.denaliLtssmLinkNumber ); |
| 840 | } |
| 841 | |
| 842 | |
| 843 | |
| 844 | } |
| 845 | |
| 846 | task ilupeuLinkTrainingStrategy::Check_LPUSD_Rx_Phy_Stat3(){ |
| 847 | |
| 848 | //Read Receive Phy Status3 registers in the LPUSD to make sure they are correct |
| 849 | ilupeuRegTmpData = CSR.fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat3.read(); |
| 850 | //Make sure byte sync status is correctly set |
| 851 | if( ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_SLC] !== {calculatedWidth{1'b1}} ){ |
| 852 | Report.report(RTYP_TEST_ERROR, "Receive Phy Status3 register byte sync status WRONG! RX_PHY_STAT3_BYTE_SYNC_STS_SLC=%0b denaliLinkCapMaxLinkWdth=%0b \n", ilupeuRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_SLC],Scenario.denaliLinkCapMaxLinkWdth ); |
| 853 | } |
| 854 | |
| 855 | // review DENALI problem causes multiple bits to be inverted |
| 856 | //Make sure polarity reversal status is correctly set |
| 857 | if( ilupeuRegTmpData[31:16] !== Scenario.denaliLanePolarityInvert ){ |
| 858 | Report.report(RTYP_TEST_ERROR, "Receive Phy Status3 register Lane Polarity Reversal Status WRONG! RX_PHY_STAT3=%8b denaliLanePolarityInvert=%8b \n", ilupeuRegTmpData[31:16],Scenario.denaliLanePolarityInvert ); |
| 859 | } |
| 860 | |
| 861 | } |
| 862 | */ |
| 863 | |
| 864 | task ilupeuLinkTrainingStrategy::Check_Denali_Status(){ |
| 865 | #ifndef N2_FC |
| 866 | |
| 867 | integer masterLane; |
| 868 | |
| 869 | //Make sure the right N_FTS bits were correctly transmitted by ilupeu |
| 870 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_RX_NFTS ); |
| 871 | if( denRegTmpData !== Scenario.ilupeuLtssmNFTS){ |
| 872 | Report.report(RTYP_TEST_ERROR, "Denali PCIE_REG_DEN_RX_NFTS register does NOT have the correct NFTS value ilupeuLtssmNFTS=%0h PCIE_REG_DEN_RX_NFTS=%0h \n",Scenario.ilupeuLtssmNFTS, denRegTmpData ); |
| 873 | } |
| 874 | |
| 875 | //Read the Denali Link Status Register |
| 876 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_LINK_ST ); |
| 877 | |
| 878 | //Make sure the link is up |
| 879 | if( denRegTmpData[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_UP_SLC] !== 1'b1 ){ |
| 880 | Report.report(RTYP_TEST_ERROR, "Denali PCIE_REG_DEN_LINK_ST register does NOT have the Phy Laye Link Up bit set \n" ); |
| 881 | } |
| 882 | |
| 883 | if( denRegTmpData[FNX_PCIE_XTR_REG_DEN_LINK_ST_DL_LINK_UP_SLC] !== 1'b1 ){ |
| 884 | Report.report(RTYP_TEST_ERROR, "Denali PCIE_REG_DEN_LINK_ST register does NOT have the Data Layer Link Up bit set \n" ); |
| 885 | } |
| 886 | |
| 887 | //Make sure the right Link Width is set |
| 888 | if( denRegTmpData[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_WIDTH_SLC] !== calculatedWidth ){ |
| 889 | Report.report(RTYP_TEST_ERROR, "Denali PCIE_REG_DEN_LINK_ST register does NOT have the correct Link Width value calculatedWidth=%0h PCIE_REG_DEN_LINK_ST=%0h \n",calculatedWidth, denRegTmpData[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_WIDTH_SLC] ); |
| 890 | } |
| 891 | |
| 892 | //Make sure the right Link Number was correctly transmitted by ilupeu |
| 893 | if( denRegTmpData[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_NUM_SLC] !== Scenario.ilupeuLtssmLinkNumber){ |
| 894 | Report.report(RTYP_TEST_ERROR, "Denali PCIE_REG_DEN_LINK_ST register does NOT have the correct Link Number value ilupeuLtssmLinkNumber=%0h PCIE_REG_DEN_LINK_ST=%0h \n",Scenario.ilupeuLtssmLinkNumber, denRegTmpData[FNX_PCIE_XTR_REG_DEN_LINK_ST_LINK_NUM_SLC] ); |
| 895 | } |
| 896 | |
| 897 | //Make sure the right Master Lane number is set |
| 898 | if( !Scenario.denaliLaneReverse ){ |
| 899 | masterLane = 0; |
| 900 | } |
| 901 | else{ |
| 902 | masterLane = calculatedWidth - 1; |
| 903 | } |
| 904 | if( denRegTmpData[FNX_PCIE_XTR_REG_DEN_LINK_ST_LANE_NUM_SLC] !== masterLane ){ |
| 905 | Report.report(RTYP_TEST_ERROR, "Denali PCIE_REG_DEN_LINK_ST register does NOT have the correct Master Lane number value = %0h PCIE_REG_DEN_LINK_ST=%0h \n",masterLane,denRegTmpData[FNX_PCIE_XTR_REG_DEN_LINK_ST_LANE_NUM_SLC] ); |
| 906 | } |
| 907 | |
| 908 | //Make sure the Lanes are reversed if commanded to |
| 909 | if( denRegTmpData[FNX_PCIE_XTR_REG_DEN_LINK_ST_LANES_REVERSED_SLC] !== Scenario.denaliLaneReverse ){ |
| 910 | Report.report(RTYP_TEST_ERROR, "Denali PCIE_REG_DEN_LINK_ST register does NOT have the lane reversed bit = 0 PCIE_REG_DEN_LINK_ST=%0h \n" ); |
| 911 | } |
| 912 | |
| 913 | //Make sure the Scrambling bit is set correctly - it is a disable scrambling status bit and not a received |
| 914 | // bit only like the ilupeu |
| 915 | if( denRegTmpData[FNX_PCIE_XTR_REG_DEN_LINK_ST_SCRAMBLING_SLC] !== ( Scenario.ilupeuLtssmDisableScrambling || Scenario.denaliLtssmDisableScrambling ) ){ |
| 916 | Report.report(RTYP_TEST_ERROR, "Denali PCIE_REG_DEN_LINK_ST register does NOT have the Scrambling bit set correctly denaliLtssmDisableScrambling=%0h ilupeuLtssmDisableScrambling=%0h PCIE_REG_DEN_LINK_ST=%0h \n",Scenario.denaliLtssmDisableScrambling, Scenario.ilupeuLtssmDisableScrambling,denRegTmpData[FNX_PCIE_XTR_REG_DEN_LINK_ST_SCRAMBLING_SLC] ); |
| 917 | } |
| 918 | #endif |
| 919 | } |
| 920 | |
| 921 | |
| 922 | task ilupeuLinkTrainingStrategy::Denali_Flow_Control_Timers(){ |
| 923 | |
| 924 | //Just set the Denali Flow Control timer values |
| 925 | denRegTmpData = 0; |
| 926 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_OP_SLC] = PCIE_FCCTRL_set_timer; |
| 927 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_VC_SLC] = 0; //VC 0 |
| 928 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_PH; |
| 929 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] = 75; |
| 930 | |
| 931 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 932 | |
| 933 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_PD; |
| 934 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] = 80; |
| 935 | |
| 936 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 937 | |
| 938 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_NPH; |
| 939 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] = 85; |
| 940 | |
| 941 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 942 | |
| 943 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_NPD; |
| 944 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] = 90; |
| 945 | |
| 946 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 947 | |
| 948 | // denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_CPLH; |
| 949 | // denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] = 95; |
| 950 | |
| 951 | // regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 952 | |
| 953 | // denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_CPLD; |
| 954 | // denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] = 100; |
| 955 | |
| 956 | // regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 957 | |
| 958 | //Just read and print out Denali Flow Control timer values |
| 959 | denRegTmpData = 0; |
| 960 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_OP_SLC] = PCIE_FCCTRL_get_timer_limit; |
| 961 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_VC_SLC] = 0; //VC 0 |
| 962 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_PH; |
| 963 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] = 0; |
| 964 | |
| 965 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 966 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_FC_CTRL ); |
| 967 | |
| 968 | Report.report(RTYP_INFO, "Denali Flow Control Timer Limit Posted Header = %0d %h\n", denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC],denRegTmpData ); |
| 969 | |
| 970 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_PD; |
| 971 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] = 0; |
| 972 | |
| 973 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 974 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_FC_CTRL ); |
| 975 | |
| 976 | Report.report(RTYP_INFO, "Denali Flow Control Timer Limit Posted Data = %0d \n", denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] ); |
| 977 | |
| 978 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_NPH; |
| 979 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] = 0; |
| 980 | |
| 981 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 982 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_FC_CTRL ); |
| 983 | |
| 984 | Report.report(RTYP_INFO, "Denali Flow Control Timer Limit Non-Posted Header = %0d \n", denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] ); |
| 985 | |
| 986 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_NPD; |
| 987 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] = 0; |
| 988 | |
| 989 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 990 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_FC_CTRL ); |
| 991 | |
| 992 | Report.report(RTYP_INFO, "Denali Flow Control Timer Limit Non-Posted Data = %0d \n", denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] ); |
| 993 | |
| 994 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_CPLH; |
| 995 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] = 0; |
| 996 | |
| 997 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 998 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_FC_CTRL ); |
| 999 | |
| 1000 | Report.report(RTYP_INFO, "Denali Flow Control Timer Limit Completion Header = %0d \n", denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] ); |
| 1001 | |
| 1002 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_FC_TYPE_SLC] = PCIE_FCTYPE_CPLD; |
| 1003 | denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] = 0; |
| 1004 | |
| 1005 | regTrans.WriteDenaliReg( PCIE_REG_DEN_FC_CTRL, denRegTmpData ); |
| 1006 | denRegTmpData = regTrans.ReadDenaliReg( PCIE_REG_DEN_FC_CTRL ); |
| 1007 | |
| 1008 | Report.report(RTYP_INFO, "Denali Flow Control Timer Limit Completion Data = %0d \n", denRegTmpData[FNX_PCIE_XTR_REG_DEN_FC_CTRL_TIMER_VAL_SLC] ); |
| 1009 | |
| 1010 | } |
| 1011 | |
| 1012 | task ilupeuLinkTrainingStrategy::toLtssmState( bit [4:0] ltssmState, |
| 1013 | (integer timer=2000), |
| 1014 | (integer accessMethod=OMNI) ){ |
| 1015 | bit [63:0] csrRegTmpData; |
| 1016 | string msg; |
| 1017 | |
| 1018 | csrRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_core_status.read(accessMethod); |
| 1019 | fork |
| 1020 | { |
| 1021 | while( (csrRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_LTSSM_STATE_SLC ] !== ltssmState) && timer ){ |
| 1022 | csrRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_core_status.read(accessMethod); |
| 1023 | if( accessMethod === OMNI ) @(posedge CLOCK); |
| 1024 | } |
| 1025 | } |
| 1026 | { |
| 1027 | while( timer ){ |
| 1028 | @(posedge CLOCK); |
| 1029 | timer--; |
| 1030 | } |
| 1031 | } |
| 1032 | join any |
| 1033 | |
| 1034 | if( !timer ){ |
| 1035 | Report.report(RTYP_TEST_ERROR,"::toLtssmState timed out waiting to enter LTSSM_STATE -%0h- ---Still in state -%0h- ",ltssmState, csrRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_LTSSM_STATE_SLC ] ); |
| 1036 | }else{ |
| 1037 | printf("\n=========== PEU Entered LTSSM_STATE -%h- at cycle %0d ===========\n",csrRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_LTSSM_STATE_SLC ], get_cycle()); |
| 1038 | } |
| 1039 | |
| 1040 | terminate; //Kill timer if transition happens |
| 1041 | } |
| 1042 | |