| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_mac_reset.vr |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #include <vera_defines.vrh> |
| 36 | #include "mac_defines.vri" |
| 37 | #include "pio_driver.vrh" |
| 38 | #include "mac_pio_class.vrh" |
| 39 | #include "xmac_util.vrh" |
| 40 | #include "bmac_util.vrh" |
| 41 | #include "pcs_util.vrh" |
| 42 | #include "xpcs_util.vrh" |
| 43 | #include "pktConfig.vrh" |
| 44 | #include "mac_init_class.vrh" |
| 45 | #include "pkt_configurator.vrh" |
| 46 | |
| 47 | extern mac_util_class mac_util; |
| 48 | extern bmac_util_class bmac_util; |
| 49 | extern pcs_util_class pcs_util; |
| 50 | extern xpcs_util_class xpcs_util; |
| 51 | extern pio_drv pio_driver_class; |
| 52 | extern mac_pio_cl mac_pio_class; |
| 53 | extern mac_init_class mac_init; |
| 54 | extern bit[3:0] rtl_mac; |
| 55 | |
| 56 | class niu_mac_reset_class { |
| 57 | bit keep_resetting = 0; |
| 58 | string name = "niu_mac_reset_class"; |
| 59 | integer time_out = 0; |
| 60 | bit [31:0] XMAC_CONFIG_reinit_values; |
| 61 | bit [31:0] RxMAC_CONFIG_reinit_values; |
| 62 | bit [31:0] TxMAC_CONFIG_reinit_values; |
| 63 | integer max_mac_DAs; |
| 64 | pkt_configurator pkt_cfgrator; |
| 65 | |
| 66 | task mac_reset_periodically(integer interval = 20000); |
| 67 | task mac_warm_reset_rx(bit[1:0] mac_id); |
| 68 | task mac_warm_reset_tx(bit[1:0] mac_id); |
| 69 | task new(pkt_configurator pkt_cfgrator_in = null) { |
| 70 | pkt_cfgrator = pkt_cfgrator_in; |
| 71 | } |
| 72 | } |
| 73 | |
| 74 | task niu_mac_reset_class::mac_warm_reset_rx(bit[1:0] mac_id) { |
| 75 | bit [31:0] rd_data; |
| 76 | bit [31:0] bmac_rd_data; |
| 77 | bit[39:0] base_addr; |
| 78 | bit[47:0] mac_addr; |
| 79 | integer ii, tbl_num; |
| 80 | integer timeout_iterations = 10; |
| 81 | integer timeout_cnt = 0; |
| 82 | bit mpr; |
| 83 | |
| 84 | /* |
| 85 | The following information is extracted from MAC PRM version 4.9 |
| 86 | |
| 87 | 22.11 MAC Warm Reset Sequence |
| 88 | To apply MAC Warm Reset, Software should perform MAC Stop Sequence first |
| 89 | followed by Software Reset sequence second. |
| 90 | ################################## |
| 91 | # MAC Stop Sequence |
| 92 | ################################## |
| 93 | =====> Transmit xMAC Stop Sequence |
| 94 | Program XMAC_CONFIG register (FZC_MAC+00060) bit 0 (tx_enable) to ?0?. |
| 95 | Software should wait for one max_pkt_size time for xMAC to stop gracefully. |
| 96 | Use xtlm_state== 0 in xMAC State Machines Register (FZC_MAC+0x001A8) as |
| 97 | stop_done indicator. |
| 98 | =====> Receive xMAC Stop Sequence |
| 99 | Program XMAC_CONFIG register (FZC_MAC+00060) bit 8 (rx_enable) to ?0?. |
| 100 | Software should wait for one max_pkt_size time for xMAC to stop gracefully. |
| 101 | Use xrlm_state== 0 in xMAC State Machines Register (FZC_MAC+0x001A8) as |
| 102 | stop_done indicator. |
| 103 | -----> Transmit bMAC Stop Sequence |
| 104 | Program TxMAC_CONFIG register (FZC_MAC+0C060) bit 0 (tx_enable) to ?0?. |
| 105 | Software should wait for one max_pkt_size time for bMAC to stop gracefully. |
| 106 | Use tlm_state== 0 in bMAC State Machines Register (FZC_MAC+0x0C3A0) as |
| 107 | stop_done indicator. |
| 108 | -----> Receive bMAC Stop Sequence |
| 109 | Program RxMAC_CONFIG register (FZC_MAC+0C068) bit 0 (rx_enable) to ?0?. |
| 110 | Software should wait for one max_pkt_size time for bMAC to stop gracefully. |
| 111 | Use rlm_state== 0 in bMAC State Machines Register (FZC_MAC+0x0C3A0) as |
| 112 | stop_done indicator. |
| 113 | |
| 114 | ################################ |
| 115 | # MAC Software Reset Sequence |
| 116 | ################################ |
| 117 | =====> Transmit xMAC Software Reset Sequence |
| 118 | Software should write ?1? to bit 0 (TxMacSoftRst) and bit 1 |
| 119 | (TxMacRegRst) in register XTxMAC_SW_RST (FZC_MAC+00000). |
| 120 | Use TxMacSoftRst==0 and TxMacRegRst==0 as reset_done indicator. |
| 121 | =====> Receive xMAC Software Reset Sequencef |
| 122 | Software should write ?1? to bit 0 (RxMacSoftRst) and bit 1 (RxMacRegRst) in register |
| 123 | XRxMAC_SW_RST (FZC_MAC+00008). |
| 124 | Use RxMacSoftRst==0 and RxMacRegRst==0 as reset_done indicator. |
| 125 | -----> Transmit bMAC Software Reset Sequence |
| 126 | Software should write ?1? to bit 0 (txmac_sw_rst) in register BTxMAC_SW_RST |
| 127 | (FZC_MAC+0C000). |
| 128 | Use txmac_sw_rst==0 as reset_done indicator. |
| 129 | -----> Receive bMAC Software Reset Sequence |
| 130 | Software should write ?1? to bit 0 (rxmac_sw_rst) in register BRxMAC_SW_RST |
| 131 | (FZC_MAC+0C008). |
| 132 | Use rxmac_sw_rst==0 as reset_done indicator. |
| 133 | */ |
| 134 | |
| 135 | |
| 136 | printf("<%0d> niu_mac_reset_class::mac_warm_reset_rx mac_id:%0d \n", get_time(LO), mac_id); |
| 137 | |
| 138 | |
| 139 | if(mac_id == 0 | mac_id == 1) max_mac_DAs = 16; |
| 140 | else max_mac_DAs = 8; |
| 141 | |
| 142 | base_addr = bmac_util.get_mac_reg_base(mac_id); |
| 143 | if ( (mac_id ==0 | mac_id == 1) && rtl_mac[mac_id]) { |
| 144 | // STEP 1 // Receive xMAC Stop Sequence |
| 145 | mac_pio_class.xmac_pio_rd( base_addr + XMAC_CONFIG, rd_data,1'b0 ); |
| 146 | XMAC_CONFIG_reinit_values = rd_data; |
| 147 | rd_data[8] = 0; // RxMacEnable |
| 148 | mac_pio_class.xmac_pio_wr( base_addr + XMAC_CONFIG, rd_data); |
| 149 | printf ("niu_mac_reset_class::mac_warm_reset_rx XMAC_CONFIG(addr=0x%h) for Port %0d after disabling rx bits = 0x%h\n", base_addr + XMAC_CONFIG, mac_id, rd_data); |
| 150 | // STEP 2 // wait for one max_pkt_size time for xMAC to stop gracefully |
| 151 | repeat (3000) @(posedge CLOCK); |
| 152 | // STEP 3 // poll state machine register |
| 153 | rd_data[7] = 1; // xrlm_state |
| 154 | while(rd_data[7] !== 0) { |
| 155 | repeat (100) @(posedge CLOCK); |
| 156 | mac_pio_class.xmac_pio_rd( base_addr + XMAC_SM_REG, rd_data,1'b0 ); |
| 157 | printf ("niu_mac_reset_class::mac_warm_reset_rx max=%0d XMAC_SM_REG=0x%h time=%0d\n", mac_id, rd_data, get_time(LO)); |
| 158 | timeout_cnt++; |
| 159 | if(timeout_cnt > timeout_iterations) { |
| 160 | printf("<%0d> %s ERROR timeout for XMAC_SM_REG:xrlm_state[bit 7] to go 0 rd_data:%h\n", get_time(LO), name, rd_data); |
| 161 | } |
| 162 | } |
| 163 | |
| 164 | // STEP 4 // Receive xMAC Software Reset Sequence |
| 165 | mac_pio_class.xmac_pio_rd( base_addr + XRxMAC_SW_RST, rd_data,1'b0 ); |
| 166 | rd_data[0] = 1; // RxMacSoftRst |
| 167 | rd_data[1] = 1; // RxMacRegRst |
| 168 | mac_pio_class.xmac_pio_wr( base_addr + XRxMAC_SW_RST, rd_data); |
| 169 | // STEP 5 // poll RxMacSoftRst and RxMacRegRst done |
| 170 | rd_data[0] = 1; |
| 171 | rd_data[1] = 1; |
| 172 | timeout_cnt = 0; |
| 173 | while(rd_data[0] !== 0 | rd_data[1] !== 0) { |
| 174 | repeat (100) @(posedge CLOCK); |
| 175 | mac_pio_class.xmac_pio_rd( base_addr + XRxMAC_SW_RST, rd_data,1'b0 ); |
| 176 | printf ("niu_mac_reset_class::mac_warm_reset_rx max=%0d XRxMAC_SW_RST=0x%h time=%0d to_cnt=%0d\n", mac_id, rd_data, get_time(LO), timeout_cnt); |
| 177 | timeout_cnt++; |
| 178 | if(timeout_cnt > timeout_iterations) { |
| 179 | printf("<%0d> %s ERROR timeout for XTxMAC_SW_RST:rx_reset[bit 0,1] to go 0 rd_data:%h\n", get_time(LO), name, rd_data); |
| 180 | } |
| 181 | } |
| 182 | } else if ( (mac_id ==2 | mac_id == 3) && rtl_mac[mac_id]) { |
| 183 | // STEP 1 // Receive bMAC Stop Sequence |
| 184 | mac_pio_class.bmac_pio_rd(base_addr + RxMAC_CONFIG, bmac_rd_data, 0); |
| 185 | RxMAC_CONFIG_reinit_values = bmac_rd_data; |
| 186 | bmac_rd_data[0] = 0; // rx_enable = 0 |
| 187 | mac_pio_class.bmac_pio_wr(base_addr + RxMAC_CONFIG, bmac_rd_data); |
| 188 | // STEP 2 // wait for one max_pkt_size time for bMAC to stop gracefully |
| 189 | repeat(30000) @(posedge CLOCK); // STEP 3 // Use rlm_state== 0 in bMAC State Machines Register (FZC_MAC+0x0C3A0) as stop_done indicator. |
| 190 | // poll rlm_state bits 26:23 |
| 191 | bmac_rd_data[26:23] = 4'b1111; |
| 192 | while(bmac_rd_data[26:23] !== 0) { |
| 193 | repeat (1000) @(posedge CLOCK); |
| 194 | mac_pio_class.xmac_pio_rd( base_addr + BMAC_SM_REG, bmac_rd_data,1'b0 ); |
| 195 | timeout_cnt++; |
| 196 | if(timeout_cnt > timeout_iterations) { |
| 197 | printf("<%0d> niu_mac_reset_class::mac_warm_reset_rx ERROR timeout in BMAC_SM_REG bits 26:23 rd_data:%h\n", |
| 198 | get_time(LO), bmac_rd_data); |
| 199 | } |
| 200 | } |
| 201 | // STEP 4 // Receive bMAC Software Reset Sequence |
| 202 | mac_pio_class.bmac_pio_rd(base_addr + BRxMAC_SW_RST, bmac_rd_data, 0); |
| 203 | bmac_rd_data[0] = 1; // rxmac_sw_rst = 1 |
| 204 | mac_pio_class.bmac_pio_wr(base_addr + BRxMAC_SW_RST, bmac_rd_data); |
| 205 | |
| 206 | // STEP 5 // poll reset done |
| 207 | while(bmac_rd_data[0] !== 0) { |
| 208 | repeat (100) @(posedge CLOCK); |
| 209 | mac_pio_class.xmac_pio_rd( base_addr + BRxMAC_SW_RST, bmac_rd_data,1'b0 ); |
| 210 | timeout_cnt++; |
| 211 | if(timeout_cnt > timeout_iterations) { |
| 212 | printf("<%0d> %s : ERROR : timeout waiting for BRxMAC_SW_RST:rx_reset[bit 0] to go 0 rd_data:%h\n", get_time(LO), name, bmac_rd_data); |
| 213 | } |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | // mac_init.init_mac(); |
| 218 | //for(mac_id = 0; mac_id < 4; mac_id++) { |
| 219 | base_addr = bmac_util.get_mac_reg_base(mac_id); |
| 220 | |
| 221 | if (rtl_mac[mac_id]) { |
| 222 | for(ii=0;ii<max_mac_DAs;ii++) { |
| 223 | if (get_plus_arg (CHECK, "PKT_CFG_TCAM_LOOKUP")) |
| 224 | tbl_num = 0; // allows us to have TCAM hit with a minimal no. of TCAM entries |
| 225 | else |
| 226 | tbl_num = ii%8; |
| 227 | mpr = random() % 2; // random MAC priority |
| 228 | //printf("<%0d> %s: mac_id:%0d ii:%0d mpr:%0d, tbl_num:%0d\n", get_time(LO), name, mac_id, ii, mpr, tbl_num); |
| 229 | if(pkt_cfgrator!=null) |
| 230 | pkt_cfgrator.prog_mac_reg(mac_id, ii, {mpr, tbl_num, 48'hf00102030420+ii}); |
| 231 | } |
| 232 | } |
| 233 | |
| 234 | if ( (mac_id == 0 | mac_id == 1) && rtl_mac[mac_id]) { |
| 235 | if(get_plus_arg(CHECK,"JUMBO_FRAME_EN")) { |
| 236 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_MAX, 32'h0000_3FFF); |
| 237 | printf("INFO: xmac_init: Setting up MAC to support JUMBO_FRAMES\n"); |
| 238 | } |
| 239 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT1,32'h0000_0000); |
| 240 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT2,32'h0000_0000); |
| 241 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT3,32'h0000_0000); |
| 242 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT4,32'h0000_0000); |
| 243 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT5,32'h0000_0000); |
| 244 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT6,32'h0000_0000); |
| 245 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT7,32'h0000_0000); |
| 246 | mac_pio_class.xmac_pio_rd( base_addr + XMAC_CONFIG, rd_data,1'b0 ); |
| 247 | printf ("TEST XMAC_CONFIG(addr=0x%h) for Port %0d after enabling addr filtering = 0x%h\n", |
| 248 | base_addr + XMAC_CONFIG, mac_id,rd_data); |
| 249 | mac_pio_class.xmac_pio_wr( base_addr + XMAC_ADDR_CMPEN_LSB , 32'hFFFF_FFFF); |
| 250 | printf ("TEST XMAC_CONFIG(addr=0x%h) port:%0d restoring original values = 0x%h\n", |
| 251 | base_addr + XMAC_CONFIG, mac_id,rd_data); |
| 252 | rd_data = XMAC_CONFIG_reinit_values; // Restore original values |
| 253 | mac_pio_class.xmac_pio_wr( base_addr + XMAC_CONFIG, rd_data); |
| 254 | } |
| 255 | |
| 256 | if ((mac_id == 2 | mac_id == 3) && rtl_mac[mac_id]) { |
| 257 | mac_pio_class.bmac_pio_rd(base_addr + RxMAC_CONFIG, bmac_rd_data, 0); |
| 258 | printf("<%0d> %s: Restoring original values for RxMAC_CONFIG port:%0d value:%h\n", get_time(LO), name, mac_id, RxMAC_CONFIG_reinit_values); |
| 259 | bmac_rd_data = RxMAC_CONFIG_reinit_values; |
| 260 | mac_pio_class.bmac_pio_wr(base_addr + RxMAC_CONFIG, bmac_rd_data); |
| 261 | mac_pio_class.bmac_pio_wr(base_addr + BMAC_ALTAD_CMPEN, 32'hffffffff); |
| 262 | } |
| 263 | |
| 264 | //} // for |
| 265 | } |
| 266 | |
| 267 | task niu_mac_reset_class::mac_warm_reset_tx(bit [1:0] mac_id) { |
| 268 | bit [31:0] rd_data; |
| 269 | bit [31:0] bmac_rd_data; |
| 270 | bit[39:0] base_addr; |
| 271 | bit[47:0] mac_addr; |
| 272 | integer ii, tbl_num; |
| 273 | integer timeout_iterations = 100; |
| 274 | integer timeout_cnt = 0; |
| 275 | bit mpr; |
| 276 | |
| 277 | /* |
| 278 | The following information is extracted from MAC PRM version 4.9 |
| 279 | |
| 280 | 22.11 MAC Warm Reset Sequence |
| 281 | To apply MAC Warm Reset, Software should perform MAC Stop Sequence first |
| 282 | followed by Software Reset sequence second. |
| 283 | ################################## |
| 284 | # MAC Stop Sequence |
| 285 | ################################## |
| 286 | =====> Transmit xMAC Stop Sequence |
| 287 | Program XMAC_CONFIG register (FZC_MAC+00060) bit 0 (tx_enable) to ?0?. |
| 288 | Software should wait for one max_pkt_size time for xMAC to stop gracefully. |
| 289 | Use xtlm_state== 0 in xMAC State Machines Register (FZC_MAC+0x001A8) as |
| 290 | stop_done indicator. |
| 291 | =====> Receive xMAC Stop Sequence |
| 292 | Program XMAC_CONFIG register (FZC_MAC+00060) bit 8 (rx_enable) to ?0?. |
| 293 | Software should wait for one max_pkt_size time for xMAC to stop gracefully. |
| 294 | Use xrlm_state== 0 in xMAC State Machines Register (FZC_MAC+0x001A8) as |
| 295 | stop_done indicator. |
| 296 | -----> Transmit bMAC Stop Sequence |
| 297 | Program TxMAC_CONFIG register (FZC_MAC+0C060) bit 0 (tx_enable) to ?0?. |
| 298 | Software should wait for one max_pkt_size time for bMAC to stop gracefully. |
| 299 | Use tlm_state== 0 in bMAC State Machines Register (FZC_MAC+0x0C3A0) as |
| 300 | stop_done indicator. |
| 301 | -----> Receive bMAC Stop Sequence |
| 302 | Program RxMAC_CONFIG register (FZC_MAC+0C068) bit 0 (rx_enable) to ?0?. |
| 303 | Software should wait for one max_pkt_size time for bMAC to stop gracefully. |
| 304 | Use rlm_state== 0 in bMAC State Machines Register (FZC_MAC+0x0C3A0) as |
| 305 | stop_done indicator. |
| 306 | |
| 307 | ################################ |
| 308 | # MAC Software Reset Sequence |
| 309 | ################################ |
| 310 | =====> Transmit xMAC Software Reset Sequence |
| 311 | Software should write ?1? to bit 0 (TxMacSoftRst) and bit 1 |
| 312 | (TxMacRegRst) in register XTxMAC_SW_RST (FZC_MAC+00000). |
| 313 | Use TxMacSoftRst==0 and TxMacRegRst==0 as reset_done indicator. |
| 314 | =====> Receive xMAC Software Reset Sequencef |
| 315 | Software should write ?1? to bit 0 (RxMacSoftRst) and bit 1 (RxMacRegRst) in register |
| 316 | XRxMAC_SW_RST (FZC_MAC+00008). |
| 317 | Use RxMacSoftRst==0 and RxMacRegRst==0 as reset_done indicator. |
| 318 | -----> Transmit bMAC Software Reset Sequence |
| 319 | Software should write ?1? to bit 0 (txmac_sw_rst) in register BTxMAC_SW_RST |
| 320 | (FZC_MAC+0C000). |
| 321 | Use txmac_sw_rst==0 as reset_done indicator. |
| 322 | -----> Receive bMAC Software Reset Sequence |
| 323 | Software should write ?1? to bit 0 (rxmac_sw_rst) in register BRxMAC_SW_RST |
| 324 | (FZC_MAC+0C008). |
| 325 | Use rxmac_sw_rst==0 as reset_done indicator. |
| 326 | */ |
| 327 | |
| 328 | printf("<%0d> niu_mac_reset_class::mac_warm_reset_tx mac_id:%0d \n", get_time(LO), mac_id); |
| 329 | |
| 330 | |
| 331 | if(mac_id == 0 | mac_id == 1) max_mac_DAs = 16; |
| 332 | else max_mac_DAs = 8; |
| 333 | |
| 334 | base_addr = bmac_util.get_mac_reg_base(mac_id); |
| 335 | if ( (mac_id ==0 | mac_id == 1) && rtl_mac[mac_id]) { |
| 336 | // STEP 1 // Transmit xMAC Stop Sequence |
| 337 | mac_pio_class.xmac_pio_rd( base_addr + XMAC_CONFIG, rd_data,1'b0 ); |
| 338 | XMAC_CONFIG_reinit_values = rd_data; |
| 339 | rd_data[0] = 0; // tx_enable |
| 340 | mac_pio_class.xmac_pio_wr( base_addr + XMAC_CONFIG, rd_data); |
| 341 | printf ("niu_mac_reset_class::mac_warm_reset_tx XMAC_CONFIG(addr=0x%h) for Port %0d after disabling tx bits = 0x%h\n", base_addr + XMAC_CONFIG, mac_id, rd_data); |
| 342 | // STEP 2 // wait for one max_pkt_size time for xMAC to stop gracefully |
| 343 | repeat (3000) @(posedge CLOCK); |
| 344 | // STEP 3 // poll state machine register |
| 345 | rd_data[2:0] = 3'b111; // xtlm_state |
| 346 | while(rd_data[2:0] !== 3'b000) { |
| 347 | repeat (100) @(posedge CLOCK); |
| 348 | mac_pio_class.xmac_pio_rd( base_addr + XMAC_SM_REG, rd_data,1'b0 ); |
| 349 | timeout_cnt++; |
| 350 | if(timeout_cnt > timeout_iterations) { |
| 351 | printf("<%0d> %s : ERROR : timeout waiting for XMAC_SM_REG:xrlm_state[bit 7] to go 0 rd_data:%h\n", get_time(LO), name, rd_data); |
| 352 | } |
| 353 | } |
| 354 | |
| 355 | // STEP 4 // Receive xMAC Software Reset Sequence |
| 356 | mac_pio_class.xmac_pio_rd( base_addr + XTxMAC_SW_RST, rd_data,1'b0 ); |
| 357 | rd_data[0] = 1; // TxMacSoftRst |
| 358 | rd_data[1] = 1; // TxMacRegRst |
| 359 | mac_pio_class.xmac_pio_wr( base_addr + XTxMAC_SW_RST, rd_data); |
| 360 | // STEP 5 // poll TxMacSoftRst and TxMacRegRst done |
| 361 | rd_data[0] = 1; |
| 362 | rd_data[1] = 1; |
| 363 | timeout_cnt = 0; |
| 364 | while(rd_data[0] !== 0 | rd_data[1] !== 0) { |
| 365 | repeat (100) @(posedge CLOCK); |
| 366 | mac_pio_class.xmac_pio_rd( base_addr + XTxMAC_SW_RST, rd_data,1'b0 ); |
| 367 | timeout_cnt++; |
| 368 | if(timeout_cnt > timeout_iterations) { |
| 369 | printf("<%0d> %s : ERROR : timeout waiting for XTxMAC_SW_RST:rx_reset[bit 0,1] to go 0 rd_data:%h\n", get_time(LO), name, rd_data); |
| 370 | } |
| 371 | } |
| 372 | } else if ( (mac_id ==2 | mac_id == 3) && rtl_mac[mac_id]) { |
| 373 | // STEP 1 // Receive bMAC Stop Sequence |
| 374 | mac_pio_class.bmac_pio_rd(base_addr + TxMAC_CONFIG, bmac_rd_data, 0); |
| 375 | TxMAC_CONFIG_reinit_values = bmac_rd_data; |
| 376 | bmac_rd_data[0] = 0; // rx_enable = 0 |
| 377 | mac_pio_class.bmac_pio_wr(base_addr + TxMAC_CONFIG, bmac_rd_data); |
| 378 | // STEP 2 // wait for one max_pkt_size time for bMAC to stop gracefully |
| 379 | repeat(30000) @(posedge CLOCK); // STEP 3 // Use tlm_state== 0 in bMAC State Machines Register (FZC_MAC+0x0C3A0) as stop_done indicator. |
| 380 | // poll tlm_state bits 19:16 |
| 381 | bmac_rd_data[19:16] = 4'b1111; |
| 382 | while(bmac_rd_data[19:16] !== 0) { |
| 383 | repeat (1000) @(posedge CLOCK); |
| 384 | mac_pio_class.xmac_pio_rd( base_addr + BMAC_SM_REG, bmac_rd_data,1'b0 ); |
| 385 | timeout_cnt++; |
| 386 | if(timeout_cnt > timeout_iterations) { |
| 387 | printf("<%0d> niu_mac_reset_class::mac_warm_reset_tx ERROR timeout in BMAC_SM_REG bits 19:16 rd_data:%h\n", |
| 388 | get_time(LO), bmac_rd_data); |
| 389 | } |
| 390 | } |
| 391 | // STEP 4 // Transmit bMAC Software Reset Sequence |
| 392 | mac_pio_class.bmac_pio_rd(base_addr + BTxMAC_SW_RST, bmac_rd_data, 0); |
| 393 | bmac_rd_data[0] = 1; // rxmac_sw_rst = 1 |
| 394 | mac_pio_class.bmac_pio_wr(base_addr + BTxMAC_SW_RST, bmac_rd_data); |
| 395 | |
| 396 | // STEP 5 // poll reset done |
| 397 | bmac_rd_data[0] = 1; |
| 398 | while(bmac_rd_data[0] !== 0) { |
| 399 | repeat (100) @(posedge CLOCK); |
| 400 | mac_pio_class.xmac_pio_rd( base_addr + BTxMAC_SW_RST, bmac_rd_data,1'b0 ); |
| 401 | timeout_cnt++; |
| 402 | if(timeout_cnt > timeout_iterations) { |
| 403 | printf("<%0d> %s : ERROR : timeout waiting for BTxMAC_SW_RST:rx_reset[bit 0] to go 0 rd_data:%h\n", get_time(LO), name, bmac_rd_data); |
| 404 | } |
| 405 | } |
| 406 | } |
| 407 | |
| 408 | // mac_init.init_mac(); |
| 409 | base_addr = bmac_util.get_mac_reg_base(mac_id); |
| 410 | |
| 411 | if (rtl_mac[mac_id]) { |
| 412 | for(ii=0;ii<max_mac_DAs;ii++) { |
| 413 | if (get_plus_arg (CHECK, "PKT_CFG_TCAM_LOOKUP")) |
| 414 | tbl_num = 0; // allows us to have TCAM hit with a minimal no. of TCAM entries |
| 415 | else |
| 416 | tbl_num = ii%8; |
| 417 | mpr = random() % 2; // random MAC priority |
| 418 | if(pkt_cfgrator!=null) |
| 419 | pkt_cfgrator.prog_mac_reg(mac_id, ii, {mpr, tbl_num, 48'hf00102030420+ii}); |
| 420 | } |
| 421 | } |
| 422 | |
| 423 | if ( (mac_id == 0 | mac_id == 1) && rtl_mac[mac_id]) { |
| 424 | if(get_plus_arg(CHECK,"JUMBO_FRAME_EN")) { |
| 425 | mac_pio_class.xmac_pio_wr(base_addr + XMAC_MAX, 32'h0000_3FFF); |
| 426 | printf("INFO: xmac_init: Setting up MAC to support JUMBO_FRAMES\n"); |
| 427 | } |
| 428 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT1,32'h0000_0000); |
| 429 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT2,32'h0000_0000); |
| 430 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT3,32'h0000_0000); |
| 431 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT4,32'h0000_0000); |
| 432 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT5,32'h0000_0000); |
| 433 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT6,32'h0000_0000); |
| 434 | mac_pio_class.xmac_pio_wr(base_addr + RxMAC_HIST_CNT7,32'h0000_0000); |
| 435 | mac_pio_class.xmac_pio_rd( base_addr + XMAC_CONFIG, rd_data,1'b0 ); |
| 436 | rd_data = XMAC_CONFIG_reinit_values; |
| 437 | printf ("<%0d> %s: Restoring original values for XMAC_CONFIG port:%0d value:%h\n", get_time(LO), name, mac_id, XMAC_CONFIG_reinit_values); |
| 438 | mac_pio_class.xmac_pio_wr( base_addr + XMAC_CONFIG, rd_data); |
| 439 | mac_pio_class.xmac_pio_wr( base_addr + XMAC_ADDR_CMPEN_LSB , 32'hFFFF_FFFF); |
| 440 | } |
| 441 | |
| 442 | if ((mac_id == 2 | mac_id == 3) && rtl_mac[mac_id]) { |
| 443 | mac_pio_class.bmac_pio_rd(base_addr + RxMAC_CONFIG, bmac_rd_data, 0); |
| 444 | bmac_rd_data[3] = 0; // Turn off the promiscuous mode |
| 445 | mac_pio_class.bmac_pio_wr(base_addr + RxMAC_CONFIG, bmac_rd_data); |
| 446 | mac_pio_class.bmac_pio_wr(base_addr + BMAC_ALTAD_CMPEN, 32'hffffffff); |
| 447 | bmac_rd_data = TxMAC_CONFIG_reinit_values; |
| 448 | mac_pio_class.bmac_pio_wr(base_addr + TxMAC_CONFIG, bmac_rd_data); |
| 449 | } |
| 450 | } |
| 451 | |
| 452 | task niu_mac_reset_class :: mac_reset_periodically(integer interval = 3000) { |
| 453 | integer i; |
| 454 | bit [1:0] mac_id = 0; |
| 455 | printf("niu_mac_reset_class::mac_reset_periodically interval:%0d\n", interval); |
| 456 | repeat(10000) @(posedge CLOCK); // Initial delay |
| 457 | |
| 458 | while(1) { |
| 459 | repeat(100) @(posedge CLOCK); // to Avoid infinite loop |
| 460 | repeat(interval) @(posedge CLOCK); |
| 461 | if(keep_resetting) { |
| 462 | mac_warm_reset_rx(mac_id); |
| 463 | repeat(3000) @(posedge CLOCK); |
| 464 | mac_warm_reset_tx(mac_id); |
| 465 | } |
| 466 | mac_id++; |
| 467 | } |
| 468 | } |