| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fflp_util.vr |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #include <vera_defines.vrh> |
| 36 | #include "fflp_memory_map.vri" |
| 37 | #include "dmc_memory_map.vri" |
| 38 | #include "pio_driver.vrh" |
| 39 | #include "fflp_defines.vri" |
| 40 | //#include "ncu_stub.vrh" |
| 41 | // extern Cncu_stub gen_pio_drv; |
| 42 | extern niu_gen_pio gen_pio_drv; |
| 43 | |
| 44 | |
| 45 | |
| 46 | #include "cMesg.vrh" |
| 47 | |
| 48 | extern Mesg be_msg; |
| 49 | |
| 50 | class fflp_util_class { |
| 51 | |
| 52 | |
| 53 | //@@@@ FFLP Shadow Register Variables @@@@ |
| 54 | bit [63:0] fflp_config; |
| 55 | bit [63:0] fflp_tcp_cflag_mask; |
| 56 | bit [63:0] fflp_fcram_ref_tmr; |
| 57 | bit [63:0] fflp_l2_cls_2; |
| 58 | bit [63:0] fflp_l2_cls_3; |
| 59 | bit [63:0] fflp_l2_cls_4; |
| 60 | bit [63:0] fflp_l2_cls_5; |
| 61 | bit [63:0] fflp_l2_cls_6; |
| 62 | bit [63:0] fflp_l2_cls_7; |
| 63 | bit [63:0] fflp_cam_key_reg0; |
| 64 | bit [63:0] fflp_cam_key_reg1; |
| 65 | bit [63:0] fflp_cam_key_reg2; |
| 66 | bit [63:0] fflp_cam_key_reg3; |
| 67 | bit [63:0] fflp_cam_key_mask_reg0; |
| 68 | bit [63:0] fflp_cam_key_mask_reg1; |
| 69 | bit [63:0] fflp_cam_key_mask_reg2; |
| 70 | bit [63:0] fflp_cam_key_mask_reg3; |
| 71 | bit [63:0] fflp_cam_key_control; |
| 72 | bit [63:0] fflp_how_tcam_key_cls_4; |
| 73 | bit [63:0] fflp_how_tcam_key_cls_5; |
| 74 | bit [63:0] fflp_how_tcam_key_cls_6; |
| 75 | bit [63:0] fflp_how_tcam_key_cls_7; |
| 76 | bit [63:0] fflp_how_tcam_key_cls_8; |
| 77 | bit [63:0] fflp_how_tcam_key_cls_9; |
| 78 | bit [63:0] fflp_how_tcam_key_cls_A; |
| 79 | bit [63:0] fflp_how_tcam_key_cls_B; |
| 80 | bit [63:0] fflp_how_tcam_key_cls_C; |
| 81 | bit [63:0] fflp_how_tcam_key_cls_D; |
| 82 | bit [63:0] fflp_how_tcam_key_cls_E; |
| 83 | bit [63:0] fflp_how_tcam_key_cls_F; |
| 84 | |
| 85 | bit [63:0] fflp_how_flow_key_cls_4; |
| 86 | bit [63:0] fflp_how_flow_key_cls_5; |
| 87 | bit [63:0] fflp_how_flow_key_cls_6; |
| 88 | bit [63:0] fflp_how_flow_key_cls_7; |
| 89 | bit [63:0] fflp_how_flow_key_cls_8; |
| 90 | bit [63:0] fflp_how_flow_key_cls_9; |
| 91 | bit [63:0] fflp_how_flow_key_cls_A; |
| 92 | bit [63:0] fflp_how_flow_key_cls_B; |
| 93 | bit [63:0] fflp_how_flow_key_cls_C; |
| 94 | bit [63:0] fflp_how_flow_key_cls_D; |
| 95 | bit [63:0] fflp_how_flow_key_cls_E; |
| 96 | bit [63:0] fflp_how_flow_key_cls_F; |
| 97 | bit [63:0] fflp_flow_h1poly; |
| 98 | bit ext_lookup [8]; |
| 99 | bit [63:0] rdc_def_pt0_rdc; |
| 100 | bit [63:0] rdc_def_pt1_rdc; |
| 101 | bit [63:0] rdc_def_pt2_rdc; |
| 102 | bit [63:0] rdc_def_pt3_rdc; |
| 103 | |
| 104 | task new( ) ; |
| 105 | function bit check_cmd(bit [63:0]cmd, bit [63:0] opt); |
| 106 | task fflp_init ( integer iport, bit[63:0] cmd); |
| 107 | function bit [199:0] pio_rd_tcam_key (bit [9:0] tcam_index, |
| 108 | var bit [199:0] pio_rd_tcam_mask); |
| 109 | task pio_wr_tcam_key (bit [9:0] tcam_index, |
| 110 | bit [199:0] wr_tcam_key, |
| 111 | bit [199:0] wr_tcam_mask); |
| 112 | function bit [63:0] pio_rd_tcam_asdata (bit [9:0] tcam_index); |
| 113 | task pio_wr_tcam_asdata (bit [9:0] tcam_index, |
| 114 | bit [63:0] wr_tcam_asdata); |
| 115 | task wait_for_done_bit(); |
| 116 | task fflp_pio_wrapper ( bit [39:0] pio_addr, bit [63:0] wr_data); |
| 117 | task init_cam_entries(); |
| 118 | task pio_cmp_tcam_key (bit [199:0] cmp_tcam_key); |
| 119 | function bit [10:0] pio_comp_tcam_key (bit [199:0] cmp_tcam_key); |
| 120 | |
| 121 | } |
| 122 | |
| 123 | task fflp_util_class::new( ) |
| 124 | { |
| 125 | fflp_config = -1; |
| 126 | fflp_tcp_cflag_mask = -1; |
| 127 | fflp_fcram_ref_tmr = -1; |
| 128 | fflp_l2_cls_2 = -1; |
| 129 | fflp_l2_cls_3 = -1; |
| 130 | fflp_l2_cls_4 = -1; |
| 131 | fflp_l2_cls_5 = -1; |
| 132 | fflp_l2_cls_6 = -1; |
| 133 | fflp_l2_cls_7 = -1; |
| 134 | fflp_cam_key_reg0 = -1; |
| 135 | fflp_cam_key_reg1 = -1; |
| 136 | fflp_cam_key_reg2 = -1; |
| 137 | fflp_cam_key_reg3 = -1; |
| 138 | fflp_cam_key_mask_reg0 = -1; |
| 139 | fflp_cam_key_mask_reg1 = -1; |
| 140 | fflp_cam_key_mask_reg2 = -1; |
| 141 | fflp_cam_key_mask_reg3 = -1; |
| 142 | fflp_cam_key_control = -1; |
| 143 | fflp_how_tcam_key_cls_4 = -1; |
| 144 | fflp_how_tcam_key_cls_5 = -1; |
| 145 | fflp_how_tcam_key_cls_6 = -1; |
| 146 | fflp_how_tcam_key_cls_7 = -1; |
| 147 | fflp_how_tcam_key_cls_8 = -1; |
| 148 | fflp_how_tcam_key_cls_9 = -1; |
| 149 | fflp_how_tcam_key_cls_A = -1; |
| 150 | fflp_how_tcam_key_cls_B = -1; |
| 151 | fflp_how_tcam_key_cls_C = -1; |
| 152 | fflp_how_tcam_key_cls_D = -1; |
| 153 | fflp_how_tcam_key_cls_E = -1; |
| 154 | fflp_how_tcam_key_cls_F = -1; |
| 155 | |
| 156 | fflp_how_flow_key_cls_4 = -1; |
| 157 | fflp_how_flow_key_cls_5 = -1; |
| 158 | fflp_how_flow_key_cls_6 = -1; |
| 159 | fflp_how_flow_key_cls_7 = -1; |
| 160 | fflp_how_flow_key_cls_8 = -1; |
| 161 | fflp_how_flow_key_cls_9 = -1; |
| 162 | fflp_how_flow_key_cls_A = -1; |
| 163 | fflp_how_flow_key_cls_B = -1; |
| 164 | fflp_how_flow_key_cls_C = -1; |
| 165 | fflp_how_flow_key_cls_D = -1; |
| 166 | fflp_how_flow_key_cls_E = -1; |
| 167 | fflp_how_flow_key_cls_F = -1; |
| 168 | fflp_flow_h1poly = -1; |
| 169 | ext_lookup[0] = -1; |
| 170 | ext_lookup[1] = -1; |
| 171 | ext_lookup[2] = -1; |
| 172 | ext_lookup[3] = -1; |
| 173 | ext_lookup[4] = -1; |
| 174 | ext_lookup[5] = -1; |
| 175 | ext_lookup[6] = -1; |
| 176 | ext_lookup[7] = -1; |
| 177 | rdc_def_pt0_rdc = -1; |
| 178 | rdc_def_pt1_rdc = -1; |
| 179 | rdc_def_pt2_rdc = -1; |
| 180 | rdc_def_pt3_rdc = -1; |
| 181 | |
| 182 | } |
| 183 | |
| 184 | |
| 185 | task fflp_util_class::fflp_pio_wrapper ( bit [39:0] pio_addr, bit [63:0] wr_data) |
| 186 | { |
| 187 | case(pio_addr) |
| 188 | { |
| 189 | FFLP_ADDRESS_RANGE+FFLP_CONFIG: |
| 190 | { |
| 191 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_CONFIG,wr_data); |
| 192 | fflp_config = wr_data; |
| 193 | } |
| 194 | FFLP_ADDRESS_RANGE+FFLP_TCP_CFLAG_MASK: |
| 195 | { |
| 196 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_TCP_CFLAG_MASK,wr_data); |
| 197 | fflp_tcp_cflag_mask = wr_data; |
| 198 | } |
| 199 | FFLP_ADDRESS_RANGE+FFLP_FCRAM_REF_TMR: |
| 200 | { |
| 201 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_FCRAM_REF_TMR,wr_data); |
| 202 | fflp_fcram_ref_tmr = wr_data; |
| 203 | } |
| 204 | FFLP_ADDRESS_RANGE+FFLP_L2_CLS_2: |
| 205 | { |
| 206 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_L2_CLS_2,wr_data); |
| 207 | fflp_l2_cls_2 = wr_data; |
| 208 | } |
| 209 | FFLP_ADDRESS_RANGE+FFLP_L2_CLS_3: |
| 210 | { |
| 211 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_L2_CLS_3,wr_data); |
| 212 | fflp_l2_cls_3 = wr_data; |
| 213 | } |
| 214 | FFLP_ADDRESS_RANGE+FFLP_L3_CLS_4: |
| 215 | { |
| 216 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_L3_CLS_4,wr_data); |
| 217 | fflp_l2_cls_4 = wr_data; |
| 218 | } |
| 219 | FFLP_ADDRESS_RANGE+FFLP_L3_CLS_5: |
| 220 | { |
| 221 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_L3_CLS_5,wr_data); |
| 222 | fflp_l2_cls_5 = wr_data; |
| 223 | } |
| 224 | FFLP_ADDRESS_RANGE+FFLP_L3_CLS_6: |
| 225 | { |
| 226 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_L3_CLS_6,wr_data); |
| 227 | fflp_l2_cls_6 = wr_data; |
| 228 | } |
| 229 | FFLP_ADDRESS_RANGE+FFLP_L3_CLS_7: |
| 230 | { |
| 231 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_L3_CLS_7,wr_data); |
| 232 | fflp_l2_cls_7 = wr_data; |
| 233 | } |
| 234 | FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG0: |
| 235 | { |
| 236 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_CAM_KEY_REG0,wr_data); |
| 237 | fflp_cam_key_reg0 = wr_data; |
| 238 | } |
| 239 | FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG1: |
| 240 | { |
| 241 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_CAM_KEY_REG1,wr_data); |
| 242 | fflp_cam_key_reg1 = wr_data; |
| 243 | } |
| 244 | FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG2: |
| 245 | { |
| 246 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_CAM_KEY_REG2,wr_data); |
| 247 | fflp_cam_key_reg2 = wr_data; |
| 248 | } |
| 249 | FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_REG3: |
| 250 | { |
| 251 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_CAM_KEY_REG3,wr_data); |
| 252 | fflp_cam_key_reg3 = wr_data; |
| 253 | } |
| 254 | FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_MASK_REG0: |
| 255 | { |
| 256 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_CAM_KEY_MASK_REG0,wr_data); |
| 257 | fflp_cam_key_mask_reg0 = wr_data; |
| 258 | } |
| 259 | FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_MASK_REG1: |
| 260 | { |
| 261 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_CAM_KEY_MASK_REG1,wr_data); |
| 262 | fflp_cam_key_mask_reg1 = wr_data; |
| 263 | } |
| 264 | FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_MASK_REG2: |
| 265 | { |
| 266 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_CAM_KEY_MASK_REG2,wr_data); |
| 267 | fflp_cam_key_mask_reg2 = wr_data; |
| 268 | } |
| 269 | FFLP_ADDRESS_RANGE+FFLP_CAM_KEY_MASK_REG3: |
| 270 | { |
| 271 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_CAM_KEY_MASK_REG3,wr_data); |
| 272 | fflp_cam_key_mask_reg3 = wr_data; |
| 273 | } |
| 274 | FFLP_ADDRESS_RANGE+FFLP_CAM_CONTROL: |
| 275 | { |
| 276 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_CAM_CONTROL,wr_data); |
| 277 | fflp_cam_key_control = wr_data; |
| 278 | } |
| 279 | FFLP_ADDRESS_RANGE+FFLP_HOW_TCAM_KEY_CLS_4: |
| 280 | { |
| 281 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_HOW_TCAM_KEY_CLS_4,wr_data); |
| 282 | fflp_how_tcam_key_cls_4 = wr_data; |
| 283 | } |
| 284 | FFLP_ADDRESS_RANGE+FFLP_HOW_TCAM_KEY_CLS_5: |
| 285 | { |
| 286 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_HOW_TCAM_KEY_CLS_5,wr_data); |
| 287 | fflp_how_tcam_key_cls_5 = wr_data; |
| 288 | } |
| 289 | FFLP_ADDRESS_RANGE+FFLP_HOW_TCAM_KEY_CLS_6: |
| 290 | { |
| 291 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_HOW_TCAM_KEY_CLS_6,wr_data); |
| 292 | fflp_how_tcam_key_cls_6 = wr_data; |
| 293 | } |
| 294 | FFLP_ADDRESS_RANGE+FFLP_HOW_TCAM_KEY_CLS_7: |
| 295 | { |
| 296 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_HOW_TCAM_KEY_CLS_7,wr_data); |
| 297 | fflp_how_tcam_key_cls_7 = wr_data; |
| 298 | } |
| 299 | FFLP_ADDRESS_RANGE+FFLP_HOW_TCAM_KEY_CLS_8: |
| 300 | { |
| 301 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_HOW_TCAM_KEY_CLS_8,wr_data); |
| 302 | fflp_how_tcam_key_cls_8 = wr_data; |
| 303 | } |
| 304 | FFLP_ADDRESS_RANGE+FFLP_HOW_TCAM_KEY_CLS_9: |
| 305 | { |
| 306 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_HOW_TCAM_KEY_CLS_9,wr_data); |
| 307 | fflp_how_tcam_key_cls_9 = wr_data; |
| 308 | } |
| 309 | FFLP_ADDRESS_RANGE+FFLP_HOW_TCAM_KEY_CLS_A: |
| 310 | { |
| 311 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_HOW_TCAM_KEY_CLS_A,wr_data); |
| 312 | fflp_how_tcam_key_cls_A = wr_data; |
| 313 | } |
| 314 | FFLP_ADDRESS_RANGE+FFLP_HOW_TCAM_KEY_CLS_B: |
| 315 | { |
| 316 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_HOW_TCAM_KEY_CLS_B,wr_data); |
| 317 | fflp_how_tcam_key_cls_B = wr_data; |
| 318 | } |
| 319 | FFLP_ADDRESS_RANGE+FFLP_HOW_TCAM_KEY_CLS_C: |
| 320 | { |
| 321 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_HOW_TCAM_KEY_CLS_C,wr_data); |
| 322 | fflp_how_tcam_key_cls_C = wr_data; |
| 323 | } |
| 324 | FFLP_ADDRESS_RANGE+FFLP_HOW_TCAM_KEY_CLS_D: |
| 325 | { |
| 326 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_HOW_TCAM_KEY_CLS_D,wr_data); |
| 327 | fflp_how_tcam_key_cls_D = wr_data; |
| 328 | } |
| 329 | FFLP_ADDRESS_RANGE+FFLP_HOW_TCAM_KEY_CLS_E: |
| 330 | { |
| 331 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_HOW_TCAM_KEY_CLS_E,wr_data); |
| 332 | fflp_how_tcam_key_cls_E = wr_data; |
| 333 | } |
| 334 | FFLP_ADDRESS_RANGE+FFLP_HOW_TCAM_KEY_CLS_F: |
| 335 | { |
| 336 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_HOW_TCAM_KEY_CLS_F,wr_data); |
| 337 | fflp_how_tcam_key_cls_F = wr_data; |
| 338 | } |
| 339 | FFLP_FLOW_ADDRESS_RANGE+FFLP_HOW_FLOW_KEY_CLS_4: |
| 340 | { |
| 341 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE +FFLP_HOW_FLOW_KEY_CLS_4,wr_data); |
| 342 | fflp_how_flow_key_cls_4 = wr_data; |
| 343 | } |
| 344 | FFLP_FLOW_ADDRESS_RANGE+FFLP_HOW_FLOW_KEY_CLS_5: |
| 345 | { |
| 346 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE +FFLP_HOW_FLOW_KEY_CLS_5,wr_data); |
| 347 | fflp_how_flow_key_cls_5 = wr_data; |
| 348 | } |
| 349 | FFLP_FLOW_ADDRESS_RANGE+FFLP_HOW_FLOW_KEY_CLS_6: |
| 350 | { |
| 351 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE +FFLP_HOW_FLOW_KEY_CLS_6,wr_data); |
| 352 | fflp_how_flow_key_cls_6 = wr_data; |
| 353 | } |
| 354 | FFLP_FLOW_ADDRESS_RANGE+FFLP_HOW_FLOW_KEY_CLS_7: |
| 355 | { |
| 356 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE +FFLP_HOW_FLOW_KEY_CLS_7,wr_data); |
| 357 | fflp_how_flow_key_cls_7 = wr_data; |
| 358 | } |
| 359 | FFLP_FLOW_ADDRESS_RANGE+FFLP_HOW_FLOW_KEY_CLS_8: |
| 360 | { |
| 361 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE +FFLP_HOW_FLOW_KEY_CLS_8,wr_data); |
| 362 | fflp_how_flow_key_cls_8 = wr_data; |
| 363 | } |
| 364 | FFLP_FLOW_ADDRESS_RANGE+FFLP_HOW_FLOW_KEY_CLS_9: |
| 365 | { |
| 366 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE +FFLP_HOW_FLOW_KEY_CLS_9,wr_data); |
| 367 | fflp_how_flow_key_cls_9 = wr_data; |
| 368 | } |
| 369 | FFLP_FLOW_ADDRESS_RANGE+FFLP_HOW_FLOW_KEY_CLS_A: |
| 370 | { |
| 371 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE +FFLP_HOW_FLOW_KEY_CLS_A,wr_data); |
| 372 | fflp_how_flow_key_cls_A = wr_data; |
| 373 | } |
| 374 | FFLP_FLOW_ADDRESS_RANGE+FFLP_HOW_FLOW_KEY_CLS_B: |
| 375 | { |
| 376 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE +FFLP_HOW_FLOW_KEY_CLS_B,wr_data); |
| 377 | fflp_how_flow_key_cls_B = wr_data; |
| 378 | } |
| 379 | FFLP_FLOW_ADDRESS_RANGE+FFLP_HOW_FLOW_KEY_CLS_C: |
| 380 | { |
| 381 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE +FFLP_HOW_FLOW_KEY_CLS_C,wr_data); |
| 382 | fflp_how_flow_key_cls_C = wr_data; |
| 383 | } |
| 384 | FFLP_FLOW_ADDRESS_RANGE+FFLP_HOW_FLOW_KEY_CLS_D: |
| 385 | { |
| 386 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE +FFLP_HOW_FLOW_KEY_CLS_D,wr_data); |
| 387 | fflp_how_flow_key_cls_D = wr_data; |
| 388 | } |
| 389 | FFLP_FLOW_ADDRESS_RANGE+FFLP_HOW_FLOW_KEY_CLS_E: |
| 390 | { |
| 391 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE +FFLP_HOW_FLOW_KEY_CLS_E,wr_data); |
| 392 | fflp_how_flow_key_cls_E = wr_data; |
| 393 | } |
| 394 | FFLP_FLOW_ADDRESS_RANGE+FFLP_HOW_FLOW_KEY_CLS_F: |
| 395 | { |
| 396 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE +FFLP_HOW_FLOW_KEY_CLS_F,wr_data); |
| 397 | fflp_how_flow_key_cls_F = wr_data; |
| 398 | } |
| 399 | FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_H1POLY: |
| 400 | { |
| 401 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_H1POLY,wr_data); |
| 402 | fflp_flow_h1poly = wr_data; |
| 403 | } |
| 404 | FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL: |
| 405 | { |
| 406 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL,wr_data); |
| 407 | ext_lookup[0] = wr_data[16]; |
| 408 | } |
| 409 | FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (1*8): |
| 410 | { |
| 411 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (1*8),wr_data); |
| 412 | ext_lookup[1] = wr_data[16]; |
| 413 | } |
| 414 | FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (2*8): |
| 415 | { |
| 416 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (2*8),wr_data); |
| 417 | ext_lookup[2] = wr_data[16]; |
| 418 | } |
| 419 | FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (3*8): |
| 420 | { |
| 421 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (3*8),wr_data); |
| 422 | ext_lookup[3] = wr_data[16]; |
| 423 | } |
| 424 | FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (4*8): |
| 425 | { |
| 426 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (4*8),wr_data); |
| 427 | ext_lookup[4] = wr_data[16]; |
| 428 | } |
| 429 | FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (5*8): |
| 430 | { |
| 431 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (5*8),wr_data); |
| 432 | ext_lookup[5] = wr_data[16]; |
| 433 | } |
| 434 | FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (6*8): |
| 435 | { |
| 436 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (6*8),wr_data); |
| 437 | ext_lookup[6] = wr_data[16]; |
| 438 | } |
| 439 | FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (7*8): |
| 440 | { |
| 441 | gen_pio_drv.pio_wr(FFLP_FLOW_ADDRESS_RANGE + FFLP_FLOW_PARTITION_SEL + (7*8),wr_data); |
| 442 | ext_lookup[7] = wr_data[16]; |
| 443 | } |
| 444 | RDC_DEF_PT0_RDC: |
| 445 | { |
| 446 | gen_pio_drv.pio_wr(RDC_DEF_PT0_RDC,wr_data); |
| 447 | rdc_def_pt0_rdc = wr_data; |
| 448 | } |
| 449 | RDC_DEF_PT1_RDC: |
| 450 | { |
| 451 | gen_pio_drv.pio_wr(RDC_DEF_PT1_RDC,wr_data); |
| 452 | rdc_def_pt1_rdc = wr_data; |
| 453 | } |
| 454 | RDC_DEF_PT2_RDC: |
| 455 | { |
| 456 | gen_pio_drv.pio_wr(RDC_DEF_PT2_RDC,wr_data); |
| 457 | rdc_def_pt2_rdc = wr_data; |
| 458 | } |
| 459 | RDC_DEF_PT3_RDC: |
| 460 | { |
| 461 | gen_pio_drv.pio_wr(RDC_DEF_PT3_RDC,wr_data); |
| 462 | rdc_def_pt3_rdc = wr_data; |
| 463 | } |
| 464 | default: |
| 465 | { |
| 466 | |
| 467 | } |
| 468 | } |
| 469 | } |
| 470 | |
| 471 | task fflp_util_class::fflp_init ( integer iport, bit[63:0] cmd) { |
| 472 | |
| 473 | |
| 474 | bit [39:0] base_addr; |
| 475 | bit [63:0] i, wr_data; |
| 476 | bit [39:0] addr; |
| 477 | |
| 478 | // FFLP_CONFIG |
| 479 | printf(" Initializing FFLP_CONFIG REG \n"); |
| 480 | wr_data = 64'h0000_0000_0004_3301; |
| 481 | |
| 482 | // gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_CONFIG,wr_data); |
| 483 | gen_pio_drv.pio_wr(FFLP_ADDRESS_RANGE +FFLP_CONFIG,wr_data); |
| 484 | |
| 485 | be_msg.print(e_mesg_info, "fflp_util_class", "fflp_init", |
| 486 | "WROTE %h TO FFLP CONFIG REG.\n",wr_data); |
| 487 | |
| 488 | // FFLP_L2_CLS_2 |
| 489 | printf(" Initializing FFLP_L2_CLS_2 REG \n"); |
| 490 | addr = FFLP_ADDRESS_RANGE + FFLP_L2_CLS_2; |
| 491 | // gen_pio_drv.pio_wr(addr, 64'h0); |
| 492 | gen_pio_drv.pio_wr(addr, 64'h0); |
| 493 | |
| 494 | // FFLP_L2_CLS_3 |
| 495 | printf(" Initializing FFLP_L2_CLS_3 REG \n"); |
| 496 | addr = FFLP_ADDRESS_RANGE + FFLP_L2_CLS_3; |
| 497 | // gen_pio_drv.pio_wr(addr, 64'h0); |
| 498 | gen_pio_drv.pio_wr(addr, 64'h0); |
| 499 | |
| 500 | // FFLP L3 class4-7 |
| 501 | printf(" Initializing FFLP L3 class4-7 REG \n"); |
| 502 | for (addr = FFLP_ADDRESS_RANGE + FFLP_L3_CLS_4; addr < FFLP_ADDRESS_RANGE + FFLP_L3_CLS_7 + 32'h8; addr = addr + 32'h8) { |
| 503 | // gen_pio_drv.pio_wr(addr, 64'h0); |
| 504 | gen_pio_drv.pio_wr(addr, 64'h0); |
| 505 | |
| 506 | repeat (5) @(posedge CLOCK); |
| 507 | } |
| 508 | |
| 509 | // FFLP CAM KEY 0-3 |
| 510 | printf(" Initializing FFLP CAM KEY 0-3 REG \n"); |
| 511 | for (addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG0; addr < FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG3 + 32'h8; addr = addr + 32'h8) { |
| 512 | // gen_pio_drv.pio_wr(addr, 64'h0); |
| 513 | gen_pio_drv.pio_wr(addr, 64'h0); |
| 514 | |
| 515 | repeat (5) @(posedge CLOCK); |
| 516 | } |
| 517 | |
| 518 | // FFLP CAM KEY MASK 0-3 |
| 519 | printf(" Initializing FFLP CAM KEY MASK 0-3 REG \n"); |
| 520 | for (addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_MASK_REG0; addr < FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_MASK_REG3 + 32'h8; addr = addr + 32'h8) { |
| 521 | // gen_pio_drv.pio_wr(addr, 64'h0); |
| 522 | gen_pio_drv.pio_wr(addr, 64'h0); |
| 523 | |
| 524 | repeat (5) @(posedge CLOCK); |
| 525 | } |
| 526 | |
| 527 | if ( get_plus_arg(CHECK, "INIT_TCAM_RAM") ) |
| 528 | { |
| 529 | // FFLP CAM 128-entry |
| 530 | printf(" Initializing FFLP CAM 128-entry \n"); |
| 531 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_CONTROL; |
| 532 | for (wr_data = 10'd0; wr_data < 10'd128; wr_data = wr_data + 1'd1) { |
| 533 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 534 | gen_pio_drv.pio_wr(addr, wr_data); |
| 535 | printf(" Write data %h to addr %h for CAM 128-entry\n", wr_data, addr); |
| 536 | |
| 537 | repeat (8) @(posedge CLOCK); |
| 538 | } |
| 539 | |
| 540 | // FFLP CAM associated RAM 128-entry |
| 541 | printf(" Initializing FFLP CAM associated RAM 128-entry \n"); |
| 542 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_CONTROL; |
| 543 | for (i = 10'd0; i < 10'd128; i = i + 1'd1) { |
| 544 | wr_data = i + 64'h10_0000; |
| 545 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 546 | gen_pio_drv.pio_wr(addr, wr_data); |
| 547 | printf(" Write data %h to addr %h for RAM 128-entry\n", wr_data, addr); |
| 548 | |
| 549 | repeat (8) @(posedge CLOCK); |
| 550 | } |
| 551 | } |
| 552 | |
| 553 | // VLAN table |
| 554 | |
| 555 | if ( get_plus_arg(CHECK, "INIT_VLAN_TBL") ) |
| 556 | { |
| 557 | printf(" Initializing VLAN Table.\n"); |
| 558 | for (i=0;i<4096;i++) |
| 559 | { |
| 560 | wr_data = 64'h0; |
| 561 | addr = FFLP_VLAN_TBL_ADDRESS_RANGE + (i*8); |
| 562 | |
| 563 | gen_pio_drv.pio_wr(addr, wr_data); |
| 564 | // fflp_util.fflp_pio_wrapper(addr, wr_data); NO SUPPORT YET |
| 565 | } |
| 566 | printf(" VLAN Table Initialized.\n"); |
| 567 | } |
| 568 | } // end of task fflp_init |
| 569 | |
| 570 | function bit fflp_util_class :: check_cmd(bit [63:0]cmd, bit [63:0] opt){ |
| 571 | if((cmd & opt) > 0) check_cmd=1; |
| 572 | else check_cmd=0; |
| 573 | } |
| 574 | |
| 575 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ |
| 576 | //@@ FFLP PIO WRAPPERS @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ |
| 577 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ |
| 578 | //@@@@@@@@@@@@@@@@@ TCAM index based read TCAM key @@@@@@@@@@@@@@@@@@@ |
| 579 | function bit [199:0] fflp_util_class::pio_rd_tcam_key (bit [9:0] tcam_index, |
| 580 | var bit [199:0] pio_rd_tcam_mask) |
| 581 | { |
| 582 | |
| 583 | integer stat; |
| 584 | bit [63:0] rd_data; |
| 585 | bit [63:0] wr_data; |
| 586 | |
| 587 | bit [39:0] addr; |
| 588 | |
| 589 | bit [63:0] rd_data0; |
| 590 | bit [63:0] rd_data1; |
| 591 | bit [63:0] rd_data2; |
| 592 | bit [63:0] rd_data3; |
| 593 | bit [63:0] rdm_data0; |
| 594 | bit [63:0] rdm_data1; |
| 595 | bit [63:0] rdm_data2; |
| 596 | bit [63:0] rdm_data3; |
| 597 | |
| 598 | //**************************************** |
| 599 | // CPU checks the done bit before start ** |
| 600 | //**************************************** |
| 601 | wait_for_done_bit(); |
| 602 | |
| 603 | //**************************************** |
| 604 | // CPU write to command register ********* |
| 605 | //**************************************** |
| 606 | //printf("KEY_TYPE IS = %d\n", key_type); |
| 607 | //printf("L3_L2 = %h, L3_L2 = %d\n", key_size, key_size); |
| 608 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_CONTROL; |
| 609 | wr_data = {43'h0,3'b001,8'h00,tcam_index}; |
| 610 | gen_pio_drv.pio_wr(addr, wr_data); |
| 611 | |
| 612 | //**************************************** |
| 613 | // CPU checks the done bit before start ** |
| 614 | //**************************************** |
| 615 | wait_for_done_bit(); |
| 616 | |
| 617 | //**************************************** |
| 618 | // CPU reads "read CAM key registers" **** |
| 619 | //**************************************** |
| 620 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_MASK_REG0; |
| 621 | gen_pio_drv.pio_rd(addr, rdm_data0, stat); |
| 622 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_MASK_REG1; |
| 623 | gen_pio_drv.pio_rd(addr, rdm_data1, stat); |
| 624 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_MASK_REG2; |
| 625 | gen_pio_drv.pio_rd(addr, rdm_data2, stat); |
| 626 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_MASK_REG3; |
| 627 | gen_pio_drv.pio_rd(addr, rdm_data3, stat); |
| 628 | |
| 629 | pio_rd_tcam_mask = {rdm_data0[7:0],rdm_data1,rdm_data2,rdm_data3}; |
| 630 | printf("Index = %d, Read_TCAM_Mask Value = %h.\n",tcam_index,pio_rd_tcam_mask); |
| 631 | |
| 632 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG0; |
| 633 | gen_pio_drv.pio_rd(addr, rd_data0, stat); |
| 634 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG1; |
| 635 | gen_pio_drv.pio_rd(addr, rd_data1, stat); |
| 636 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG2; |
| 637 | gen_pio_drv.pio_rd(addr, rd_data2, stat); |
| 638 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG3; |
| 639 | gen_pio_drv.pio_rd(addr, rd_data3, stat); |
| 640 | |
| 641 | pio_rd_tcam_key = {rd_data0[7:0],rd_data1,rd_data2,rd_data3}; |
| 642 | printf("Index = %d, Read_TCAM Value = %h.\n",tcam_index,pio_rd_tcam_key); |
| 643 | |
| 644 | } |
| 645 | |
| 646 | //@@@@@@@@@@@@@@@@@ TCAM index based write TCAM key @@@@@@@@@@@@@@@@@@@ |
| 647 | task fflp_util_class::pio_wr_tcam_key (bit [9:0] tcam_index, |
| 648 | bit [199:0] wr_tcam_key, |
| 649 | bit [199:0] wr_tcam_mask) |
| 650 | { |
| 651 | bit [63:0] wr_data; |
| 652 | bit [39:0] addr; |
| 653 | |
| 654 | //**************************************** |
| 655 | // CPU checks the done bit before start ** |
| 656 | //**************************************** |
| 657 | wait_for_done_bit(); |
| 658 | |
| 659 | //******************************************** |
| 660 | // CPU writes CAM keys to wrt_cam_key regs. ** |
| 661 | //******************************************** |
| 662 | |
| 663 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_MASK_REG0; |
| 664 | wr_data = {56'h0,wr_tcam_mask[199:192]}; |
| 665 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 666 | fflp_pio_wrapper ( addr, wr_data); |
| 667 | |
| 668 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_MASK_REG1; |
| 669 | wr_data = wr_tcam_mask[191:128]; |
| 670 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 671 | fflp_pio_wrapper ( addr, wr_data); |
| 672 | |
| 673 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_MASK_REG2; |
| 674 | wr_data = wr_tcam_mask[127:64]; |
| 675 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 676 | fflp_pio_wrapper ( addr, wr_data); |
| 677 | |
| 678 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_MASK_REG3; |
| 679 | wr_data = wr_tcam_mask[63:0]; |
| 680 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 681 | fflp_pio_wrapper ( addr, wr_data); |
| 682 | printf("Index = %d, Write_TCAM_Mask Value = %h.\n",tcam_index,wr_tcam_mask); |
| 683 | |
| 684 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG0; |
| 685 | wr_data = {56'h0,wr_tcam_key[199:192]}; |
| 686 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 687 | fflp_pio_wrapper ( addr, wr_data); |
| 688 | |
| 689 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG1; |
| 690 | wr_data = wr_tcam_key[191:128]; |
| 691 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 692 | fflp_pio_wrapper ( addr, wr_data); |
| 693 | |
| 694 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG2; |
| 695 | wr_data = wr_tcam_key[127:64]; |
| 696 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 697 | fflp_pio_wrapper ( addr, wr_data); |
| 698 | |
| 699 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG3; |
| 700 | wr_data = wr_tcam_key[63:0]; |
| 701 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 702 | fflp_pio_wrapper ( addr, wr_data); |
| 703 | printf("Index = %d, Write_TCAM Value = %h.\n",tcam_index,wr_tcam_key); |
| 704 | |
| 705 | //**************************************** |
| 706 | // CPU write to command register ********* |
| 707 | //**************************************** |
| 708 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_CONTROL; |
| 709 | wr_data = {43'h0,3'b000,8'h00,tcam_index}; |
| 710 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 711 | fflp_pio_wrapper ( addr, wr_data); |
| 712 | } |
| 713 | |
| 714 | //@@TASK Version@@@ TCAM Compare based on TCAM key @@@@@@@@@@@@@@@@@@@ |
| 715 | task fflp_util_class::pio_cmp_tcam_key (bit [199:0] cmp_tcam_key) |
| 716 | { |
| 717 | bit [63:0] wr_data; |
| 718 | bit [39:0] addr; |
| 719 | bit [9:0] tcam_index = 10'h0; |
| 720 | |
| 721 | //**************************************** |
| 722 | // CPU checks the done bit before start ** |
| 723 | //**************************************** |
| 724 | wait_for_done_bit(); |
| 725 | |
| 726 | //******************************************** |
| 727 | // CPU writes CAM keys to wrt_cam_key regs. ** |
| 728 | //******************************************** |
| 729 | |
| 730 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG0; |
| 731 | wr_data = {56'h0,cmp_tcam_key[199:192]}; |
| 732 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 733 | fflp_pio_wrapper ( addr, wr_data); |
| 734 | |
| 735 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG1; |
| 736 | wr_data = cmp_tcam_key[191:128]; |
| 737 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 738 | fflp_pio_wrapper ( addr, wr_data); |
| 739 | |
| 740 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG2; |
| 741 | wr_data = cmp_tcam_key[127:64]; |
| 742 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 743 | fflp_pio_wrapper ( addr, wr_data); |
| 744 | |
| 745 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG3; |
| 746 | wr_data = cmp_tcam_key[63:0]; |
| 747 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 748 | fflp_pio_wrapper ( addr, wr_data); |
| 749 | printf("Index = %d, Compare TCAM Value = %h.\n",cmp_tcam_key); |
| 750 | |
| 751 | //**************************************** |
| 752 | // CPU write to command register ********* |
| 753 | //**************************************** |
| 754 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_CONTROL; |
| 755 | wr_data = {43'h0,3'b010,8'h00,tcam_index}; |
| 756 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 757 | fflp_pio_wrapper ( addr, wr_data); |
| 758 | } |
| 759 | |
| 760 | //@@FUNCTION Version@@@@TCAM Compare based on TCAM key @@@@@@@@@@@@@@@@@@@ |
| 761 | function bit [10:0] fflp_util_class::pio_comp_tcam_key (bit [199:0] cmp_tcam_key) |
| 762 | { |
| 763 | bit [63:0] rd_data; |
| 764 | bit [63:0] wr_data; |
| 765 | bit [39:0] addr; |
| 766 | bit [9:0] tcam_index = 10'h0; |
| 767 | integer stat; |
| 768 | |
| 769 | //**************************************** |
| 770 | // CPU checks the done bit before start ** |
| 771 | //**************************************** |
| 772 | wait_for_done_bit(); |
| 773 | |
| 774 | //******************************************** |
| 775 | // CPU writes CAM keys to wrt_cam_key regs. ** |
| 776 | //******************************************** |
| 777 | |
| 778 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG0; |
| 779 | wr_data = {56'h0,cmp_tcam_key[199:192]}; |
| 780 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 781 | fflp_pio_wrapper ( addr, wr_data); |
| 782 | |
| 783 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG1; |
| 784 | wr_data = cmp_tcam_key[191:128]; |
| 785 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 786 | fflp_pio_wrapper ( addr, wr_data); |
| 787 | |
| 788 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG2; |
| 789 | wr_data = cmp_tcam_key[127:64]; |
| 790 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 791 | fflp_pio_wrapper ( addr, wr_data); |
| 792 | |
| 793 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG3; |
| 794 | wr_data = cmp_tcam_key[63:0]; |
| 795 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 796 | fflp_pio_wrapper ( addr, wr_data); |
| 797 | printf("Index = %d, Compare TCAM Value = %h.\n",cmp_tcam_key); |
| 798 | |
| 799 | //**************************************** |
| 800 | // CPU write to command register ********* |
| 801 | //**************************************** |
| 802 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_CONTROL; |
| 803 | wr_data = {43'h0,3'b010,8'h00,tcam_index}; |
| 804 | // gen_pio_drv.pio_wr(addr, wr_data); |
| 805 | fflp_pio_wrapper ( addr, wr_data); |
| 806 | |
| 807 | //**************************************** |
| 808 | // CPU checks the done bit before start ** |
| 809 | //**************************************** |
| 810 | wait_for_done_bit(); |
| 811 | |
| 812 | gen_pio_drv.pio_rd(addr, rd_data, stat); |
| 813 | pio_comp_tcam_key = {rd_data[16],rd_data[9:0]}; |
| 814 | } |
| 815 | |
| 816 | //@@@@@@@@@@@@@@@@@ TCAM index based read AS_DATA @@@@@@@@@@@@@@@@@@@ |
| 817 | function bit [63:0] fflp_util_class::pio_rd_tcam_asdata (bit [9:0] tcam_index) |
| 818 | { |
| 819 | |
| 820 | integer stat; |
| 821 | bit [63:0] rd_data; |
| 822 | bit [63:0] rd_data1; |
| 823 | bit [63:0] wr_data; |
| 824 | |
| 825 | bit [39:0] addr; |
| 826 | |
| 827 | //**************************************** |
| 828 | // CPU checks the done bit before start ** |
| 829 | //**************************************** |
| 830 | wait_for_done_bit(); |
| 831 | |
| 832 | //**************************************** |
| 833 | // CPU write to command register ********* |
| 834 | //**************************************** |
| 835 | //printf("KEY_TYPE IS = %d\n", key_type); |
| 836 | //printf("L3_L2 = %h, L3_L2 = %d\n", key_size, key_size); |
| 837 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_CONTROL; |
| 838 | wr_data = {43'h0,3'b101,8'h00,tcam_index}; |
| 839 | gen_pio_drv.pio_wr(addr, wr_data); |
| 840 | |
| 841 | //**************************************** |
| 842 | // CPU checks the done bit before start ** |
| 843 | //**************************************** |
| 844 | wait_for_done_bit(); |
| 845 | |
| 846 | //**************************************** |
| 847 | // CPU reads "read CAM key registers" **** |
| 848 | //**************************************** |
| 849 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG1; |
| 850 | gen_pio_drv.pio_rd(addr, rd_data1, stat); |
| 851 | |
| 852 | pio_rd_tcam_asdata = rd_data1; |
| 853 | printf("Index = %d, Read_TCAM ASDATA Value = %h.\n",tcam_index,pio_rd_tcam_asdata); |
| 854 | |
| 855 | } |
| 856 | |
| 857 | //@@@@@@@@@@@@@@@@@ TCAM index based write AS_DATA @@@@@@@@@@@@@@@@@@@ |
| 858 | task fflp_util_class::pio_wr_tcam_asdata (bit [9:0] tcam_index, |
| 859 | bit [63:0] wr_tcam_asdata) |
| 860 | { |
| 861 | bit [63:0] wr_data; |
| 862 | bit [39:0] addr; |
| 863 | |
| 864 | //**************************************** |
| 865 | // CPU checks the done bit before start ** |
| 866 | //**************************************** |
| 867 | wait_for_done_bit(); |
| 868 | |
| 869 | //******************************************** |
| 870 | // CPU writes CAM keys to wrt_cam_key regs. ** |
| 871 | //******************************************** |
| 872 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_KEY_REG1; |
| 873 | wr_data = wr_tcam_asdata; |
| 874 | gen_pio_drv.pio_wr(addr, wr_data); |
| 875 | printf("Index = %d, Writing TCAM_ASDATA Value = %h.\n",tcam_index,wr_tcam_asdata); |
| 876 | |
| 877 | //**************************************** |
| 878 | // CPU write to command register ********* |
| 879 | //**************************************** |
| 880 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_CONTROL; |
| 881 | wr_data = {43'h0,3'b100,8'h00,tcam_index}; |
| 882 | gen_pio_drv.pio_wr(addr, wr_data); |
| 883 | } |
| 884 | |
| 885 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ |
| 886 | //@@@@@@@@ Wait for cmd completion bit @@@@@@@@@@ |
| 887 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ |
| 888 | task fflp_util_class::wait_for_done_bit() |
| 889 | { |
| 890 | integer stat; |
| 891 | bit [63:0] rd_data =0; |
| 892 | bit [39:0] addr =0; |
| 893 | |
| 894 | addr = FFLP_ADDRESS_RANGE + FFLP_CAM_CONTROL; |
| 895 | gen_pio_drv.pio_rd(addr, rd_data, stat); |
| 896 | while(!rd_data[17]) |
| 897 | { |
| 898 | gen_pio_drv.pio_rd(addr, rd_data, stat); |
| 899 | } |
| 900 | repeat(5) @(posedge CLOCK); |
| 901 | } |
| 902 | task fflp_util_class::init_cam_entries() |
| 903 | { |
| 904 | integer i; |
| 905 | bit [9:0] cam_addr; |
| 906 | bit [199:0] cam_key; |
| 907 | bit [199:0] cam_lmask; |
| 908 | bit [63:0] adata; |
| 909 | |
| 910 | bit [4:0] hdr_class = 5'b00000; |
| 911 | bit [4:0] l2_drc_tbl_num = 5'b00000; |
| 912 | bit noport = 1'b0; |
| 913 | bit [7:0] tos = 8'h0; |
| 914 | bit [7:0] next_hdr = 8'h0; |
| 915 | bit [15:0] src_port_num = 16'h0; |
| 916 | bit [15:0] dst_port_num = 16'h0; |
| 917 | bit [127:0] dst_src_addr = 128'h0; |
| 918 | bit [7:0] protocol = 8'h0; |
| 919 | bit [31:0] src_addr = 32'h0; |
| 920 | bit [31:0] dst_addr = 32'h0; |
| 921 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ |
| 922 | //@ 1st Packet cam/ram setup CL_TCP @ |
| 923 | //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ |
| 924 | cam_addr = 10'h0_00; |
| 925 | cam_key = 200'h0; |
| 926 | cam_lmask = 200'hff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff; |
| 927 | |
| 928 | if ( get_plus_arg(CHECK, "DO_PIO_TRANS") ) |
| 929 | { |
| 930 | be_msg.print(e_mesg_info, *, "test_class::init_cam_entries()", |
| 931 | "Initializing CAM, Performing PIO Transactions to CAM_RAM.\n"); |
| 932 | for (i=0;i<IP_DB_ENTRIES;i++) |
| 933 | { |
| 934 | pio_wr_tcam_key(cam_addr, cam_key, cam_lmask); |
| 935 | cam_addr = cam_addr + 1; |
| 936 | } |
| 937 | } |
| 938 | else |
| 939 | { |
| 940 | be_msg.print(e_mesg_info, *, "test_class::init_cam_entries()", |
| 941 | "Performing Backdoor Operation to CAM_RAM.\n"); |
| 942 | } |
| 943 | } |