// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: l2t_mb0_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
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// ========== Copyright Header End ============================================
mb0_l2t_mbist_write_data,
wire array_usr_reg_scanin;
wire array_usr_reg_scanout;
wire [3:0] user_array_sel_in;
wire [3:0] user_array_sel;
wire user_addr_mode_reg_scanin;
wire user_addr_mode_reg_scanout;
wire user_start_addr_reg_scanin;
wire user_start_addr_reg_scanout;
wire [7:0] user_start_addr_in;
wire [7:0] user_start_addr;
wire user_stop_addr_reg_scanin;
wire user_stop_addr_reg_scanout;
wire [7:0] user_stop_addr_in;
wire [7:0] user_stop_addr;
wire user_incr_addr_reg_scanin;
wire user_incr_addr_reg_scanout;
wire [7:0] user_incr_addr_in;
wire [7:0] user_incr_addr;
wire user_data_mode_reg_scanin;
wire user_data_mode_reg_scanout;
wire user_data_reg_scanin;
wire user_data_reg_scanout;
wire user_cmpsel_hold_reg_scanin;
wire user_cmpsel_hold_reg_scanout;
wire user_cmpsel_hold_in;
wire user_cmpsel_reg_scanin;
wire user_cmpsel_reg_scanout;
wire [3:0] user_cmpsel_in;
wire user_loop_mode_reg_scanin;
wire user_loop_mode_reg_scanout;
wire ten_n_mode_reg_scanin;
wire ten_n_mode_reg_scanout;
wire user_cam_mode_reg_scanin;
wire user_cam_mode_reg_scanout;
wire user_cam_select_reg_scanin;
wire user_cam_select_reg_scanout;
wire [1:0] user_cam_sel_in;
wire user_cam_test_select_reg_scanin;
wire user_cam_test_select_reg_scanout;
wire [1:0] user_cam_test_sel_in;
wire [1:0] user_cam_test_sel;
wire user_bisi_wr_mode_reg_scanin;
wire user_bisi_wr_mode_reg_scanout;
wire user_bisi_wr_mode_in;
wire user_bisi_rd_mode_reg_scanin;
wire user_bisi_rd_mode_reg_scanout;
wire user_bisi_rd_mode_in;
wire mb_user_cmpsel_hold;
wire mb_user_bisi_wr_mode;
wire mb_user_bisi_rd_mode;
wire mb_user_bisi_rw_mode;
wire input_signals_reg_scanin;
wire input_signals_reg_scanout;
wire mb_enable_reg_scanin;
wire mb_enable_reg_scanout;
wire loop_again_reg_scanin;
wire loop_again_reg_scanout;
wire cam_cntl_reg_scanin;
wire cam_cntl_reg_scanout;
wire cam_shift_reg_scanin;
wire cam_shift_reg_scanout;
wire [1:0] cam_array_sel;
wire [1:0] cam_panel_sel;
wire [15:0] lookup_wdata;
wire cam_hit_reg_scanout;
wire exp_cam_hit_delay_reg_scanin;
wire exp_cam_hit_delay_reg_scanout;
wire exp_cam_exp_delay_reg_scanin;
wire exp_cam_exp_delay_reg_scanout;
wire cam_sel_icrow_delay_reg_scanin;
wire cam_sel_icrow_delay_reg_scanout;
wire cam_sel_dcrow_delay_reg_scanin;
wire cam_sel_dcrow_delay_reg_scanout;
wire [3:0] icrow_lookup_en;
wire [3:0] dcrow_lookup_en;
wire [3:0] icrow_panel_en;
wire [3:0] dcrow_panel_en;
wire mbist_output_reg_scanin;
wire mbist_output_reg_scanout;
wire [15:0] mb_lookup_wdata;
wire mbist_output_data_reg_scanin;
wire mbist_output_data_reg_scanout;
wire sel_nextaddr_restart;
wire sel_nextaddr_incred;
wire [3:0] cntl_array_sel;
wire [1:0] cntl_data_sel;
wire [3:0] cntl_march_element;
wire [3:0] march_element_pre;
wire [3:0] march_element;
wire [1:0] cseq_cntl_out;
wire [1:0] cam_sel_cntl_out;
wire [1:0] ctest_sel_cntl_out;
wire ctest_sel_reg_scanin;
wire ctest_sel_reg_scanout;
wire [1:0] ctest_sel_out;
wire [3:0] array_sel_cntl_out;
wire array_sel_reg_scanin;
wire array_sel_reg_scanout;
wire [3:0] array_sel_out;
wire [3:0] cmp_sel_cntl_out;
wire cmp_sel_reg_scanout;
wire [3:0] march_element_cntl_out;
wire marche_element_reg_scanin;
wire marche_element_reg_scanout;
wire [3:0] march_element_out;
wire [7:0] mb_write_data;
wire run3_transition_reg_scanin;
wire run3_transition_reg_scanout;
wire done_delay_reg_scanin;
wire done_delay_reg_scanout;
wire [4:0] done_delay_in;
wire oqarray_fail_sticky;
wire icrow0_cam_fail_sticky;
wire icrow1_cam_fail_sticky;
wire dcrow0_cam_fail_sticky;
wire dcrow1_cam_fail_sticky;
wire mbist_fail_input_reg_scanin;
wire mbist_fail_input_reg_scanout;
wire out_mb_tcu_done_reg_scanin;
wire out_mb_tcu_done_reg_scanout;
wire inv_mask_reg_scanin;
wire inv_mask_reg_scanout;
wire out_mb_tcu_fail_reg_scanin;
wire out_mb_tcu_fail_reg_scanout;
wire out_cmp_sel_reg_scanin;
wire out_cmp_sel_reg_scanout;
wire [3:0] mb_cmpsel_out;
wire out_run_mb_arrays_reg_scanin;
wire out_run_mb_arrays_reg_scanout;
wire out_data_mb_arrays_reg_scanin;
wire out_data_mb_arrays_reg_scanout;
wire [7:0] mb_write_data_out;
wire out_addr_mb_arrays_reg_scanin;
wire out_addr_mb_arrays_reg_scanout;
wire out_wr_mb_arrays_reg_scanin;
wire out_wr_mb_arrays_reg_scanout;
wire out_rd_mb_arrays_reg_scanin;
wire out_rd_mb_arrays_reg_scanout;
// Please note that this is going to be used as a place holder.
// The inputs and outputs are defined based on the analysis of cluster memories.
// For this version, the outputs of memories are taken into mbist controller.
// /////////////////////////////////////////////////////////////////////////////
// /////////////////////////////////////////////////////////////////////////////
output [5:0] mb0_l2t_addr; // Writing to 1/64 entries
output mb0_l2t_icrow_wr_en;
output mb0_l2t_icrow_rd_en;
output [15:0] mb0_l2t_lookup_wdata; // CAM compare data
output [3:0] mb0_l2t_icrow_lookup_en; // CAM enable for 4 panels
output [1:0] mb0_l2t_icrow_row_en; // pick 1/2 rows
output [3:0] mb0_l2t_icrow_panel_en; // one of 4 panels select
output [7:0] mb0_l2t_mbist_write_data; // only for oqarray
output mb0_l2t_dcrow_wr_en;
output mb0_l2t_dcrow_rd_en;
output [3:0] mb0_l2t_dcrow_lookup_en; // CAM enable for 4 panels
output [1:0] mb0_l2t_dcrow_row_en; // pick 1/2 rows
output [3:0] mb0_l2t_dcrow_panel_en; // one of 4 panels select
output [7:0] mb0_l2t_mask; // mask to mask off the cam hit resetting valid bit
output mb0_l2t_oqarray_wr_en;
output mb0_l2t_oqarray_rd_en;
output [3:0] mb0_l2t_cmpsel; // 1/16 mux select
input [1:0] dc_cam_fail; // free flowing will be qualified in mb0
input [1:0] ic_cam_fail; // free flowing will be qualified in mb0
input [3:0] dir_dc_rw_fail; // free flowing will be qualified in mb0
input [3:0] dir_ic_rw_fail; // free flowing will be qualified in mb0
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
input tcu_pce_ov; // scan signals
// /////////////////////////////////////////////////////////////////////////////
// /////////////////////////////////////////////////////////////////////////////
assign pce_ov = tcu_pce_ov;
assign stop = tcu_clk_stop;
////////////////////////////////////////////////////////////////////////////////
l2t_mb0_ctl_l1clkhdr_ctl_macro clkgen_freeclk (
assign clock_enable = start_in | mb0_l2t_done | mb0_l2t_run | mb0_l2t_fail ;
l2t_mb0_ctl_l1clkhdr_ctl_macro clkgen (
// /////////////////////////////////////////////////////////////////////////////
// MBIST PGM Control Register
// /////////////////////////////////////////////////////////////////////////////
// /////////////////////////////////////////////////////////////////////////////
// there are 4 panels in the directory and 2 rows.
// One of the rows depending on the read enable/row select
// picks the row and muxes the top/bottom column
// Hence there are 4 places where in the data gets compared
// and 4 bit NOT fail. All the 4 bit fails should be OR-ed
assign mb_ic_rw_fail = |(~(dir_ic_rw_fail[3:0]));
assign mb_dc_rw_fail = |(~(dir_dc_rw_fail[3:0]));
////////////////////////////////////////////////////////////////////////////////
// user control registers
l2t_mb0_ctl_msff_ctl_macro__width_4 array_usr_reg (
.scan_in(array_usr_reg_scanin),
.scan_out(array_usr_reg_scanout),
.din ( user_array_sel_in[3:0] ),
.dout ( user_array_sel[3:0] ),
assign user_array_sel_in[3:0]=user_array_sel[3:0];
l2t_mb0_ctl_msff_ctl_macro__width_1 user_addr_mode_reg (
.scan_in(user_addr_mode_reg_scanin),
.scan_out(user_addr_mode_reg_scanout),
.din ( user_addr_mode_in ),
.dout ( user_addr_mode ),
assign user_addr_mode_in=user_addr_mode;
l2t_mb0_ctl_msff_ctl_macro__width_8 user_start_addr_reg (
.scan_in(user_start_addr_reg_scanin),
.scan_out(user_start_addr_reg_scanout),
.din ( user_start_addr_in[7:0] ),
.dout ( user_start_addr[7:0] ),
assign user_start_addr_in[7:0]=user_start_addr[7:0];
l2t_mb0_ctl_msff_ctl_macro__width_8 user_stop_addr_reg (
.scan_in(user_stop_addr_reg_scanin),
.scan_out(user_stop_addr_reg_scanout),
.din ( user_stop_addr_in[7:0] ),
.dout ( user_stop_addr[7:0] ),
assign user_stop_addr_in[7:0]=user_stop_addr[7:0];
// user increment address
l2t_mb0_ctl_msff_ctl_macro__width_8 user_incr_addr_reg (
.scan_in(user_incr_addr_reg_scanin),
.scan_out(user_incr_addr_reg_scanout),
.din ( user_incr_addr_in[7:0] ),
.dout ( user_incr_addr[7:0] ),
assign user_incr_addr_in[7:0]=user_incr_addr[7:0];
l2t_mb0_ctl_msff_ctl_macro__width_1 user_data_mode_reg (
.scan_in(user_data_mode_reg_scanin),
.scan_out(user_data_mode_reg_scanout),
.din ( user_data_mode_in ),
.dout ( user_data_mode ),
assign user_data_mode_in=user_data_mode;
l2t_mb0_ctl_msff_ctl_macro__width_8 user_data_reg (
.scan_in(user_data_reg_scanin),
.scan_out(user_data_reg_scanout),
.din ( user_data_in[7:0] ),
.dout ( user_data[7:0] ),
assign user_data_in[7:0] = user_data[7:0];
// if its one, user need to program the cmpselinc register
// otherwise it will loop all cmpsel
l2t_mb0_ctl_msff_ctl_macro__width_1 user_cmpsel_hold_reg (
.scan_in(user_cmpsel_hold_reg_scanin),
.scan_out(user_cmpsel_hold_reg_scanout),
.din ( user_cmpsel_hold_in ),
.dout ( user_cmpsel_hold ),
assign user_cmpsel_hold_in=user_cmpsel_hold;
l2t_mb0_ctl_msff_ctl_macro__width_4 user_cmpsel_reg (
.scan_in(user_cmpsel_reg_scanin),
.scan_out(user_cmpsel_reg_scanout),
.din ( user_cmpsel_in[3:0] ),
.dout ( user_cmpsel[3:0] ),
assign user_cmpsel_in[3:0]=user_cmpsel[3:0];
l2t_mb0_ctl_msff_ctl_macro__width_1 user_loop_mode_reg (
.scan_in(user_loop_mode_reg_scanin),
.scan_out(user_loop_mode_reg_scanout),
.din ( user_loop_mode_in ),
.dout ( user_loop_mode ),
assign user_loop_mode_in=user_loop_mode;
// 10N Algorithm for bit mapping
l2t_mb0_ctl_msff_ctl_macro__width_1 ten_n_mode_reg (
.scan_in(ten_n_mode_reg_scanin),
.scan_out(ten_n_mode_reg_scanout),
assign ten_n_mode_in=ten_n_mode;
// cambist: user array select
l2t_mb0_ctl_msff_ctl_macro__width_1 user_cam_mode_reg (
.scan_in(user_cam_mode_reg_scanin),
.scan_out(user_cam_mode_reg_scanout),
.din ( user_cam_mode_in ),
assign user_cam_mode_in=user_cam_mode;
l2t_mb0_ctl_msff_ctl_macro__width_2 user_cam_select_reg (
.scan_in(user_cam_select_reg_scanin),
.scan_out(user_cam_select_reg_scanout),
.din ( user_cam_sel_in[1:0] ),
.dout ( user_cam_sel[1:0] ),
assign user_cam_sel_in[1:0]=user_cam_sel[1:0];
l2t_mb0_ctl_msff_ctl_macro__width_2 user_cam_test_select_reg (
.scan_in(user_cam_test_select_reg_scanin),
.scan_out(user_cam_test_select_reg_scanout),
.din ( user_cam_test_sel_in[1:0] ),
.dout ( user_cam_test_sel[1:0] ),
assign user_cam_test_sel_in[1:0]=user_cam_test_sel[1:0];
l2t_mb0_ctl_msff_ctl_macro__width_1 user_bisi_wr_mode_reg (
.scan_in(user_bisi_wr_mode_reg_scanin),
.scan_out(user_bisi_wr_mode_reg_scanout),
.din ( user_bisi_wr_mode_in ),
.dout ( user_bisi_wr_mode ),
assign user_bisi_wr_mode_in=user_bisi_wr_mode;
l2t_mb0_ctl_msff_ctl_macro__width_1 user_bisi_rd_mode_reg (
.scan_in(user_bisi_rd_mode_reg_scanin),
.scan_out(user_bisi_rd_mode_reg_scanout),
.din ( user_bisi_rd_mode_in ),
.dout ( user_bisi_rd_mode ),
assign user_bisi_rd_mode_in=user_bisi_rd_mode;
assign mb_user_data_mode = user_mode & user_data_mode;
assign mb_user_addr_mode = user_mode & user_addr_mode;
assign mb_user_cmpsel_hold = user_mode & user_cmpsel_hold;
assign mb_user_cam_mode = user_mode & user_cam_mode;
assign mb_user_ram_mode = user_mode & ~user_cam_mode;
assign mb_user_loop_mode = user_mode & user_loop_mode;
assign mb_user_bisi_wr_mode = user_mode & user_bisi_wr_mode & bisi_mode;
assign mb_user_bisi_rd_mode = user_mode & user_bisi_rd_mode & bisi_mode;
assign mb_user_bisi_rw_mode = ((~user_bisi_wr_mode & ~user_bisi_rd_mode) | (user_bisi_wr_mode & user_bisi_rd_mode)) & bisi_mode;
assign mb_default_bisi = bisi_mode & ~user_mode;
// /////////////////////////////////////////////////////////////////////////////
// /////////////////////////////////////////////////////////////////////////////
// A low to high transition on mbist_start will reset and start the engine.
// mbist_start must remain active high for the duration of MBIST.
// If mbist_start deasserts the engine will stop but not reset.
// Once MBIST has completed mb0_done will assert and the fail status
// signals will be valid.
// To run MBIST again the mbist_start signal must transition low then high.
// Loop on Address will disable the address mix function.
// /////////////////////////////////////////////////////////////////////////////
// flop incoming signals:
l2t_mb0_ctl_msff_ctl_macro__width_3 input_signals_reg (
.scan_in(input_signals_reg_scanin),
.scan_out(input_signals_reg_scanout),
.din ( {mbist_start,mbist_bisi_mode,mbist_user_mode} ),
.dout ( {start_in,bisi_mode,user_mode} ),
// user_mode : mb_enable=depend on programmed value
l2t_mb0_ctl_msff_ctl_macro__width_1 mb_enable_reg (
.scan_in(mb_enable_reg_scanin),
.scan_out(mb_enable_reg_scanout),
assign mb_enable = user_mode ? mb_enable_out : 1'b0;
assign start = user_mode ? (mb_enable_out & start_in) :
l2t_mb0_ctl_msff_ctl_macro__width_2 config_reg (
.scan_in(config_reg_scanin),
.scan_out(config_reg_scanout),
.dout ( config_out[1:0] ),
assign config_in[0] = start;
assign config_in[1] = config_out[0];
assign start_transition = config_out[0] & ~config_out[1];
assign end_transition = ~config_out[0] & config_out[1];
assign reset_engine = start_transition | loop_again | end_transition;
assign run = config_out[1];
l2t_mb0_ctl_msff_ctl_macro__width_1 loop_again_reg (
.scan_in(loop_again_reg_scanin),
.scan_out(loop_again_reg_scanout),
.dout ( stop_engine_l_q ),
assign loop_again=mb_user_loop_mode ? stop_engine_l & ~stop_engine_l_q: 1'b0;
// /////////////////////////////////////////////////////////////////////////////
// MBIST Control Register
// /////////////////////////////////////////////////////////////////////////////
// /////////////////////////////////////////////////////////////////////////////
// ^(W0);^(R0W1);^(R1W0);v(R0W1);v(R1W0);v(R0);^(W1W0*R1R0W0);^(W1);v(W0W1*R0R1W1);
// /////////////////////////////////////////////////////////////////////////////
// /////////////////////////////////////////////////////////////////////////////
// - ctest 0: match camdata 0
// - cam data 0 ^(W0C0RxW1);
// this requires (cseq0, cseq1, cseq2, cseq3)
// - ctest 1: match camdata 1
// - camdata 1 ^(W1C1RxW0);
// this requires (cseq0, cseq1, cseq2, cseq3)
// - ctest 2: walking1 mismatch
// cseq1: camdata (valid bit test)
// cseq2: camdata (valid bit test)
l2t_mb0_ctl_msff_ctl_macro__width_19 cam_cntl_reg (
.scan_in(cam_cntl_reg_scanin),
.scan_out(cam_cntl_reg_scanout),
l2t_mb0_ctl_msff_ctl_macro__width_1 cam_shift_reg (
.scan_in(cam_shift_reg_scanin),
.scan_out(cam_shift_reg_scanout),
assign cam_msb = start_in & cam_out[18]; //
assign cam_array_sel[1:0] = mb_user_cam_mode ? 2'b11:
cam_out[17:16]; // 2 bits
assign cam_panel_sel[1:0] = cam_out[15:14];
// assign ctest[1:0] = mb_user_cam_mode ? user_cam_test_sel[1:0] :
assign ctest[1:0] = mb_user_cam_mode ? 2'b11 :
assign cam_cseq[1:0] = sel_cseq_pass ? 2'b11 : cam_out[11:10];
// assign cam_addr[7:0] = (ctest2_out & cseq2_out) ? cam_out[9:2]:
// (ctest3_out & cseq2_out) ? cam_out[9:2]:
// (cam_walk1 & cseq3_out) ? {4'b1111,cam_out[5:2]}:
assign cam_addr[7:0] = (ctest2 | ctest3) & cseq1 ? {1'b1, cam_out[8:2]}:
// assign cam_crw[1:0] = (cseq2_out) ? 2'b11:
// cam_out[1:0]; // read write control
assign cam_crw[1:0] = sel_crw_pass ? 2'b11:
cam_out[1:0]; // read write control
assign crw[1:0] = cam_out[1:0];
assign sel_cseq_pass = (ctest2 & cseq1) |
assign sel_crw_pass = ((cseq0 | cseq2 | ((ctest2 | ctest3) & cseq1)) & cambist);
// assign ctest2_out=cam_out[13:12]==2'b10;
// assign ctest3_out=cam_out[13:12]==2'b11;
assign ctest0 = ctest_sel[1:0]==2'b00 & cambist;
assign ctest1 = ctest_sel[1:0]==2'b01 & cambist;
assign ctest2 = ctest_sel[1:0]==2'b10 & cambist;
assign ctest3 = ctest_sel[1:0]==2'b11 & cambist;
assign cseq0 = ~( cseq[1] | cseq[0]);
assign cseq1 = ~( cseq[1] | ~cseq[0]);
assign cseq2 = ~(~cseq[1] | cseq[0]);
assign cseq3 = ~(~cseq[1] | ~cseq[0]);
assign crw0 = ~( crw[1] | crw[0]);
assign crw1 = ~( crw[1] | ~crw[0]);
assign crw2 = ~(~crw[1] | crw[0]);
assign crw3 = ~(~crw[1] | ~crw[0]);
// use lookup_wdata for write data and cam data
// bit 15 valid, bit 14 parity
assign lookup_wdata[15:0] = (ctest0 & (cseq1 | cseq3) & (crw0 | crw1 | crw2)) |
(ctest1 & (cseq0 | cseq2) & crw0) |
(ctest1 & (cseq1 | cseq3) & crw3) |
(ctest2 & cseq0) ? 16'hBFFF:
(ctest3 & cseq0 ) ? 16'h8000:
(ctest3 & cseq2 ) ? 16'h0000:
(ctest3 & cam_zero) ? 16'h8001:
(ctest3 & cam_shift) ? {2'b10,mb0_l2t_lookup_wdata[12:0],1'b0}:
(ctest2 & cam_zero) ? 16'hBFFE:
(ctest2 & cam_shift) ? {2'b10,mb0_l2t_lookup_wdata[12:0],1'b1}:
assign l2_mask[7:0] = (ctest0 & cseq1 ) |
(ctest1 & cseq1 ) ? 8'hFF:
// assign cam_wr_en = (ctest0 & cseq2) ? crw3 :
// (ctest0 & cseq3) ? (crw0 | crw2) :
// (ctest1 & cseq2) ? crw3 :
// (ctest1 & cseq3) ? (crw0 | crw2) :
// (ctest2 & cseq2) ? crw3 :
// (ctest3 & cseq2) ? crw3 :
assign cam_wr_en = ( ctest0 & (cseq0 | cseq2) & crw0) |
( ctest0 & (cseq1 | cseq3) & (crw0 | crw3)) |
( ctest1 & (cseq0 | cseq2) & crw0) |
( ctest1 & (cseq1 | cseq3) & (crw0 | crw3)) |
( ctest2 & cseq0 & crw0) |
( ctest3 & cseq0 & crw0) |
// assign cam_en = (ctest0 & cseq3) ? crw1 :
// (ctest1 & cseq3) ? crw1 :
// (ctest2 & cseq3) ? cam_shift :
// (ctest3 & cseq3) ? cam_shift :
assign cam_en = (ctest0 & (cseq1 | cseq3) & (crw1 | crw2)) |
(ctest1 & (cseq1 | cseq3) & (crw1 | crw2)) |
(cam_shift | cam_zero); // valid bit test
assign cam_walk1 = (ctest2 | ctest3) & cseq1;
// assign end_shift = cam_walk1 & (tlb_addr[6] & tlb_addr[5] & ~tlb_addr[4] & tlb_addr[3] & ~tlb_addr[2] & ~tlb_addr[1] & ~tlb_addr[0]);
assign cam_zero = ~|cam_addr[6:0] & cam_walk1 & cseq1;
assign end_shift = cambist ? (cam_walk1 & (cam_addr[7:0]==8'b10001101)):
assign cam_shift_val = ~cambist | end_shift ? 1'b0 :
cam_zero & cseq1 ? 1'b1 :
assign qual_cam[18:0]={cam_msb,
assign cam_in[18:0]=reset_engine ? 19'b0: // set zero
~run3 | ~cambist ? qual_cam[18:0]: // save value
qual_cam[18:0]+19'h1; // increment
assign mb_icrow0_cam_hit= ic_cam_fail[0] & icrow_sel_d3[0];
assign mb_icrow1_cam_hit= ic_cam_fail[1] & icrow_sel_d3[1];
assign mb_dcrow0_cam_hit= dc_cam_fail[0] & dcrow_sel_d3[0];
assign mb_dcrow1_cam_hit= dc_cam_fail[1] & dcrow_sel_d3[1];
l2t_mb0_ctl_msff_ctl_macro__width_4 cam_hit_reg (
.scan_in(cam_hit_reg_scanin),
.scan_out(cam_hit_reg_scanout),
.din ( {mb_icrow0_cam_hit, mb_icrow1_cam_hit, mb_dcrow0_cam_hit, mb_dcrow1_cam_hit} ),
.dout ( {icrow0_cam_hit, icrow1_cam_hit, dcrow0_cam_hit, dcrow1_cam_hit} ),
l2t_mb0_ctl_msff_ctl_macro__width_5 exp_cam_hit_delay_reg (
.scan_in(exp_cam_hit_delay_reg_scanin),
.scan_out(exp_cam_hit_delay_reg_scanout),
.din ( {cam_hit_cmp, cam_hit_cmp_d1,cam_hit_cmp_d2,cam_hit_cmp_d3, cam_hit_cmp_d4}),
.dout ( {cam_hit_cmp_d1,cam_hit_cmp_d2,cam_hit_cmp_d3,cam_hit_cmp_d4, cam_hit_cmp_d5}),
l2t_mb0_ctl_msff_ctl_macro__width_5 exp_cam_exp_delay_reg (
.scan_in(exp_cam_exp_delay_reg_scanin),
.scan_out(exp_cam_exp_delay_reg_scanout),
.din ( {cam_hit_exp, cam_hit_exp_d1,cam_hit_exp_d2,cam_hit_exp_d3, cam_hit_exp_d4}),
.dout ( {cam_hit_exp_d1,cam_hit_exp_d2,cam_hit_exp_d3,cam_hit_exp_d4, cam_hit_exp_d5}),
l2t_mb0_ctl_msff_ctl_macro__width_10 cam_sel_icrow_delay_reg (
.scan_in(cam_sel_icrow_delay_reg_scanin),
.scan_out(cam_sel_icrow_delay_reg_scanout),
.din ( {mb0_l2t_icrow_row_en[1:0],icrow_sel_d1[1:0],icrow_sel_d2[1:0],icrow_sel_d3[1:0],icrow_sel_d4[1:0]}),
.dout ( {icrow_sel_d1[1:0], icrow_sel_d2[1:0],icrow_sel_d3[1:0],icrow_sel_d4[1:0],icrow_sel_d5[1:0]}),
l2t_mb0_ctl_msff_ctl_macro__width_10 cam_sel_dcrow_delay_reg (
.scan_in(cam_sel_dcrow_delay_reg_scanin),
.scan_out(cam_sel_dcrow_delay_reg_scanout),
.din ( {mb0_l2t_dcrow_row_en[1:0],dcrow_sel_d1[1:0],dcrow_sel_d2[1:0],dcrow_sel_d3[1:0],dcrow_sel_d4[1:0]}),
.dout ( {dcrow_sel_d1[1:0], dcrow_sel_d2[1:0],dcrow_sel_d3[1:0],dcrow_sel_d4[1:0],dcrow_sel_d5[1:0]}),
assign cam_hit_cmp =cam_en;
assign cam_hit_exp =(ctest0 & cseq1 & crw1) |
(ctest0 & cseq3 & (crw1 | crw2)) |
(ctest1 & cseq1 & crw1) |
(ctest1 & cseq3 & (crw1 | crw2)) ;
assign icrow0_cam_pass = (~cam_hit_cmp_d5) | (cam_hit_cmp_d5 & (cam_hit_exp_d5 == icrow0_cam_hit));
assign icrow1_cam_pass = (~cam_hit_cmp_d5) | (cam_hit_cmp_d5 & (cam_hit_exp_d5 == icrow1_cam_hit));
assign dcrow0_cam_pass = (~cam_hit_cmp_d5) | (cam_hit_cmp_d5 & (cam_hit_exp_d5 == dcrow0_cam_hit));
assign dcrow1_cam_pass = (~cam_hit_cmp_d5) | (cam_hit_cmp_d5 & (cam_hit_exp_d5 == dcrow1_cam_hit));
assign icrow0_cam_fail = ~icrow0_cam_pass & icrow_sel_d5[0];
assign icrow1_cam_fail = ~icrow1_cam_pass & icrow_sel_d5[1];
assign dcrow0_cam_fail = ~dcrow0_cam_pass & dcrow_sel_d5[0];
assign dcrow1_cam_fail = ~dcrow1_cam_pass & dcrow_sel_d5[1];
assign cambist = ((mb_user_cam_mode | (cntl_msb & ~bisi_mode)) & (valid_fail & ~mb_user_ram_mode));
assign cam_0 = (cam_sel[1:0]==2'b00) & cambist;
assign cam_1 = (cam_sel[1:0]==2'b01) & cambist;
assign cam_2 = (cam_sel[1:0]==2'b10) & cambist;
assign cam_3 = (cam_sel[1:0]==2'b11) & cambist;
// assign icrow_rd = mb_array_0_rd | mb_array_1_rd;
// assign icrow_wr = mb_array_0_wr | mb_array_1_wr;
// assign dcrow_rd = mb_array_2_rd | mb_array_3_rd;
// assign dcrow_wr = mb_array_2_wr | mb_array_3_wr;
assign icrow_lookup_en[0]=cam_en & (cam_0 | cam_1) & cam_panel_en_0;
assign icrow_lookup_en[1]=cam_en & (cam_0 | cam_1) & cam_panel_en_1;
assign icrow_lookup_en[2]=cam_en & (cam_0 | cam_1) & cam_panel_en_2;
assign icrow_lookup_en[3]=cam_en & (cam_0 | cam_1) & cam_panel_en_3;
assign dcrow_lookup_en[0]=cam_en & (cam_2 | cam_3) & cam_panel_en_0;
assign dcrow_lookup_en[1]=cam_en & (cam_2 | cam_3) & cam_panel_en_1;
assign dcrow_lookup_en[2]=cam_en & (cam_2 | cam_3) & cam_panel_en_2;
assign dcrow_lookup_en[3]=cam_en & (cam_2 | cam_3) & cam_panel_en_3;
assign icrow_row_en[0]=array_0 | cam_0;
assign icrow_row_en[1]=array_1 | cam_1;
assign dcrow_row_en[0]=array_2 | cam_2;
assign dcrow_row_en[1]=array_3 | cam_3;
assign panel_en_0 = cmp_0 & ~cambist;
assign panel_en_1 = cmp_1 & ~cambist;
assign panel_en_2 = cmp_2 & ~cambist;
assign panel_en_3 = cmp_3 & ~cambist;
assign cam_panel_en_0 = ~( cam_panel_sel[1] | cam_panel_sel[0]) & cambist;
assign cam_panel_en_1 = ~( cam_panel_sel[1] | ~cam_panel_sel[0]) & cambist;
assign cam_panel_en_2 = ~(~cam_panel_sel[1] | cam_panel_sel[0]) & cambist;
assign cam_panel_en_3 = ~(~cam_panel_sel[1] | ~cam_panel_sel[0]) & cambist;
assign icrow_arrays = array_0 | array_1 | cam_0 | cam_1;
assign dcrow_arrays = array_2 | array_3 | cam_2 | cam_3;
assign icrow_panel_en[0] = icrow_arrays & (panel_en_0 | cam_panel_en_0);
assign icrow_panel_en[1] = icrow_arrays & (panel_en_1 | cam_panel_en_1);
assign icrow_panel_en[2] = icrow_arrays & (panel_en_2 | cam_panel_en_2);
assign icrow_panel_en[3] = icrow_arrays & (panel_en_3 | cam_panel_en_3);
assign dcrow_panel_en[0] = dcrow_arrays & (panel_en_0 | cam_panel_en_0);
assign dcrow_panel_en[1] = dcrow_arrays & (panel_en_1 | cam_panel_en_1);
assign dcrow_panel_en[2] = dcrow_arrays & (panel_en_2 | cam_panel_en_2);
assign dcrow_panel_en[3] = dcrow_arrays & (panel_en_3 | cam_panel_en_3);
l2t_mb0_ctl_msff_ctl_macro__width_21 mbist_output_reg (
.scan_in(mbist_output_reg_scanin),
.scan_out(mbist_output_reg_scanout),
mb0_l2t_icrow_lookup_en[3:0],
mb0_l2t_icrow_row_en[1:0],
mb0_l2t_icrow_panel_en[3:0],
mb0_l2t_dcrow_lookup_en[3:0],
mb0_l2t_dcrow_row_en[1:0],
mb0_l2t_dcrow_panel_en[3:0]
assign mb_lookup_wdata[15:0] = cambist ? lookup_wdata[15:0] :
{mem_data[7:0],mem_data[7:0]};
l2t_mb0_ctl_msff_ctl_macro__width_16 mbist_output_data_reg (
.scan_in(mbist_output_data_reg_scanin),
.scan_out(mbist_output_data_reg_scanout),
.din (mb_lookup_wdata[15:0]),
.dout (mb0_l2t_lookup_wdata[15:0]),
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////// ////////////////////////////////////
//////////////////////////////////// ////////////////////////////////////
l2t_mb0_ctl_msff_ctl_macro__width_36 cntl_reg (
.scan_in(cntl_reg_scanin),
.scan_out(cntl_reg_scanout),
.dout ( cntl_out[35:0] ),
assign cntl_in[35:19] = reset_engine ? {17'b000000_0000000000}:
(~run3 | cambist) ? cntl_algr[16:0]:
// assign cntl_in[12:3] = reset_engine ? start_addr[7:0]:
// ~run3 ? cntl_addr[7:0]:
// reset_engine run3 overflow cout_rw output
// ---------------------------------------------------------
assign sel_nextaddr_reset = reset_engine;
assign sel_nextaddr_restart = ~reset_engine & run3 & overflow;
assign sel_nextaddr_incred = ~reset_engine & run3 & ~overflow & cout_rw;
assign sel_nextaddr_same = ~(sel_nextaddr_reset | sel_nextaddr_restart | sel_nextaddr_incred) | cambist;
assign cntl_in[10:3] = ({8{sel_nextaddr_reset}} & start_addr[7:0]) |
({8{sel_nextaddr_restart}} & restart_addr[7:0]) |
({8{sel_nextaddr_incred}} & incred_addr[7:0]) |
({8{sel_nextaddr_same}} & cntl_addr[7:0]);
assign cntl_in[18:11] = 8'b00000000;
assign cntl_in[2:0] = reset_engine ? 3'b000 :
(~run3 | cambist) ? cntl_rw[2:0]:
//////////////////////////////////// ////////////////////////////////////
//////////////////////////////////// ////////////////////////////////////
assign cntl_msb = start_in & cntl_out[ 35]; // done selection
assign cntl_bisi = mb_default_bisi | mb_user_bisi_rw_mode ? cntl_out[34] :
assign cntl_array_sel[3:0] = (user_mode | last_array) ? 4'b1111:
cntl_out[33:30]; // array selection
assign cntl_cmp_sel[3:0] = sel_cmp_pass ? {4'b1111} :
assign cntl_data_sel[1:0] = (bisi_mode | mb_user_data_mode) ? 2'b11 : cntl_out[25:24]; // data selection
assign cntl_addr_mix = (mb_user_addr_mode | bisi_mode) ? 1'b1 : cntl_out[ 23]; // address mix
assign cntl_march_element[3:0] = sel_march_1_pass ? 4'b1111:
cntl_out[22:19]; // march element
assign addr_mix = (bisi_mode | mb_user_addr_mode) ? 1'b0 :
assign cntl_algr[16:0] = {cntl_msb,
cntl_march_element[3:0]};
assign next_algr[16:0] = cout_addr ? cntl_algr[16:0] + 17'h1 : cntl_algr[16:0]; // mbist control
//////////////////////////////////// ////////////////////////////////////
//////////////////////////////////// ////////////////////////////////////
/////////////////////////
/////////////////////////
assign upaddr = march_0 | march_1 | march_2 | march_6 | march_7 | bisi_mode ;
assign march_element_pre[3:0]=next_algr[3:0];
assign march_pre_0 = march_element_pre[3:0]==4'h0;
assign march_pre_1 = march_element_pre[3:0]==4'h1;
assign march_pre_2 = march_element_pre[3:0]==4'h2;
assign march_pre_6 = march_element_pre[3:0]==4'h6;
assign march_pre_7 = march_element_pre[3:0]==4'h7;
assign upaddr_pre = march_pre_0 | march_pre_1 | march_pre_2 | march_pre_6 | march_pre_7;
assign incr_addr[7:0] = mb_user_addr_mode ? user_incr_addr[7:0] : 8'b00000001;
assign start_addr[7:0] = mb_user_addr_mode ? user_start_addr[7:0] : 8'b00000000;
// assign next_addr_out[8:0] = cout_rw ? cntl_addr[8:0] + incr_addr[8:0] : cntl_addr[8:0]; // next address
assign incred_addr[7:0] = cntl_addr[7:0] + incr_addr[7:0];
assign overflow = upaddr ? ( cntl_addr[7:0] == stop_addr[7:0]) & (cntl_rw[2:0]==3'b111):
(~cntl_addr[7:0] == start_addr[7:0]) & (cntl_rw[2:0]==3'b111);
// assign next_addr[7:0]= overflow ? restart_addr[7:0] : next_addr_out[7:0];
assign restart_addr[7:0] = upaddr_pre ? start_addr[7:0] : ~stop_addr[7:0];
assign cout_addr = overflow;
//////////////////////////////////// ////////////////////////////////////
//////////////////////////////////// ////////////////////////////////////
assign cntl_rw[2:0] = sel_rw_pass ? 3'b111:
cntl_out[ 2: 0]; // read write control
assign next_rw[2:0] = cntl_rw[2:0]+3'b001 ;
assign cout_rw = &cntl_rw[2:0]; // carry over for rw
//////////////////////////////////// ////////////////////////////////////
//////////////////////////////////// ////////////////////////////////////
assign one_cycle_march = march_0 | march_5 | march_7;
assign five_cycle_march = march_6 | march_8;
assign two_cycle_march = ~(one_cycle_march | five_cycle_march);
/////////////////////////
/////////////////////////
assign mem_wr_pbi = run3 & (
((march_1 | march_2 | march_3 | march_4 ) & rw_1) |
(march_6 & (rw_0 | rw_1 | rw_4)) |
(march_8 & (rw_0 | rw_1 | rw_4))
assign mem_wr = bisi_wr_mode ? 1'b1 :
/////////////////////////
/////////////////////////
assign mem_rd_pbi = run3 & ~mem_wr;
assign mem_rd= bisi_rd_mode ? 1'b1 : mem_rd_pbi;
assign cntl_addr[7:0] = cntl_out[10:3];
assign adj_addr = (five_cycle_march & (rw_1 | rw_3)) ? {cntl_addr[7:4],~cntl_addr[3],cntl_addr[2:0]}:
assign mem_addr1[7:0] = upaddr ? adj_addr[7:0]: ~adj_addr[7:0];
assign true_data_l = bisi_mode |
(march_6 & (rw_1 | rw_3 | rw_4)) |
(march_8 & (rw_0 | rw_2));
assign true_data=~true_data_l;
assign data_pat_sel[7:0] = (mb_user_data_mode & bisi_mode) ? ~user_data[7:0]:
(mb_user_data_mode) ? user_data[7:0]:
(cntl_data_sel[1:0] == 2'h0) ? 8'hAA:
(cntl_data_sel[1:0] == 2'h1) ? 8'h99:
(cntl_data_sel[1:0] == 2'h2) ? 8'hCC:
assign mem_data[7:0] = true_data ? data_pat_sel[7:0] : ~data_pat_sel[7:0];
//////////////////////////////////// ////////////////////////////////////
//////////////////////////////////// ////////////////////////////////////
assign stop_addr[7:0] = mb_user_addr_mode ? user_stop_addr[7:0] :
array_0 ? 8'b00111111: // icrow0
array_1 ? 8'b00111111: // icrow1
array_2 ? 8'b00111111: // dcrow0
array_3 ? 8'b00111111: // dcrow1
array_4 ? 8'b00001111: // oqarray
//////////////////////////////////// ////////////////////////////////////
//////////////////////////////////// ////////////////////////////////////
assign mem_addr[7:0] = (addr_mix & (array_0 | array_1 | array_2 | array_3))
? {mem_addr1[7:6],mem_addr1[0],mem_addr1[5:1]} : // done
(addr_mix & array_4) ? {mem_addr1[7:4],mem_addr1[0],mem_addr1[3:1]} : // done
//////////////////////////////////// ////////////////////////////////////
//////////////////////////////////// ////////////////////////////////////
assign array_0 = array_sel[3:0]==4'h0 & ~cambist;
assign array_1 = array_sel[3:0]==4'h1 & ~cambist;
assign array_2 = array_sel[3:0]==4'h2 & ~cambist;
assign array_3 = array_sel[3:0]==4'h3 & ~cambist;
assign array_4 = array_sel[3:0]==4'h4 & ~cambist;
assign last_array = array_4;
assign cmp_0 = cmp_sel[3:0]==4'b0000;
assign cmp_1 = cmp_sel[3:0]==4'b0001;
assign cmp_2 = cmp_sel[3:0]==4'b0010;
assign cmp_3 = cmp_sel[3:0]==4'b0011;
// assign cmp_4 = cmp_sel[3:0]==4'b0100;
// assign cmp_5 = cmp_sel[3:0]==4'b0101;
// assign cmp_6 = cmp_sel[3:0]==4'b0110;
// assign cmp_7 = cmp_sel[3:0]==4'b0111;
// assign cmp_15 = cmp_sel[3:0]==4'b1111;
assign march_0 = (march_element[3:0]==4'h0);
assign march_1 = (march_element[3:0]==4'h1);
assign march_2 = (march_element[3:0]==4'h2);
assign march_3 = (march_element[3:0]==4'h3);
assign march_4 = (march_element[3:0]==4'h4);
assign march_5 = (march_element[3:0]==4'h5);
assign march_6 = (march_element[3:0]==4'h6);
assign march_7 = (march_element[3:0]==4'h7);
assign march_8 = (march_element[3:0]==4'h8);
assign rw_0 = (rw[2:0]==3'b000);
assign rw_1 = (rw[2:0]==3'b001);
assign rw_2 = (rw[2:0]==3'b010);
assign rw_3 = (rw[2:0]==3'b011);
assign rw_4 = (rw[2:0]==3'b100);
// assign rw_5 = (rw[2:0]==3'b101);
// assign rw_6 = (rw[2:0]==3'b110);
// assign rw_7 = (rw[2:0]==3'b111);
//////////////////////////////////// ////////////////////////////////////
//////////////////////////////////// ////////////////////////////////////
assign cseq_cntl_out[1:0]=cam_out[11:10];
l2t_mb0_ctl_msff_ctl_macro__width_2 cseq_reg (
.scan_in(cseq_reg_scanin),
.scan_out(cseq_reg_scanout),
assign cseq[1:0]=(&cseq_cntl_out[1:0] & ~(ctest0 | ctest1)) ? cseq_out[1:0] :
assign cam_sel_cntl_out[1:0]=cam_out[17:16];
assign cam_sel[1:0]= user_mode ? user_cam_sel[1:0] :
assign ctest_sel_cntl_out[1:0]=cam_out[13:12];
l2t_mb0_ctl_msff_ctl_macro__width_2 ctest_sel_reg (
.scan_in(ctest_sel_reg_scanin),
.scan_out(ctest_sel_reg_scanout),
.dout ( ctest_sel_out[1:0] ),
assign ctest_sel[1:0]=(&ctest_sel_cntl_out[1:0] & ~(ctest[1:0]==2'b11)) ? ctest_sel_out[1:0] :
mb_user_cam_mode ? user_cam_test_sel[1:0] :
assign array_sel_cntl_out[3:0]=cntl_out[33:30];
l2t_mb0_ctl_msff_ctl_macro__width_4 array_sel_reg (
.scan_in(array_sel_reg_scanin),
.scan_out(array_sel_reg_scanout),
.dout ( array_sel_out[3:0] ),
assign array_sel[3:0]=(&array_sel_cntl_out[3:0]) ? array_sel_out[3:0] :
user_mode ? user_array_sel[3:0] :
assign cmp_sel_cntl_out[3:0] = cntl_out[29:26];
l2t_mb0_ctl_msff_ctl_macro__width_4 cmp_sel_reg (
.scan_in(cmp_sel_reg_scanin),
.scan_out(cmp_sel_reg_scanout),
.dout ( cmp_sel_out[3:0] ),
assign cmp_sel[3:0]= (&cmp_sel_cntl_out[3:0] & ~array_4) ? cmp_sel_out[3:0] :
mb_user_cmpsel_hold ? user_cmpsel[3:0] :
assign march_element_cntl_out[3:0]=cntl_out[22:19];
l2t_mb0_ctl_msff_ctl_macro__width_4 marche_element_reg (
.scan_in(marche_element_reg_scanin),
.scan_out(marche_element_reg_scanout),
.din ( march_element[3:0] ),
.dout ( march_element_out ),
assign march_element[3:0]=(&march_element_cntl_out[3:0]) ? march_element_out[3:0] :
march_element_cntl_out[3:0];
assign rw[2:0]=cntl_out[2:0];
//////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////
assign sel_march_1_pass = bisi_mode | (ten_n_mode & march_5) | march_8 ;
assign bisi_wr_mode = mb_default_bisi | mb_user_bisi_rw_mode ? ~cntl_bisi & run3 :
mb_user_bisi_wr_mode & run3;
assign bisi_rd_mode =mb_default_bisi | mb_user_bisi_rw_mode ? cntl_bisi & run3 :
mb_user_bisi_rd_mode & run3;
assign sel_cmp_pass= (mb_user_cmpsel_hold ) |
assign sel_rw_1_pass = bisi_mode | one_cycle_march ;
assign sel_rw_2_pass = two_cycle_march;
assign sel_rw_5_pass = five_cycle_march;
assign sel_rw_pass = (run3 & sel_rw_1_pass & rw_0) |
(run3 & sel_rw_2_pass & rw_1) |
(run3 & sel_rw_5_pass & rw_4) ;
//////////////////////////////////// ////////////////////////////////////
// membist control assignment
//////////////////////////////////// ////////////////////////////////////
assign mb_cmp_sel[0] = cmp_sel[1:0]==2'b00 & array_4;
assign mb_cmp_sel[1] = cmp_sel[1:0]==2'b01 & array_4;
assign mb_cmp_sel[2] = cmp_sel[1:0]==2'b10 & array_4;
assign mb_cmp_sel[3] = cmp_sel[1:0]==2'b11 & array_4;
assign mb_addr[7:0]= cambist ? cam_addr[7:0] : mem_addr[7:0];
assign mb_write_data[7:0] = mem_data[7:0];
// only one array read signal should be active
assign mb_array_0_rd = array_0 & mem_rd;
assign mb_array_1_rd = array_1 & mem_rd;
assign mb_array_2_rd = array_2 & mem_rd;
assign mb_array_3_rd = array_3 & mem_rd;
assign mb_array_4_rd = array_4 & mem_rd;
assign mb_array_0_wr = (array_0 & mem_wr & run) | (cam_0 & cam_wr_en & run);
assign mb_array_1_wr = (array_1 & mem_wr & run) | (cam_1 & cam_wr_en & run);
assign mb_array_2_wr = (array_2 & mem_wr & run) | (cam_2 & cam_wr_en & run);
assign mb_array_3_wr = (array_3 & mem_wr & run) | (cam_3 & cam_wr_en & run);
assign mb_array_4_wr = array_4 & mem_wr & run;
assign mb_run = run | ((cntl_msb | cam_msb) & ~&done_delay[2:1]);
//////////////////////////////////// ////////////////////////////////////
//////////////////////////////////// ////////////////////////////////////
l2t_mb0_ctl_msff_ctl_macro__width_1 msb_latch (
.scan_in(msb_latch_scanin),
.scan_out(msb_latch_scanout),
assign msb_in= (~start_in ) | (mb_user_loop_mode & mb_done) ? 1'b0 :
(cntl_msb | cam_msb) ? 1'b1 :
assign stop_engine_l = ~start_in ? 1'b0 :
mb_user_cam_mode ? cam_msb :
mb_user_loop_mode ? cntl_msb :
(mb_user_ram_mode | bisi_mode) ? cntl_msb :
assign mb_done= ~start_in ? 1'b0 :
bisi_mode | mb_user_loop_mode | mb_user_ram_mode ? msb_out & (done_delay[4:0]==5'b11110):
cam_msb & (done_delay[4:0]==5'b11110) ;
assign run3 = &done_delay[4:1] & ~stop_engine_l & start_in;
l2t_mb0_ctl_msff_ctl_macro__width_1 run3_transition_reg (
.scan_in(run3_transition_reg_scanin),
.scan_out(run3_transition_reg_scanout),
assign run3_transition = run3 & ~run3_out;
l2t_mb0_ctl_msff_ctl_macro__width_5 done_delay_reg (
.scan_in(done_delay_reg_scanin),
.scan_out(done_delay_reg_scanout),
.din ( done_delay_in[4:0] ),
.dout ( done_delay[4:0] ),
assign done_delay_in[4:0] = run3 ? 5'b11111 :
(run & ~run3) ? done_delay[4:0] + 5'b00001 :
//////////////////////////////////// ////////////////////////////////////
//////////////////////////////////// ////////////////////////////////////
assign mb_ic0_rw_fail = (array_0 & mb_ic_rw_fail);
assign mb_ic1_rw_fail = (array_1 & mb_ic_rw_fail);
assign mb_dc0_rw_fail = (array_2 & mb_dc_rw_fail);
assign mb_dc1_rw_fail = (array_3 & mb_dc_rw_fail);
assign mb_oqarray_rw_fail = ~oqarray_rw_fail;
assign ic0_fail_d = run3_transition ? 1'b0 : mb_ic0_rw_fail | ic0_fail_sticky;
assign ic1_fail_d = run3_transition ? 1'b0 : mb_ic1_rw_fail | ic1_fail_sticky;
assign dc0_fail_d = run3_transition ? 1'b0 : mb_dc0_rw_fail | dc0_fail_sticky;
assign dc1_fail_d = run3_transition ? 1'b0 : mb_dc1_rw_fail | dc1_fail_sticky;
assign oqarray_fail_d = run3_transition ? 1'b0 : mb_oqarray_rw_fail | oqarray_fail_sticky;
assign icrow0_cam_fail_d = run3_transition ? 1'b0 : icrow0_cam_fail | icrow0_cam_fail_sticky;
assign icrow1_cam_fail_d = run3_transition ? 1'b0 : icrow1_cam_fail | icrow1_cam_fail_sticky;
assign dcrow0_cam_fail_d = run3_transition ? 1'b0 : dcrow0_cam_fail | dcrow0_cam_fail_sticky;
assign dcrow1_cam_fail_d = run3_transition ? 1'b0 : dcrow1_cam_fail | dcrow1_cam_fail_sticky;
l2t_mb0_ctl_msff_ctl_macro__width_9 mbist_fail_input_reg (
.scan_in(mbist_fail_input_reg_scanin),
.scan_out(mbist_fail_input_reg_scanout),
assign mbist_fail_sticky = ic0_fail_sticky |
assign mbist_fail_array = mb_ic0_rw_fail |
assign valid_fail=run3 | (stop_engine_l & ~mb_done);
assign mb_fail = mb_done ? mbist_fail_sticky : mbist_fail_array & valid_fail;
//////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////
l2t_mb0_ctl_msff_ctl_macro__width_1 out_mb_tcu_done_reg (
.scan_in(out_mb_tcu_done_reg_scanin),
.scan_out(out_mb_tcu_done_reg_scanout),
l2t_mb0_ctl_msff_ctl_macro__width_8 inv_mask_reg (
.scan_in(inv_mask_reg_scanin),
.scan_out(inv_mask_reg_scanout),
.dout ( mb0_l2t_mask[7:0] ),
l2t_mb0_ctl_msff_ctl_macro__width_1 out_mb_tcu_fail_reg (
.scan_in(out_mb_tcu_fail_reg_scanin),
.scan_out(out_mb_tcu_fail_reg_scanout),
l2t_mb0_ctl_msff_ctl_macro__width_4 out_cmp_sel_reg (
.scan_in(out_cmp_sel_reg_scanin),
.scan_out(out_cmp_sel_reg_scanout),
// thes are all the output flops to arrays
// for the following signals:
l2t_mb0_ctl_msff_ctl_macro__width_1 out_run_mb_arrays_reg (
.scan_in(out_run_mb_arrays_reg_scanin),
.scan_out(out_run_mb_arrays_reg_scanout),
l2t_mb0_ctl_msff_ctl_macro__width_8 out_data_mb_arrays_reg (
.scan_in(out_data_mb_arrays_reg_scanin),
.scan_out(out_data_mb_arrays_reg_scanout),
.din ( mb_write_data[7:0]),
.dout ( mb_write_data_out[7:0]),
l2t_mb0_ctl_msff_ctl_macro__width_8 out_addr_mb_arrays_reg (
.scan_in(out_addr_mb_arrays_reg_scanin),
.scan_out(out_addr_mb_arrays_reg_scanout),
.dout ( mb_addr_out[7:0]),
l2t_mb0_ctl_msff_ctl_macro__width_5 out_wr_mb_arrays_reg (
.scan_in(out_wr_mb_arrays_reg_scanin),
.scan_out(out_wr_mb_arrays_reg_scanout),
l2t_mb0_ctl_msff_ctl_macro__width_5 out_rd_mb_arrays_reg (
.scan_in(out_rd_mb_arrays_reg_scanin),
.scan_out(out_rd_mb_arrays_reg_scanout),
// port name re-assignment
assign mb0_l2t_run =mb_run_out;
assign mb0_l2t_mbist_write_data[7:0] =mb_write_data_out[7:0];
assign mb0_l2t_addr[5:0] =mb_addr_out[5:0];
assign mb0_l2t_cmpsel[3:0] =mb_cmpsel_out[3:0];
assign mb0_l2t_fail =mb_fail_out;
assign mb0_l2t_done =mb_done_out;
assign mb0_l2t_icrow_wr_en =mb_array_0_wr_out | mb_array_1_wr_out;
assign mb0_l2t_dcrow_wr_en =mb_array_2_wr_out | mb_array_3_wr_out;
assign mb0_l2t_oqarray_wr_en =mb_array_4_wr_out;
assign mb0_l2t_icrow_rd_en =mb_array_0_rd_out | mb_array_1_rd_out;
assign mb0_l2t_dcrow_rd_en =mb_array_2_rd_out | mb_array_3_rd_out;
assign mb0_l2t_oqarray_rd_en =mb_array_4_rd_out;
l2t_mb0_ctl_spare_ctl_macro__num_2 spares (
.scan_out(spares_scanout),
supply0 vss; // <- port for ground
supply1 vdd; // <- port for power
// /////////////////////////////////////////////////////////////////////////////
assign array_usr_reg_scanin = scan_in ;
assign user_addr_mode_reg_scanin = array_usr_reg_scanout ;
assign user_start_addr_reg_scanin = user_addr_mode_reg_scanout;
assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout;
assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout;
assign user_data_mode_reg_scanin = user_incr_addr_reg_scanout;
assign user_data_reg_scanin = user_data_mode_reg_scanout;
assign user_cmpsel_hold_reg_scanin = user_data_reg_scanout ;
assign user_cmpsel_reg_scanin = user_cmpsel_hold_reg_scanout;
assign user_loop_mode_reg_scanin = user_cmpsel_reg_scanout ;
assign ten_n_mode_reg_scanin = user_loop_mode_reg_scanout;
assign user_cam_mode_reg_scanin = ten_n_mode_reg_scanout ;
assign user_cam_select_reg_scanin = user_cam_mode_reg_scanout;
assign user_cam_test_select_reg_scanin = user_cam_select_reg_scanout;
assign user_bisi_wr_mode_reg_scanin = user_cam_test_select_reg_scanout;
assign user_bisi_rd_mode_reg_scanin = user_bisi_wr_mode_reg_scanout;
assign input_signals_reg_scanin = user_bisi_rd_mode_reg_scanout;
assign mb_enable_reg_scanin = input_signals_reg_scanout;
assign config_reg_scanin = mb_enable_reg_scanout ;
assign loop_again_reg_scanin = config_reg_scanout ;
assign cam_cntl_reg_scanin = loop_again_reg_scanout ;
assign cam_shift_reg_scanin = cam_cntl_reg_scanout ;
assign cam_hit_reg_scanin = cam_shift_reg_scanout ;
assign exp_cam_hit_delay_reg_scanin = cam_hit_reg_scanout ;
assign exp_cam_exp_delay_reg_scanin = exp_cam_hit_delay_reg_scanout;
assign cam_sel_icrow_delay_reg_scanin = exp_cam_exp_delay_reg_scanout;
assign cam_sel_dcrow_delay_reg_scanin = cam_sel_icrow_delay_reg_scanout;
assign mbist_output_reg_scanin = cam_sel_dcrow_delay_reg_scanout;
assign mbist_output_data_reg_scanin = mbist_output_reg_scanout ;
assign cntl_reg_scanin = mbist_output_data_reg_scanout;
assign cseq_reg_scanin = cntl_reg_scanout ;
assign ctest_sel_reg_scanin = cseq_reg_scanout ;
assign array_sel_reg_scanin = ctest_sel_reg_scanout ;
assign cmp_sel_reg_scanin = array_sel_reg_scanout ;
assign marche_element_reg_scanin = cmp_sel_reg_scanout ;
assign msb_latch_scanin = marche_element_reg_scanout;
assign run3_transition_reg_scanin = msb_latch_scanout ;
assign done_delay_reg_scanin = run3_transition_reg_scanout;
assign mbist_fail_input_reg_scanin = done_delay_reg_scanout ;
assign out_mb_tcu_done_reg_scanin = mbist_fail_input_reg_scanout;
assign inv_mask_reg_scanin = out_mb_tcu_done_reg_scanout;
assign out_mb_tcu_fail_reg_scanin = inv_mask_reg_scanout ;
assign out_cmp_sel_reg_scanin = out_mb_tcu_fail_reg_scanout;
assign out_run_mb_arrays_reg_scanin = out_cmp_sel_reg_scanout ;
assign out_data_mb_arrays_reg_scanin = out_run_mb_arrays_reg_scanout;
assign out_addr_mb_arrays_reg_scanin = out_data_mb_arrays_reg_scanout;
assign out_wr_mb_arrays_reg_scanin = out_addr_mb_arrays_reg_scanout;
assign out_rd_mb_arrays_reg_scanin = out_wr_mb_arrays_reg_scanout;
assign spares_scanin = out_rd_mb_arrays_reg_scanout;
assign scan_out = spares_scanout ;
// /////////////////////////////////////////////////////////////////////////////
// any PARAMS parms go into naming of macro
module l2t_mb0_ctl_l1clkhdr_ctl_macro (
// any PARAMS parms go into naming of macro
module l2t_mb0_ctl_msff_ctl_macro__width_4 (
assign fdin[3:0] = din[3:0];
// any PARAMS parms go into naming of macro
module l2t_mb0_ctl_msff_ctl_macro__width_1 (
assign fdin[0:0] = din[0:0];
// any PARAMS parms go into naming of macro
module l2t_mb0_ctl_msff_ctl_macro__width_8 (
assign fdin[7:0] = din[7:0];
// any PARAMS parms go into naming of macro
module l2t_mb0_ctl_msff_ctl_macro__width_2 (
assign fdin[1:0] = din[1:0];
// any PARAMS parms go into naming of macro
module l2t_mb0_ctl_msff_ctl_macro__width_3 (
assign fdin[2:0] = din[2:0];
// any PARAMS parms go into naming of macro
module l2t_mb0_ctl_msff_ctl_macro__width_19 (
assign fdin[18:0] = din[18:0];
.so({so[17:0],scan_out}),
// any PARAMS parms go into naming of macro
module l2t_mb0_ctl_msff_ctl_macro__width_5 (
assign fdin[4:0] = din[4:0];
// any PARAMS parms go into naming of macro
module l2t_mb0_ctl_msff_ctl_macro__width_10 (
assign fdin[9:0] = din[9:0];
// any PARAMS parms go into naming of macro
module l2t_mb0_ctl_msff_ctl_macro__width_21 (
assign fdin[20:0] = din[20:0];
.so({so[19:0],scan_out}),
// any PARAMS parms go into naming of macro
module l2t_mb0_ctl_msff_ctl_macro__width_16 (
assign fdin[15:0] = din[15:0];
.so({so[14:0],scan_out}),
// any PARAMS parms go into naming of macro
module l2t_mb0_ctl_msff_ctl_macro__width_36 (
assign fdin[35:0] = din[35:0];
.so({so[34:0],scan_out}),
// any PARAMS parms go into naming of macro
module l2t_mb0_ctl_msff_ctl_macro__width_9 (
assign fdin[8:0] = din[8:0];
// Description: Spare gate macro for control blocks
// Param num controls the number of times the macro is added
// flops=0 can be used to use only combination spare logic
module l2t_mb0_ctl_spare_ctl_macro__num_2 (
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
.out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
.out(spare0_nand3_8x_unused));
cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
.out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
.out(spare0_aoi22_4x_unused));
cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
.out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
.out(spare0_oai22_4x_unused));
cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
.out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
.out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
.out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
.out(spare0_nand2_8x_unused));
cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
.out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
.out(spare0_nor2_16x_unused));
cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
.out(spare0_inv_32x_unused));
cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
cl_u1_buf_32x spare1_buf_32x (.in(1'b1),
.out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
.out(spare1_nand3_8x_unused));
cl_u1_inv_8x spare1_inv_8x (.in(1'b1),
.out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
.out(spare1_aoi22_4x_unused));
cl_u1_buf_8x spare1_buf_8x (.in(1'b1),
.out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
.out(spare1_oai22_4x_unused));
cl_u1_inv_16x spare1_inv_16x (.in(1'b1),
.out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
.out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
.out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
.out(spare1_nand2_8x_unused));
cl_u1_buf_16x spare1_buf_16x (.in(1'b1),
.out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
.out(spare1_nor2_16x_unused));
cl_u1_inv_32x spare1_inv_32x (.in(1'b1),
.out(spare1_inv_32x_unused));