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* OpenSPARC T2 Processor File: n2_err_dram_DSC_trap.s
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#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define MAIN_PAGE_HV_ALSO
#define DRAM_ERR_INJ_REG 0x8400000290
#define DRAM_ERR_STAT_REG 0x8400000280
#define L2_ERR_STAT_REG 0xAB00000000
#define L2_ERR_ADDR_REG 0xAC00000000
#define ERROR_ADDR 0x20200000
#define DRAM_CHANNEL_ADDR 0x2000
#define TEST_DATA1 0x1000100081c3e008
#define L2_ES_W1C_VALUE 0xc03ffff800000000
#define DRAM_ES_W1C_VALUE 0xfe00000000000000
#define DRAM_ESR_REG 0x8400000280
#define DRAM_ERR_INJ_REG 0x8400000290
#define DRAM_SCRB_FREQ_REG 0x8400000018
#define DRAM_SCRB_ENB_REG 0x8400000040
.global My_Corrected_ECC_error_trap
! Boot code does not provide TLB translation for IO address space
setx TEST_DATA1, %l0, %g3
setx DRAM_ES_W1C_VALUE, %l0, %g4
setx DRAM_ESR_REG, %l0, %g5
! Clear DRAM Error status register (Bit[63:57] write-1-clear)
stx %g4, [%g5] ! %g5 set to ESR Reg
ldxa [%g0] ASI_LSU_CONTROL, %l0
! Remove the lower 2 bits (I-Cache and D-Cache enables)
stxa %l0, [%g0] ASI_LSU_CONTROL
! Write 1 to clear L2 Error status registers
setx L2_ES_W1C_VALUE, %l0, %l1
! Set up DRAM error injection
mov 0x4, %l1 ! ECC Mask (single bit error)
sllx %l2, DRAM_EI_SSHOT, %l3
or %l1, %l3, %l1 ! Set single shot
sllx %l2, DRAM_EI_ENB, %l3
or %l1, %l3, %l1 ! Enable error injection for the next write
setx DRAM_ERR_INJ_REG, %l0, %l2 ! DRAM error injection
set_L2_Directly_Mapped_Mode:
setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
setx 0x0003000000, %l0, %g2 ! bits [21:18] select way
setx TEST_DATA1, %l2, %l1
setx 0x0002000000, %l0, %g2 ! bits [21:18] select way
ldxa [%g0] ASI_LSU_CONTROL, %l0
stxa %l0, [%g0] ASI_LSU_CONTROL
set_DRAM_scrub_frequency:
setx DRAM_SCRB_FREQ_REG, %l0, %l1
setx DRAM_SCRB_ENB_REG, %l0, %l1
! cmp %g1, 5 ! original number
compute_expected_DRAM_ESR:
! Compute expected value of DRAM error status register
sllx %l6, DRAM_ES_DSC, %l7
! Due to DDR design, a single shot for one clock cycle results in errors for two 16-Byte chunks
! This also implies that a disrupting 0x78 trap will follow a 0x32 precise trap
sllx %l6, DRAM_ES_MEC, %l5
! Not checking syndrome because it varies with environment timing (e.g. different in cmp and ciop)
! Compute expected value of L2 error status register
! Clear DRAM Error status register
! Check if error is corrected
! Check DRAM ES again - should be zero
! Check if a Corrected ECC Trap happened
mov TT_Corrected_ECC, %l0
My_Corrected_ECC_error_trap:
/*******************************************************
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