* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: niu_macros.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* ========== Copyright Header End ============================================
#ifndef ALREADY_INCLUDED_NIU_MACROS_DOT_H
#define ALREADY_INCLUDED_NIU_MACROS_DOT_H
/****************************************************************
* Set up to allow an interrupt on transmit frame completion of
* a marked frame. The registers LD_IM0, LDGIMGN, LDGITMRES,
* SID and TX_ENT_MSK are programmed.
* NIU_TX_LD_IM0_INTR_ON_MARK(
* tx_dma_channel, tmp_reg_1, tmp_reg_2, tmp_reg_3,
* tmp_reg_4, ldg_number, device_number
* tx_dma_channel -> NIU Tx DMA channel # to use, 0 to 15.
* tmp_reg_1/2/3/4 -> temporary registers
* ldg_number -> number of logical device group to use.
* device_number -> device number to send to NCU, NOT logical
* number nor logical group device number.
define(NIU_TX_LD_IM0_INTR_ON_MARK
,`
stxa
%g0
, [$
4]ASI_PRIMARY_LITTLE
setx LDG_NUM_STEP
, $
3, $
4
stxa $
2, [$
4]ASI_PRIMARY_LITTLE
setx LDGIMGN_STEP
, $
3, $
5
stxa $
2, [$
4]ASI_PRIMARY_LITTLE
stxa $
2, [$
4]ASI_PRIMARY_LITTLE
stxa $
3, [$
4]ASI_PRIMARY_LITTLE
stxa
%g0
, [$
4]ASI_PRIMARY_LITTLE
define(NIU_RX_LD_IM0_INTR_ON_MARK,`
stxa %g0, [$4]ASI_PRIMARY_LITTLE
setx LDG_NUM_STEP, $3, $4
stxa $2, [$4]ASI_PRIMARY_LITTLE
setx LDGIMGN_STEP, $3, $5
stxa $2, [$4]ASI_PRIMARY_LITTLE
stxa $2, [$4]ASI_PRIMARY_LITTLE
stxa $3, [$4]ASI_PRIMARY_LITTLE
mulx $5, RX_DMA_CTL_STAT_STEP, $5
setx RX_DMA_ENT_MSK, $3, $4
ldxa [$4]ASI_PRIMARY_LITTLE, $2
stxa $2, [$4]ASI_PRIMARY_LITTLE
setx RX_DMA_CTL_STAT, $3, $4
ldxa [$4]ASI_PRIMARY_LITTLE, $2
stxa $2, [$4]ASI_PRIMARY_LITTLE
ldxa [$4]ASI_PRIMARY_LITTLE, $2
setx 0x000000000000ffff, $3, $5
stxa $2, [$4]ASI_PRIMARY_LITTLE
/****************************************************************
* Set up to allow an interrupt on transmit packet completion
* from the MAC. The register TxMAC Mask, xtxmac_stat_msk, is programmed.
* NIU_TX_MAC_COMPL_INTR (
* mac_port, tmp_reg_2, tmp_reg_3
* mac_port -> 0 = MAC port 0, 1 = MAC port 1
* tmp_reg_2/3 -> temporary registers
define(NIU_TX_MAC_COMPL_INTR
,`
setx xtxmac_stat_msk0_addr
, $
2, $
3
setx xtxmac_stat_msk1_addr
, $
2, $
3
stxa
%g0
, [$
3]ASI_PRIMARY_LITTLE
/****************************************************************
* Set up to allow an interrupt on receive packet completion
* from the MAC. The register RxMAC Mask, xrxmac_stat_msk, is programmed.
* NIU_RX_MAC_COMPL_INTR (
* mac_port, tmp_reg_2, tmp_reg_3
* mac_port -> 0 = MAC port 0, 1 = MAC port 1
* tmp_reg_2/3 -> temporary registers
define(NIU_RX_MAC_COMPL_INTR,`
setx xrxmac_stat_msk0_addr, $2, $3
setx xrxmac_stat_msk1_addr, $2, $3
stxa %g0, [$3]ASI_PRIMARY_LITTLE
/****************************************************************
* Set up to allow an interrupt receive channel configuration logical
* page violation error. The registers LD_IM0, LDGNUM, LDGIMGN, LDGITMRES,
* SID, RXDMA_CFIG1 and RX_DMA_ENT_MSK are programmed.
* NIU_RX_DMA_INTR_ON_CFIGLOGPAGE (
* rx_dma_channel, ldg_number, device_number, tmp_reg_1,
* tmp_reg_2, tmp_reg_3, tmp_reg_4 )
* rx_dma_channel -> NIU Rx DMA channel #, 0 to 15, aka logical device number.
* ldg_number -> number of logical device group to use.
* device_number -> device number to send to NCU, NOT logical
* number nor logical group device number.
* tmp_reg_1/2/3/4 -> 4 temporary registers
define(NIU_RX_DMA_INTR_ON_CFIGLOGPAGE
,`
stxa
%g0
, [$
5]ASI_PRIMARY_LITTLE
setx LDG_NUM_STEP
, $
4, $
6
stxa $
7, [$
5]ASI_PRIMARY_LITTLE
setx LDGIMGN_STEP
, $
4, $
6
stxa $
7, [$
5]ASI_PRIMARY_LITTLE
stxa $
6, [$
5]ASI_PRIMARY_LITTLE
stxa $
7, [$
5]ASI_PRIMARY_LITTLE
setx RX_DMA_ENT_MSK
, $
4, $
5
setx RX_DMA_CTL_STAT_STEP
, $
4, $
6
stxa
%g0
, [$
5]ASI_PRIMARY_LITTLE
/* following endif needs to be at very bottom -- 6/27/05 */