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* OpenSPARC T2 Processor File: isa3_pmu_cpu_ldst.s
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#define MAIN_PAGE_NUCLEUS_ALSO
/************************************************************************
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!# Initialize registers ..
set 0x28094042, %l0 ! count spu load operations to L2
set 0x28114082, %l1 ! count spu store operations to l2
set 0x28214102, %l2 ! count cpu loads to l2
set 0x28414202, %l3 ! count cpu ifetch to l2
set 0x28814402, %l4 ! count cpu stores to l2
set 0x20000000, %l5 ! do not use
set 0x10000000, %l6 ! do not ues
ta T_CHANGE_PRIV ! Should cause Watchdog_reset trap
rd %pic, %g2 ! load the current pic value into %g2
wr %g0, %g0, %pic ! zero out the counter
! before sending branches, update the PCR to be in UT.?
rd %pcr, %g3 ! load the current pcr value into %g3
wr %l2, %g0, %pcr ! count dcache misses
ld [%g3 + 0x0], %g1 !should not be counted as a dmiss
rd %pic, %g2 !check pic value
wr %l4, %g0, %pcr !count stores
rd %pic, %g2 ! load the current pic value into %g2
wr %g0, %g0, %pcr !stop counting
rd %pic, %g2 !check pic value
EXIT_GOOD /* test finish */
/************************************************************************
************************************************************************/
.xword 0xABCDEF0123456789