* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: PCIeLinkDisable.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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* ========== Copyright Header End ============================================
#define ENABLE_PCIE_LINK_TRAINING
#define MAIN_PAGE_HV_ALSO
#include "dmu_peu_regs.h"
#define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) | IO_ACCESS_PA)
#define DMA_DATA_ADDR 0x0000000123457000
#define DMA_DATA_BYP_ADDR1 0xfffc000123457000
#define DMA_DATA_BYP_ADDR2 0xfffc000123457100
#define DMA_DATA_BYP_ADDR3 0xfffc000123457200
#define DMA_DATA_BYP_ADDR4 0xfffc000123457300
/************************************************************
Check if this is the first time thru here
************************************************************/
setx test_entered, %g1, %g2
brnz %g3, After_Warm_Reset
! First time thru, Store a non-zero value there
/************************************************************
************************************************************/
! set bit to remain in Detect.Quiet state
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
orcc %g5, %g4, %g5 ! OR in bit 8 == 1
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_ADDR, %g1, %g3
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3 ! 0x680000
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g4 ! 0x681018
mov 25, %l1 ! loop timeout count
setx 0x0000020000000200, %g1, %g5 ! mask for Link Down Primary & Secondary events
! Wait for Link Down primary or secondary event before doing a Warm Reset
ldx [%g3 + 8], %l3 ! read the PEU Status Reg
ldx [%g4], %l4 ! read the PEU Other Event Status Clear Reg
/************************************************************
************************************************************/
stx %l4, [%g4] ! clear the PEU Other Event Status Clear Reg
#ifdef PCIE_USE_SSYS_RESET
setx RST_SSYS_RESET, %g1, %g5 ! subsystem reset reg
mov RST_SSYS_RESET__DMU_PEU, %g7 ! subsystem reset reg data
stx %g7, [%g5] ! Subsystem Reset
mov 255, %l0 ! loop timeout count
ldx [%g5], %l7 ! check if reset bit has cleared
brz %l7, redo_link_training
ba test_failed ! Subsystem reset should have completed
/************************************************************
Now redo link training...
************************************************************/
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR, %g2, %g3
mov 0x0010, %g5 ! FAST LINK MODE, for simulation.
! clear bit 8, to not remain in Detect.Quiet state
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g3
setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
! wait for the "Link Up" status bit to get set in the PEU
! (this code copied from peu_init.h)
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR, %g1, %g3
stx %l4, [%g3] ! clear any status bits that are set
setx FIRE_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR, %g1, %g4
mov FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR__LUP_P, %l1
ldx [%g3], %l4 ! bit 8 is Link Up primary event
ldx [%g4], %l5 ! bits 48:44 are the LTSSM state
brnz %l0, LinkTrainingLoop2
setx RST_RESET_GEN, %g1, %g5 ! warm reset reg
mov RST_RESET_GEN__WMR_GEN, %g7 ! warm reset reg data
mov 25, %l0 ! loop timeout count
stx %g7, [%g5] ! Warm Reset
ba test_failed ! Warm reset didn't happen
/************************************************************
Do a couple of PIOs and DMAs to verify that its working fine.
************************************************************/
nop ! $EV trig_pc_d(1, @VA(.MAIN.After_Warm_Reset)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR2, "64'h40", 1 )
nop ! $EV trig_pc_d(1, @VA(.MAIN.After_Warm_Reset2)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR3, DMA_DATA_BYP_ADDR4, "64'h40", 1 )
! Do PIOs to IO address space
! load byte - all byte offsets within an octlet
setx IO_RD_ADDR, %g1, %g2
ldub [%g2 + 1*8 + 0], %l0
ldub [%g2 + 2*8 + 1], %l1
ldub [%g2 + 3*8 + 2], %l2
ldub [%g2 + 4*8 + 3], %l3
ldub [%g2 + 5*8 + 4], %l4
ldub [%g2 + 6*8 + 5], %l5
ldub [%g2 + 7*8 + 6], %l6
ldub [%g2 + 8*8 + 7], %l7
/************************************************************************
************************************************************************/
SECTION .PIODATA DATA_VA=IO_RD_ADDR
.xword 0xdeadbeefdeadbeef
.xword 0x1101010101010101
.xword 0x0122010101010101
.xword 0x0101330101010101
.xword 0x0101014401010101
.xword 0x0101010155010101
.xword 0x0101010101660101
.xword 0x0101010101017701
.xword 0x0101010101010188
.xword 0x1122010101010101
.xword 0x0101334401010101
.xword 0x0101010155660101
.xword 0x0101010101017788
.xword 0x1122334401010101
.xword 0x0101010155667788
.xword 0xdeadbeefdeadbeef
/************************************************************************/
SECTION .DMADATA DATA_VA=DMA_DATA_ADDR
init_mem(0x0101010201030104, 256, 8, +, 0, +, 0x0004000400040004)