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// 
// OpenSPARC T2 Processor File: dmu_cmu_ctx_clstreg_array.v
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module dmu_cmu_ctx_clstreg_array (
		clk, 	
		rst_l,
		addr,
		data_in, 
		rw,
		data_out
		);
     
//************************************************
//				PARAMETERS
//************************************************

  parameter WIDTH 	 = 8,
			DEPTH 	 = 8,
			ADDR_WDTH = 3;

//************************************************
//				PORTS
//************************************************

  input clk;                             // input clock
  input rst_l;                           // synopsys sync_set_reset "rst_l"
  
  input [ADDR_WDTH -1 :0] addr;
  input [WIDTH -1 :0] data_in;          // input data
  input rw;                             // syncronous write strobe
  output [WIDTH - 1:0] data_out;        // output data 


// Flop Array    

  reg [WIDTH -1 :0] reg_array[0 :DEPTH -1];    	// The fifo storge arrary

   integer i;
   
   
//************************************************
//				SIGNALS
//************************************************

  
//************************************************
// Zero In checkers
//************************************************ 

// *************** Procedures *************************************/
    // Write access, put the data on the input bus into
    // the location referenced by the write pointer.
    // Write contention is guaranteed not to happen
    // because accessing agents never access same address

always @(posedge clk) begin
	if(~rst_l) begin : reg_reset
		integer j;
		for(j=0; j < DEPTH; j=j+1)
		begin
		  reg_array[j] <= {WIDTH{1'b0}};
		end
	end
      else begin
	 if (rw) begin           //rw = 1 to write
		reg_array[addr] <=  data_in;
	         end
	 else begin
		for(i=0; i < DEPTH; i=i+1)
		  reg_array[i] <= reg_array[i];
	      end
	   end
  end // always @ (posedge clk)   

// ***********************Assignments *****************************/


//***********************************************
// A read returns data referenced by the read pointer
//************************************************

assign data_out = reg_array[addr];
	 
endmodule // dmu_cmu_ctx_clstreg_array