// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_imu_eqs_csr_eq_base_address.v
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module dmu_imu_eqs_csr_eq_base_address 
	(
	clk,
	rst_l,
	eq_base_address_w_ld,
	csrbus_wr_data,
	eq_base_address_csrbus_read_data,
	eq_base_address_address_hw_read
	);

//====================================================================
//     Polarity declarations
//====================================================================
input  clk;  // Clock
input  rst_l;  // Reset signal
input  eq_base_address_w_ld;  // SW load bus
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
output [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH-1:0] eq_base_address_csrbus_read_data;
    // SW read data
output [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_INT_SLC] eq_base_address_address_hw_read;
    // This signal provides the current value of eq_base_address_address.

//====================================================================
//     Type declarations
//====================================================================
wire clk;  // Clock
wire rst_l;  // Reset signal
wire eq_base_address_w_ld;  // SW load bus
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
wire [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH-1:0] eq_base_address_csrbus_read_data;
    // SW read data
wire [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_INT_SLC] eq_base_address_address_hw_read;
    // This signal provides the current value of eq_base_address_address.

//====================================================================
//     Logic     
//====================================================================

// synopsys translate_off
// verilint 123 off
// verilint 498 off
reg omni_ld;
reg [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH-1:0] omni_data;

// vlint flag_unsynthesizable_initial off
initial
  begin
     omni_ld         = 1'b0;
     omni_data       = `FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH'b0;
  end// vlint flag_unsynthesizable_initial on

// verilint 123 on
// verilint 498 on
// synopsys translate_on

//----- Hardware Data Out Mux Assignments
assign eq_base_address_address_hw_read=
           eq_base_address_csrbus_read_data
               [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_SLC];

//====================================================================
//     Instantiation of entries
//====================================================================

//----- Entry 0
dmu_imu_eqs_csr_eq_base_address_entry eq_base_address_0
	(
	// synopsys translate_off
	  .omni_ld	(omni_ld),
	  .omni_data	(omni_data),
	// synopsys translate_on
	.clk	(clk),
	.rst_l	(rst_l),
	.w_ld	(eq_base_address_w_ld),
	.csrbus_wr_data	(csrbus_wr_data),
	.eq_base_address_csrbus_read_data	(eq_base_address_csrbus_read_data)
	);

endmodule // dmu_imu_eqs_csr_eq_base_address