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// 
// OpenSPARC T2 Processor File: dmu_mmu_csr_flts.v
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module dmu_mmu_csr_flts
	(
	clk,
	por_l,
	flts_w_ld,
	csrbus_wr_data,
	flts_csrbus_read_data,
	flts_entry_hw_ld,
	flts_entry_hw_write,
	flts_type_hw_ld,
	flts_type_hw_write,
	flts_id_hw_ld,
	flts_id_hw_write
	);

//====================================================================
//     Polarity declarations
//====================================================================
input  clk;  // Clock
input  por_l;  // Reset signal
input  flts_w_ld;  // SW load bus
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
output [`FIRE_DLC_MMU_CSR_FLTS_WIDTH-1:0] flts_csrbus_read_data;  // SW read
                                                                  // data
input  flts_entry_hw_ld;  // Hardware load enable for flts_entry. When set, <hw
                          // write signal>  will be loaded into flts.
input  [`FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC] flts_entry_hw_write;
    // data bus for hw loading of flts_entry.
input  flts_type_hw_ld;  // Hardware load enable for flts_type. When set, <hw
                         // write signal>  will be loaded into flts.
input  [`FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC] flts_type_hw_write;  // data bus
                                                                  // for hw
                                                                  // loading of
                                                                  // flts_type.
input  flts_id_hw_ld;  // Hardware load enable for flts_id. When set, <hw write
                       // signal>  will be loaded into flts.
input  [`FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC] flts_id_hw_write;  // data bus for hw
                                                              // loading of
                                                              // flts_id.

//====================================================================
//     Type declarations
//====================================================================
wire clk;  // Clock
wire por_l;  // Reset signal
wire flts_w_ld;  // SW load bus
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
wire [`FIRE_DLC_MMU_CSR_FLTS_WIDTH-1:0] flts_csrbus_read_data;  // SW read data
wire flts_entry_hw_ld;  // Hardware load enable for flts_entry. When set, <hw
                        // write signal>  will be loaded into flts.
wire [`FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC] flts_entry_hw_write;  // data bus
                                                                  // for hw
                                                                  // loading of
                                                                  // flts_entry.
wire flts_type_hw_ld;  // Hardware load enable for flts_type. When set, <hw
                       // write signal>  will be loaded into flts.
wire [`FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC] flts_type_hw_write;  // data bus for
                                                                // hw loading of
                                                                // flts_type.
wire flts_id_hw_ld;  // Hardware load enable for flts_id. When set, <hw write
                     // signal>  will be loaded into flts.
wire [`FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC] flts_id_hw_write;  // data bus for hw
                                                            // loading of
                                                            // flts_id.

//====================================================================
//     Logic     
//====================================================================

// synopsys translate_off
// verilint 123 off
// verilint 498 off
reg omni_ld;
reg [`FIRE_DLC_MMU_CSR_FLTS_WIDTH-1:0] omni_data;

// vlint flag_unsynthesizable_initial off
initial
  begin
     omni_ld         = 1'b0;
     omni_data       = `FIRE_DLC_MMU_CSR_FLTS_WIDTH'b0;
  end// vlint flag_unsynthesizable_initial on

// verilint 123 on
// verilint 498 on
// synopsys translate_on

//----- Hardware Data Out Mux Assignments

//====================================================================
//     Instantiation of entries
//====================================================================

//----- Entry 0
dmu_mmu_csr_flts_entry flts_0
	(
	// synopsys translate_off
	  .omni_ld	(omni_ld),
	  .omni_data	(omni_data),
	// synopsys translate_on
	.clk	(clk),
	.por_l	(por_l),
	.w_ld	(flts_w_ld),
	.csrbus_wr_data	(csrbus_wr_data),
	.flts_csrbus_read_data	(flts_csrbus_read_data),
	.flts_entry_hw_ld	(flts_entry_hw_ld),
	.flts_entry_hw_write	(flts_entry_hw_write),
	.flts_type_hw_ld	(flts_type_hw_ld),
	.flts_type_hw_write	(flts_type_hw_write),
	.flts_id_hw_ld	(flts_id_hw_ld),
	.flts_id_hw_write	(flts_id_hw_write)
	);

endmodule // dmu_mmu_csr_flts