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// 
// OpenSPARC T2 Processor File: dmu_mmu_srq.v
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module dmu_mmu_srq 
  (
   clk,				// clock
   rst_l,			// rst_l
   ld,				// load
   ds,				// data select
   di,				// data in
   do				// data out
   );
     
// ----------------------------------------------------------------------------
// Parameters
// ----------------------------------------------------------------------------
  parameter	QD = 4,		// queue depth
		QW = 2;		// queue width

// ----------------------------------------------------------------------------
// Ports
// ----------------------------------------------------------------------------
  input			clk;
  input			rst_l;

  input  [QD-1:0]	ld;
  input  [QD-2:0]	ds;

  input  [QW-1:0]	di;
  output [QW-1:0]	do;

// ----------------------------------------------------------------------------
// Variables
// ----------------------------------------------------------------------------
  wire [QW-1:0] 	do;
  reg  [QW-1:0]		que [0:QD-1];

  integer i;

// ----------------------------------------------------------------------------
// Combinational
// ----------------------------------------------------------------------------
  assign do = que[0];

// ----------------------------------------------------------------------------
// Sequential
// ----------------------------------------------------------------------------
  always @ (posedge clk) 
	if(~rst_l) begin : que_rst
	   integer j;
    for (j = 0; j < QD; j = j + 1) begin
        que[j] <= {QW{1'b0}};
	end
      end
	else begin
    for (i = 0; i < QD-1; i = i + 1) begin
      if (ld[i]) que[i] <= ds[i] ? que[i+1] : di;
    end
    if (ld[QD-1]) que[QD-1] <= di;
  end

endmodule // dmu_mmu_srq