// ========== Copyright Header Begin ========================================== // // OpenSPARC T2 Processor File: mcu_crcn_ctl.v // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved // 4150 Network Circle, Santa Clara, California 95054, U.S.A. // // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by // the Free Software Foundation; version 2 of the License. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA // // For the avoidance of doubt, and except that if any non-GPL license // choice is available it will apply instead, Sun elects to use only // the General Public License version 2 (GPLv2) at this time for any // software where a choice of GPL license versions is made // available with the language indicating that GPLv2 or any later version // may be used, or where a choice of which version of the GPL is applied is // otherwise unspecified. // // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, // CA 95054 USA or visit www.sun.com if you need additional information or // have any questions. // // ========== Copyright Header End ============================================ module mcu_crcn_ctl ( crcnd_crc0_0, crcnd_crc0_1, crcnd_crc1_0, crcnd_crc1_1, crcndf_crc0_0, crcndf_crc0_1, crcndf_crc1_0, crcndf_crc1_1, bd00, bd01, bd10, bd11, drl2clk, scan_in, scan_out, tcu_pce_ov, tcu_aclk, tcu_bclk, tcu_scan_en); wire pce_ov; wire siclk; wire soclk; wire se; wire l1clk; wire spares_scanin; wire spares_scanout; output [11:0] crcnd_crc0_0; output [11:0] crcnd_crc0_1; output [11:0] crcnd_crc1_0; output [11:0] crcnd_crc1_1; output [5:0] crcndf_crc0_0; output [5:0] crcndf_crc0_1; output [5:0] crcndf_crc1_0; output [5:0] crcndf_crc1_1; input [71:0] bd00; input [71:0] bd01; input [71:0] bd10; input [71:0] bd11; input drl2clk; input scan_in; output scan_out; input tcu_pce_ov; input tcu_aclk; input tcu_bclk; input tcu_scan_en; // Code assign pce_ov = tcu_pce_ov; assign siclk = tcu_aclk; assign soclk = tcu_bclk; assign se = tcu_scan_en; // 0in set_clock drl2clk -default mcu_crcn_ctl_l1clkhdr_ctl_macro clkgen ( .l2clk(drl2clk), .l1en (1'b1 ), .stop(1'b0), .l1clk(l1clk), .pce_ov(pce_ov), .se(se)); mcu_crcnd_ctl crcnd0_0 ( .in(bd00[71:0]), .crc(crcnd_crc0_0[11:0]) ); mcu_crcndf_ctl crcndf0_0 ( .in(bd00[71:0]), .crc(crcndf_crc0_0[5:0]) ); mcu_crcnd_ctl crcnd0_1 ( .in(bd01[71:0]), .crc(crcnd_crc0_1[11:0]) ); mcu_crcndf_ctl crcndf0_1 ( .in(bd01[71:0]), .crc(crcndf_crc0_1[5:0]) ); mcu_crcnd_ctl crcnd1_0 ( .in(bd10[71:0]), .crc(crcnd_crc1_0[11:0]) ); mcu_crcndf_ctl crcndf1_0 ( .in(bd10[71:0]), .crc(crcndf_crc1_0[5:0]) ); mcu_crcnd_ctl crcnd1_1 ( .in(bd11[71:0]), .crc(crcnd_crc1_1[11:0]) ); mcu_crcndf_ctl crcndf1_1 ( .in(bd11[71:0]), .crc(crcndf_crc1_1[5:0]) ); mcu_crcn_ctl_spare_ctl_macro__num_1 spares ( .scan_in(spares_scanin), .scan_out(spares_scanout), .l1clk(l1clk), .siclk(siclk), .soclk(soclk) ); // fixscan start: assign spares_scanin = scan_in ; assign scan_out = spares_scanout ; // fixscan end: endmodule // any PARAMS parms go into naming of macro module mcu_crcn_ctl_l1clkhdr_ctl_macro ( l2clk, l1en, pce_ov, stop, se, l1clk); input l2clk; input l1en; input pce_ov; input stop; input se; output l1clk; cl_sc1_l1hdr_8x c_0 ( .l2clk(l2clk), .pce(l1en), .l1clk(l1clk), .se(se), .pce_ov(pce_ov), .stop(stop) ); endmodule // Description: Spare gate macro for control blocks // // Param num controls the number of times the macro is added // flops=0 can be used to use only combination spare logic module mcu_crcn_ctl_spare_ctl_macro__num_1 ( l1clk, scan_in, siclk, soclk, scan_out); wire si_0; wire so_0; wire spare0_flop_unused; wire spare0_buf_32x_unused; wire spare0_nand3_8x_unused; wire spare0_inv_8x_unused; wire spare0_aoi22_4x_unused; wire spare0_buf_8x_unused; wire spare0_oai22_4x_unused; wire spare0_inv_16x_unused; wire spare0_nand2_16x_unused; wire spare0_nor3_4x_unused; wire spare0_nand2_8x_unused; wire spare0_buf_16x_unused; wire spare0_nor2_16x_unused; wire spare0_inv_32x_unused; input l1clk; input scan_in; input siclk; input soclk; output scan_out; cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), .siclk(siclk), .soclk(soclk), .si(si_0), .so(so_0), .d(1'b0), .q(spare0_flop_unused)); assign si_0 = scan_in; cl_u1_buf_32x spare0_buf_32x (.in(1'b1), .out(spare0_buf_32x_unused)); cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), .in1(1'b1), .in2(1'b1), .out(spare0_nand3_8x_unused)); cl_u1_inv_8x spare0_inv_8x (.in(1'b1), .out(spare0_inv_8x_unused)); cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), .in01(1'b1), .in10(1'b1), .in11(1'b1), .out(spare0_aoi22_4x_unused)); cl_u1_buf_8x spare0_buf_8x (.in(1'b1), .out(spare0_buf_8x_unused)); cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), .in01(1'b1), .in10(1'b1), .in11(1'b1), .out(spare0_oai22_4x_unused)); cl_u1_inv_16x spare0_inv_16x (.in(1'b1), .out(spare0_inv_16x_unused)); cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), .in1(1'b1), .out(spare0_nand2_16x_unused)); cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), .in1(1'b0), .in2(1'b0), .out(spare0_nor3_4x_unused)); cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), .in1(1'b1), .out(spare0_nand2_8x_unused)); cl_u1_buf_16x spare0_buf_16x (.in(1'b1), .out(spare0_buf_16x_unused)); cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), .in1(1'b0), .out(spare0_nor2_16x_unused)); cl_u1_inv_32x spare0_inv_32x (.in(1'b1), .out(spare0_inv_32x_unused)); assign scan_out = so_0; endmodule