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// OpenSPARC T2 Processor File: niu_ram_128_42.v
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/**********************************************************
***********************************************************

    Project         : Niu

    File name       : niu_ram_128_42.v

    Module(s) name  : niu_ram_128_42

    Parent modules  :            

    Child modules   :           

    Author's name   : George Chu

    Date            : April. 2004

    Description     :

    Synthesis Notes:

    Modification History:
    Date       Description
    ----       -----------

************************************************************
***********************************************************/

`timescale 1ns/10ps

module niu_ram_128_42 (
                         tcu_aclk,
                         tcu_bclk,
                         tcu_se_scancollar_in,
                         tcu_array_wr_inhibit,
                         scan_in,
                         scan_out,
                         mbi_wdata,
                         mbi_rd_adr,
                         mbi_wr_adr,
                         mbi_wr_en,
                         mbi_rd_en,
                         mbi_run,
                         data_inp,
                         addr_rd,
                         addr_wt,
                         wt_enable,
                         cs_rd,
                         clk,
                         data_out
                       );

parameter DATA_WIDTH_MINUS1 = 41; 
parameter ADDR_WIDTH_MINUS1 = 6; 

input                          tcu_aclk;
input                          tcu_bclk;
input                          tcu_se_scancollar_in;
input                          tcu_array_wr_inhibit;
input                          scan_in;
output                         scan_out;

input    [DATA_WIDTH_MINUS1:0] mbi_wdata;
input    [ADDR_WIDTH_MINUS1:0] mbi_rd_adr;
input    [ADDR_WIDTH_MINUS1:0] mbi_wr_adr;
input                          mbi_wr_en;
input                          mbi_rd_en;
input                          mbi_run;

input    [DATA_WIDTH_MINUS1:0] data_inp;      // data_input,               via port_B
input    [ADDR_WIDTH_MINUS1:0] addr_rd;       //  read_address,            via port_A
input    [ADDR_WIDTH_MINUS1:0] addr_wt;       // write_address,            via port_B
input                          wt_enable;     // write_enable,             via port_B
input                          cs_rd;         // chip_selet_rd_port,     i.e., port_A
input                          clk;
output   [DATA_WIDTH_MINUS1:0] data_out;      // data read out, via port_A

wire     [DATA_WIDTH_MINUS1:0] data_out;
wire                           scan_out;

wire     [ADDR_WIDTH_MINUS1:0] mux_wr_adr;
wire                           mux_wr_en;
wire     [ADDR_WIDTH_MINUS1:0] mux_rd_adr;
wire                           mux_rd_en;
wire     [DATA_WIDTH_MINUS1:0] mux_wdata;

  assign mux_wdata  = mbi_run ? mbi_wdata  : data_inp;
  assign mux_rd_adr = mbi_run ? mbi_rd_adr : addr_rd;
  assign mux_wr_adr = mbi_run ? mbi_wr_adr : addr_wt;
  assign mux_wr_en  = mbi_run ? mbi_wr_en  : wt_enable;
  assign mux_rd_en  = mbi_run ? mbi_rd_en  : cs_rd;

  n2_com_dp_128x42s_cust  ram_128_42_0    (
                                           .tcu_pce_ov            (1'h1),
                                           .tcu_aclk              (tcu_aclk),
                                           .tcu_bclk              (tcu_bclk),
                                           .tcu_se_scancollar_in  (tcu_se_scancollar_in),
                                           .rd_pce                (1'h1),
                                           .wr_pce                (1'h1),
                                           .bist_clk_mux_sel      (1'h0),
                                           .tcu_array_wr_inhibit  (tcu_array_wr_inhibit),
                                           .scan_in               (scan_in),
                                           .scan_out              (scan_out),
                                           .wr_adr                (mux_wr_adr[6:0]),
                                           .wr_en                 (mux_wr_en),
                                           .rd_adr                (mux_rd_adr[6:0]),
                                           .rd_en                 (mux_rd_en),
                                           .din                   (mux_wdata[41:0]),
                                           .dout                  (data_out[41:0]),
                                           .rdclk                 (clk),
                                           .wrclk                 (clk)
                                          );

endmodule